1 /*
2 * linux/drivers/char/8250.c
3 *
4 * Driver for 8250/16550-type serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * $Id: 8250.c,v 1.90 2002/07/28 10:03:27 rmk Exp $
16 *
17 * A note about mapbase / membase
18 *
19 * mapbase is the physical address of the IO port.
20 * membase is an 'ioremapped' cookie.
21 */
22
23 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
24 #define SUPPORT_SYSRQ
25 #endif
26
27 #include <linux/module.h>
28 #include <linux/moduleparam.h>
29 #include <linux/ioport.h>
30 #include <linux/init.h>
31 #include <linux/console.h>
32 #include <linux/sysrq.h>
33 #include <linux/delay.h>
34 #include <linux/platform_device.h>
35 #include <linux/tty.h>
36 #include <linux/tty_flip.h>
37 #include <linux/serial_reg.h>
38 #include <linux/serial_core.h>
39 #include <linux/serial.h>
40 #include <linux/serial_8250.h>
41 #include <linux/nmi.h>
42 #include <linux/mutex.h>
43
44 #include <asm/io.h>
45 #include <asm/irq.h>
46
47 #include "8250.h"
48
49 /*
50 * Configuration:
51 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
52 * is unsafe when used on edge-triggered interrupts.
53 */
54 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
55
56 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
57
58 /*
59 * Debugging.
60 */
61 #if 0
62 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
63 #else
64 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
65 #endif
66
67 #if 0
68 #define DEBUG_INTR(fmt...) printk(fmt)
69 #else
70 #define DEBUG_INTR(fmt...) do { } while (0)
71 #endif
72
73 #define PASS_LIMIT 256
74
75 /*
76 * We default to IRQ0 for the "no irq" hack. Some
77 * machine types want others as well - they're free
78 * to redefine this in their header file.
79 */
80 #define is_real_interrupt(irq) ((irq) != 0)
81
82 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
83 #define CONFIG_SERIAL_DETECT_IRQ 1
84 #endif
85 #ifdef CONFIG_SERIAL_8250_MANY_PORTS
86 #define CONFIG_SERIAL_MANY_PORTS 1
87 #endif
88
89 /*
90 * HUB6 is always on. This will be removed once the header
91 * files have been cleaned.
92 */
93 #define CONFIG_HUB6 1
94
95 #include <asm/serial.h>
96
97 /*
98 * SERIAL_PORT_DFNS tells us about built-in ports that have no
99 * standard enumeration mechanism. Platforms that can find all
100 * serial ports via mechanisms like ACPI or PCI need not supply it.
101 */
102 #ifndef SERIAL_PORT_DFNS
103 #define SERIAL_PORT_DFNS
104 #endif
105
106 static const struct old_serial_port old_serial_port[] = {
107 SERIAL_PORT_DFNS /* defined in asm/serial.h */
108 };
109
110 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
111
112 #ifdef CONFIG_SERIAL_8250_RSA
113
114 #define PORT_RSA_MAX 4
115 static unsigned long probe_rsa[PORT_RSA_MAX];
116 static unsigned int probe_rsa_count;
117 #endif /* CONFIG_SERIAL_8250_RSA */
118
119 struct uart_8250_port {
120 struct uart_port port;
121 struct timer_list timer; /* "no irq" timer */
122 struct list_head list; /* ports on this IRQ */
123 unsigned short capabilities; /* port capabilities */
124 unsigned short bugs; /* port bugs */
125 unsigned int tx_loadsz; /* transmit fifo load size */
126 unsigned char acr;
127 unsigned char ier;
128 unsigned char lcr;
129 unsigned char mcr;
130 unsigned char mcr_mask; /* mask of user bits */
131 unsigned char mcr_force; /* mask of forced bits */
132
133 /*
134 * Some bits in registers are cleared on a read, so they must
135 * be saved whenever the register is read but the bits will not
136 * be immediately processed.
137 */
138 #define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
139 unsigned char lsr_saved_flags;
140 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
141 unsigned char msr_saved_flags;
142
143 /*
144 * We provide a per-port pm hook.
145 */
146 void (*pm)(struct uart_port *port,
147 unsigned int state, unsigned int old);
148 };
149
150 struct irq_info {
151 spinlock_t lock;
152 struct list_head *head;
153 };
154
155 static struct irq_info irq_lists[NR_IRQS];
156
157 /*
158 * Here we define the default xmit fifo size used for each type of UART.
159 */
160 static const struct serial8250_config uart_config[] = {
161 [PORT_UNKNOWN] = {
162 .name = "unknown",
163 .fifo_size = 1,
164 .tx_loadsz = 1,
165 },
166 [PORT_8250] = {
167 .name = "8250",
168 .fifo_size = 1,
169 .tx_loadsz = 1,
170 },
171 [PORT_16450] = {
172 .name = "16450",
173 .fifo_size = 1,
174 .tx_loadsz = 1,
175 },
176 [PORT_16550] = {
177 .name = "16550",
178 .fifo_size = 1,
179 .tx_loadsz = 1,
180 },
181 [PORT_16550A] = {
182 .name = "16550A",
183 .fifo_size = 16,
184 .tx_loadsz = 16,
185 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
186 .flags = UART_CAP_FIFO,
187 },
188 [PORT_CIRRUS] = {
189 .name = "Cirrus",
190 .fifo_size = 1,
191 .tx_loadsz = 1,
192 },
193 [PORT_16650] = {
194 .name = "ST16650",
195 .fifo_size = 1,
196 .tx_loadsz = 1,
197 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
198 },
199 [PORT_16650V2] = {
200 .name = "ST16650V2",
201 .fifo_size = 32,
202 .tx_loadsz = 16,
203 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
204 UART_FCR_T_TRIG_00,
205 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
206 },
207 [PORT_16750] = {
208 .name = "TI16750",
209 .fifo_size = 64,
210 .tx_loadsz = 64,
211 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
212 UART_FCR7_64BYTE,
213 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
214 },
215 [PORT_STARTECH] = {
216 .name = "Startech",
217 .fifo_size = 1,
218 .tx_loadsz = 1,
219 },
220 [PORT_16C950] = {
221 .name = "16C950/954",
222 .fifo_size = 128,
223 .tx_loadsz = 128,
224 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
225 .flags = UART_CAP_FIFO,
226 },
227 [PORT_16654] = {
228 .name = "ST16654",
229 .fifo_size = 64,
230 .tx_loadsz = 32,
231 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
232 UART_FCR_T_TRIG_10,
233 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
234 },
235 [PORT_16850] = {
236 .name = "XR16850",
237 .fifo_size = 128,
238 .tx_loadsz = 128,
239 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
240 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
241 },
242 [PORT_RSA] = {
243 .name = "RSA",
244 .fifo_size = 2048,
245 .tx_loadsz = 2048,
246 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
247 .flags = UART_CAP_FIFO,
248 },
249 [PORT_NS16550A] = {
250 .name = "NS16550A",
251 .fifo_size = 16,
252 .tx_loadsz = 16,
253 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
254 .flags = UART_CAP_FIFO | UART_NATSEMI,
255 },
256 [PORT_XSCALE] = {
257 .name = "XScale",
258 .fifo_size = 32,
259 .tx_loadsz = 32,
260 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
261 .flags = UART_CAP_FIFO | UART_CAP_UUE,
262 },
263 [PORT_RM9000] = {
264 .name = "RM9000",
265 .fifo_size = 16,
266 .tx_loadsz = 16,
267 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
268 .flags = UART_CAP_FIFO,
269 },
270 };
271
272 #if defined (CONFIG_SERIAL_8250_AU1X00)
273
274 /* Au1x00 UART hardware has a weird register layout */
275 static const u8 au_io_in_map[] = {
276 [UART_RX] = 0,
277 [UART_IER] = 2,
278 [UART_IIR] = 3,
279 [UART_LCR] = 5,
280 [UART_MCR] = 6,
281 [UART_LSR] = 7,
282 [UART_MSR] = 8,
283 };
284
285 static const u8 au_io_out_map[] = {
286 [UART_TX] = 1,
287 [UART_IER] = 2,
288 [UART_FCR] = 4,
289 [UART_LCR] = 5,
290 [UART_MCR] = 6,
291 };
292
293 /* sane hardware needs no mapping */
294 static inline int map_8250_in_reg(struct uart_8250_port *up, int offset)
295 {
296 if (up->port.iotype != UPIO_AU)
297 return offset;
298 return au_io_in_map[offset];
299 }
300
301 static inline int map_8250_out_reg(struct uart_8250_port *up, int offset)
302 {
303 if (up->port.iotype != UPIO_AU)
304 return offset;
305 return au_io_out_map[offset];
306 }
307
308 #elif defined(CONFIG_SERIAL_8250_RM9K)
309
310 static const u8
311 regmap_in[8] = {
312 [UART_RX] = 0x00,
313 [UART_IER] = 0x0c,
314 [UART_IIR] = 0x14,
315 [UART_LCR] = 0x1c,
316 [UART_MCR] = 0x20,
317 [UART_LSR] = 0x24,
318 [UART_MSR] = 0x28,
319 [UART_SCR] = 0x2c
320 },
321 regmap_out[8] = {
322 [UART_TX] = 0x04,
323 [UART_IER] = 0x0c,
324 [UART_FCR] = 0x18,
325 [UART_LCR] = 0x1c,
326 [UART_MCR] = 0x20,
327 [UART_LSR] = 0x24,
328 [UART_MSR] = 0x28,
329 [UART_SCR] = 0x2c
330 };
331
332 static inline int map_8250_in_reg(struct uart_8250_port *up, int offset)
333 {
334 if (up->port.iotype != UPIO_RM9000)
335 return offset;
336 return regmap_in[offset];
337 }
338
339 static inline int map_8250_out_reg(struct uart_8250_port *up, int offset)
340 {
341 if (up->port.iotype != UPIO_RM9000)
342 return offset;
343 return regmap_out[offset];
344 }
345
346 #else
347
348 /* sane hardware needs no mapping */
349 #define map_8250_in_reg(up, offset) (offset)
350 #define map_8250_out_reg(up, offset) (offset)
351
352 #endif
353
354 static unsigned int serial_in(struct uart_8250_port *up, int offset)
355 {
356 unsigned int tmp;
357 offset = map_8250_in_reg(up, offset) << up->port.regshift;
358
359 switch (up->port.iotype) {
360 case UPIO_HUB6:
361 outb(up->port.hub6 - 1 + offset, up->port.iobase);
362 return inb(up->port.iobase + 1);
363
364 case UPIO_MEM:
365 case UPIO_DWAPB:
366 return readb(up->port.membase + offset);
367
368 case UPIO_RM9000:
369 case UPIO_MEM32:
370 return readl(up->port.membase + offset);
371
372 #ifdef CONFIG_SERIAL_8250_AU1X00
373 case UPIO_AU:
374 return __raw_readl(up->port.membase + offset);
375 #endif
376
377 case UPIO_TSI:
378 if (offset == UART_IIR) {
379 tmp = readl(up->port.membase + (UART_IIR & ~3));
380 return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
381 } else
382 return readb(up->port.membase + offset);
383
384 default:
385 return inb(up->port.iobase + offset);
386 }
387 }
388
389 static void
390 serial_out(struct uart_8250_port *up, int offset, int value)
391 {
392 /* Save the offset before it's remapped */
393 int save_offset = offset;
394 offset = map_8250_out_reg(up, offset) << up->port.regshift;
395
396 switch (up->port.iotype) {
397 case UPIO_HUB6:
398 outb(up->port.hub6 - 1 + offset, up->port.iobase);
399 outb(value, up->port.iobase + 1);
400 break;
401
402 case UPIO_MEM:
403 writeb(value, up->port.membase + offset);
404 break;
405
406 case UPIO_RM9000:
407 case UPIO_MEM32:
408 writel(value, up->port.membase + offset);
409 break;
410
411 #ifdef CONFIG_SERIAL_8250_AU1X00
412 case UPIO_AU:
413 __raw_writel(value, up->port.membase + offset);
414 break;
415 #endif
416 case UPIO_TSI:
417 if (!((offset == UART_IER) && (value & UART_IER_UUE)))
418 writeb(value, up->port.membase + offset);
419 break;
420
421 case UPIO_DWAPB:
422 /* Save the LCR value so it can be re-written when a
423 * Busy Detect interrupt occurs. */
424 if (save_offset == UART_LCR)
425 up->lcr = value;
426 writeb(value, up->port.membase + offset);
427 /* Read the IER to ensure any interrupt is cleared before
428 * returning from ISR. */
429 if (save_offset == UART_TX || save_offset == UART_IER)
430 value = serial_in(up, UART_IER);
431 break;
432
433 default:
434 outb(value, up->port.iobase + offset);
435 }
436 }
437
438 static void
439 serial_out_sync(struct uart_8250_port *up, int offset, int value)
440 {
441 switch (up->port.iotype) {
442 case UPIO_MEM:
443 case UPIO_MEM32:
444 #ifdef CONFIG_SERIAL_8250_AU1X00
445 case UPIO_AU:
446 #endif
447 case UPIO_DWAPB:
448 serial_out(up, offset, value);
449 serial_in(up, UART_LCR); /* safe, no side-effects */
450 break;
451 default:
452 serial_out(up, offset, value);
453 }
454 }
455
456 /*
457 * We used to support using pause I/O for certain machines. We
458 * haven't supported this for a while, but just in case it's badly
459 * needed for certain old 386 machines, I've left these #define's
460 * in....
461 */
462 #define serial_inp(up, offset) serial_in(up, offset)
463 #define serial_outp(up, offset, value) serial_out(up, offset, value)
464
465 /* Uart divisor latch read */
466 static inline int _serial_dl_read(struct uart_8250_port *up)
467 {
468 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
469 }
470
471 /* Uart divisor latch write */
472 static inline void _serial_dl_write(struct uart_8250_port *up, int value)
473 {
474 serial_outp(up, UART_DLL, value & 0xff);
475 serial_outp(up, UART_DLM, value >> 8 & 0xff);
476 }
477
478 #if defined(CONFIG_SERIAL_8250_AU1X00)
479 /* Au1x00 haven't got a standard divisor latch */
480 static int serial_dl_read(struct uart_8250_port *up)
481 {
482 if (up->port.iotype == UPIO_AU)
483 return __raw_readl(up->port.membase + 0x28);
484 else
485 return _serial_dl_read(up);
486 }
487
488 static void serial_dl_write(struct uart_8250_port *up, int value)
489 {
490 if (up->port.iotype == UPIO_AU)
491 __raw_writel(value, up->port.membase + 0x28);
492 else
493 _serial_dl_write(up, value);
494 }
495 #elif defined(CONFIG_SERIAL_8250_RM9K)
496 static int serial_dl_read(struct uart_8250_port *up)
497 {
498 return (up->port.iotype == UPIO_RM9000) ?
499 (((__raw_readl(up->port.membase + 0x10) << 8) |
500 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
501 _serial_dl_read(up);
502 }
503
504 static void serial_dl_write(struct uart_8250_port *up, int value)
505 {
506 if (up->port.iotype == UPIO_RM9000) {
507 __raw_writel(value, up->port.membase + 0x08);
508 __raw_writel(value >> 8, up->port.membase + 0x10);
509 } else {
510 _serial_dl_write(up, value);
511 }
512 }
513 #else
514 #define serial_dl_read(up) _serial_dl_read(up)
515 #define serial_dl_write(up, value) _serial_dl_write(up, value)
516 #endif
517
518 /*
519 * For the 16C950
520 */
521 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
522 {
523 serial_out(up, UART_SCR, offset);
524 serial_out(up, UART_ICR, value);
525 }
526
527 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
528 {
529 unsigned int value;
530
531 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
532 serial_out(up, UART_SCR, offset);
533 value = serial_in(up, UART_ICR);
534 serial_icr_write(up, UART_ACR, up->acr);
535
536 return value;
537 }
538
539 /*
540 * FIFO support.
541 */
542 static inline void serial8250_clear_fifos(struct uart_8250_port *p)
543 {
544 if (p->capabilities & UART_CAP_FIFO) {
545 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
546 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
547 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
548 serial_outp(p, UART_FCR, 0);
549 }
550 }
551
552 /*
553 * IER sleep support. UARTs which have EFRs need the "extended
554 * capability" bit enabled. Note that on XR16C850s, we need to
555 * reset LCR to write to IER.
556 */
557 static inline void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
558 {
559 if (p->capabilities & UART_CAP_SLEEP) {
560 if (p->capabilities & UART_CAP_EFR) {
561 serial_outp(p, UART_LCR, 0xBF);
562 serial_outp(p, UART_EFR, UART_EFR_ECB);
563 serial_outp(p, UART_LCR, 0);
564 }
565 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
566 if (p->capabilities & UART_CAP_EFR) {
567 serial_outp(p, UART_LCR, 0xBF);
568 serial_outp(p, UART_EFR, 0);
569 serial_outp(p, UART_LCR, 0);
570 }
571 }
572 }
573
574 #ifdef CONFIG_SERIAL_8250_RSA
575 /*
576 * Attempts to turn on the RSA FIFO. Returns zero on failure.
577 * We set the port uart clock rate if we succeed.
578 */
579 static int __enable_rsa(struct uart_8250_port *up)
580 {
581 unsigned char mode;
582 int result;
583
584 mode = serial_inp(up, UART_RSA_MSR);
585 result = mode & UART_RSA_MSR_FIFO;
586
587 if (!result) {
588 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
589 mode = serial_inp(up, UART_RSA_MSR);
590 result = mode & UART_RSA_MSR_FIFO;
591 }
592
593 if (result)
594 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
595
596 return result;
597 }
598
599 static void enable_rsa(struct uart_8250_port *up)
600 {
601 if (up->port.type == PORT_RSA) {
602 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
603 spin_lock_irq(&up->port.lock);
604 __enable_rsa(up);
605 spin_unlock_irq(&up->port.lock);
606 }
607 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
608 serial_outp(up, UART_RSA_FRR, 0);
609 }
610 }
611
612 /*
613 * Attempts to turn off the RSA FIFO. Returns zero on failure.
614 * It is unknown why interrupts were disabled in here. However,
615 * the caller is expected to preserve this behaviour by grabbing
616 * the spinlock before calling this function.
617 */
618 static void disable_rsa(struct uart_8250_port *up)
619 {
620 unsigned char mode;
621 int result;
622
623 if (up->port.type == PORT_RSA &&
624 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
625 spin_lock_irq(&up->port.lock);
626
627 mode = serial_inp(up, UART_RSA_MSR);
628 result = !(mode & UART_RSA_MSR_FIFO);
629
630 if (!result) {
631 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
632 mode = serial_inp(up, UART_RSA_MSR);
633 result = !(mode & UART_RSA_MSR_FIFO);
634 }
635
636 if (result)
637 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
638 spin_unlock_irq(&up->port.lock);
639 }
640 }
641 #endif /* CONFIG_SERIAL_8250_RSA */
642
643 /*
644 * This is a quickie test to see how big the FIFO is.
645 * It doesn't work at all the time, more's the pity.
646 */
647 static int size_fifo(struct uart_8250_port *up)
648 {
649 unsigned char old_fcr, old_mcr, old_lcr;
650 unsigned short old_dl;
651 int count;
652
653 old_lcr = serial_inp(up, UART_LCR);
654 serial_outp(up, UART_LCR, 0);
655 old_fcr = serial_inp(up, UART_FCR);
656 old_mcr = serial_inp(up, UART_MCR);
657 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
658 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
659 serial_outp(up, UART_MCR, UART_MCR_LOOP);
660 serial_outp(up, UART_LCR, UART_LCR_DLAB);
661 old_dl = serial_dl_read(up);
662 serial_dl_write(up, 0x0001);
663 serial_outp(up, UART_LCR, 0x03);
664 for (count = 0; count < 256; count++)
665 serial_outp(up, UART_TX, count);
666 mdelay(20);/* FIXME - schedule_timeout */
667 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
668 (count < 256); count++)
669 serial_inp(up, UART_RX);
670 serial_outp(up, UART_FCR, old_fcr);
671 serial_outp(up, UART_MCR, old_mcr);
672 serial_outp(up, UART_LCR, UART_LCR_DLAB);
673 serial_dl_write(up, old_dl);
674 serial_outp(up, UART_LCR, old_lcr);
675
676 return count;
677 }
678
679 /*
680 * Read UART ID using the divisor method - set DLL and DLM to zero
681 * and the revision will be in DLL and device type in DLM. We
682 * preserve the device state across this.
683 */
684 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
685 {
686 unsigned char old_dll, old_dlm, old_lcr;
687 unsigned int id;
688
689 old_lcr = serial_inp(p, UART_LCR);
690 serial_outp(p, UART_LCR, UART_LCR_DLAB);
691
692 old_dll = serial_inp(p, UART_DLL);
693 old_dlm = serial_inp(p, UART_DLM);
694
695 serial_outp(p, UART_DLL, 0);
696 serial_outp(p, UART_DLM, 0);
697
698 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
699
700 serial_outp(p, UART_DLL, old_dll);
701 serial_outp(p, UART_DLM, old_dlm);
702 serial_outp(p, UART_LCR, old_lcr);
703
704 return id;
705 }
706
707 /*
708 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
709 * When this function is called we know it is at least a StarTech
710 * 16650 V2, but it might be one of several StarTech UARTs, or one of
711 * its clones. (We treat the broken original StarTech 16650 V1 as a
712 * 16550, and why not? Startech doesn't seem to even acknowledge its
713 * existence.)
714 *
715 * What evil have men's minds wrought...
716 */
717 static void autoconfig_has_efr(struct uart_8250_port *up)
718 {
719 unsigned int id1, id2, id3, rev;
720
721 /*
722 * Everything with an EFR has SLEEP
723 */
724 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
725
726 /*
727 * First we check to see if it's an Oxford Semiconductor UART.
728 *
729 * If we have to do this here because some non-National
730 * Semiconductor clone chips lock up if you try writing to the
731 * LSR register (which serial_icr_read does)
732 */
733
734 /*
735 * Check for Oxford Semiconductor 16C950.
736 *
737 * EFR [4] must be set else this test fails.
738 *
739 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
740 * claims that it's needed for 952 dual UART's (which are not
741 * recommended for new designs).
742 */
743 up->acr = 0;
744 serial_out(up, UART_LCR, 0xBF);
745 serial_out(up, UART_EFR, UART_EFR_ECB);
746 serial_out(up, UART_LCR, 0x00);
747 id1 = serial_icr_read(up, UART_ID1);
748 id2 = serial_icr_read(up, UART_ID2);
749 id3 = serial_icr_read(up, UART_ID3);
750 rev = serial_icr_read(up, UART_REV);
751
752 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
753
754 if (id1 == 0x16 && id2 == 0xC9 &&
755 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
756 up->port.type = PORT_16C950;
757
758 /*
759 * Enable work around for the Oxford Semiconductor 952 rev B
760 * chip which causes it to seriously miscalculate baud rates
761 * when DLL is 0.
762 */
763 if (id3 == 0x52 && rev == 0x01)
764 up->bugs |= UART_BUG_QUOT;
765 return;
766 }
767
768 /*
769 * We check for a XR16C850 by setting DLL and DLM to 0, and then
770 * reading back DLL and DLM. The chip type depends on the DLM
771 * value read back:
772 * 0x10 - XR16C850 and the DLL contains the chip revision.
773 * 0x12 - XR16C2850.
774 * 0x14 - XR16C854.
775 */
776 id1 = autoconfig_read_divisor_id(up);
777 DEBUG_AUTOCONF("850id=%04x ", id1);
778
779 id2 = id1 >> 8;
780 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
781 up->port.type = PORT_16850;
782 return;
783 }
784
785 /*
786 * It wasn't an XR16C850.
787 *
788 * We distinguish between the '654 and the '650 by counting
789 * how many bytes are in the FIFO. I'm using this for now,
790 * since that's the technique that was sent to me in the
791 * serial driver update, but I'm not convinced this works.
792 * I've had problems doing this in the past. -TYT
793 */
794 if (size_fifo(up) == 64)
795 up->port.type = PORT_16654;
796 else
797 up->port.type = PORT_16650V2;
798 }
799
800 /*
801 * We detected a chip without a FIFO. Only two fall into
802 * this category - the original 8250 and the 16450. The
803 * 16450 has a scratch register (accessible with LCR=0)
804 */
805 static void autoconfig_8250(struct uart_8250_port *up)
806 {
807 unsigned char scratch, status1, status2;
808
809 up->port.type = PORT_8250;
810
811 scratch = serial_in(up, UART_SCR);
812 serial_outp(up, UART_SCR, 0xa5);
813 status1 = serial_in(up, UART_SCR);
814 serial_outp(up, UART_SCR, 0x5a);
815 status2 = serial_in(up, UART_SCR);
816 serial_outp(up, UART_SCR, scratch);
817
818 if (status1 == 0xa5 && status2 == 0x5a)
819 up->port.type = PORT_16450;
820 }
821
822 static int broken_efr(struct uart_8250_port *up)
823 {
824 /*
825 * Exar ST16C2550 "A2" devices incorrectly detect as
826 * having an EFR, and report an ID of 0x0201. See
827 * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
828 */
829 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
830 return 1;
831
832 return 0;
833 }
834
835 /*
836 * We know that the chip has FIFOs. Does it have an EFR? The
837 * EFR is located in the same register position as the IIR and
838 * we know the top two bits of the IIR are currently set. The
839 * EFR should contain zero. Try to read the EFR.
840 */
841 static void autoconfig_16550a(struct uart_8250_port *up)
842 {
843 unsigned char status1, status2;
844 unsigned int iersave;
845
846 up->port.type = PORT_16550A;
847 up->capabilities |= UART_CAP_FIFO;
848
849 /*
850 * Check for presence of the EFR when DLAB is set.
851 * Only ST16C650V1 UARTs pass this test.
852 */
853 serial_outp(up, UART_LCR, UART_LCR_DLAB);
854 if (serial_in(up, UART_EFR) == 0) {
855 serial_outp(up, UART_EFR, 0xA8);
856 if (serial_in(up, UART_EFR) != 0) {
857 DEBUG_AUTOCONF("EFRv1 ");
858 up->port.type = PORT_16650;
859 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
860 } else {
861 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
862 }
863 serial_outp(up, UART_EFR, 0);
864 return;
865 }
866
867 /*
868 * Maybe it requires 0xbf to be written to the LCR.
869 * (other ST16C650V2 UARTs, TI16C752A, etc)
870 */
871 serial_outp(up, UART_LCR, 0xBF);
872 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
873 DEBUG_AUTOCONF("EFRv2 ");
874 autoconfig_has_efr(up);
875 return;
876 }
877
878 /*
879 * Check for a National Semiconductor SuperIO chip.
880 * Attempt to switch to bank 2, read the value of the LOOP bit
881 * from EXCR1. Switch back to bank 0, change it in MCR. Then
882 * switch back to bank 2, read it from EXCR1 again and check
883 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
884 */
885 serial_outp(up, UART_LCR, 0);
886 status1 = serial_in(up, UART_MCR);
887 serial_outp(up, UART_LCR, 0xE0);
888 status2 = serial_in(up, 0x02); /* EXCR1 */
889
890 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
891 serial_outp(up, UART_LCR, 0);
892 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
893 serial_outp(up, UART_LCR, 0xE0);
894 status2 = serial_in(up, 0x02); /* EXCR1 */
895 serial_outp(up, UART_LCR, 0);
896 serial_outp(up, UART_MCR, status1);
897
898 if ((status2 ^ status1) & UART_MCR_LOOP) {
899 unsigned short quot;
900
901 serial_outp(up, UART_LCR, 0xE0);
902
903 quot = serial_dl_read(up);
904 quot <<= 3;
905
906 status1 = serial_in(up, 0x04); /* EXCR2 */
907 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
908 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
909 serial_outp(up, 0x04, status1);
910
911 serial_dl_write(up, quot);
912
913 serial_outp(up, UART_LCR, 0);
914
915 up->port.uartclk = 921600*16;
916 up->port.type = PORT_NS16550A;
917 up->capabilities |= UART_NATSEMI;
918 return;
919 }
920 }
921
922 /*
923 * No EFR. Try to detect a TI16750, which only sets bit 5 of
924 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
925 * Try setting it with and without DLAB set. Cheap clones
926 * set bit 5 without DLAB set.
927 */
928 serial_outp(up, UART_LCR, 0);
929 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
930 status1 = serial_in(up, UART_IIR) >> 5;
931 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
932 serial_outp(up, UART_LCR, UART_LCR_DLAB);
933 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
934 status2 = serial_in(up, UART_IIR) >> 5;
935 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
936 serial_outp(up, UART_LCR, 0);
937
938 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
939
940 if (status1 == 6 && status2 == 7) {
941 up->port.type = PORT_16750;
942 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
943 return;
944 }
945
946 /*
947 * Try writing and reading the UART_IER_UUE bit (b6).
948 * If it works, this is probably one of the Xscale platform's
949 * internal UARTs.
950 * We're going to explicitly set the UUE bit to 0 before
951 * trying to write and read a 1 just to make sure it's not
952 * already a 1 and maybe locked there before we even start start.
953 */
954 iersave = serial_in(up, UART_IER);
955 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
956 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
957 /*
958 * OK it's in a known zero state, try writing and reading
959 * without disturbing the current state of the other bits.
960 */
961 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
962 if (serial_in(up, UART_IER) & UART_IER_UUE) {
963 /*
964 * It's an Xscale.
965 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
966 */
967 DEBUG_AUTOCONF("Xscale ");
968 up->port.type = PORT_XSCALE;
969 up->capabilities |= UART_CAP_UUE;
970 return;
971 }
972 } else {
973 /*
974 * If we got here we couldn't force the IER_UUE bit to 0.
975 * Log it and continue.
976 */
977 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
978 }
979 serial_outp(up, UART_IER, iersave);
980 }
981
982 /*
983 * This routine is called by rs_init() to initialize a specific serial
984 * port. It determines what type of UART chip this serial port is
985 * using: 8250, 16450, 16550, 16550A. The important question is
986 * whether or not this UART is a 16550A or not, since this will
987 * determine whether or not we can use its FIFO features or not.
988 */
989 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
990 {
991 unsigned char status1, scratch, scratch2, scratch3;
992 unsigned char save_lcr, save_mcr;
993 unsigned long flags;
994
995 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
996 return;
997
998 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04x, 0x%p): ",
999 up->port.line, up->port.iobase, up->port.membase);
1000
1001 /*
1002 * We really do need global IRQs disabled here - we're going to
1003 * be frobbing the chips IRQ enable register to see if it exists.
1004 */
1005 spin_lock_irqsave(&up->port.lock, flags);
1006
1007 up->capabilities = 0;
1008 up->bugs = 0;
1009
1010 if (!(up->port.flags & UPF_BUGGY_UART)) {
1011 /*
1012 * Do a simple existence test first; if we fail this,
1013 * there's no point trying anything else.
1014 *
1015 * 0x80 is used as a nonsense port to prevent against
1016 * false positives due to ISA bus float. The
1017 * assumption is that 0x80 is a non-existent port;
1018 * which should be safe since include/asm/io.h also
1019 * makes this assumption.
1020 *
1021 * Note: this is safe as long as MCR bit 4 is clear
1022 * and the device is in "PC" mode.
1023 */
1024 scratch = serial_inp(up, UART_IER);
1025 serial_outp(up, UART_IER, 0);
1026 #ifdef __i386__
1027 outb(0xff, 0x080);
1028 #endif
1029 /*
1030 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1031 * 16C754B) allow only to modify them if an EFR bit is set.
1032 */
1033 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1034 serial_outp(up, UART_IER, 0x0F);
1035 #ifdef __i386__
1036 outb(0, 0x080);
1037 #endif
1038 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1039 serial_outp(up, UART_IER, scratch);
1040 if (scratch2 != 0 || scratch3 != 0x0F) {
1041 /*
1042 * We failed; there's nothing here
1043 */
1044 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1045 scratch2, scratch3);
1046 goto out;
1047 }
1048 }
1049
1050 save_mcr = serial_in(up, UART_MCR);
1051 save_lcr = serial_in(up, UART_LCR);
1052
1053 /*
1054 * Check to see if a UART is really there. Certain broken
1055 * internal modems based on the Rockwell chipset fail this
1056 * test, because they apparently don't implement the loopback
1057 * test mode. So this test is skipped on the COM 1 through
1058 * COM 4 ports. This *should* be safe, since no board
1059 * manufacturer would be stupid enough to design a board
1060 * that conflicts with COM 1-4 --- we hope!
1061 */
1062 if (!(up->port.flags & UPF_SKIP_TEST)) {
1063 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1064 status1 = serial_inp(up, UART_MSR) & 0xF0;
1065 serial_outp(up, UART_MCR, save_mcr);
1066 if (status1 != 0x90) {
1067 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1068 status1);
1069 goto out;
1070 }
1071 }
1072
1073 /*
1074 * We're pretty sure there's a port here. Lets find out what
1075 * type of port it is. The IIR top two bits allows us to find
1076 * out if it's 8250 or 16450, 16550, 16550A or later. This
1077 * determines what we test for next.
1078 *
1079 * We also initialise the EFR (if any) to zero for later. The
1080 * EFR occupies the same register location as the FCR and IIR.
1081 */
1082 serial_outp(up, UART_LCR, 0xBF);
1083 serial_outp(up, UART_EFR, 0);
1084 serial_outp(up, UART_LCR, 0);
1085
1086 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1087 scratch = serial_in(up, UART_IIR) >> 6;
1088
1089 DEBUG_AUTOCONF("iir=%d ", scratch);
1090
1091 switch (scratch) {
1092 case 0:
1093 autoconfig_8250(up);
1094 break;
1095 case 1:
1096 up->port.type = PORT_UNKNOWN;
1097 break;
1098 case 2:
1099 up->port.type = PORT_16550;
1100 break;
1101 case 3:
1102 autoconfig_16550a(up);
1103 break;
1104 }
1105
1106 #ifdef CONFIG_SERIAL_8250_RSA
1107 /*
1108 * Only probe for RSA ports if we got the region.
1109 */
1110 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1111 int i;
1112
1113 for (i = 0 ; i < probe_rsa_count; ++i) {
1114 if (probe_rsa[i] == up->port.iobase &&
1115 __enable_rsa(up)) {
1116 up->port.type = PORT_RSA;
1117 break;
1118 }
1119 }
1120 }
1121 #endif
1122
1123 #ifdef CONFIG_SERIAL_8250_AU1X00
1124 /* if access method is AU, it is a 16550 with a quirk */
1125 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
1126 up->bugs |= UART_BUG_NOMSR;
1127 #endif
1128
1129 serial_outp(up, UART_LCR, save_lcr);
1130
1131 if (up->capabilities != uart_config[up->port.type].flags) {
1132 printk(KERN_WARNING
1133 "ttyS%d: detected caps %08x should be %08x\n",
1134 up->port.line, up->capabilities,
1135 uart_config[up->port.type].flags);
1136 }
1137
1138 up->port.fifosize = uart_config[up->port.type].fifo_size;
1139 up->capabilities = uart_config[up->port.type].flags;
1140 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1141
1142 if (up->port.type == PORT_UNKNOWN)
1143 goto out;
1144
1145 /*
1146 * Reset the UART.
1147 */
1148 #ifdef CONFIG_SERIAL_8250_RSA
1149 if (up->port.type == PORT_RSA)
1150 serial_outp(up, UART_RSA_FRR, 0);
1151 #endif
1152 serial_outp(up, UART_MCR, save_mcr);
1153 serial8250_clear_fifos(up);
1154 serial_in(up, UART_RX);
1155 if (up->capabilities & UART_CAP_UUE)
1156 serial_outp(up, UART_IER, UART_IER_UUE);
1157 else
1158 serial_outp(up, UART_IER, 0);
1159
1160 out:
1161 spin_unlock_irqrestore(&up->port.lock, flags);
1162 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1163 }
1164
1165 static void autoconfig_irq(struct uart_8250_port *up)
1166 {
1167 unsigned char save_mcr, save_ier;
1168 unsigned char save_ICP = 0;
1169 unsigned int ICP = 0;
1170 unsigned long irqs;
1171 int irq;
1172
1173 if (up->port.flags & UPF_FOURPORT) {
1174 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1175 save_ICP = inb_p(ICP);
1176 outb_p(0x80, ICP);
1177 (void) inb_p(ICP);
1178 }
1179
1180 /* forget possible initially masked and pending IRQ */
1181 probe_irq_off(probe_irq_on());
1182 save_mcr = serial_inp(up, UART_MCR);
1183 save_ier = serial_inp(up, UART_IER);
1184 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1185
1186 irqs = probe_irq_on();
1187 serial_outp(up, UART_MCR, 0);
1188 udelay(10);
1189 if (up->port.flags & UPF_FOURPORT) {
1190 serial_outp(up, UART_MCR,
1191 UART_MCR_DTR | UART_MCR_RTS);
1192 } else {
1193 serial_outp(up, UART_MCR,
1194 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1195 }
1196 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1197 (void)serial_inp(up, UART_LSR);
1198 (void)serial_inp(up, UART_RX);
1199 (void)serial_inp(up, UART_IIR);
1200 (void)serial_inp(up, UART_MSR);
1201 serial_outp(up, UART_TX, 0xFF);
1202 udelay(20);
1203 irq = probe_irq_off(irqs);
1204
1205 serial_outp(up, UART_MCR, save_mcr);
1206 serial_outp(up, UART_IER, save_ier);
1207
1208 if (up->port.flags & UPF_FOURPORT)
1209 outb_p(save_ICP, ICP);
1210
1211 up->port.irq = (irq > 0) ? irq : 0;
1212 }
1213
1214 static inline void __stop_tx(struct uart_8250_port *p)
1215 {
1216 if (p->ier & UART_IER_THRI) {
1217 p->ier &= ~UART_IER_THRI;
1218 serial_out(p, UART_IER, p->ier);
1219 }
1220 }
1221
1222 static void serial8250_stop_tx(struct uart_port *port)
1223 {
1224 struct uart_8250_port *up = (struct uart_8250_port *)port;
1225
1226 __stop_tx(up);
1227
1228 /*
1229 * We really want to stop the transmitter from sending.
1230 */
1231 if (up->port.type == PORT_16C950) {
1232 up->acr |= UART_ACR_TXDIS;
1233 serial_icr_write(up, UART_ACR, up->acr);
1234 }
1235 }
1236
1237 static void transmit_chars(struct uart_8250_port *up);
1238
1239 static void serial8250_start_tx(struct uart_port *port)
1240 {
1241 struct uart_8250_port *up = (struct uart_8250_port *)port;
1242
1243 if (!(up->ier & UART_IER_THRI)) {
1244 up->ier |= UART_IER_THRI;
1245 serial_out(up, UART_IER, up->ier);
1246
1247 if (up->bugs & UART_BUG_TXEN) {
1248 unsigned char lsr, iir;
1249 lsr = serial_in(up, UART_LSR);
1250 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1251 iir = serial_in(up, UART_IIR) & 0x0f;
1252 if ((up->port.type == PORT_RM9000) ?
1253 (lsr & UART_LSR_THRE &&
1254 (iir == UART_IIR_NO_INT || iir == UART_IIR_THRI)) :
1255 (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT))
1256 transmit_chars(up);
1257 }
1258 }
1259
1260 /*
1261 * Re-enable the transmitter if we disabled it.
1262 */
1263 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1264 up->acr &= ~UART_ACR_TXDIS;
1265 serial_icr_write(up, UART_ACR, up->acr);
1266 }
1267 }
1268
1269 static void serial8250_stop_rx(struct uart_port *port)
1270 {
1271 struct uart_8250_port *up = (struct uart_8250_port *)port;
1272
1273 up->ier &= ~UART_IER_RLSI;
1274 up->port.read_status_mask &= ~UART_LSR_DR;
1275 serial_out(up, UART_IER, up->ier);
1276 }
1277
1278 static void serial8250_enable_ms(struct uart_port *port)
1279 {
1280 struct uart_8250_port *up = (struct uart_8250_port *)port;
1281
1282 /* no MSR capabilities */
1283 if (up->bugs & UART_BUG_NOMSR)
1284 return;
1285
1286 up->ier |= UART_IER_MSI;
1287 serial_out(up, UART_IER, up->ier);
1288 }
1289
1290 static void
1291 receive_chars(struct uart_8250_port *up, unsigned int *status)
1292 {
1293 struct tty_struct *tty = up->port.info->tty;
1294 unsigned char ch, lsr = *status;
1295 int max_count = 256;
1296 char flag;
1297
1298 do {
1299 ch = serial_inp(up, UART_RX);
1300 flag = TTY_NORMAL;
1301 up->port.icount.rx++;
1302
1303 lsr |= up->lsr_saved_flags;
1304 up->lsr_saved_flags = 0;
1305
1306 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1307 /*
1308 * For statistics only
1309 */
1310 if (lsr & UART_LSR_BI) {
1311 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1312 up->port.icount.brk++;
1313 /*
1314 * We do the SysRQ and SAK checking
1315 * here because otherwise the break
1316 * may get masked by ignore_status_mask
1317 * or read_status_mask.
1318 */
1319 if (uart_handle_break(&up->port))
1320 goto ignore_char;
1321 } else if (lsr & UART_LSR_PE)
1322 up->port.icount.parity++;
1323 else if (lsr & UART_LSR_FE)
1324 up->port.icount.frame++;
1325 if (lsr & UART_LSR_OE)
1326 up->port.icount.overrun++;
1327
1328 /*
1329 * Mask off conditions which should be ignored.
1330 */
1331 lsr &= up->port.read_status_mask;
1332
1333 if (lsr & UART_LSR_BI) {
1334 DEBUG_INTR("handling break....");
1335 flag = TTY_BREAK;
1336 } else if (lsr & UART_LSR_PE)
1337 flag = TTY_PARITY;
1338 else if (lsr & UART_LSR_FE)
1339 flag = TTY_FRAME;
1340 }
1341 if (uart_handle_sysrq_char(&up->port, ch))
1342 goto ignore_char;
1343
1344 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1345
1346 ignore_char:
1347 lsr = serial_inp(up, UART_LSR);
1348 } while ((lsr & UART_LSR_DR) && (max_count-- > 0));
1349 spin_unlock(&up->port.lock);
1350 tty_flip_buffer_push(tty);
1351 spin_lock(&up->port.lock);
1352 *status = lsr;
1353 }
1354
1355 static void transmit_chars(struct uart_8250_port *up)
1356 {
1357 struct circ_buf *xmit = &up->port.info->xmit;
1358 int count;
1359
1360 if (up->port.x_char) {
1361 serial_outp(up, UART_TX, up->port.x_char);
1362 up->port.icount.tx++;
1363 up->port.x_char = 0;
1364 return;
1365 }
1366 if (uart_tx_stopped(&up->port)) {
1367 serial8250_stop_tx(&up->port);
1368 return;
1369 }
1370 if (uart_circ_empty(xmit)) {
1371 __stop_tx(up);
1372 return;
1373 }
1374
1375 count = up->tx_loadsz;
1376 do {
1377 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1378 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1379 up->port.icount.tx++;
1380 if (uart_circ_empty(xmit))
1381 break;
1382 } while (--count > 0);
1383
1384 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1385 uart_write_wakeup(&up->port);
1386
1387 DEBUG_INTR("THRE...");
1388
1389 if (uart_circ_empty(xmit))
1390 __stop_tx(up);
1391 }
1392
1393 static unsigned int check_modem_status(struct uart_8250_port *up)
1394 {
1395 unsigned int status = serial_in(up, UART_MSR);
1396
1397 status |= up->msr_saved_flags;
1398 up->msr_saved_flags = 0;
1399 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1400 up->port.info != NULL) {
1401 if (status & UART_MSR_TERI)
1402 up->port.icount.rng++;
1403 if (status & UART_MSR_DDSR)
1404 up->port.icount.dsr++;
1405 if (status & UART_MSR_DDCD)
1406 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1407 if (status & UART_MSR_DCTS)
1408 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1409
1410 wake_up_interruptible(&up->port.info->delta_msr_wait);
1411 }
1412
1413 return status;
1414 }
1415
1416 /*
1417 * This handles the interrupt from one port.
1418 */
1419 static inline void
1420 serial8250_handle_port(struct uart_8250_port *up)
1421 {
1422 unsigned int status;
1423 unsigned long flags;
1424
1425 spin_lock_irqsave(&up->port.lock, flags);
1426
1427 status = serial_inp(up, UART_LSR);
1428
1429 DEBUG_INTR("status = %x...", status);
1430
1431 if (status & UART_LSR_DR)
1432 receive_chars(up, &status);
1433 check_modem_status(up);
1434 if (status & UART_LSR_THRE)
1435 transmit_chars(up);
1436
1437 spin_unlock_irqrestore(&up->port.lock, flags);
1438 }
1439
1440 /*
1441 * This is the serial driver's interrupt routine.
1442 *
1443 * Arjan thinks the old way was overly complex, so it got simplified.
1444 * Alan disagrees, saying that need the complexity to handle the weird
1445 * nature of ISA shared interrupts. (This is a special exception.)
1446 *
1447 * In order to handle ISA shared interrupts properly, we need to check
1448 * that all ports have been serviced, and therefore the ISA interrupt
1449 * line has been de-asserted.
1450 *
1451 * This means we need to loop through all ports. checking that they
1452 * don't have an interrupt pending.
1453 */
1454 static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1455 {
1456 struct irq_info *i = dev_id;
1457 struct list_head *l, *end = NULL;
1458 #ifndef CONFIG_PREEMPT_RT
1459 int pass_counter = 0;
1460 #endif
1461 int handled = 0;
1462
1463 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1464
1465 spin_lock(&i->lock);
1466
1467 l = i->head;
1468 do {
1469 struct uart_8250_port *up;
1470 unsigned int iir;
1471
1472 up = list_entry(l, struct uart_8250_port, list);
1473
1474 iir = serial_in(up, UART_IIR);
1475 if (!(iir & UART_IIR_NO_INT)) {
1476 serial8250_handle_port(up);
1477
1478 handled = 1;
1479
1480 end = NULL;
1481 } else if (up->port.iotype == UPIO_DWAPB &&
1482 (iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
1483 /* The DesignWare APB UART has an Busy Detect (0x07)
1484 * interrupt meaning an LCR write attempt occured while the
1485 * UART was busy. The interrupt must be cleared by reading
1486 * the UART status register (USR) and the LCR re-written. */
1487 unsigned int status;
1488 status = *(volatile u32 *)up->port.private_data;
1489 serial_out(up, UART_LCR, up->lcr);
1490
1491 handled = 1;
1492
1493 end = NULL;
1494 } else if (end == NULL)
1495 end = l;
1496
1497 l = l->next;
1498
1499 /*
1500 * On preempt-rt we can be preempted and run in our
1501 * own thread.
1502 */
1503 #ifndef CONFIG_PREEMPT_RT
1504 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1505 /* If we hit this, we're dead. */
1506 printk(KERN_ERR "serial8250: too much work for "
1507 "irq%d\n", irq);
1508 break;
1509 }
1510 #endif
1511 } while (l != end);
1512
1513 spin_unlock(&i->lock);
1514
1515 DEBUG_INTR("end.\n");
1516
1517 return IRQ_RETVAL(handled);
1518 }
1519
1520 /*
1521 * To support ISA shared interrupts, we need to have one interrupt
1522 * handler that ensures that the IRQ line has been deasserted
1523 * before returning. Failing to do this will result in the IRQ
1524 * line being stuck active, and, since ISA irqs are edge triggered,
1525 * no more IRQs will be seen.
1526 */
1527 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1528 {
1529 spin_lock_irq(&i->lock);
1530
1531 if (!list_empty(i->head)) {
1532 if (i->head == &up->list)
1533 i->head = i->head->next;
1534 list_del(&up->list);
1535 } else {
1536 BUG_ON(i->head != &up->list);
1537 i->head = NULL;
1538 }
1539
1540 spin_unlock_irq(&i->lock);
1541 }
1542
1543 static int serial_link_irq_chain(struct uart_8250_port *up)
1544 {
1545 struct irq_info *i = irq_lists + up->port.irq;
1546 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1547
1548 spin_lock_irq(&i->lock);
1549
1550 if (i->head) {
1551 list_add(&up->list, i->head);
1552 spin_unlock_irq(&i->lock);
1553
1554 ret = 0;
1555 } else {
1556 INIT_LIST_HEAD(&up->list);
1557 i->head = &up->list;
1558 spin_unlock_irq(&i->lock);
1559
1560 ret = request_irq(up->port.irq, serial8250_interrupt,
1561 irq_flags, "serial", i);
1562 if (ret < 0)
1563 serial_do_unlink(i, up);
1564 }
1565
1566 return ret;
1567 }
1568
1569 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1570 {
1571 struct irq_info *i = irq_lists + up->port.irq;
1572
1573 BUG_ON(i->head == NULL);
1574
1575 if (list_empty(i->head))
1576 free_irq(up->port.irq, i);
1577
1578 serial_do_unlink(i, up);
1579 }
1580
1581 /* Base timer interval for polling */
1582 static inline int poll_timeout(int timeout)
1583 {
1584 return timeout > 6 ? (timeout / 2 - 2) : 1;
1585 }
1586
1587 /*
1588 * This function is used to handle ports that do not have an
1589 * interrupt. This doesn't work very well for 16450's, but gives
1590 * barely passable results for a 16550A. (Although at the expense
1591 * of much CPU overhead).
1592 */
1593 static void serial8250_timeout(unsigned long data)
1594 {
1595 struct uart_8250_port *up = (struct uart_8250_port *)data;
1596 unsigned int iir;
1597
1598 iir = serial_in(up, UART_IIR);
1599 if (!(iir & UART_IIR_NO_INT))
1600 serial8250_handle_port(up);
1601 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
1602 }
1603
1604 static void serial8250_backup_timeout(unsigned long data)
1605 {
1606 struct uart_8250_port *up = (struct uart_8250_port *)data;
1607 unsigned int iir, ier = 0, lsr;
1608 unsigned long flags;
1609
1610 /*
1611 * Must disable interrupts or else we risk racing with the interrupt
1612 * based handler.
1613 */
1614 if (is_real_interrupt(up->port.irq)) {
1615 ier = serial_in(up, UART_IER);
1616 serial_out(up, UART_IER, 0);
1617 }
1618
1619 iir = serial_in(up, UART_IIR);
1620
1621 /*
1622 * This should be a safe test for anyone who doesn't trust the
1623 * IIR bits on their UART, but it's specifically designed for
1624 * the "Diva" UART used on the management processor on many HP
1625 * ia64 and parisc boxes.
1626 */
1627 spin_lock_irqsave(&up->port.lock, flags);
1628 lsr = serial_in(up, UART_LSR);
1629 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1630 spin_unlock_irqrestore(&up->port.lock, flags);
1631 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1632 (!uart_circ_empty(&up->port.info->xmit) || up->port.x_char) &&
1633 (lsr & UART_LSR_THRE)) {
1634 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1635 iir |= UART_IIR_THRI;
1636 }
1637
1638 if (!(iir & UART_IIR_NO_INT))
1639 serial8250_handle_port(up);
1640
1641 if (is_real_interrupt(up->port.irq))
1642 serial_out(up, UART_IER, ier);
1643
1644 /* Standard timer interval plus 0.2s to keep the port running */
1645 mod_timer(&up->timer,
1646 jiffies + poll_timeout(up->port.timeout) + HZ / 5);
1647 }
1648
1649 static unsigned int serial8250_tx_empty(struct uart_port *port)
1650 {
1651 struct uart_8250_port *up = (struct uart_8250_port *)port;
1652 unsigned long flags;
1653 unsigned int lsr;
1654
1655 spin_lock_irqsave(&up->port.lock, flags);
1656 lsr = serial_in(up, UART_LSR);
1657 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1658 spin_unlock_irqrestore(&up->port.lock, flags);
1659
1660 return lsr & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
1661 }
1662
1663 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1664 {
1665 struct uart_8250_port *up = (struct uart_8250_port *)port;
1666 unsigned int status;
1667 unsigned int ret;
1668
1669 status = check_modem_status(up);
1670
1671 ret = 0;
1672 if (status & UART_MSR_DCD)
1673 ret |= TIOCM_CAR;
1674 if (status & UART_MSR_RI)
1675 ret |= TIOCM_RNG;
1676 if (status & UART_MSR_DSR)
1677 ret |= TIOCM_DSR;
1678 if (status & UART_MSR_CTS)
1679 ret |= TIOCM_CTS;
1680 return ret;
1681 }
1682
1683 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1684 {
1685 struct uart_8250_port *up = (struct uart_8250_port *)port;
1686 unsigned char mcr = 0;
1687
1688 if (mctrl & TIOCM_RTS)
1689 mcr |= UART_MCR_RTS;
1690 if (mctrl & TIOCM_DTR)
1691 mcr |= UART_MCR_DTR;
1692 if (mctrl & TIOCM_OUT1)
1693 mcr |= UART_MCR_OUT1;
1694 if (mctrl & TIOCM_OUT2)
1695 mcr |= UART_MCR_OUT2;
1696 if (mctrl & TIOCM_LOOP)
1697 mcr |= UART_MCR_LOOP;
1698
1699 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1700
1701 serial_out(up, UART_MCR, mcr);
1702 }
1703
1704 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1705 {
1706 struct uart_8250_port *up = (struct uart_8250_port *)port;
1707 unsigned long flags;
1708
1709 spin_lock_irqsave(&up->port.lock, flags);
1710 if (break_state == -1)
1711 up->lcr |= UART_LCR_SBC;
1712 else
1713 up->lcr &= ~UART_LCR_SBC;
1714 serial_out(up, UART_LCR, up->lcr);
1715 spin_unlock_irqrestore(&up->port.lock, flags);
1716 }
1717
1718 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1719
1720 /*
1721 * Wait for transmitter & holding register to empty
1722 */
1723 static inline void wait_for_xmitr(struct uart_8250_port *up, int bits)
1724 {
1725 unsigned int status, tmout = 10000;
1726
1727 /* Wait up to 10ms for the character(s) to be sent. */
1728 do {
1729 status = serial_in(up, UART_LSR);
1730
1731 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1732
1733 if (--tmout == 0)
1734 break;
1735 udelay(1);
1736 } while ((status & bits) != bits);
1737
1738 /* Wait up to 1s for flow control if necessary */
1739 if (up->port.flags & UPF_CONS_FLOW) {
1740 unsigned int tmout;
1741 for (tmout = 1000000; tmout; tmout--) {
1742 unsigned int msr = serial_in(up, UART_MSR);
1743 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1744 if (msr & UART_MSR_CTS)
1745 break;
1746 udelay(1);
1747 touch_nmi_watchdog();
1748 }
1749 }
1750 }
1751
1752 static int serial8250_startup(struct uart_port *port)
1753 {
1754 struct uart_8250_port *up = (struct uart_8250_port *)port;
1755 unsigned long flags;
1756 unsigned char lsr, iir;
1757 int retval;
1758
1759 up->capabilities = uart_config[up->port.type].flags;
1760 up->mcr = 0;
1761
1762 if (up->port.type == PORT_16C950) {
1763 /* Wake up and initialize UART */
1764 up->acr = 0;
1765 serial_outp(up, UART_LCR, 0xBF);
1766 serial_outp(up, UART_EFR, UART_EFR_ECB);
1767 serial_outp(up, UART_IER, 0);
1768 serial_outp(up, UART_LCR, 0);
1769 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1770 serial_outp(up, UART_LCR, 0xBF);
1771 serial_outp(up, UART_EFR, UART_EFR_ECB);
1772 serial_outp(up, UART_LCR, 0);
1773 }
1774
1775 #ifdef CONFIG_SERIAL_8250_RSA
1776 /*
1777 * If this is an RSA port, see if we can kick it up to the
1778 * higher speed clock.
1779 */
1780 enable_rsa(up);
1781 #endif
1782
1783 /*
1784 * Clear the FIFO buffers and disable them.
1785 * (they will be reenabled in set_termios())
1786 */
1787 serial8250_clear_fifos(up);
1788
1789 /*
1790 * Clear the interrupt registers.
1791 */
1792 (void) serial_inp(up, UART_LSR);
1793 (void) serial_inp(up, UART_RX);
1794 (void) serial_inp(up, UART_IIR);
1795 (void) serial_inp(up, UART_MSR);
1796
1797 /*
1798 * At this point, there's no way the LSR could still be 0xff;
1799 * if it is, then bail out, because there's likely no UART
1800 * here.
1801 */
1802 if (!(up->port.flags & UPF_BUGGY_UART) &&
1803 (serial_inp(up, UART_LSR) == 0xff)) {
1804 printk("ttyS%d: LSR safety check engaged!\n", up->port.line);
1805 return -ENODEV;
1806 }
1807
1808 /*
1809 * For a XR16C850, we need to set the trigger levels
1810 */
1811 if (up->port.type == PORT_16850) {
1812 unsigned char fctr;
1813
1814 serial_outp(up, UART_LCR, 0xbf);
1815
1816 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
1817 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1818 serial_outp(up, UART_TRG, UART_TRG_96);
1819 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1820 serial_outp(up, UART_TRG, UART_TRG_96);
1821
1822 serial_outp(up, UART_LCR, 0);
1823 }
1824
1825 if (is_real_interrupt(up->port.irq)) {
1826 /*
1827 * Test for UARTs that do not reassert THRE when the
1828 * transmitter is idle and the interrupt has already
1829 * been cleared. Real 16550s should always reassert
1830 * this interrupt whenever the transmitter is idle and
1831 * the interrupt is enabled. Delays are necessary to
1832 * allow register changes to become visible.
1833 */
1834 spin_lock_irqsave(&up->port.lock, flags);
1835
1836 wait_for_xmitr(up, UART_LSR_THRE);
1837 serial_out_sync(up, UART_IER, UART_IER_THRI);
1838 udelay(1); /* allow THRE to set */
1839 serial_in(up, UART_IIR);
1840 serial_out(up, UART_IER, 0);
1841 serial_out_sync(up, UART_IER, UART_IER_THRI);
1842 udelay(1); /* allow a working UART time to re-assert THRE */
1843 iir = serial_in(up, UART_IIR);
1844 serial_out(up, UART_IER, 0);
1845
1846 spin_unlock_irqrestore(&up->port.lock, flags);
1847
1848 /*
1849 * If the interrupt is not reasserted, setup a timer to
1850 * kick the UART on a regular basis.
1851 */
1852 if (iir & UART_IIR_NO_INT) {
1853 pr_debug("ttyS%d - using backup timer\n", port->line);
1854 up->timer.function = serial8250_backup_timeout;
1855 up->timer.data = (unsigned long)up;
1856 mod_timer(&up->timer, jiffies +
1857 poll_timeout(up->port.timeout) + HZ / 5);
1858 }
1859 }
1860
1861 /*
1862 * If the "interrupt" for this port doesn't correspond with any
1863 * hardware interrupt, we use a timer-based system. The original
1864 * driver used to do this with IRQ0.
1865 */
1866 if (!is_real_interrupt(up->port.irq)) {
1867 up->timer.data = (unsigned long)up;
1868 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
1869 } else {
1870 retval = serial_link_irq_chain(up);
1871 if (retval)
1872 return retval;
1873 }
1874
1875 /*
1876 * Now, initialize the UART
1877 */
1878 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
1879
1880 spin_lock_irqsave(&up->port.lock, flags);
1881 if (up->port.flags & UPF_FOURPORT) {
1882 if (!is_real_interrupt(up->port.irq))
1883 up->port.mctrl |= TIOCM_OUT1;
1884 } else
1885 /*
1886 * Most PC uarts need OUT2 raised to enable interrupts.
1887 */
1888 if (is_real_interrupt(up->port.irq))
1889 up->port.mctrl |= TIOCM_OUT2;
1890
1891 serial8250_set_mctrl(&up->port, up->port.mctrl);
1892
1893 /*
1894 * Do a quick test to see if we receive an
1895 * interrupt when we enable the TX irq.
1896 */
1897 serial_outp(up, UART_IER, UART_IER_THRI);
1898 lsr = serial_in(up, UART_LSR);
1899 iir = serial_in(up, UART_IIR);
1900 serial_outp(up, UART_IER, 0);
1901
1902 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
1903 if (!(up->bugs & UART_BUG_TXEN)) {
1904 up->bugs |= UART_BUG_TXEN;
1905 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
1906 port->line);
1907 }
1908 } else {
1909 up->bugs &= ~UART_BUG_TXEN;
1910 }
1911
1912 spin_unlock_irqrestore(&up->port.lock, flags);
1913
1914 /*
1915 * Clear the interrupt registers again for luck, and clear the
1916 * saved flags to avoid getting false values from polling
1917 * routines or the previous session.
1918 */
1919 serial_inp(up, UART_LSR);
1920 serial_inp(up, UART_RX);
1921 serial_inp(up, UART_IIR);
1922 serial_inp(up, UART_MSR);
1923 up->lsr_saved_flags = 0;
1924 up->msr_saved_flags = 0;
1925
1926 /*
1927 * Finally, enable interrupts. Note: Modem status interrupts
1928 * are set via set_termios(), which will be occurring imminently
1929 * anyway, so we don't enable them here.
1930 */
1931 up->ier = UART_IER_RLSI | UART_IER_RDI;
1932 serial_outp(up, UART_IER, up->ier);
1933
1934 if (up->port.flags & UPF_FOURPORT) {
1935 unsigned int icp;
1936 /*
1937 * Enable interrupts on the AST Fourport board
1938 */
1939 icp = (up->port.iobase & 0xfe0) | 0x01f;
1940 outb_p(0x80, icp);
1941 (void) inb_p(icp);
1942 }
1943
1944 return 0;
1945 }
1946
1947 static void serial8250_shutdown(struct uart_port *port)
1948 {
1949 struct uart_8250_port *up = (struct uart_8250_port *)port;
1950 unsigned long flags;
1951
1952 /*
1953 * Disable interrupts from this port
1954 */
1955 up->ier = 0;
1956 serial_outp(up, UART_IER, 0);
1957
1958 spin_lock_irqsave(&up->port.lock, flags);
1959 if (up->port.flags & UPF_FOURPORT) {
1960 /* reset interrupts on the AST Fourport board */
1961 inb((up->port.iobase & 0xfe0) | 0x1f);
1962 up->port.mctrl |= TIOCM_OUT1;
1963 } else
1964 up->port.mctrl &= ~TIOCM_OUT2;
1965
1966 serial8250_set_mctrl(&up->port, up->port.mctrl);
1967 spin_unlock_irqrestore(&up->port.lock, flags);
1968
1969 /*
1970 * Disable break condition and FIFOs
1971 */
1972 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
1973 serial8250_clear_fifos(up);
1974
1975 #ifdef CONFIG_SERIAL_8250_RSA
1976 /*
1977 * Reset the RSA board back to 115kbps compat mode.
1978 */
1979 disable_rsa(up);
1980 #endif
1981
1982 /*
1983 * Read data port to reset things, and then unlink from
1984 * the IRQ chain.
1985 */
1986 (void) serial_in(up, UART_RX);
1987
1988 del_timer_sync(&up->timer);
1989 up->timer.function = serial8250_timeout;
1990 if (is_real_interrupt(up->port.irq))
1991 serial_unlink_irq_chain(up);
1992 }
1993
1994 static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
1995 {
1996 unsigned int quot;
1997
1998 /*
1999 * Handle magic divisors for baud rates above baud_base on
2000 * SMSC SuperIO chips.
2001 */
2002 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2003 baud == (port->uartclk/4))
2004 quot = 0x8001;
2005 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2006 baud == (port->uartclk/8))
2007 quot = 0x8002;
2008 else
2009 quot = uart_get_divisor(port, baud);
2010
2011 return quot;
2012 }
2013
2014 static void
2015 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2016 struct ktermios *old)
2017 {
2018 struct uart_8250_port *up = (struct uart_8250_port *)port;
2019 unsigned char cval, fcr = 0;
2020 unsigned long flags;
2021 unsigned int baud, quot;
2022
2023 switch (termios->c_cflag & CSIZE) {
2024 case CS5:
2025 cval = UART_LCR_WLEN5;
2026 break;
2027 case CS6:
2028 cval = UART_LCR_WLEN6;
2029 break;
2030 case CS7:
2031 cval = UART_LCR_WLEN7;
2032 break;
2033 default:
2034 case CS8:
2035 cval = UART_LCR_WLEN8;
2036 break;
2037 }
2038
2039 if (termios->c_cflag & CSTOPB)
2040 cval |= UART_LCR_STOP;
2041 if (termios->c_cflag & PARENB)
2042 cval |= UART_LCR_PARITY;
2043 if (!(termios->c_cflag & PARODD))
2044 cval |= UART_LCR_EPAR;
2045 #ifdef CMSPAR
2046 if (termios->c_cflag & CMSPAR)
2047 cval |= UART_LCR_SPAR;
2048 #endif
2049
2050 /*
2051 * Ask the core to calculate the divisor for us.
2052 */
2053 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
2054 quot = serial8250_get_divisor(port, baud);
2055
2056 /*
2057 * Oxford Semi 952 rev B workaround
2058 */
2059 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2060 quot++;
2061
2062 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2063 if (baud < 2400)
2064 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2065 else
2066 fcr = uart_config[up->port.type].fcr;
2067 }
2068
2069 /*
2070 * MCR-based auto flow control. When AFE is enabled, RTS will be
2071 * deasserted when the receive FIFO contains more characters than
2072 * the trigger, or the MCR RTS bit is cleared. In the case where
2073 * the remote UART is not using CTS auto flow control, we must
2074 * have sufficient FIFO entries for the latency of the remote
2075 * UART to respond. IOW, at least 32 bytes of FIFO.
2076 */
2077 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2078 up->mcr &= ~UART_MCR_AFE;
2079 if (termios->c_cflag & CRTSCTS)
2080 up->mcr |= UART_MCR_AFE;
2081 }
2082
2083 /*
2084 * Ok, we're now changing the port state. Do it with
2085 * interrupts disabled.
2086 */
2087 spin_lock_irqsave(&up->port.lock, flags);
2088
2089 /*
2090 * Update the per-port timeout.
2091 */
2092 uart_update_timeout(port, termios->c_cflag, baud);
2093
2094 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2095 if (termios->c_iflag & INPCK)
2096 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2097 if (termios->c_iflag & (BRKINT | PARMRK))
2098 up->port.read_status_mask |= UART_LSR_BI;
2099
2100 /*
2101 * Characteres to ignore
2102 */
2103 up->port.ignore_status_mask = 0;
2104 if (termios->c_iflag & IGNPAR)
2105 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2106 if (termios->c_iflag & IGNBRK) {
2107 up->port.ignore_status_mask |= UART_LSR_BI;
2108 /*
2109 * If we're ignoring parity and break indicators,
2110 * ignore overruns too (for real raw support).
2111 */
2112 if (termios->c_iflag & IGNPAR)
2113 up->port.ignore_status_mask |= UART_LSR_OE;
2114 }
2115
2116 /*
2117 * ignore all characters if CREAD is not set
2118 */
2119 if ((termios->c_cflag & CREAD) == 0)
2120 up->port.ignore_status_mask |= UART_LSR_DR;
2121
2122 /*
2123 * CTS flow control flag and modem status interrupts
2124 */
2125 up->ier &= ~UART_IER_MSI;
2126 if (!(up->bugs & UART_BUG_NOMSR) &&
2127 UART_ENABLE_MS(&up->port, termios->c_cflag))
2128 up->ier |= UART_IER_MSI;
2129 if (up->capabilities & UART_CAP_UUE)
2130 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
2131
2132 serial_out(up, UART_IER, up->ier);
2133
2134 if (up->capabilities & UART_CAP_EFR) {
2135 unsigned char efr = 0;
2136 /*
2137 * TI16C752/Startech hardware flow control. FIXME:
2138 * - TI16C752 requires control thresholds to be set.
2139 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2140 */
2141 if (termios->c_cflag & CRTSCTS)
2142 efr |= UART_EFR_CTS;
2143
2144 serial_outp(up, UART_LCR, 0xBF);
2145 serial_outp(up, UART_EFR, efr);
2146 }
2147
2148 #ifdef CONFIG_ARCH_OMAP15XX
2149 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2150 if (cpu_is_omap1510() && is_omap_port((unsigned int)up->port.membase)) {
2151 if (baud == 115200) {
2152 quot = 1;
2153 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2154 } else
2155 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2156 }
2157 #endif
2158
2159 if (up->capabilities & UART_NATSEMI) {
2160 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2161 serial_outp(up, UART_LCR, 0xe0);
2162 } else {
2163 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2164 }
2165
2166 serial_dl_write(up, quot);
2167
2168 /*
2169 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2170 * is written without DLAB set, this mode will be disabled.
2171 */
2172 if (up->port.type == PORT_16750)
2173 serial_outp(up, UART_FCR, fcr);
2174
2175 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2176 up->lcr = cval; /* Save LCR */
2177 if (up->port.type != PORT_16750) {
2178 if (fcr & UART_FCR_ENABLE_FIFO) {
2179 /* emulated UARTs (Lucent Venus 167x) need two steps */
2180 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2181 }
2182 serial_outp(up, UART_FCR, fcr); /* set fcr */
2183 }
2184 serial8250_set_mctrl(&up->port, up->port.mctrl);
2185 spin_unlock_irqrestore(&up->port.lock, flags);
2186 /* Don't rewrite B0 */
2187 if (tty_termios_baud_rate(termios))
2188 tty_termios_encode_baud_rate(termios, baud, baud);
2189 }
2190
2191 static void
2192 serial8250_pm(struct uart_port *port, unsigned int state,
2193 unsigned int oldstate)
2194 {
2195 struct uart_8250_port *p = (struct uart_8250_port *)port;
2196
2197 serial8250_set_sleep(p, state != 0);
2198
2199 if (p->pm)
2200 p->pm(port, state, oldstate);
2201 }
2202
2203 /*
2204 * Resource handling.
2205 */
2206 static int serial8250_request_std_resource(struct uart_8250_port *up)
2207 {
2208 unsigned int size = 8 << up->port.regshift;
2209 int ret = 0;
2210
2211 switch (up->port.iotype) {
2212 case UPIO_AU:
2213 size = 0x100000;
2214 /* fall thru */
2215 case UPIO_TSI:
2216 case UPIO_MEM32:
2217 case UPIO_MEM:
2218 case UPIO_DWAPB:
2219 if (!up->port.mapbase)
2220 break;
2221
2222 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2223 ret = -EBUSY;
2224 break;
2225 }
2226
2227 if (up->port.flags & UPF_IOREMAP) {
2228 up->port.membase = ioremap(up->port.mapbase, size);
2229 if (!up->port.membase) {
2230 release_mem_region(up->port.mapbase, size);
2231 ret = -ENOMEM;
2232 }
2233 }
2234 break;
2235
2236 case UPIO_HUB6:
2237 case UPIO_PORT:
2238 if (!request_region(up->port.iobase, size, "serial"))
2239 ret = -EBUSY;
2240 break;
2241 }
2242 return ret;
2243 }
2244
2245 static void serial8250_release_std_resource(struct uart_8250_port *up)
2246 {
2247 unsigned int size = 8 << up->port.regshift;
2248
2249 switch (up->port.iotype) {
2250 case UPIO_AU:
2251 size = 0x100000;
2252 /* fall thru */
2253 case UPIO_TSI:
2254 case UPIO_MEM32:
2255 case UPIO_MEM:
2256 case UPIO_DWAPB:
2257 if (!up->port.mapbase)
2258 break;
2259
2260 if (up->port.flags & UPF_IOREMAP) {
2261 iounmap(up->port.membase);
2262 up->port.membase = NULL;
2263 }
2264
2265 release_mem_region(up->port.mapbase, size);
2266 break;
2267
2268 case UPIO_HUB6:
2269 case UPIO_PORT:
2270 release_region(up->port.iobase, size);
2271 break;
2272 }
2273 }
2274
2275 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2276 {
2277 unsigned long start = UART_RSA_BASE << up->port.regshift;
2278 unsigned int size = 8 << up->port.regshift;
2279 int ret = -EINVAL;
2280
2281 switch (up->port.iotype) {
2282 case UPIO_HUB6:
2283 case UPIO_PORT:
2284 start += up->port.iobase;
2285 if (request_region(start, size, "serial-rsa"))
2286 ret = 0;
2287 else
2288 ret = -EBUSY;
2289 break;
2290 }
2291
2292 return ret;
2293 }
2294
2295 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2296 {
2297 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2298 unsigned int size = 8 << up->port.regshift;
2299
2300 switch (up->port.iotype) {
2301 case UPIO_HUB6:
2302 case UPIO_PORT:
2303 release_region(up->port.iobase + offset, size);
2304 break;
2305 }
2306 }
2307
2308 static void serial8250_release_port(struct uart_port *port)
2309 {
2310 struct uart_8250_port *up = (struct uart_8250_port *)port;
2311
2312 serial8250_release_std_resource(up);
2313 if (up->port.type == PORT_RSA)
2314 serial8250_release_rsa_resource(up);
2315 }
2316
2317 static int serial8250_request_port(struct uart_port *port)
2318 {
2319 struct uart_8250_port *up = (struct uart_8250_port *)port;
2320 int ret = 0;
2321
2322 ret = serial8250_request_std_resource(up);
2323 if (ret == 0 && up->port.type == PORT_RSA) {
2324 ret = serial8250_request_rsa_resource(up);
2325 if (ret < 0)
2326 serial8250_release_std_resource(up);
2327 }
2328
2329 return ret;
2330 }
2331
2332 static void serial8250_config_port(struct uart_port *port, int flags)
2333 {
2334 struct uart_8250_port *up = (struct uart_8250_port *)port;
2335 int probeflags = PROBE_ANY;
2336 int ret;
2337
2338 /*
2339 * Find the region that we can probe for. This in turn
2340 * tells us whether we can probe for the type of port.
2341 */
2342 ret = serial8250_request_std_resource(up);
2343 if (ret < 0)
2344 return;
2345
2346 ret = serial8250_request_rsa_resource(up);
2347 if (ret < 0)
2348 probeflags &= ~PROBE_RSA;
2349
2350 if (flags & UART_CONFIG_TYPE)
2351 autoconfig(up, probeflags);
2352 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2353 autoconfig_irq(up);
2354
2355 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2356 serial8250_release_rsa_resource(up);
2357 if (up->port.type == PORT_UNKNOWN)
2358 serial8250_release_std_resource(up);
2359 }
2360
2361 static int
2362 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2363 {
2364 if (ser->irq >= NR_IRQS || ser->irq < 0 ||
2365 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2366 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2367 ser->type == PORT_STARTECH)
2368 return -EINVAL;
2369 return 0;
2370 }
2371
2372 static const char *
2373 serial8250_type(struct uart_port *port)
2374 {
2375 int type = port->type;
2376
2377 if (type >= ARRAY_SIZE(uart_config))
2378 type = 0;
2379 return uart_config[type].name;
2380 }
2381
2382 static struct uart_ops serial8250_pops = {
2383 .tx_empty = serial8250_tx_empty,
2384 .set_mctrl = serial8250_set_mctrl,
2385 .get_mctrl = serial8250_get_mctrl,
2386 .stop_tx = serial8250_stop_tx,
2387 .start_tx = serial8250_start_tx,
2388 .stop_rx = serial8250_stop_rx,
2389 .enable_ms = serial8250_enable_ms,
2390 .break_ctl = serial8250_break_ctl,
2391 .startup = serial8250_startup,
2392 .shutdown = serial8250_shutdown,
2393 .set_termios = serial8250_set_termios,
2394 .pm = serial8250_pm,
2395 .type = serial8250_type,
2396 .release_port = serial8250_release_port,
2397 .request_port = serial8250_request_port,
2398 .config_port = serial8250_config_port,
2399 .verify_port = serial8250_verify_port,
2400 };
2401
2402 static struct uart_8250_port serial8250_ports[UART_NR];
2403
2404 static void __init serial8250_isa_init_ports(void)
2405 {
2406 struct uart_8250_port *up;
2407 static int first = 1;
2408 int i;
2409
2410 if (!first)
2411 return;
2412 first = 0;
2413
2414 for (i = 0; i < nr_uarts; i++) {
2415 struct uart_8250_port *up = &serial8250_ports[i];
2416
2417 up->port.line = i;
2418 spin_lock_init(&up->port.lock);
2419
2420 init_timer(&up->timer);
2421 up->timer.function = serial8250_timeout;
2422
2423 /*
2424 * ALPHA_KLUDGE_MCR needs to be killed.
2425 */
2426 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2427 up->mcr_force = ALPHA_KLUDGE_MCR;
2428
2429 up->port.ops = &serial8250_pops;
2430 }
2431
2432 for (i = 0, up = serial8250_ports;
2433 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2434 i++, up++) {
2435 up->port.iobase = old_serial_port[i].port;
2436 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2437 up->port.uartclk = old_serial_port[i].baud_base * 16;
2438 up->port.flags = old_serial_port[i].flags;
2439 up->port.hub6 = old_serial_port[i].hub6;
2440 up->port.membase = old_serial_port[i].iomem_base;
2441 up->port.iotype = old_serial_port[i].io_type;
2442 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2443 if (share_irqs)
2444 up->port.flags |= UPF_SHARE_IRQ;
2445 }
2446 }
2447
2448 static void __init
2449 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2450 {
2451 int i;
2452
2453 serial8250_isa_init_ports();
2454
2455 for (i = 0; i < nr_uarts; i++) {
2456 struct uart_8250_port *up = &serial8250_ports[i];
2457
2458 up->port.dev = dev;
2459 uart_add_one_port(drv, &up->port);
2460 }
2461 }
2462
2463 #ifdef CONFIG_SERIAL_8250_CONSOLE
2464
2465 static void serial8250_console_putchar(struct uart_port *port, int ch)
2466 {
2467 struct uart_8250_port *up = (struct uart_8250_port *)port;
2468
2469 wait_for_xmitr(up, UART_LSR_THRE);
2470 serial_out(up, UART_TX, ch);
2471 }
2472
2473 /*
2474 * Print a string to the serial port trying not to disturb
2475 * any possible real use of the port...
2476 *
2477 * The console_lock must be held when we get here.
2478 */
2479 static void
2480 serial8250_console_write(struct console *co, const char *s, unsigned int count)
2481 {
2482 struct uart_8250_port *up = &serial8250_ports[co->index];
2483 unsigned long flags;
2484 unsigned int ier;
2485 int locked = 1;
2486
2487 touch_nmi_watchdog();
2488
2489 if (up->port.sysrq || oops_in_progress)
2490 locked = spin_trylock_irqsave(&up->port.lock, flags);
2491 else
2492 spin_lock_irqsave(&up->port.lock, flags);
2493
2494 /*
2495 * First save the IER then disable the interrupts
2496 */
2497 ier = serial_in(up, UART_IER);
2498
2499 if (up->capabilities & UART_CAP_UUE)
2500 serial_out(up, UART_IER, UART_IER_UUE);
2501 else
2502 serial_out(up, UART_IER, 0);
2503
2504 uart_console_write(&up->port, s, count, serial8250_console_putchar);
2505
2506 /*
2507 * Finally, wait for transmitter to become empty
2508 * and restore the IER
2509 */
2510 wait_for_xmitr(up, BOTH_EMPTY);
2511 serial_out(up, UART_IER, ier);
2512
2513 /*
2514 * The receive handling will happen properly because the
2515 * receive ready bit will still be set; it is not cleared
2516 * on read. However, modem control will not, we must
2517 * call it if we have saved something in the saved flags
2518 * while processing with interrupts off.
2519 */
2520 if (up->msr_saved_flags)
2521 check_modem_status(up);
2522
2523 if (locked)
2524 spin_unlock_irqrestore(&up->port.lock, flags);
2525 }
2526
2527 static int __init serial8250_console_setup(struct console *co, char *options)
2528 {
2529 struct uart_port *port;
2530 int baud = 9600;
2531 int bits = 8;
2532 int parity = 'n';
2533 int flow = 'n';
2534
2535 /*
2536 * Check whether an invalid uart number has been specified, and
2537 * if so, search for the first available port that does have
2538 * console support.
2539 */
2540 if (co->index >= nr_uarts)
2541 co->index = 0;
2542 port = &serial8250_ports[co->index].port;
2543 if (!port->iobase && !port->membase)
2544 return -ENODEV;
2545
2546 if (options)
2547 uart_parse_options(options, &baud, &parity, &bits, &flow);
2548
2549 return uart_set_options(port, co, baud, parity, bits, flow);
2550 }
2551
2552 static int serial8250_console_early_setup(void)
2553 {
2554 return serial8250_find_port_for_earlycon();
2555 }
2556
2557 static struct uart_driver serial8250_reg;
2558 static struct console serial8250_console = {
2559 .name = "ttyS",
2560 .write = serial8250_console_write,
2561 .device = uart_console_device,
2562 .setup = serial8250_console_setup,
2563 .early_setup = serial8250_console_early_setup,
2564 .flags = CON_PRINTBUFFER,
2565 .index = -1,
2566 .data = &serial8250_reg,
2567 };
2568
2569 static int __init serial8250_console_init(void)
2570 {
2571 serial8250_isa_init_ports();
2572 register_console(&serial8250_console);
2573 return 0;
2574 }
2575 console_initcall(serial8250_console_init);
2576
2577 int serial8250_find_port(struct uart_port *p)
2578 {
2579 int line;
2580 struct uart_port *port;
2581
2582 for (line = 0; line < nr_uarts; line++) {
2583 port = &serial8250_ports[line].port;
2584 if (uart_match_port(p, port))
2585 return line;
2586 }
2587 return -ENODEV;
2588 }
2589
2590 #define SERIAL8250_CONSOLE &serial8250_console
2591 #else
2592 #define SERIAL8250_CONSOLE NULL
2593 #endif
2594
2595 static struct uart_driver serial8250_reg = {
2596 .owner = THIS_MODULE,
2597 .driver_name = "serial",
2598 .dev_name = "ttyS",
2599 .major = TTY_MAJOR,
2600 .minor = 64,
2601 .nr = UART_NR,
2602 .cons = SERIAL8250_CONSOLE,
2603 };
2604
2605 /*
2606 * early_serial_setup - early registration for 8250 ports
2607 *
2608 * Setup an 8250 port structure prior to console initialisation. Use
2609 * after console initialisation will cause undefined behaviour.
2610 */
2611 int __init early_serial_setup(struct uart_port *port)
2612 {
2613 if (port->line >= ARRAY_SIZE(serial8250_ports))
2614 return -ENODEV;
2615
2616 serial8250_isa_init_ports();
2617 serial8250_ports[port->line].port = *port;
2618 serial8250_ports[port->line].port.ops = &serial8250_pops;
2619 return 0;
2620 }
2621
2622 /**
2623 * serial8250_suspend_port - suspend one serial port
2624 * @line: serial line number
2625 *
2626 * Suspend one serial port.
2627 */
2628 void serial8250_suspend_port(int line)
2629 {
2630 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2631 }
2632
2633 /**
2634 * serial8250_resume_port - resume one serial port
2635 * @line: serial line number
2636 *
2637 * Resume one serial port.
2638 */
2639 void serial8250_resume_port(int line)
2640 {
2641 struct uart_8250_port *up = &serial8250_ports[line];
2642
2643 if (up->capabilities & UART_NATSEMI) {
2644 unsigned char tmp;
2645
2646 /* Ensure it's still in high speed mode */
2647 serial_outp(up, UART_LCR, 0xE0);
2648
2649 tmp = serial_in(up, 0x04); /* EXCR2 */
2650 tmp &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
2651 tmp |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
2652 serial_outp(up, 0x04, tmp);
2653
2654 serial_outp(up, UART_LCR, 0);
2655 }
2656 uart_resume_port(&serial8250_reg, &up->port);
2657 }
2658
2659 /*
2660 * Register a set of serial devices attached to a platform device. The
2661 * list is terminated with a zero flags entry, which means we expect
2662 * all entries to have at least UPF_BOOT_AUTOCONF set.
2663 */
2664 static int __devinit serial8250_probe(struct platform_device *dev)
2665 {
2666 struct plat_serial8250_port *p = dev->dev.platform_data;
2667 struct uart_port port;
2668 int ret, i;
2669
2670 memset(&port, 0, sizeof(struct uart_port));
2671
2672 for (i = 0; p && p->flags != 0; p++, i++) {
2673 port.iobase = p->iobase;
2674 port.membase = p->membase;
2675 port.irq = p->irq;
2676 port.uartclk = p->uartclk;
2677 port.regshift = p->regshift;
2678 port.iotype = p->iotype;
2679 port.flags = p->flags;
2680 port.mapbase = p->mapbase;
2681 port.hub6 = p->hub6;
2682 port.private_data = p->private_data;
2683 port.dev = &dev->dev;
2684 if (share_irqs)
2685 port.flags |= UPF_SHARE_IRQ;
2686 ret = serial8250_register_port(&port);
2687 if (ret < 0) {
2688 dev_err(&dev->dev, "unable to register port at index %d "
2689 "(IO%lx MEM%llx IRQ%d): %d\n", i,
2690 p->iobase, (unsigned long long)p->mapbase,
2691 p->irq, ret);
2692 }
2693 }
2694 return 0;
2695 }
2696
2697 /*
2698 * Remove serial ports registered against a platform device.
2699 */
2700 static int __devexit serial8250_remove(struct platform_device *dev)
2701 {
2702 int i;
2703
2704 for (i = 0; i < nr_uarts; i++) {
2705 struct uart_8250_port *up = &serial8250_ports[i];
2706
2707 if (up->port.dev == &dev->dev)
2708 serial8250_unregister_port(i);
2709 }
2710 return 0;
2711 }
2712
2713 static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
2714 {
2715 int i;
2716
2717 for (i = 0; i < UART_NR; i++) {
2718 struct uart_8250_port *up = &serial8250_ports[i];
2719
2720 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
2721 uart_suspend_port(&serial8250_reg, &up->port);
2722 }
2723
2724 return 0;
2725 }
2726
2727 static int serial8250_resume(struct platform_device *dev)
2728 {
2729 int i;
2730
2731 for (i = 0; i < UART_NR; i++) {
2732 struct uart_8250_port *up = &serial8250_ports[i];
2733
2734 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
2735 serial8250_resume_port(i);
2736 }
2737
2738 return 0;
2739 }
2740
2741 static struct platform_driver serial8250_isa_driver = {
2742 .probe = serial8250_probe,
2743 .remove = __devexit_p(serial8250_remove),
2744 .suspend = serial8250_suspend,
2745 .resume = serial8250_resume,
2746 .driver = {
2747 .name = "serial8250",
2748 .owner = THIS_MODULE,
2749 },
2750 };
2751
2752 /*
2753 * This "device" covers _all_ ISA 8250-compatible serial devices listed
2754 * in the table in include/asm/serial.h
2755 */
2756 static struct platform_device *serial8250_isa_devs;
2757
2758 /*
2759 * serial8250_register_port and serial8250_unregister_port allows for
2760 * 16x50 serial ports to be configured at run-time, to support PCMCIA
2761 * modems and PCI multiport cards.
2762 */
2763 static DEFINE_MUTEX(serial_mutex);
2764
2765 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
2766 {
2767 int i;
2768
2769 /*
2770 * First, find a port entry which matches.
2771 */
2772 for (i = 0; i < nr_uarts; i++)
2773 if (uart_match_port(&serial8250_ports[i].port, port))
2774 return &serial8250_ports[i];
2775
2776 /*
2777 * We didn't find a matching entry, so look for the first
2778 * free entry. We look for one which hasn't been previously
2779 * used (indicated by zero iobase).
2780 */
2781 for (i = 0; i < nr_uarts; i++)
2782 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
2783 serial8250_ports[i].port.iobase == 0)
2784 return &serial8250_ports[i];
2785
2786 /*
2787 * That also failed. Last resort is to find any entry which
2788 * doesn't have a real port associated with it.
2789 */
2790 for (i = 0; i < nr_uarts; i++)
2791 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
2792 return &serial8250_ports[i];
2793
2794 return NULL;
2795 }
2796
2797 /**
2798 * serial8250_register_port - register a serial port
2799 * @port: serial port template
2800 *
2801 * Configure the serial port specified by the request. If the
2802 * port exists and is in use, it is hung up and unregistered
2803 * first.
2804 *
2805 * The port is then probed and if necessary the IRQ is autodetected
2806 * If this fails an error is returned.
2807 *
2808 * On success the port is ready to use and the line number is returned.
2809 */
2810 int serial8250_register_port(struct uart_port *port)
2811 {
2812 struct uart_8250_port *uart;
2813 int ret = -ENOSPC;
2814
2815 if (port->uartclk == 0)
2816 return -EINVAL;
2817
2818 mutex_lock(&serial_mutex);
2819
2820 uart = serial8250_find_match_or_unused(port);
2821 if (uart) {
2822 uart_remove_one_port(&serial8250_reg, &uart->port);
2823
2824 uart->port.iobase = port->iobase;
2825 uart->port.membase = port->membase;
2826 uart->port.irq = port->irq;
2827 uart->port.uartclk = port->uartclk;
2828 uart->port.fifosize = port->fifosize;
2829 uart->port.regshift = port->regshift;
2830 uart->port.iotype = port->iotype;
2831 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
2832 uart->port.mapbase = port->mapbase;
2833 uart->port.private_data = port->private_data;
2834 if (port->dev)
2835 uart->port.dev = port->dev;
2836
2837 ret = uart_add_one_port(&serial8250_reg, &uart->port);
2838 if (ret == 0)
2839 ret = uart->port.line;
2840 }
2841 mutex_unlock(&serial_mutex);
2842
2843 return ret;
2844 }
2845 EXPORT_SYMBOL(serial8250_register_port);
2846
2847 /**
2848 * serial8250_unregister_port - remove a 16x50 serial port at runtime
2849 * @line: serial line number
2850 *
2851 * Remove one serial port. This may not be called from interrupt
2852 * context. We hand the port back to the our control.
2853 */
2854 void serial8250_unregister_port(int line)
2855 {
2856 struct uart_8250_port *uart = &serial8250_ports[line];
2857
2858 mutex_lock(&serial_mutex);
2859 uart_remove_one_port(&serial8250_reg, &uart->port);
2860 if (serial8250_isa_devs) {
2861 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
2862 uart->port.type = PORT_UNKNOWN;
2863 uart->port.dev = &serial8250_isa_devs->dev;
2864 uart_add_one_port(&serial8250_reg, &uart->port);
2865 } else {
2866 uart->port.dev = NULL;
2867 }
2868 mutex_unlock(&serial_mutex);
2869 }
2870 EXPORT_SYMBOL(serial8250_unregister_port);
2871
2872 static int __init serial8250_init(void)
2873 {
2874 int ret, i;
2875
2876 if (nr_uarts > UART_NR)
2877 nr_uarts = UART_NR;
2878
2879 printk(KERN_INFO "Serial: 8250/16550 driver $Revision: 1.90 $ "
2880 "%d ports, IRQ sharing %sabled\n", nr_uarts,
2881 share_irqs ? "en" : "dis");
2882
2883 for (i = 0; i < NR_IRQS; i++)
2884 spin_lock_init(&irq_lists[i].lock);
2885
2886 ret = uart_register_driver(&serial8250_reg);
2887 if (ret)
2888 goto out;
2889
2890 serial8250_isa_devs = platform_device_alloc("serial8250",
2891 PLAT8250_DEV_LEGACY);
2892 if (!serial8250_isa_devs) {
2893 ret = -ENOMEM;
2894 goto unreg_uart_drv;
2895 }
2896
2897 ret = platform_device_add(serial8250_isa_devs);
2898 if (ret)
2899 goto put_dev;
2900
2901 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
2902
2903 ret = platform_driver_register(&serial8250_isa_driver);
2904 if (ret == 0)
2905 goto out;
2906
2907 platform_device_del(serial8250_isa_devs);
2908 put_dev:
2909 platform_device_put(serial8250_isa_devs);
2910 unreg_uart_drv:
2911 uart_unregister_driver(&serial8250_reg);
2912 out:
2913 return ret;
2914 }
2915
2916 static void __exit serial8250_exit(void)
2917 {
2918 struct platform_device *isa_dev = serial8250_isa_devs;
2919
2920 /*
2921 * This tells serial8250_unregister_port() not to re-register
2922 * the ports (thereby making serial8250_isa_driver permanently
2923 * in use.)
2924 */
2925 serial8250_isa_devs = NULL;
2926
2927 platform_driver_unregister(&serial8250_isa_driver);
2928 platform_device_unregister(isa_dev);
2929
2930 uart_unregister_driver(&serial8250_reg);
2931 }
2932
2933 module_init(serial8250_init);
2934 module_exit(serial8250_exit);
2935
2936 EXPORT_SYMBOL(serial8250_suspend_port);
2937 EXPORT_SYMBOL(serial8250_resume_port);
2938
2939 MODULE_LICENSE("GPL");
2940 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver $Revision: 1.90 $");
2941
2942 module_param(share_irqs, uint, 0644);
2943 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
2944 " (unsafe)");
2945
2946 module_param(nr_uarts, uint, 0644);
2947 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
2948
2949 #ifdef CONFIG_SERIAL_8250_RSA
2950 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
2951 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
2952 #endif
2953 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
2954
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