1 /*
2 * linux/drivers/char/8250.c
3 *
4 * Driver for 8250/16550-type serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * $Id: 8250.c,v 1.90 2002/07/28 10:03:27 rmk Exp $
16 *
17 * A note about mapbase / membase
18 *
19 * mapbase is the physical address of the IO port.
20 * membase is an 'ioremapped' cookie.
21 */
22 #include <linux/config.h>
23
24 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
25 #define SUPPORT_SYSRQ
26 #endif
27
28 #include <linux/module.h>
29 #include <linux/moduleparam.h>
30 #include <linux/ioport.h>
31 #include <linux/init.h>
32 #include <linux/console.h>
33 #include <linux/sysrq.h>
34 #include <linux/mca.h>
35 #include <linux/delay.h>
36 #include <linux/device.h>
37 #include <linux/tty.h>
38 #include <linux/tty_flip.h>
39 #include <linux/serial_reg.h>
40 #include <linux/serial_core.h>
41 #include <linux/serial.h>
42 #include <linux/serial_8250.h>
43
44 #include <asm/io.h>
45 #include <asm/irq.h>
46
47 #include "8250.h"
48
49 /*
50 * Configuration:
51 * share_irqs - whether we pass SA_SHIRQ to request_irq(). This option
52 * is unsafe when used on edge-triggered interrupts.
53 */
54 unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
55
56 /*
57 * Debugging.
58 */
59 #if 0
60 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
61 #else
62 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
63 #endif
64
65 #if 0
66 #define DEBUG_INTR(fmt...) printk(fmt)
67 #else
68 #define DEBUG_INTR(fmt...) do { } while (0)
69 #endif
70
71 #define PASS_LIMIT 256
72
73 /*
74 * We default to IRQ0 for the "no irq" hack. Some
75 * machine types want others as well - they're free
76 * to redefine this in their header file.
77 */
78 #define is_real_interrupt(irq) ((irq) != 0)
79
80 /*
81 * This converts from our new CONFIG_ symbols to the symbols
82 * that asm/serial.h expects. You _NEED_ to comment out the
83 * linux/config.h include contained inside asm/serial.h for
84 * this to work.
85 */
86 #undef CONFIG_SERIAL_MANY_PORTS
87 #undef CONFIG_SERIAL_DETECT_IRQ
88 #undef CONFIG_SERIAL_MULTIPORT
89 #undef CONFIG_HUB6
90
91 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
92 #define CONFIG_SERIAL_DETECT_IRQ 1
93 #endif
94 #ifdef CONFIG_SERIAL_8250_MULTIPORT
95 #define CONFIG_SERIAL_MULTIPORT 1
96 #endif
97 #ifdef CONFIG_SERIAL_8250_MANY_PORTS
98 #define CONFIG_SERIAL_MANY_PORTS 1
99 #endif
100
101 /*
102 * HUB6 is always on. This will be removed once the header
103 * files have been cleaned.
104 */
105 #define CONFIG_HUB6 1
106
107 #include <asm/serial.h>
108
109 /*
110 * SERIAL_PORT_DFNS tells us about built-in ports that have no
111 * standard enumeration mechanism. Platforms that can find all
112 * serial ports via mechanisms like ACPI or PCI need not supply it.
113 */
114 #ifndef SERIAL_PORT_DFNS
115 #define SERIAL_PORT_DFNS
116 #endif
117
118 static struct old_serial_port old_serial_port[] = {
119 SERIAL_PORT_DFNS /* defined in asm/serial.h */
120 };
121
122 #define UART_NR (ARRAY_SIZE(old_serial_port) + CONFIG_SERIAL_8250_NR_UARTS)
123
124 #ifdef CONFIG_SERIAL_8250_RSA
125
126 #define PORT_RSA_MAX 4
127 static unsigned long probe_rsa[PORT_RSA_MAX];
128 static unsigned int probe_rsa_count;
129 #endif /* CONFIG_SERIAL_8250_RSA */
130
131 struct uart_8250_port {
132 struct uart_port port;
133 struct timer_list timer; /* "no irq" timer */
134 struct list_head list; /* ports on this IRQ */
135 unsigned int capabilities; /* port capabilities */
136 unsigned int tx_loadsz; /* transmit fifo load size */
137 unsigned short rev;
138 unsigned char acr;
139 unsigned char ier;
140 unsigned char lcr;
141 unsigned char mcr;
142 unsigned char mcr_mask; /* mask of user bits */
143 unsigned char mcr_force; /* mask of forced bits */
144 unsigned char lsr_break_flag;
145
146 /*
147 * We provide a per-port pm hook.
148 */
149 void (*pm)(struct uart_port *port,
150 unsigned int state, unsigned int old);
151 };
152
153 struct irq_info {
154 spinlock_t lock;
155 struct list_head *head;
156 };
157
158 static struct irq_info irq_lists[NR_IRQS];
159
160 /*
161 * Here we define the default xmit fifo size used for each type of UART.
162 */
163 static const struct serial8250_config uart_config[] = {
164 [PORT_UNKNOWN] = {
165 .name = "unknown",
166 .fifo_size = 1,
167 .tx_loadsz = 1,
168 },
169 [PORT_8250] = {
170 .name = "8250",
171 .fifo_size = 1,
172 .tx_loadsz = 1,
173 },
174 [PORT_16450] = {
175 .name = "16450",
176 .fifo_size = 1,
177 .tx_loadsz = 1,
178 },
179 [PORT_16550] = {
180 .name = "16550",
181 .fifo_size = 1,
182 .tx_loadsz = 1,
183 },
184 [PORT_16550A] = {
185 .name = "16550A",
186 .fifo_size = 16,
187 .tx_loadsz = 16,
188 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
189 .flags = UART_CAP_FIFO,
190 },
191 [PORT_CIRRUS] = {
192 .name = "Cirrus",
193 .fifo_size = 1,
194 .tx_loadsz = 1,
195 },
196 [PORT_16650] = {
197 .name = "ST16650",
198 .fifo_size = 1,
199 .tx_loadsz = 1,
200 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
201 },
202 [PORT_16650V2] = {
203 .name = "ST16650V2",
204 .fifo_size = 32,
205 .tx_loadsz = 16,
206 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
207 UART_FCR_T_TRIG_00,
208 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
209 },
210 [PORT_16750] = {
211 .name = "TI16750",
212 .fifo_size = 64,
213 .tx_loadsz = 64,
214 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
215 UART_FCR7_64BYTE,
216 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
217 },
218 [PORT_STARTECH] = {
219 .name = "Startech",
220 .fifo_size = 1,
221 .tx_loadsz = 1,
222 },
223 [PORT_16C950] = {
224 .name = "16C950/954",
225 .fifo_size = 128,
226 .tx_loadsz = 128,
227 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
228 .flags = UART_CAP_FIFO,
229 },
230 [PORT_16654] = {
231 .name = "ST16654",
232 .fifo_size = 64,
233 .tx_loadsz = 32,
234 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
235 UART_FCR_T_TRIG_10,
236 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
237 },
238 [PORT_16850] = {
239 .name = "XR16850",
240 .fifo_size = 128,
241 .tx_loadsz = 128,
242 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
243 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
244 },
245 [PORT_RSA] = {
246 .name = "RSA",
247 .fifo_size = 2048,
248 .tx_loadsz = 2048,
249 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
250 .flags = UART_CAP_FIFO,
251 },
252 [PORT_NS16550A] = {
253 .name = "NS16550A",
254 .fifo_size = 16,
255 .tx_loadsz = 16,
256 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
257 .flags = UART_CAP_FIFO | UART_NATSEMI,
258 },
259 [PORT_XSCALE] = {
260 .name = "XScale",
261 .fifo_size = 32,
262 .tx_loadsz = 32,
263 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
264 .flags = UART_CAP_FIFO,
265 },
266 };
267
268 static _INLINE_ unsigned int serial_in(struct uart_8250_port *up, int offset)
269 {
270 offset <<= up->port.regshift;
271
272 switch (up->port.iotype) {
273 case UPIO_HUB6:
274 outb(up->port.hub6 - 1 + offset, up->port.iobase);
275 return inb(up->port.iobase + 1);
276
277 case UPIO_MEM:
278 return readb(up->port.membase + offset);
279
280 case UPIO_MEM32:
281 return readl(up->port.membase + offset);
282
283 default:
284 return inb(up->port.iobase + offset);
285 }
286 }
287
288 static _INLINE_ void
289 serial_out(struct uart_8250_port *up, int offset, int value)
290 {
291 offset <<= up->port.regshift;
292
293 switch (up->port.iotype) {
294 case UPIO_HUB6:
295 outb(up->port.hub6 - 1 + offset, up->port.iobase);
296 outb(value, up->port.iobase + 1);
297 break;
298
299 case UPIO_MEM:
300 writeb(value, up->port.membase + offset);
301 break;
302
303 case UPIO_MEM32:
304 writel(value, up->port.membase + offset);
305 break;
306
307 default:
308 outb(value, up->port.iobase + offset);
309 }
310 }
311
312 /*
313 * We used to support using pause I/O for certain machines. We
314 * haven't supported this for a while, but just in case it's badly
315 * needed for certain old 386 machines, I've left these #define's
316 * in....
317 */
318 #define serial_inp(up, offset) serial_in(up, offset)
319 #define serial_outp(up, offset, value) serial_out(up, offset, value)
320
321
322 /*
323 * For the 16C950
324 */
325 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
326 {
327 serial_out(up, UART_SCR, offset);
328 serial_out(up, UART_ICR, value);
329 }
330
331 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
332 {
333 unsigned int value;
334
335 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
336 serial_out(up, UART_SCR, offset);
337 value = serial_in(up, UART_ICR);
338 serial_icr_write(up, UART_ACR, up->acr);
339
340 return value;
341 }
342
343 /*
344 * FIFO support.
345 */
346 static inline void serial8250_clear_fifos(struct uart_8250_port *p)
347 {
348 if (p->capabilities & UART_CAP_FIFO) {
349 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
350 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
351 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
352 serial_outp(p, UART_FCR, 0);
353 }
354 }
355
356 /*
357 * IER sleep support. UARTs which have EFRs need the "extended
358 * capability" bit enabled. Note that on XR16C850s, we need to
359 * reset LCR to write to IER.
360 */
361 static inline void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
362 {
363 if (p->capabilities & UART_CAP_SLEEP) {
364 if (p->capabilities & UART_CAP_EFR) {
365 serial_outp(p, UART_LCR, 0xBF);
366 serial_outp(p, UART_EFR, UART_EFR_ECB);
367 serial_outp(p, UART_LCR, 0);
368 }
369 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
370 if (p->capabilities & UART_CAP_EFR) {
371 serial_outp(p, UART_LCR, 0xBF);
372 serial_outp(p, UART_EFR, 0);
373 serial_outp(p, UART_LCR, 0);
374 }
375 }
376 }
377
378 #ifdef CONFIG_SERIAL_8250_RSA
379 /*
380 * Attempts to turn on the RSA FIFO. Returns zero on failure.
381 * We set the port uart clock rate if we succeed.
382 */
383 static int __enable_rsa(struct uart_8250_port *up)
384 {
385 unsigned char mode;
386 int result;
387
388 mode = serial_inp(up, UART_RSA_MSR);
389 result = mode & UART_RSA_MSR_FIFO;
390
391 if (!result) {
392 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
393 mode = serial_inp(up, UART_RSA_MSR);
394 result = mode & UART_RSA_MSR_FIFO;
395 }
396
397 if (result)
398 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
399
400 return result;
401 }
402
403 static void enable_rsa(struct uart_8250_port *up)
404 {
405 if (up->port.type == PORT_RSA) {
406 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
407 spin_lock_irq(&up->port.lock);
408 __enable_rsa(up);
409 spin_unlock_irq(&up->port.lock);
410 }
411 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
412 serial_outp(up, UART_RSA_FRR, 0);
413 }
414 }
415
416 /*
417 * Attempts to turn off the RSA FIFO. Returns zero on failure.
418 * It is unknown why interrupts were disabled in here. However,
419 * the caller is expected to preserve this behaviour by grabbing
420 * the spinlock before calling this function.
421 */
422 static void disable_rsa(struct uart_8250_port *up)
423 {
424 unsigned char mode;
425 int result;
426
427 if (up->port.type == PORT_RSA &&
428 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
429 spin_lock_irq(&up->port.lock);
430
431 mode = serial_inp(up, UART_RSA_MSR);
432 result = !(mode & UART_RSA_MSR_FIFO);
433
434 if (!result) {
435 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
436 mode = serial_inp(up, UART_RSA_MSR);
437 result = !(mode & UART_RSA_MSR_FIFO);
438 }
439
440 if (result)
441 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
442 spin_unlock_irq(&up->port.lock);
443 }
444 }
445 #endif /* CONFIG_SERIAL_8250_RSA */
446
447 /*
448 * This is a quickie test to see how big the FIFO is.
449 * It doesn't work at all the time, more's the pity.
450 */
451 static int size_fifo(struct uart_8250_port *up)
452 {
453 unsigned char old_fcr, old_mcr, old_dll, old_dlm, old_lcr;
454 int count;
455
456 old_lcr = serial_inp(up, UART_LCR);
457 serial_outp(up, UART_LCR, 0);
458 old_fcr = serial_inp(up, UART_FCR);
459 old_mcr = serial_inp(up, UART_MCR);
460 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
461 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
462 serial_outp(up, UART_MCR, UART_MCR_LOOP);
463 serial_outp(up, UART_LCR, UART_LCR_DLAB);
464 old_dll = serial_inp(up, UART_DLL);
465 old_dlm = serial_inp(up, UART_DLM);
466 serial_outp(up, UART_DLL, 0x01);
467 serial_outp(up, UART_DLM, 0x00);
468 serial_outp(up, UART_LCR, 0x03);
469 for (count = 0; count < 256; count++)
470 serial_outp(up, UART_TX, count);
471 mdelay(20);/* FIXME - schedule_timeout */
472 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
473 (count < 256); count++)
474 serial_inp(up, UART_RX);
475 serial_outp(up, UART_FCR, old_fcr);
476 serial_outp(up, UART_MCR, old_mcr);
477 serial_outp(up, UART_LCR, UART_LCR_DLAB);
478 serial_outp(up, UART_DLL, old_dll);
479 serial_outp(up, UART_DLM, old_dlm);
480 serial_outp(up, UART_LCR, old_lcr);
481
482 return count;
483 }
484
485 /*
486 * Read UART ID using the divisor method - set DLL and DLM to zero
487 * and the revision will be in DLL and device type in DLM. We
488 * preserve the device state across this.
489 */
490 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
491 {
492 unsigned char old_dll, old_dlm, old_lcr;
493 unsigned int id;
494
495 old_lcr = serial_inp(p, UART_LCR);
496 serial_outp(p, UART_LCR, UART_LCR_DLAB);
497
498 old_dll = serial_inp(p, UART_DLL);
499 old_dlm = serial_inp(p, UART_DLM);
500
501 serial_outp(p, UART_DLL, 0);
502 serial_outp(p, UART_DLM, 0);
503
504 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
505
506 serial_outp(p, UART_DLL, old_dll);
507 serial_outp(p, UART_DLM, old_dlm);
508 serial_outp(p, UART_LCR, old_lcr);
509
510 return id;
511 }
512
513 /*
514 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
515 * When this function is called we know it is at least a StarTech
516 * 16650 V2, but it might be one of several StarTech UARTs, or one of
517 * its clones. (We treat the broken original StarTech 16650 V1 as a
518 * 16550, and why not? Startech doesn't seem to even acknowledge its
519 * existence.)
520 *
521 * What evil have men's minds wrought...
522 */
523 static void autoconfig_has_efr(struct uart_8250_port *up)
524 {
525 unsigned int id1, id2, id3, rev;
526
527 /*
528 * Everything with an EFR has SLEEP
529 */
530 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
531
532 /*
533 * First we check to see if it's an Oxford Semiconductor UART.
534 *
535 * If we have to do this here because some non-National
536 * Semiconductor clone chips lock up if you try writing to the
537 * LSR register (which serial_icr_read does)
538 */
539
540 /*
541 * Check for Oxford Semiconductor 16C950.
542 *
543 * EFR [4] must be set else this test fails.
544 *
545 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
546 * claims that it's needed for 952 dual UART's (which are not
547 * recommended for new designs).
548 */
549 up->acr = 0;
550 serial_out(up, UART_LCR, 0xBF);
551 serial_out(up, UART_EFR, UART_EFR_ECB);
552 serial_out(up, UART_LCR, 0x00);
553 id1 = serial_icr_read(up, UART_ID1);
554 id2 = serial_icr_read(up, UART_ID2);
555 id3 = serial_icr_read(up, UART_ID3);
556 rev = serial_icr_read(up, UART_REV);
557
558 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
559
560 if (id1 == 0x16 && id2 == 0xC9 &&
561 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
562 up->port.type = PORT_16C950;
563 up->rev = rev | (id3 << 8);
564 return;
565 }
566
567 /*
568 * We check for a XR16C850 by setting DLL and DLM to 0, and then
569 * reading back DLL and DLM. The chip type depends on the DLM
570 * value read back:
571 * 0x10 - XR16C850 and the DLL contains the chip revision.
572 * 0x12 - XR16C2850.
573 * 0x14 - XR16C854.
574 */
575 id1 = autoconfig_read_divisor_id(up);
576 DEBUG_AUTOCONF("850id=%04x ", id1);
577
578 id2 = id1 >> 8;
579 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
580 if (id2 == 0x10)
581 up->rev = id1 & 255;
582 up->port.type = PORT_16850;
583 return;
584 }
585
586 /*
587 * It wasn't an XR16C850.
588 *
589 * We distinguish between the '654 and the '650 by counting
590 * how many bytes are in the FIFO. I'm using this for now,
591 * since that's the technique that was sent to me in the
592 * serial driver update, but I'm not convinced this works.
593 * I've had problems doing this in the past. -TYT
594 */
595 if (size_fifo(up) == 64)
596 up->port.type = PORT_16654;
597 else
598 up->port.type = PORT_16650V2;
599 }
600
601 /*
602 * We detected a chip without a FIFO. Only two fall into
603 * this category - the original 8250 and the 16450. The
604 * 16450 has a scratch register (accessible with LCR=0)
605 */
606 static void autoconfig_8250(struct uart_8250_port *up)
607 {
608 unsigned char scratch, status1, status2;
609
610 up->port.type = PORT_8250;
611
612 scratch = serial_in(up, UART_SCR);
613 serial_outp(up, UART_SCR, 0xa5);
614 status1 = serial_in(up, UART_SCR);
615 serial_outp(up, UART_SCR, 0x5a);
616 status2 = serial_in(up, UART_SCR);
617 serial_outp(up, UART_SCR, scratch);
618
619 if (status1 == 0xa5 && status2 == 0x5a)
620 up->port.type = PORT_16450;
621 }
622
623 static int broken_efr(struct uart_8250_port *up)
624 {
625 /*
626 * Exar ST16C2550 "A2" devices incorrectly detect as
627 * having an EFR, and report an ID of 0x0201. See
628 * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
629 */
630 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
631 return 1;
632
633 return 0;
634 }
635
636 /*
637 * We know that the chip has FIFOs. Does it have an EFR? The
638 * EFR is located in the same register position as the IIR and
639 * we know the top two bits of the IIR are currently set. The
640 * EFR should contain zero. Try to read the EFR.
641 */
642 static void autoconfig_16550a(struct uart_8250_port *up)
643 {
644 unsigned char status1, status2;
645
646 up->port.type = PORT_16550A;
647 up->capabilities |= UART_CAP_FIFO;
648
649 /*
650 * Check for presence of the EFR when DLAB is set.
651 * Only ST16C650V1 UARTs pass this test.
652 */
653 serial_outp(up, UART_LCR, UART_LCR_DLAB);
654 if (serial_in(up, UART_EFR) == 0) {
655 serial_outp(up, UART_EFR, 0xA8);
656 if (serial_in(up, UART_EFR) != 0) {
657 DEBUG_AUTOCONF("EFRv1 ");
658 up->port.type = PORT_16650;
659 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
660 } else {
661 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
662 }
663 serial_outp(up, UART_EFR, 0);
664 return;
665 }
666
667 /*
668 * Maybe it requires 0xbf to be written to the LCR.
669 * (other ST16C650V2 UARTs, TI16C752A, etc)
670 */
671 serial_outp(up, UART_LCR, 0xBF);
672 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
673 DEBUG_AUTOCONF("EFRv2 ");
674 autoconfig_has_efr(up);
675 return;
676 }
677
678 /*
679 * Check for a National Semiconductor SuperIO chip.
680 * Attempt to switch to bank 2, read the value of the LOOP bit
681 * from EXCR1. Switch back to bank 0, change it in MCR. Then
682 * switch back to bank 2, read it from EXCR1 again and check
683 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
684 * On PowerPC we don't want to change baud_base, as we have
685 * a number of different divisors. -- Tom Rini
686 */
687 serial_outp(up, UART_LCR, 0);
688 status1 = serial_in(up, UART_MCR);
689 serial_outp(up, UART_LCR, 0xE0);
690 status2 = serial_in(up, 0x02); /* EXCR1 */
691
692 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
693 serial_outp(up, UART_LCR, 0);
694 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
695 serial_outp(up, UART_LCR, 0xE0);
696 status2 = serial_in(up, 0x02); /* EXCR1 */
697 serial_outp(up, UART_LCR, 0);
698 serial_outp(up, UART_MCR, status1);
699
700 if ((status2 ^ status1) & UART_MCR_LOOP) {
701 #ifndef CONFIG_PPC
702 serial_outp(up, UART_LCR, 0xE0);
703 status1 = serial_in(up, 0x04); /* EXCR1 */
704 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
705 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
706 serial_outp(up, 0x04, status1);
707 serial_outp(up, UART_LCR, 0);
708 up->port.uartclk = 921600*16;
709 #endif
710
711 up->port.type = PORT_NS16550A;
712 up->capabilities |= UART_NATSEMI;
713 return;
714 }
715 }
716
717 /*
718 * No EFR. Try to detect a TI16750, which only sets bit 5 of
719 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
720 * Try setting it with and without DLAB set. Cheap clones
721 * set bit 5 without DLAB set.
722 */
723 serial_outp(up, UART_LCR, 0);
724 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
725 status1 = serial_in(up, UART_IIR) >> 5;
726 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
727 serial_outp(up, UART_LCR, UART_LCR_DLAB);
728 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
729 status2 = serial_in(up, UART_IIR) >> 5;
730 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
731
732 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
733
734 if (status1 == 6 && status2 == 7) {
735 up->port.type = PORT_16750;
736 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
737 return;
738 }
739 }
740
741 /*
742 * This routine is called by rs_init() to initialize a specific serial
743 * port. It determines what type of UART chip this serial port is
744 * using: 8250, 16450, 16550, 16550A. The important question is
745 * whether or not this UART is a 16550A or not, since this will
746 * determine whether or not we can use its FIFO features or not.
747 */
748 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
749 {
750 unsigned char status1, scratch, scratch2, scratch3;
751 unsigned char save_lcr, save_mcr;
752 unsigned long flags;
753
754 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
755 return;
756
757 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04x, 0x%p): ",
758 up->port.line, up->port.iobase, up->port.membase);
759
760 /*
761 * We really do need global IRQs disabled here - we're going to
762 * be frobbing the chips IRQ enable register to see if it exists.
763 */
764 spin_lock_irqsave(&up->port.lock, flags);
765 // save_flags(flags); cli();
766
767 up->capabilities = 0;
768
769 if (!(up->port.flags & UPF_BUGGY_UART)) {
770 /*
771 * Do a simple existence test first; if we fail this,
772 * there's no point trying anything else.
773 *
774 * 0x80 is used as a nonsense port to prevent against
775 * false positives due to ISA bus float. The
776 * assumption is that 0x80 is a non-existent port;
777 * which should be safe since include/asm/io.h also
778 * makes this assumption.
779 *
780 * Note: this is safe as long as MCR bit 4 is clear
781 * and the device is in "PC" mode.
782 */
783 scratch = serial_inp(up, UART_IER);
784 serial_outp(up, UART_IER, 0);
785 #ifdef __i386__
786 outb(0xff, 0x080);
787 #endif
788 scratch2 = serial_inp(up, UART_IER);
789 serial_outp(up, UART_IER, 0x0F);
790 #ifdef __i386__
791 outb(0, 0x080);
792 #endif
793 scratch3 = serial_inp(up, UART_IER);
794 serial_outp(up, UART_IER, scratch);
795 if (scratch2 != 0 || scratch3 != 0x0F) {
796 /*
797 * We failed; there's nothing here
798 */
799 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
800 scratch2, scratch3);
801 goto out;
802 }
803 }
804
805 save_mcr = serial_in(up, UART_MCR);
806 save_lcr = serial_in(up, UART_LCR);
807
808 /*
809 * Check to see if a UART is really there. Certain broken
810 * internal modems based on the Rockwell chipset fail this
811 * test, because they apparently don't implement the loopback
812 * test mode. So this test is skipped on the COM 1 through
813 * COM 4 ports. This *should* be safe, since no board
814 * manufacturer would be stupid enough to design a board
815 * that conflicts with COM 1-4 --- we hope!
816 */
817 if (!(up->port.flags & UPF_SKIP_TEST)) {
818 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
819 status1 = serial_inp(up, UART_MSR) & 0xF0;
820 serial_outp(up, UART_MCR, save_mcr);
821 if (status1 != 0x90) {
822 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
823 status1);
824 goto out;
825 }
826 }
827
828 /*
829 * We're pretty sure there's a port here. Lets find out what
830 * type of port it is. The IIR top two bits allows us to find
831 * out if its 8250 or 16450, 16550, 16550A or later. This
832 * determines what we test for next.
833 *
834 * We also initialise the EFR (if any) to zero for later. The
835 * EFR occupies the same register location as the FCR and IIR.
836 */
837 serial_outp(up, UART_LCR, 0xBF);
838 serial_outp(up, UART_EFR, 0);
839 serial_outp(up, UART_LCR, 0);
840
841 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
842 scratch = serial_in(up, UART_IIR) >> 6;
843
844 DEBUG_AUTOCONF("iir=%d ", scratch);
845
846 switch (scratch) {
847 case 0:
848 autoconfig_8250(up);
849 break;
850 case 1:
851 up->port.type = PORT_UNKNOWN;
852 break;
853 case 2:
854 up->port.type = PORT_16550;
855 break;
856 case 3:
857 autoconfig_16550a(up);
858 break;
859 }
860
861 #ifdef CONFIG_SERIAL_8250_RSA
862 /*
863 * Only probe for RSA ports if we got the region.
864 */
865 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
866 int i;
867
868 for (i = 0 ; i < probe_rsa_count; ++i) {
869 if (probe_rsa[i] == up->port.iobase &&
870 __enable_rsa(up)) {
871 up->port.type = PORT_RSA;
872 break;
873 }
874 }
875 }
876 #endif
877 serial_outp(up, UART_LCR, save_lcr);
878
879 if (up->capabilities != uart_config[up->port.type].flags) {
880 printk(KERN_WARNING
881 "ttyS%d: detected caps %08x should be %08x\n",
882 up->port.line, up->capabilities,
883 uart_config[up->port.type].flags);
884 }
885
886 up->port.fifosize = uart_config[up->port.type].fifo_size;
887 up->capabilities = uart_config[up->port.type].flags;
888 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
889
890 if (up->port.type == PORT_UNKNOWN)
891 goto out;
892
893 /*
894 * Reset the UART.
895 */
896 #ifdef CONFIG_SERIAL_8250_RSA
897 if (up->port.type == PORT_RSA)
898 serial_outp(up, UART_RSA_FRR, 0);
899 #endif
900 serial_outp(up, UART_MCR, save_mcr);
901 serial8250_clear_fifos(up);
902 (void)serial_in(up, UART_RX);
903 serial_outp(up, UART_IER, 0);
904
905 out:
906 spin_unlock_irqrestore(&up->port.lock, flags);
907 // restore_flags(flags);
908 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
909 }
910
911 static void autoconfig_irq(struct uart_8250_port *up)
912 {
913 unsigned char save_mcr, save_ier;
914 unsigned char save_ICP = 0;
915 unsigned int ICP = 0;
916 unsigned long irqs;
917 int irq;
918
919 if (up->port.flags & UPF_FOURPORT) {
920 ICP = (up->port.iobase & 0xfe0) | 0x1f;
921 save_ICP = inb_p(ICP);
922 outb_p(0x80, ICP);
923 (void) inb_p(ICP);
924 }
925
926 /* forget possible initially masked and pending IRQ */
927 probe_irq_off(probe_irq_on());
928 save_mcr = serial_inp(up, UART_MCR);
929 save_ier = serial_inp(up, UART_IER);
930 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
931
932 irqs = probe_irq_on();
933 serial_outp(up, UART_MCR, 0);
934 udelay (10);
935 if (up->port.flags & UPF_FOURPORT) {
936 serial_outp(up, UART_MCR,
937 UART_MCR_DTR | UART_MCR_RTS);
938 } else {
939 serial_outp(up, UART_MCR,
940 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
941 }
942 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
943 (void)serial_inp(up, UART_LSR);
944 (void)serial_inp(up, UART_RX);
945 (void)serial_inp(up, UART_IIR);
946 (void)serial_inp(up, UART_MSR);
947 serial_outp(up, UART_TX, 0xFF);
948 udelay (20);
949 irq = probe_irq_off(irqs);
950
951 serial_outp(up, UART_MCR, save_mcr);
952 serial_outp(up, UART_IER, save_ier);
953
954 if (up->port.flags & UPF_FOURPORT)
955 outb_p(save_ICP, ICP);
956
957 up->port.irq = (irq > 0) ? irq : 0;
958 }
959
960 static void serial8250_stop_tx(struct uart_port *port, unsigned int tty_stop)
961 {
962 struct uart_8250_port *up = (struct uart_8250_port *)port;
963
964 if (up->ier & UART_IER_THRI) {
965 up->ier &= ~UART_IER_THRI;
966 serial_out(up, UART_IER, up->ier);
967 }
968
969 /*
970 * We only do this from uart_stop - if we run out of
971 * characters to send, we don't want to prevent the
972 * FIFO from emptying.
973 */
974 if (up->port.type == PORT_16C950 && tty_stop) {
975 up->acr |= UART_ACR_TXDIS;
976 serial_icr_write(up, UART_ACR, up->acr);
977 }
978 }
979
980 static void serial8250_start_tx(struct uart_port *port, unsigned int tty_start)
981 {
982 struct uart_8250_port *up = (struct uart_8250_port *)port;
983
984 if (!(up->ier & UART_IER_THRI)) {
985 up->ier |= UART_IER_THRI;
986 serial_out(up, UART_IER, up->ier);
987 }
988 /*
989 * We only do this from uart_start
990 */
991 if (tty_start && up->port.type == PORT_16C950) {
992 up->acr &= ~UART_ACR_TXDIS;
993 serial_icr_write(up, UART_ACR, up->acr);
994 }
995 }
996
997 static void serial8250_stop_rx(struct uart_port *port)
998 {
999 struct uart_8250_port *up = (struct uart_8250_port *)port;
1000
1001 up->ier &= ~UART_IER_RLSI;
1002 up->port.read_status_mask &= ~UART_LSR_DR;
1003 serial_out(up, UART_IER, up->ier);
1004 }
1005
1006 static void serial8250_enable_ms(struct uart_port *port)
1007 {
1008 struct uart_8250_port *up = (struct uart_8250_port *)port;
1009
1010 up->ier |= UART_IER_MSI;
1011 serial_out(up, UART_IER, up->ier);
1012 }
1013
1014 static _INLINE_ void
1015 receive_chars(struct uart_8250_port *up, int *status, struct pt_regs *regs)
1016 {
1017 struct tty_struct *tty = up->port.info->tty;
1018 unsigned char ch, lsr = *status;
1019 int max_count = 256;
1020 char flag;
1021
1022 do {
1023 /* The following is not allowed by the tty layer and
1024 unsafe. It should be fixed ASAP */
1025 if (unlikely(tty->flip.count >= TTY_FLIPBUF_SIZE)) {
1026 if (tty->low_latency) {
1027 spin_unlock(&up->port.lock);
1028 tty_flip_buffer_push(tty);
1029 spin_lock(&up->port.lock);
1030 }
1031 /* If this failed then we will throw away the
1032 bytes but must do so to clear interrupts */
1033 }
1034 ch = serial_inp(up, UART_RX);
1035 flag = TTY_NORMAL;
1036 up->port.icount.rx++;
1037
1038 #ifdef CONFIG_SERIAL_8250_CONSOLE
1039 /*
1040 * Recover the break flag from console xmit
1041 */
1042 if (up->port.line == up->port.cons->index) {
1043 lsr |= up->lsr_break_flag;
1044 up->lsr_break_flag = 0;
1045 }
1046 #endif
1047
1048 if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE |
1049 UART_LSR_FE | UART_LSR_OE))) {
1050 /*
1051 * For statistics only
1052 */
1053 if (lsr & UART_LSR_BI) {
1054 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1055 up->port.icount.brk++;
1056 /*
1057 * We do the SysRQ and SAK checking
1058 * here because otherwise the break
1059 * may get masked by ignore_status_mask
1060 * or read_status_mask.
1061 */
1062 if (uart_handle_break(&up->port))
1063 goto ignore_char;
1064 } else if (lsr & UART_LSR_PE)
1065 up->port.icount.parity++;
1066 else if (lsr & UART_LSR_FE)
1067 up->port.icount.frame++;
1068 if (lsr & UART_LSR_OE)
1069 up->port.icount.overrun++;
1070
1071 /*
1072 * Mask off conditions which should be ingored.
1073 */
1074 lsr &= up->port.read_status_mask;
1075
1076 if (lsr & UART_LSR_BI) {
1077 DEBUG_INTR("handling break....");
1078 flag = TTY_BREAK;
1079 } else if (lsr & UART_LSR_PE)
1080 flag = TTY_PARITY;
1081 else if (lsr & UART_LSR_FE)
1082 flag = TTY_FRAME;
1083 }
1084 if (uart_handle_sysrq_char(&up->port, ch, regs))
1085 goto ignore_char;
1086 if ((lsr & up->port.ignore_status_mask) == 0) {
1087 tty_insert_flip_char(tty, ch, flag);
1088 }
1089 if ((lsr & UART_LSR_OE) &&
1090 tty->flip.count < TTY_FLIPBUF_SIZE) {
1091 /*
1092 * Overrun is special, since it's reported
1093 * immediately, and doesn't affect the current
1094 * character.
1095 */
1096 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
1097 }
1098 ignore_char:
1099 lsr = serial_inp(up, UART_LSR);
1100 } while ((lsr & UART_LSR_DR) && (max_count-- > 0));
1101 spin_unlock(&up->port.lock);
1102 tty_flip_buffer_push(tty);
1103 spin_lock(&up->port.lock);
1104 *status = lsr;
1105 }
1106
1107 static _INLINE_ void transmit_chars(struct uart_8250_port *up)
1108 {
1109 struct circ_buf *xmit = &up->port.info->xmit;
1110 int count;
1111
1112 if (up->port.x_char) {
1113 serial_outp(up, UART_TX, up->port.x_char);
1114 up->port.icount.tx++;
1115 up->port.x_char = 0;
1116 return;
1117 }
1118 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
1119 serial8250_stop_tx(&up->port, 0);
1120 return;
1121 }
1122
1123 count = up->tx_loadsz;
1124 do {
1125 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1126 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1127 up->port.icount.tx++;
1128 if (uart_circ_empty(xmit))
1129 break;
1130 } while (--count > 0);
1131
1132 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1133 uart_write_wakeup(&up->port);
1134
1135 DEBUG_INTR("THRE...");
1136
1137 if (uart_circ_empty(xmit))
1138 serial8250_stop_tx(&up->port, 0);
1139 }
1140
1141 static _INLINE_ void check_modem_status(struct uart_8250_port *up)
1142 {
1143 int status;
1144
1145 status = serial_in(up, UART_MSR);
1146
1147 if ((status & UART_MSR_ANY_DELTA) == 0)
1148 return;
1149
1150 if (status & UART_MSR_TERI)
1151 up->port.icount.rng++;
1152 if (status & UART_MSR_DDSR)
1153 up->port.icount.dsr++;
1154 if (status & UART_MSR_DDCD)
1155 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1156 if (status & UART_MSR_DCTS)
1157 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1158
1159 wake_up_interruptible(&up->port.info->delta_msr_wait);
1160 }
1161
1162 /*
1163 * This handles the interrupt from one port.
1164 */
1165 static inline void
1166 serial8250_handle_port(struct uart_8250_port *up, struct pt_regs *regs)
1167 {
1168 unsigned int status = serial_inp(up, UART_LSR);
1169
1170 DEBUG_INTR("status = %x...", status);
1171
1172 if (status & UART_LSR_DR)
1173 receive_chars(up, &status, regs);
1174 check_modem_status(up);
1175 if (status & UART_LSR_THRE)
1176 transmit_chars(up);
1177 }
1178
1179 /*
1180 * This is the serial driver's interrupt routine.
1181 *
1182 * Arjan thinks the old way was overly complex, so it got simplified.
1183 * Alan disagrees, saying that need the complexity to handle the weird
1184 * nature of ISA shared interrupts. (This is a special exception.)
1185 *
1186 * In order to handle ISA shared interrupts properly, we need to check
1187 * that all ports have been serviced, and therefore the ISA interrupt
1188 * line has been de-asserted.
1189 *
1190 * This means we need to loop through all ports. checking that they
1191 * don't have an interrupt pending.
1192 */
1193 static irqreturn_t serial8250_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1194 {
1195 struct irq_info *i = dev_id;
1196 struct list_head *l, *end = NULL;
1197 int pass_counter = 0, handled = 0;
1198
1199 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1200
1201 spin_lock(&i->lock);
1202
1203 l = i->head;
1204 do {
1205 struct uart_8250_port *up;
1206 unsigned int iir;
1207
1208 up = list_entry(l, struct uart_8250_port, list);
1209
1210 iir = serial_in(up, UART_IIR);
1211 if (!(iir & UART_IIR_NO_INT)) {
1212 spin_lock(&up->port.lock);
1213 serial8250_handle_port(up, regs);
1214 spin_unlock(&up->port.lock);
1215
1216 handled = 1;
1217
1218 end = NULL;
1219 } else if (end == NULL)
1220 end = l;
1221
1222 l = l->next;
1223
1224 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1225 /* If we hit this, we're dead. */
1226 printk(KERN_ERR "serial8250: too much work for "
1227 "irq%d\n", irq);
1228 break;
1229 }
1230 } while (l != end);
1231
1232 spin_unlock(&i->lock);
1233
1234 DEBUG_INTR("end.\n");
1235
1236 return IRQ_RETVAL(handled);
1237 }
1238
1239 /*
1240 * To support ISA shared interrupts, we need to have one interrupt
1241 * handler that ensures that the IRQ line has been deasserted
1242 * before returning. Failing to do this will result in the IRQ
1243 * line being stuck active, and, since ISA irqs are edge triggered,
1244 * no more IRQs will be seen.
1245 */
1246 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1247 {
1248 spin_lock_irq(&i->lock);
1249
1250 if (!list_empty(i->head)) {
1251 if (i->head == &up->list)
1252 i->head = i->head->next;
1253 list_del(&up->list);
1254 } else {
1255 BUG_ON(i->head != &up->list);
1256 i->head = NULL;
1257 }
1258
1259 spin_unlock_irq(&i->lock);
1260 }
1261
1262 static int serial_link_irq_chain(struct uart_8250_port *up)
1263 {
1264 struct irq_info *i = irq_lists + up->port.irq;
1265 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? SA_SHIRQ : 0;
1266
1267 spin_lock_irq(&i->lock);
1268
1269 if (i->head) {
1270 list_add(&up->list, i->head);
1271 spin_unlock_irq(&i->lock);
1272
1273 ret = 0;
1274 } else {
1275 INIT_LIST_HEAD(&up->list);
1276 i->head = &up->list;
1277 spin_unlock_irq(&i->lock);
1278
1279 ret = request_irq(up->port.irq, serial8250_interrupt,
1280 irq_flags, "serial", i);
1281 if (ret < 0)
1282 serial_do_unlink(i, up);
1283 }
1284
1285 return ret;
1286 }
1287
1288 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1289 {
1290 struct irq_info *i = irq_lists + up->port.irq;
1291
1292 BUG_ON(i->head == NULL);
1293
1294 if (list_empty(i->head))
1295 free_irq(up->port.irq, i);
1296
1297 serial_do_unlink(i, up);
1298 }
1299
1300 /*
1301 * This function is used to handle ports that do not have an
1302 * interrupt. This doesn't work very well for 16450's, but gives
1303 * barely passable results for a 16550A. (Although at the expense
1304 * of much CPU overhead).
1305 */
1306 static void serial8250_timeout(unsigned long data)
1307 {
1308 struct uart_8250_port *up = (struct uart_8250_port *)data;
1309 unsigned int timeout;
1310 unsigned int iir;
1311
1312 iir = serial_in(up, UART_IIR);
1313 if (!(iir & UART_IIR_NO_INT)) {
1314 spin_lock(&up->port.lock);
1315 serial8250_handle_port(up, NULL);
1316 spin_unlock(&up->port.lock);
1317 }
1318
1319 timeout = up->port.timeout;
1320 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
1321 mod_timer(&up->timer, jiffies + timeout);
1322 }
1323
1324 static unsigned int serial8250_tx_empty(struct uart_port *port)
1325 {
1326 struct uart_8250_port *up = (struct uart_8250_port *)port;
1327 unsigned long flags;
1328 unsigned int ret;
1329
1330 spin_lock_irqsave(&up->port.lock, flags);
1331 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
1332 spin_unlock_irqrestore(&up->port.lock, flags);
1333
1334 return ret;
1335 }
1336
1337 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1338 {
1339 struct uart_8250_port *up = (struct uart_8250_port *)port;
1340 unsigned long flags;
1341 unsigned char status;
1342 unsigned int ret;
1343
1344 spin_lock_irqsave(&up->port.lock, flags);
1345 status = serial_in(up, UART_MSR);
1346 spin_unlock_irqrestore(&up->port.lock, flags);
1347
1348 ret = 0;
1349 if (status & UART_MSR_DCD)
1350 ret |= TIOCM_CAR;
1351 if (status & UART_MSR_RI)
1352 ret |= TIOCM_RNG;
1353 if (status & UART_MSR_DSR)
1354 ret |= TIOCM_DSR;
1355 if (status & UART_MSR_CTS)
1356 ret |= TIOCM_CTS;
1357 return ret;
1358 }
1359
1360 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1361 {
1362 struct uart_8250_port *up = (struct uart_8250_port *)port;
1363 unsigned char mcr = 0;
1364
1365 if (mctrl & TIOCM_RTS)
1366 mcr |= UART_MCR_RTS;
1367 if (mctrl & TIOCM_DTR)
1368 mcr |= UART_MCR_DTR;
1369 if (mctrl & TIOCM_OUT1)
1370 mcr |= UART_MCR_OUT1;
1371 if (mctrl & TIOCM_OUT2)
1372 mcr |= UART_MCR_OUT2;
1373 if (mctrl & TIOCM_LOOP)
1374 mcr |= UART_MCR_LOOP;
1375
1376 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1377
1378 serial_out(up, UART_MCR, mcr);
1379 }
1380
1381 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1382 {
1383 struct uart_8250_port *up = (struct uart_8250_port *)port;
1384 unsigned long flags;
1385
1386 spin_lock_irqsave(&up->port.lock, flags);
1387 if (break_state == -1)
1388 up->lcr |= UART_LCR_SBC;
1389 else
1390 up->lcr &= ~UART_LCR_SBC;
1391 serial_out(up, UART_LCR, up->lcr);
1392 spin_unlock_irqrestore(&up->port.lock, flags);
1393 }
1394
1395 static int serial8250_startup(struct uart_port *port)
1396 {
1397 struct uart_8250_port *up = (struct uart_8250_port *)port;
1398 unsigned long flags;
1399 int retval;
1400
1401 up->capabilities = uart_config[up->port.type].flags;
1402 up->mcr = 0;
1403
1404 if (up->port.type == PORT_16C950) {
1405 /* Wake up and initialize UART */
1406 up->acr = 0;
1407 serial_outp(up, UART_LCR, 0xBF);
1408 serial_outp(up, UART_EFR, UART_EFR_ECB);
1409 serial_outp(up, UART_IER, 0);
1410 serial_outp(up, UART_LCR, 0);
1411 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1412 serial_outp(up, UART_LCR, 0xBF);
1413 serial_outp(up, UART_EFR, UART_EFR_ECB);
1414 serial_outp(up, UART_LCR, 0);
1415 }
1416
1417 #ifdef CONFIG_SERIAL_8250_RSA
1418 /*
1419 * If this is an RSA port, see if we can kick it up to the
1420 * higher speed clock.
1421 */
1422 enable_rsa(up);
1423 #endif
1424
1425 /*
1426 * Clear the FIFO buffers and disable them.
1427 * (they will be reeanbled in set_termios())
1428 */
1429 serial8250_clear_fifos(up);
1430
1431 /*
1432 * Clear the interrupt registers.
1433 */
1434 (void) serial_inp(up, UART_LSR);
1435 (void) serial_inp(up, UART_RX);
1436 (void) serial_inp(up, UART_IIR);
1437 (void) serial_inp(up, UART_MSR);
1438
1439 /*
1440 * At this point, there's no way the LSR could still be 0xff;
1441 * if it is, then bail out, because there's likely no UART
1442 * here.
1443 */
1444 if (!(up->port.flags & UPF_BUGGY_UART) &&
1445 (serial_inp(up, UART_LSR) == 0xff)) {
1446 printk("ttyS%d: LSR safety check engaged!\n", up->port.line);
1447 return -ENODEV;
1448 }
1449
1450 /*
1451 * For a XR16C850, we need to set the trigger levels
1452 */
1453 if (up->port.type == PORT_16850) {
1454 unsigned char fctr;
1455
1456 serial_outp(up, UART_LCR, 0xbf);
1457
1458 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
1459 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1460 serial_outp(up, UART_TRG, UART_TRG_96);
1461 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1462 serial_outp(up, UART_TRG, UART_TRG_96);
1463
1464 serial_outp(up, UART_LCR, 0);
1465 }
1466
1467 /*
1468 * If the "interrupt" for this port doesn't correspond with any
1469 * hardware interrupt, we use a timer-based system. The original
1470 * driver used to do this with IRQ0.
1471 */
1472 if (!is_real_interrupt(up->port.irq)) {
1473 unsigned int timeout = up->port.timeout;
1474
1475 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
1476
1477 up->timer.data = (unsigned long)up;
1478 mod_timer(&up->timer, jiffies + timeout);
1479 } else {
1480 retval = serial_link_irq_chain(up);
1481 if (retval)
1482 return retval;
1483 }
1484
1485 /*
1486 * Now, initialize the UART
1487 */
1488 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
1489
1490 spin_lock_irqsave(&up->port.lock, flags);
1491 if (up->port.flags & UPF_FOURPORT) {
1492 if (!is_real_interrupt(up->port.irq))
1493 up->port.mctrl |= TIOCM_OUT1;
1494 } else
1495 /*
1496 * Most PC uarts need OUT2 raised to enable interrupts.
1497 */
1498 if (is_real_interrupt(up->port.irq))
1499 up->port.mctrl |= TIOCM_OUT2;
1500
1501 serial8250_set_mctrl(&up->port, up->port.mctrl);
1502 spin_unlock_irqrestore(&up->port.lock, flags);
1503
1504 /*
1505 * Finally, enable interrupts. Note: Modem status interrupts
1506 * are set via set_termios(), which will be occurring imminently
1507 * anyway, so we don't enable them here.
1508 */
1509 up->ier = UART_IER_RLSI | UART_IER_RDI;
1510 serial_outp(up, UART_IER, up->ier);
1511
1512 if (up->port.flags & UPF_FOURPORT) {
1513 unsigned int icp;
1514 /*
1515 * Enable interrupts on the AST Fourport board
1516 */
1517 icp = (up->port.iobase & 0xfe0) | 0x01f;
1518 outb_p(0x80, icp);
1519 (void) inb_p(icp);
1520 }
1521
1522 /*
1523 * And clear the interrupt registers again for luck.
1524 */
1525 (void) serial_inp(up, UART_LSR);
1526 (void) serial_inp(up, UART_RX);
1527 (void) serial_inp(up, UART_IIR);
1528 (void) serial_inp(up, UART_MSR);
1529
1530 return 0;
1531 }
1532
1533 static void serial8250_shutdown(struct uart_port *port)
1534 {
1535 struct uart_8250_port *up = (struct uart_8250_port *)port;
1536 unsigned long flags;
1537
1538 /*
1539 * Disable interrupts from this port
1540 */
1541 up->ier = 0;
1542 serial_outp(up, UART_IER, 0);
1543
1544 spin_lock_irqsave(&up->port.lock, flags);
1545 if (up->port.flags & UPF_FOURPORT) {
1546 /* reset interrupts on the AST Fourport board */
1547 inb((up->port.iobase & 0xfe0) | 0x1f);
1548 up->port.mctrl |= TIOCM_OUT1;
1549 } else
1550 up->port.mctrl &= ~TIOCM_OUT2;
1551
1552 serial8250_set_mctrl(&up->port, up->port.mctrl);
1553 spin_unlock_irqrestore(&up->port.lock, flags);
1554
1555 /*
1556 * Disable break condition and FIFOs
1557 */
1558 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
1559 serial8250_clear_fifos(up);
1560
1561 #ifdef CONFIG_SERIAL_8250_RSA
1562 /*
1563 * Reset the RSA board back to 115kbps compat mode.
1564 */
1565 disable_rsa(up);
1566 #endif
1567
1568 /*
1569 * Read data port to reset things, and then unlink from
1570 * the IRQ chain.
1571 */
1572 (void) serial_in(up, UART_RX);
1573
1574 if (!is_real_interrupt(up->port.irq))
1575 del_timer_sync(&up->timer);
1576 else
1577 serial_unlink_irq_chain(up);
1578 }
1579
1580 static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
1581 {
1582 unsigned int quot;
1583
1584 /*
1585 * Handle magic divisors for baud rates above baud_base on
1586 * SMSC SuperIO chips.
1587 */
1588 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1589 baud == (port->uartclk/4))
1590 quot = 0x8001;
1591 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1592 baud == (port->uartclk/8))
1593 quot = 0x8002;
1594 else
1595 quot = uart_get_divisor(port, baud);
1596
1597 return quot;
1598 }
1599
1600 static void
1601 serial8250_set_termios(struct uart_port *port, struct termios *termios,
1602 struct termios *old)
1603 {
1604 struct uart_8250_port *up = (struct uart_8250_port *)port;
1605 unsigned char cval, fcr = 0;
1606 unsigned long flags;
1607 unsigned int baud, quot;
1608
1609 switch (termios->c_cflag & CSIZE) {
1610 case CS5:
1611 cval = 0x00;
1612 break;
1613 case CS6:
1614 cval = 0x01;
1615 break;
1616 case CS7:
1617 cval = 0x02;
1618 break;
1619 default:
1620 case CS8:
1621 cval = 0x03;
1622 break;
1623 }
1624
1625 if (termios->c_cflag & CSTOPB)
1626 cval |= 0x04;
1627 if (termios->c_cflag & PARENB)
1628 cval |= UART_LCR_PARITY;
1629 if (!(termios->c_cflag & PARODD))
1630 cval |= UART_LCR_EPAR;
1631 #ifdef CMSPAR
1632 if (termios->c_cflag & CMSPAR)
1633 cval |= UART_LCR_SPAR;
1634 #endif
1635
1636 /*
1637 * Ask the core to calculate the divisor for us.
1638 */
1639 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
1640 quot = serial8250_get_divisor(port, baud);
1641
1642 /*
1643 * Work around a bug in the Oxford Semiconductor 952 rev B
1644 * chip which causes it to seriously miscalculate baud rates
1645 * when DLL is 0.
1646 */
1647 if ((quot & 0xff) == 0 && up->port.type == PORT_16C950 &&
1648 up->rev == 0x5201)
1649 quot ++;
1650
1651 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
1652 if (baud < 2400)
1653 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
1654 else
1655 fcr = uart_config[up->port.type].fcr;
1656 }
1657
1658 /*
1659 * MCR-based auto flow control. When AFE is enabled, RTS will be
1660 * deasserted when the receive FIFO contains more characters than
1661 * the trigger, or the MCR RTS bit is cleared. In the case where
1662 * the remote UART is not using CTS auto flow control, we must
1663 * have sufficient FIFO entries for the latency of the remote
1664 * UART to respond. IOW, at least 32 bytes of FIFO.
1665 */
1666 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
1667 up->mcr &= ~UART_MCR_AFE;
1668 if (termios->c_cflag & CRTSCTS)
1669 up->mcr |= UART_MCR_AFE;
1670 }
1671
1672 /*
1673 * Ok, we're now changing the port state. Do it with
1674 * interrupts disabled.
1675 */
1676 spin_lock_irqsave(&up->port.lock, flags);
1677
1678 /*
1679 * Update the per-port timeout.
1680 */
1681 uart_update_timeout(port, termios->c_cflag, baud);
1682
1683 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
1684 if (termios->c_iflag & INPCK)
1685 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
1686 if (termios->c_iflag & (BRKINT | PARMRK))
1687 up->port.read_status_mask |= UART_LSR_BI;
1688
1689 /*
1690 * Characteres to ignore
1691 */
1692 up->port.ignore_status_mask = 0;
1693 if (termios->c_iflag & IGNPAR)
1694 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
1695 if (termios->c_iflag & IGNBRK) {
1696 up->port.ignore_status_mask |= UART_LSR_BI;
1697 /*
1698 * If we're ignoring parity and break indicators,
1699 * ignore overruns too (for real raw support).
1700 */
1701 if (termios->c_iflag & IGNPAR)
1702 up->port.ignore_status_mask |= UART_LSR_OE;
1703 }
1704
1705 /*
1706 * ignore all characters if CREAD is not set
1707 */
1708 if ((termios->c_cflag & CREAD) == 0)
1709 up->port.ignore_status_mask |= UART_LSR_DR;
1710
1711 /*
1712 * CTS flow control flag and modem status interrupts
1713 */
1714 up->ier &= ~UART_IER_MSI;
1715 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
1716 up->ier |= UART_IER_MSI;
1717 if (up->port.type == PORT_XSCALE)
1718 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
1719
1720 serial_out(up, UART_IER, up->ier);
1721
1722 if (up->capabilities & UART_CAP_EFR) {
1723 unsigned char efr = 0;
1724 /*
1725 * TI16C752/Startech hardware flow control. FIXME:
1726 * - TI16C752 requires control thresholds to be set.
1727 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
1728 */
1729 if (termios->c_cflag & CRTSCTS)
1730 efr |= UART_EFR_CTS;
1731
1732 serial_outp(up, UART_LCR, 0xBF);
1733 serial_outp(up, UART_EFR, efr);
1734 }
1735
1736 if (up->capabilities & UART_NATSEMI) {
1737 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
1738 serial_outp(up, UART_LCR, 0xe0);
1739 } else {
1740 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
1741 }
1742
1743 serial_outp(up, UART_DLL, quot & 0xff); /* LS of divisor */
1744 serial_outp(up, UART_DLM, quot >> 8); /* MS of divisor */
1745
1746 /*
1747 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
1748 * is written without DLAB set, this mode will be disabled.
1749 */
1750 if (up->port.type == PORT_16750)
1751 serial_outp(up, UART_FCR, fcr);
1752
1753 serial_outp(up, UART_LCR, cval); /* reset DLAB */
1754 up->lcr = cval; /* Save LCR */
1755 if (up->port.type != PORT_16750) {
1756 if (fcr & UART_FCR_ENABLE_FIFO) {
1757 /* emulated UARTs (Lucent Venus 167x) need two steps */
1758 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1759 }
1760 serial_outp(up, UART_FCR, fcr); /* set fcr */
1761 }
1762 serial8250_set_mctrl(&up->port, up->port.mctrl);
1763 spin_unlock_irqrestore(&up->port.lock, flags);
1764 }
1765
1766 static void
1767 serial8250_pm(struct uart_port *port, unsigned int state,
1768 unsigned int oldstate)
1769 {
1770 struct uart_8250_port *p = (struct uart_8250_port *)port;
1771
1772 serial8250_set_sleep(p, state != 0);
1773
1774 if (p->pm)
1775 p->pm(port, state, oldstate);
1776 }
1777
1778 /*
1779 * Resource handling.
1780 */
1781 static int serial8250_request_std_resource(struct uart_8250_port *up)
1782 {
1783 unsigned int size = 8 << up->port.regshift;
1784 int ret = 0;
1785
1786 switch (up->port.iotype) {
1787 case UPIO_MEM:
1788 if (!up->port.mapbase)
1789 break;
1790
1791 if (!request_mem_region(up->port.mapbase, size, "serial")) {
1792 ret = -EBUSY;
1793 break;
1794 }
1795
1796 if (up->port.flags & UPF_IOREMAP) {
1797 up->port.membase = ioremap(up->port.mapbase, size);
1798 if (!up->port.membase) {
1799 release_mem_region(up->port.mapbase, size);
1800 ret = -ENOMEM;
1801 }
1802 }
1803 break;
1804
1805 case UPIO_HUB6:
1806 case UPIO_PORT:
1807 if (!request_region(up->port.iobase, size, "serial"))
1808 ret = -EBUSY;
1809 break;
1810 }
1811 return ret;
1812 }
1813
1814 static void serial8250_release_std_resource(struct uart_8250_port *up)
1815 {
1816 unsigned int size = 8 << up->port.regshift;
1817
1818 switch (up->port.iotype) {
1819 case UPIO_MEM:
1820 if (!up->port.mapbase)
1821 break;
1822
1823 if (up->port.flags & UPF_IOREMAP) {
1824 iounmap(up->port.membase);
1825 up->port.membase = NULL;
1826 }
1827
1828 release_mem_region(up->port.mapbase, size);
1829 break;
1830
1831 case UPIO_HUB6:
1832 case UPIO_PORT:
1833 release_region(up->port.iobase, size);
1834 break;
1835 }
1836 }
1837
1838 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
1839 {
1840 unsigned long start = UART_RSA_BASE << up->port.regshift;
1841 unsigned int size = 8 << up->port.regshift;
1842 int ret = 0;
1843
1844 switch (up->port.iotype) {
1845 case UPIO_MEM:
1846 ret = -EINVAL;
1847 break;
1848
1849 case UPIO_HUB6:
1850 case UPIO_PORT:
1851 start += up->port.iobase;
1852 if (!request_region(start, size, "serial-rsa"))
1853 ret = -EBUSY;
1854 break;
1855 }
1856
1857 return ret;
1858 }
1859
1860 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
1861 {
1862 unsigned long offset = UART_RSA_BASE << up->port.regshift;
1863 unsigned int size = 8 << up->port.regshift;
1864
1865 switch (up->port.iotype) {
1866 case UPIO_MEM:
1867 break;
1868
1869 case UPIO_HUB6:
1870 case UPIO_PORT:
1871 release_region(up->port.iobase + offset, size);
1872 break;
1873 }
1874 }
1875
1876 static void serial8250_release_port(struct uart_port *port)
1877 {
1878 struct uart_8250_port *up = (struct uart_8250_port *)port;
1879
1880 serial8250_release_std_resource(up);
1881 if (up->port.type == PORT_RSA)
1882 serial8250_release_rsa_resource(up);
1883 }
1884
1885 static int serial8250_request_port(struct uart_port *port)
1886 {
1887 struct uart_8250_port *up = (struct uart_8250_port *)port;
1888 int ret = 0;
1889
1890 ret = serial8250_request_std_resource(up);
1891 if (ret == 0 && up->port.type == PORT_RSA) {
1892 ret = serial8250_request_rsa_resource(up);
1893 if (ret < 0)
1894 serial8250_release_std_resource(up);
1895 }
1896
1897 return ret;
1898 }
1899
1900 static void serial8250_config_port(struct uart_port *port, int flags)
1901 {
1902 struct uart_8250_port *up = (struct uart_8250_port *)port;
1903 int probeflags = PROBE_ANY;
1904 int ret;
1905
1906 /*
1907 * Don't probe for MCA ports on non-MCA machines.
1908 */
1909 if (up->port.flags & UPF_BOOT_ONLYMCA && !MCA_bus)
1910 return;
1911
1912 /*
1913 * Find the region that we can probe for. This in turn
1914 * tells us whether we can probe for the type of port.
1915 */
1916 ret = serial8250_request_std_resource(up);
1917 if (ret < 0)
1918 return;
1919
1920 ret = serial8250_request_rsa_resource(up);
1921 if (ret < 0)
1922 probeflags &= ~PROBE_RSA;
1923
1924 if (flags & UART_CONFIG_TYPE)
1925 autoconfig(up, probeflags);
1926 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
1927 autoconfig_irq(up);
1928
1929 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
1930 serial8250_release_rsa_resource(up);
1931 if (up->port.type == PORT_UNKNOWN)
1932 serial8250_release_std_resource(up);
1933 }
1934
1935 static int
1936 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
1937 {
1938 if (ser->irq >= NR_IRQS || ser->irq < 0 ||
1939 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
1940 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
1941 ser->type == PORT_STARTECH)
1942 return -EINVAL;
1943 return 0;
1944 }
1945
1946 static const char *
1947 serial8250_type(struct uart_port *port)
1948 {
1949 int type = port->type;
1950
1951 if (type >= ARRAY_SIZE(uart_config))
1952 type = 0;
1953 return uart_config[type].name;
1954 }
1955
1956 static struct uart_ops serial8250_pops = {
1957 .tx_empty = serial8250_tx_empty,
1958 .set_mctrl = serial8250_set_mctrl,
1959 .get_mctrl = serial8250_get_mctrl,
1960 .stop_tx = serial8250_stop_tx,
1961 .start_tx = serial8250_start_tx,
1962 .stop_rx = serial8250_stop_rx,
1963 .enable_ms = serial8250_enable_ms,
1964 .break_ctl = serial8250_break_ctl,
1965 .startup = serial8250_startup,
1966 .shutdown = serial8250_shutdown,
1967 .set_termios = serial8250_set_termios,
1968 .pm = serial8250_pm,
1969 .type = serial8250_type,
1970 .release_port = serial8250_release_port,
1971 .request_port = serial8250_request_port,
1972 .config_port = serial8250_config_port,
1973 .verify_port = serial8250_verify_port,
1974 };
1975
1976 static struct uart_8250_port serial8250_ports[UART_NR];
1977
1978 static void __init serial8250_isa_init_ports(void)
1979 {
1980 struct uart_8250_port *up;
1981 static int first = 1;
1982 int i;
1983
1984 if (!first)
1985 return;
1986 first = 0;
1987
1988 for (i = 0; i < UART_NR; i++) {
1989 struct uart_8250_port *up = &serial8250_ports[i];
1990
1991 up->port.line = i;
1992 spin_lock_init(&up->port.lock);
1993
1994 init_timer(&up->timer);
1995 up->timer.function = serial8250_timeout;
1996
1997 /*
1998 * ALPHA_KLUDGE_MCR needs to be killed.
1999 */
2000 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2001 up->mcr_force = ALPHA_KLUDGE_MCR;
2002
2003 up->port.ops = &serial8250_pops;
2004 }
2005
2006 for (i = 0, up = serial8250_ports; i < ARRAY_SIZE(old_serial_port);
2007 i++, up++) {
2008 up->port.iobase = old_serial_port[i].port;
2009 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2010 up->port.uartclk = old_serial_port[i].baud_base * 16;
2011 up->port.flags = old_serial_port[i].flags;
2012 up->port.hub6 = old_serial_port[i].hub6;
2013 up->port.membase = old_serial_port[i].iomem_base;
2014 up->port.iotype = old_serial_port[i].io_type;
2015 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2016 if (share_irqs)
2017 up->port.flags |= UPF_SHARE_IRQ;
2018 }
2019 }
2020
2021 static void __init
2022 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2023 {
2024 int i;
2025
2026 serial8250_isa_init_ports();
2027
2028 for (i = 0; i < UART_NR; i++) {
2029 struct uart_8250_port *up = &serial8250_ports[i];
2030
2031 up->port.dev = dev;
2032 uart_add_one_port(drv, &up->port);
2033 }
2034 }
2035
2036 #ifdef CONFIG_SERIAL_8250_CONSOLE
2037
2038 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
2039
2040 /*
2041 * Wait for transmitter & holding register to empty
2042 */
2043 static inline void wait_for_xmitr(struct uart_8250_port *up)
2044 {
2045 unsigned int status, tmout = 10000;
2046
2047 /* Wait up to 10ms for the character(s) to be sent. */
2048 do {
2049 status = serial_in(up, UART_LSR);
2050
2051 if (status & UART_LSR_BI)
2052 up->lsr_break_flag = UART_LSR_BI;
2053
2054 if (--tmout == 0)
2055 break;
2056 udelay(1);
2057 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
2058
2059 /* Wait up to 1s for flow control if necessary */
2060 if (up->port.flags & UPF_CONS_FLOW) {
2061 tmout = 1000000;
2062 while (--tmout &&
2063 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
2064 udelay(1);
2065 }
2066 }
2067
2068 /*
2069 * Print a string to the serial port trying not to disturb
2070 * any possible real use of the port...
2071 *
2072 * The console_lock must be held when we get here.
2073 */
2074 static void
2075 serial8250_console_write(struct console *co, const char *s, unsigned int count)
2076 {
2077 struct uart_8250_port *up = &serial8250_ports[co->index];
2078 unsigned int ier;
2079 int i;
2080
2081 /*
2082 * First save the UER then disable the interrupts
2083 */
2084 ier = serial_in(up, UART_IER);
2085
2086 if (up->port.type == PORT_XSCALE)
2087 serial_out(up, UART_IER, UART_IER_UUE);
2088 else
2089 serial_out(up, UART_IER, 0);
2090
2091 /*
2092 * Now, do each character
2093 */
2094 for (i = 0; i < count; i++, s++) {
2095 wait_for_xmitr(up);
2096
2097 /*
2098 * Send the character out.
2099 * If a LF, also do CR...
2100 */
2101 serial_out(up, UART_TX, *s);
2102 if (*s == 10) {
2103 wait_for_xmitr(up);
2104 serial_out(up, UART_TX, 13);
2105 }
2106 }
2107
2108 /*
2109 * Finally, wait for transmitter to become empty
2110 * and restore the IER
2111 */
2112 wait_for_xmitr(up);
2113 serial_out(up, UART_IER, ier);
2114 }
2115
2116 static int serial8250_console_setup(struct console *co, char *options)
2117 {
2118 struct uart_port *port;
2119 int baud = 9600;
2120 int bits = 8;
2121 int parity = 'n';
2122 int flow = 'n';
2123
2124 /*
2125 * Check whether an invalid uart number has been specified, and
2126 * if so, search for the first available port that does have
2127 * console support.
2128 */
2129 if (co->index >= UART_NR)
2130 co->index = 0;
2131 port = &serial8250_ports[co->index].port;
2132 if (!port->iobase && !port->membase)
2133 return -ENODEV;
2134
2135 if (options)
2136 uart_parse_options(options, &baud, &parity, &bits, &flow);
2137
2138 return uart_set_options(port, co, baud, parity, bits, flow);
2139 }
2140
2141 static struct uart_driver serial8250_reg;
2142 static struct console serial8250_console = {
2143 .name = "ttyS",
2144 .write = serial8250_console_write,
2145 .device = uart_console_device,
2146 .setup = serial8250_console_setup,
2147 .flags = CON_PRINTBUFFER,
2148 .index = -1,
2149 .data = &serial8250_reg,
2150 };
2151
2152 static int __init serial8250_console_init(void)
2153 {
2154 serial8250_isa_init_ports();
2155 register_console(&serial8250_console);
2156 return 0;
2157 }
2158 console_initcall(serial8250_console_init);
2159
2160 static int __init serial8250_late_console_init(void)
2161 {
2162 if (!(serial8250_console.flags & CON_ENABLED))
2163 register_console(&serial8250_console);
2164 return 0;
2165 }
2166 late_initcall(serial8250_late_console_init);
2167
2168 static int __init find_port(struct uart_port *p)
2169 {
2170 int line;
2171 struct uart_port *port;
2172
2173 for (line = 0; line < UART_NR; line++) {
2174 port = &serial8250_ports[line].port;
2175 if (p->iotype == port->iotype &&
2176 p->iobase == port->iobase &&
2177 p->membase == port->membase)
2178 return line;
2179 }
2180 return -ENODEV;
2181 }
2182
2183 int __init serial8250_start_console(struct uart_port *port, char *options)
2184 {
2185 int line;
2186
2187 line = find_port(port);
2188 if (line < 0)
2189 return -ENODEV;
2190
2191 add_preferred_console("ttyS", line, options);
2192 printk("Adding console on ttyS%d at %s 0x%lx (options '%s')\n",
2193 line, port->iotype == UPIO_MEM ? "MMIO" : "I/O port",
2194 port->iotype == UPIO_MEM ? (unsigned long) port->mapbase :
2195 (unsigned long) port->iobase, options);
2196 if (!(serial8250_console.flags & CON_ENABLED)) {
2197 serial8250_console.flags &= ~CON_PRINTBUFFER;
2198 register_console(&serial8250_console);
2199 }
2200 return line;
2201 }
2202
2203 #define SERIAL8250_CONSOLE &serial8250_console
2204 #else
2205 #define SERIAL8250_CONSOLE NULL
2206 #endif
2207
2208 static struct uart_driver serial8250_reg = {
2209 .owner = THIS_MODULE,
2210 .driver_name = "serial",
2211 .devfs_name = "tts/",
2212 .dev_name = "ttyS",
2213 .major = TTY_MAJOR,
2214 .minor = 64,
2215 .nr = UART_NR,
2216 .cons = SERIAL8250_CONSOLE,
2217 };
2218
2219 int __init early_serial_setup(struct uart_port *port)
2220 {
2221 if (port->line >= ARRAY_SIZE(serial8250_ports))
2222 return -ENODEV;
2223
2224 serial8250_isa_init_ports();
2225 serial8250_ports[port->line].port = *port;
2226 serial8250_ports[port->line].port.ops = &serial8250_pops;
2227 return 0;
2228 }
2229
2230 /**
2231 * serial8250_suspend_port - suspend one serial port
2232 * @line: serial line number
2233 * @level: the level of port suspension, as per uart_suspend_port
2234 *
2235 * Suspend one serial port.
2236 */
2237 void serial8250_suspend_port(int line)
2238 {
2239 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2240 }
2241
2242 /**
2243 * serial8250_resume_port - resume one serial port
2244 * @line: serial line number
2245 * @level: the level of port resumption, as per uart_resume_port
2246 *
2247 * Resume one serial port.
2248 */
2249 void serial8250_resume_port(int line)
2250 {
2251 uart_resume_port(&serial8250_reg, &serial8250_ports[line].port);
2252 }
2253
2254 /*
2255 * Register a set of serial devices attached to a platform device. The
2256 * list is terminated with a zero flags entry, which means we expect
2257 * all entries to have at least UPF_BOOT_AUTOCONF set.
2258 */
2259 static int __devinit serial8250_probe(struct device *dev)
2260 {
2261 struct plat_serial8250_port *p = dev->platform_data;
2262 struct uart_port port;
2263
2264 memset(&port, 0, sizeof(struct uart_port));
2265
2266 for (; p && p->flags != 0; p++) {
2267 port.iobase = p->iobase;
2268 port.membase = p->membase;
2269 port.irq = p->irq;
2270 port.uartclk = p->uartclk;
2271 port.regshift = p->regshift;
2272 port.iotype = p->iotype;
2273 port.flags = p->flags;
2274 port.mapbase = p->mapbase;
2275 port.dev = dev;
2276 if (share_irqs)
2277 port.flags |= UPF_SHARE_IRQ;
2278 serial8250_register_port(&port);
2279 }
2280 return 0;
2281 }
2282
2283 /*
2284 * Remove serial ports registered against a platform device.
2285 */
2286 static int __devexit serial8250_remove(struct device *dev)
2287 {
2288 int i;
2289
2290 for (i = 0; i < UART_NR; i++) {
2291 struct uart_8250_port *up = &serial8250_ports[i];
2292
2293 if (up->port.dev == dev)
2294 serial8250_unregister_port(i);
2295 }
2296 return 0;
2297 }
2298
2299 static int serial8250_suspend(struct device *dev, u32 state, u32 level)
2300 {
2301 int i;
2302
2303 if (level != SUSPEND_DISABLE)
2304 return 0;
2305
2306 for (i = 0; i < UART_NR; i++) {
2307 struct uart_8250_port *up = &serial8250_ports[i];
2308
2309 if (up->port.type != PORT_UNKNOWN && up->port.dev == dev)
2310 uart_suspend_port(&serial8250_reg, &up->port);
2311 }
2312
2313 return 0;
2314 }
2315
2316 static int serial8250_resume(struct device *dev, u32 level)
2317 {
2318 int i;
2319
2320 if (level != RESUME_ENABLE)
2321 return 0;
2322
2323 for (i = 0; i < UART_NR; i++) {
2324 struct uart_8250_port *up = &serial8250_ports[i];
2325
2326 if (up->port.type != PORT_UNKNOWN && up->port.dev == dev)
2327 uart_resume_port(&serial8250_reg, &up->port);
2328 }
2329
2330 return 0;
2331 }
2332
2333 static struct device_driver serial8250_isa_driver = {
2334 .name = "serial8250",
2335 .bus = &platform_bus_type,
2336 .probe = serial8250_probe,
2337 .remove = __devexit_p(serial8250_remove),
2338 .suspend = serial8250_suspend,
2339 .resume = serial8250_resume,
2340 };
2341
2342 /*
2343 * This "device" covers _all_ ISA 8250-compatible serial devices listed
2344 * in the table in include/asm/serial.h
2345 */
2346 static struct platform_device *serial8250_isa_devs;
2347
2348 /*
2349 * serial8250_register_port and serial8250_unregister_port allows for
2350 * 16x50 serial ports to be configured at run-time, to support PCMCIA
2351 * modems and PCI multiport cards.
2352 */
2353 static DECLARE_MUTEX(serial_sem);
2354
2355 /*
2356 * Are the two ports equivalent?
2357 */
2358 static int uart_match_port(struct uart_port *port1, struct uart_port *port2)
2359 {
2360 if (port1->iotype != port2->iotype)
2361 return 0;
2362
2363 switch (port1->iotype) {
2364 case UPIO_PORT:
2365 return (port1->iobase == port2->iobase);
2366 case UPIO_HUB6:
2367 return (port1->iobase == port2->iobase) &&
2368 (port1->hub6 == port2->hub6);
2369 case UPIO_MEM:
2370 return (port1->membase == port2->membase);
2371 }
2372 return 0;
2373 }
2374
2375 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
2376 {
2377 int i;
2378
2379 /*
2380 * First, find a port entry which matches.
2381 */
2382 for (i = 0; i < UART_NR; i++)
2383 if (uart_match_port(&serial8250_ports[i].port, port))
2384 return &serial8250_ports[i];
2385
2386 /*
2387 * We didn't find a matching entry, so look for the first
2388 * free entry. We look for one which hasn't been previously
2389 * used (indicated by zero iobase).
2390 */
2391 for (i = 0; i < UART_NR; i++)
2392 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
2393 serial8250_ports[i].port.iobase == 0)
2394 return &serial8250_ports[i];
2395
2396 /*
2397 * That also failed. Last resort is to find any entry which
2398 * doesn't have a real port associated with it.
2399 */
2400 for (i = 0; i < UART_NR; i++)
2401 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
2402 return &serial8250_ports[i];
2403
2404 return NULL;
2405 }
2406
2407 /**
2408 * serial8250_register_port - register a serial port
2409 * @port: serial port template
2410 *
2411 * Configure the serial port specified by the request. If the
2412 * port exists and is in use, it is hung up and unregistered
2413 * first.
2414 *
2415 * The port is then probed and if necessary the IRQ is autodetected
2416 * If this fails an error is returned.
2417 *
2418 * On success the port is ready to use and the line number is returned.
2419 */
2420 int serial8250_register_port(struct uart_port *port)
2421 {
2422 struct uart_8250_port *uart;
2423 int ret = -ENOSPC;
2424
2425 if (port->uartclk == 0)
2426 return -EINVAL;
2427
2428 down(&serial_sem);
2429
2430 uart = serial8250_find_match_or_unused(port);
2431 if (uart) {
2432 uart_remove_one_port(&serial8250_reg, &uart->port);
2433
2434 uart->port.iobase = port->iobase;
2435 uart->port.membase = port->membase;
2436 uart->port.irq = port->irq;
2437 uart->port.uartclk = port->uartclk;
2438 uart->port.fifosize = port->fifosize;
2439 uart->port.regshift = port->regshift;
2440 uart->port.iotype = port->iotype;
2441 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
2442 uart->port.mapbase = port->mapbase;
2443 if (port->dev)
2444 uart->port.dev = port->dev;
2445
2446 ret = uart_add_one_port(&serial8250_reg, &uart->port);
2447 if (ret == 0)
2448 ret = uart->port.line;
2449 }
2450 up(&serial_sem);
2451
2452 return ret;
2453 }
2454 EXPORT_SYMBOL(serial8250_register_port);
2455
2456 /**
2457 * serial8250_unregister_port - remove a 16x50 serial port at runtime
2458 * @line: serial line number
2459 *
2460 * Remove one serial port. This may not be called from interrupt
2461 * context. We hand the port back to the our control.
2462 */
2463 void serial8250_unregister_port(int line)
2464 {
2465 struct uart_8250_port *uart = &serial8250_ports[line];
2466
2467 down(&serial_sem);
2468 uart_remove_one_port(&serial8250_reg, &uart->port);
2469 if (serial8250_isa_devs) {
2470 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
2471 uart->port.type = PORT_UNKNOWN;
2472 uart->port.dev = &serial8250_isa_devs->dev;
2473 uart_add_one_port(&serial8250_reg, &uart->port);
2474 } else {
2475 uart->port.dev = NULL;
2476 }
2477 up(&serial_sem);
2478 }
2479 EXPORT_SYMBOL(serial8250_unregister_port);
2480
2481 static int __init serial8250_init(void)
2482 {
2483 int ret, i;
2484
2485 printk(KERN_INFO "Serial: 8250/16550 driver $Revision: 1.90 $ "
2486 "%d ports, IRQ sharing %sabled\n", (int) UART_NR,
2487 share_irqs ? "en" : "dis");
2488
2489 for (i = 0; i < NR_IRQS; i++)
2490 spin_lock_init(&irq_lists[i].lock);
2491
2492 ret = uart_register_driver(&serial8250_reg);
2493 if (ret)
2494 goto out;
2495
2496 serial8250_isa_devs = platform_device_register_simple("serial8250",
2497 -1, NULL, 0);
2498 if (IS_ERR(serial8250_isa_devs)) {
2499 ret = PTR_ERR(serial8250_isa_devs);
2500 goto unreg;
2501 }
2502
2503 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
2504
2505 ret = driver_register(&serial8250_isa_driver);
2506 if (ret == 0)
2507 goto out;
2508
2509 platform_device_unregister(serial8250_isa_devs);
2510 unreg:
2511 uart_unregister_driver(&serial8250_reg);
2512 out:
2513 return ret;
2514 }
2515
2516 static void __exit serial8250_exit(void)
2517 {
2518 struct platform_device *isa_dev = serial8250_isa_devs;
2519
2520 /*
2521 * This tells serial8250_unregister_port() not to re-register
2522 * the ports (thereby making serial8250_isa_driver permanently
2523 * in use.)
2524 */
2525 serial8250_isa_devs = NULL;
2526
2527 driver_unregister(&serial8250_isa_driver);
2528 platform_device_unregister(isa_dev);
2529
2530 uart_unregister_driver(&serial8250_reg);
2531 }
2532
2533 module_init(serial8250_init);
2534 module_exit(serial8250_exit);
2535
2536 EXPORT_SYMBOL(serial8250_suspend_port);
2537 EXPORT_SYMBOL(serial8250_resume_port);
2538
2539 MODULE_LICENSE("GPL");
2540 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver $Revision: 1.90 $");
2541
2542 module_param(share_irqs, uint, 0644);
2543 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
2544 " (unsafe)");
2545
2546 #ifdef CONFIG_SERIAL_8250_RSA
2547 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
2548 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
2549 #endif
2550 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
2551
2552 /**
2553 * register_serial - configure a 16x50 serial port at runtime
2554 * @req: request structure
2555 *
2556 * Configure the serial port specified by the request. If the
2557 * port exists and is in use an error is returned. If the port
2558 * is not currently in the table it is added.
2559 *
2560 * The port is then probed and if necessary the IRQ is autodetected
2561 * If this fails an error is returned.
2562 *
2563 * On success the port is ready to use and the line number is returned.
2564 */
2565 int register_serial(struct serial_struct *req)
2566 {
2567 struct uart_port port;
2568
2569 port.iobase = req->port;
2570 port.membase = req->iomem_base;
2571 port.irq = req->irq;
2572 port.uartclk = req->baud_base * 16;
2573 port.fifosize = req->xmit_fifo_size;
2574 port.regshift = req->iomem_reg_shift;
2575 port.iotype = req->io_type;
2576 port.flags = req->flags | UPF_BOOT_AUTOCONF;
2577 port.mapbase = req->iomap_base;
2578 port.dev = NULL;
2579
2580 if (share_irqs)
2581 port.flags |= UPF_SHARE_IRQ;
2582
2583 if (HIGH_BITS_OFFSET)
2584 port.iobase |= (long) req->port_high << HIGH_BITS_OFFSET;
2585
2586 /*
2587 * If a clock rate wasn't specified by the low level driver, then
2588 * default to the standard clock rate. This should be 115200 (*16)
2589 * and should not depend on the architecture's BASE_BAUD definition.
2590 * However, since this API will be deprecated, it's probably a
2591 * better idea to convert the drivers to use the new API
2592 * (serial8250_register_port and serial8250_unregister_port).
2593 */
2594 if (port.uartclk == 0) {
2595 printk(KERN_WARNING
2596 "Serial: registering port at [%08x,%08lx,%p] irq %d with zero baud_base\n",
2597 port.iobase, port.mapbase, port.membase, port.irq);
2598 printk(KERN_WARNING "Serial: see %s:%d for more information\n",
2599 __FILE__, __LINE__);
2600 dump_stack();
2601
2602 /*
2603 * Fix it up for now, but this is only a temporary measure.
2604 */
2605 port.uartclk = BASE_BAUD * 16;
2606 }
2607
2608 return serial8250_register_port(&port);
2609 }
2610 EXPORT_SYMBOL(register_serial);
2611
2612 /**
2613 * unregister_serial - remove a 16x50 serial port at runtime
2614 * @line: serial line number
2615 *
2616 * Remove one serial port. This may not be called from interrupt
2617 * context. We hand the port back to our local PM control.
2618 */
2619 void unregister_serial(int line)
2620 {
2621 serial8250_unregister_port(line);
2622 }
2623 EXPORT_SYMBOL(unregister_serial);
2624
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