1 /*
2 * linux/drivers/char/8250.c
3 *
4 * Driver for 8250/16550-type serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * A note about mapbase / membase
16 *
17 * mapbase is the physical address of the IO port.
18 * membase is an 'ioremapped' cookie.
19 */
20
21 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22 #define SUPPORT_SYSRQ
23 #endif
24
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/ioport.h>
28 #include <linux/init.h>
29 #include <linux/console.h>
30 #include <linux/sysrq.h>
31 #include <linux/delay.h>
32 #include <linux/platform_device.h>
33 #include <linux/tty.h>
34 #include <linux/tty_flip.h>
35 #include <linux/serial_reg.h>
36 #include <linux/serial_core.h>
37 #include <linux/serial.h>
38 #include <linux/serial_8250.h>
39 #include <linux/nmi.h>
40 #include <linux/mutex.h>
41
42 #include <asm/io.h>
43 #include <asm/irq.h>
44
45 #include "8250.h"
46
47 #ifdef CONFIG_SPARC
48 #include "suncore.h"
49 #endif
50
51 /*
52 * Configuration:
53 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
54 * is unsafe when used on edge-triggered interrupts.
55 */
56 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
57
58 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
59
60 static struct uart_driver serial8250_reg;
61
62 static int serial_index(struct uart_port *port)
63 {
64 return (serial8250_reg.minor - 64) + port->line;
65 }
66
67 /*
68 * Debugging.
69 */
70 #if 0
71 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
72 #else
73 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
74 #endif
75
76 #if 0
77 #define DEBUG_INTR(fmt...) printk(fmt)
78 #else
79 #define DEBUG_INTR(fmt...) do { } while (0)
80 #endif
81
82 #define PASS_LIMIT 256
83
84 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
85
86
87 /*
88 * We default to IRQ0 for the "no irq" hack. Some
89 * machine types want others as well - they're free
90 * to redefine this in their header file.
91 */
92 #define is_real_interrupt(irq) ((irq) != 0)
93
94 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
95 #define CONFIG_SERIAL_DETECT_IRQ 1
96 #endif
97 #ifdef CONFIG_SERIAL_8250_MANY_PORTS
98 #define CONFIG_SERIAL_MANY_PORTS 1
99 #endif
100
101 /*
102 * HUB6 is always on. This will be removed once the header
103 * files have been cleaned.
104 */
105 #define CONFIG_HUB6 1
106
107 #include <asm/serial.h>
108 /*
109 * SERIAL_PORT_DFNS tells us about built-in ports that have no
110 * standard enumeration mechanism. Platforms that can find all
111 * serial ports via mechanisms like ACPI or PCI need not supply it.
112 */
113 #ifndef SERIAL_PORT_DFNS
114 #define SERIAL_PORT_DFNS
115 #endif
116
117 static const struct old_serial_port old_serial_port[] = {
118 SERIAL_PORT_DFNS /* defined in asm/serial.h */
119 };
120
121 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
122
123 #ifdef CONFIG_SERIAL_8250_RSA
124
125 #define PORT_RSA_MAX 4
126 static unsigned long probe_rsa[PORT_RSA_MAX];
127 static unsigned int probe_rsa_count;
128 #endif /* CONFIG_SERIAL_8250_RSA */
129
130 struct uart_8250_port {
131 struct uart_port port;
132 struct timer_list timer; /* "no irq" timer */
133 struct list_head list; /* ports on this IRQ */
134 unsigned short capabilities; /* port capabilities */
135 unsigned short bugs; /* port bugs */
136 unsigned int tx_loadsz; /* transmit fifo load size */
137 unsigned char acr;
138 unsigned char ier;
139 unsigned char lcr;
140 unsigned char mcr;
141 unsigned char mcr_mask; /* mask of user bits */
142 unsigned char mcr_force; /* mask of forced bits */
143 unsigned char cur_iotype; /* Running I/O type */
144
145 /*
146 * Some bits in registers are cleared on a read, so they must
147 * be saved whenever the register is read but the bits will not
148 * be immediately processed.
149 */
150 #define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
151 unsigned char lsr_saved_flags;
152 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
153 unsigned char msr_saved_flags;
154
155 /*
156 * We provide a per-port pm hook.
157 */
158 void (*pm)(struct uart_port *port,
159 unsigned int state, unsigned int old);
160 };
161
162 struct irq_info {
163 struct hlist_node node;
164 int irq;
165 spinlock_t lock; /* Protects list not the hash */
166 struct list_head *head;
167 };
168
169 #define NR_IRQ_HASH 32 /* Can be adjusted later */
170 static struct hlist_head irq_lists[NR_IRQ_HASH];
171 static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
172
173 /*
174 * Here we define the default xmit fifo size used for each type of UART.
175 */
176 static const struct serial8250_config uart_config[] = {
177 [PORT_UNKNOWN] = {
178 .name = "unknown",
179 .fifo_size = 1,
180 .tx_loadsz = 1,
181 },
182 [PORT_8250] = {
183 .name = "8250",
184 .fifo_size = 1,
185 .tx_loadsz = 1,
186 },
187 [PORT_16450] = {
188 .name = "16450",
189 .fifo_size = 1,
190 .tx_loadsz = 1,
191 },
192 [PORT_16550] = {
193 .name = "16550",
194 .fifo_size = 1,
195 .tx_loadsz = 1,
196 },
197 [PORT_16550A] = {
198 .name = "16550A",
199 .fifo_size = 16,
200 .tx_loadsz = 16,
201 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
202 .flags = UART_CAP_FIFO,
203 },
204 [PORT_CIRRUS] = {
205 .name = "Cirrus",
206 .fifo_size = 1,
207 .tx_loadsz = 1,
208 },
209 [PORT_16650] = {
210 .name = "ST16650",
211 .fifo_size = 1,
212 .tx_loadsz = 1,
213 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
214 },
215 [PORT_16650V2] = {
216 .name = "ST16650V2",
217 .fifo_size = 32,
218 .tx_loadsz = 16,
219 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
220 UART_FCR_T_TRIG_00,
221 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
222 },
223 [PORT_16750] = {
224 .name = "TI16750",
225 .fifo_size = 64,
226 .tx_loadsz = 64,
227 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
228 UART_FCR7_64BYTE,
229 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
230 },
231 [PORT_STARTECH] = {
232 .name = "Startech",
233 .fifo_size = 1,
234 .tx_loadsz = 1,
235 },
236 [PORT_16C950] = {
237 .name = "16C950/954",
238 .fifo_size = 128,
239 .tx_loadsz = 128,
240 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
241 .flags = UART_CAP_FIFO,
242 },
243 [PORT_16654] = {
244 .name = "ST16654",
245 .fifo_size = 64,
246 .tx_loadsz = 32,
247 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
248 UART_FCR_T_TRIG_10,
249 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
250 },
251 [PORT_16850] = {
252 .name = "XR16850",
253 .fifo_size = 128,
254 .tx_loadsz = 128,
255 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
256 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
257 },
258 [PORT_RSA] = {
259 .name = "RSA",
260 .fifo_size = 2048,
261 .tx_loadsz = 2048,
262 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
263 .flags = UART_CAP_FIFO,
264 },
265 [PORT_NS16550A] = {
266 .name = "NS16550A",
267 .fifo_size = 16,
268 .tx_loadsz = 16,
269 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
270 .flags = UART_CAP_FIFO | UART_NATSEMI,
271 },
272 [PORT_XSCALE] = {
273 .name = "XScale",
274 .fifo_size = 32,
275 .tx_loadsz = 32,
276 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
277 .flags = UART_CAP_FIFO | UART_CAP_UUE,
278 },
279 [PORT_RM9000] = {
280 .name = "RM9000",
281 .fifo_size = 16,
282 .tx_loadsz = 16,
283 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
284 .flags = UART_CAP_FIFO,
285 },
286 [PORT_OCTEON] = {
287 .name = "OCTEON",
288 .fifo_size = 64,
289 .tx_loadsz = 64,
290 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
291 .flags = UART_CAP_FIFO,
292 },
293 [PORT_AR7] = {
294 .name = "AR7",
295 .fifo_size = 16,
296 .tx_loadsz = 16,
297 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
298 .flags = UART_CAP_FIFO | UART_CAP_AFE,
299 },
300 };
301
302 #if defined (CONFIG_SERIAL_8250_AU1X00)
303
304 /* Au1x00 UART hardware has a weird register layout */
305 static const u8 au_io_in_map[] = {
306 [UART_RX] = 0,
307 [UART_IER] = 2,
308 [UART_IIR] = 3,
309 [UART_LCR] = 5,
310 [UART_MCR] = 6,
311 [UART_LSR] = 7,
312 [UART_MSR] = 8,
313 };
314
315 static const u8 au_io_out_map[] = {
316 [UART_TX] = 1,
317 [UART_IER] = 2,
318 [UART_FCR] = 4,
319 [UART_LCR] = 5,
320 [UART_MCR] = 6,
321 };
322
323 /* sane hardware needs no mapping */
324 static inline int map_8250_in_reg(struct uart_port *p, int offset)
325 {
326 if (p->iotype != UPIO_AU)
327 return offset;
328 return au_io_in_map[offset];
329 }
330
331 static inline int map_8250_out_reg(struct uart_port *p, int offset)
332 {
333 if (p->iotype != UPIO_AU)
334 return offset;
335 return au_io_out_map[offset];
336 }
337
338 #elif defined(CONFIG_SERIAL_8250_RM9K)
339
340 static const u8
341 regmap_in[8] = {
342 [UART_RX] = 0x00,
343 [UART_IER] = 0x0c,
344 [UART_IIR] = 0x14,
345 [UART_LCR] = 0x1c,
346 [UART_MCR] = 0x20,
347 [UART_LSR] = 0x24,
348 [UART_MSR] = 0x28,
349 [UART_SCR] = 0x2c
350 },
351 regmap_out[8] = {
352 [UART_TX] = 0x04,
353 [UART_IER] = 0x0c,
354 [UART_FCR] = 0x18,
355 [UART_LCR] = 0x1c,
356 [UART_MCR] = 0x20,
357 [UART_LSR] = 0x24,
358 [UART_MSR] = 0x28,
359 [UART_SCR] = 0x2c
360 };
361
362 static inline int map_8250_in_reg(struct uart_port *p, int offset)
363 {
364 if (p->iotype != UPIO_RM9000)
365 return offset;
366 return regmap_in[offset];
367 }
368
369 static inline int map_8250_out_reg(struct uart_port *p, int offset)
370 {
371 if (p->iotype != UPIO_RM9000)
372 return offset;
373 return regmap_out[offset];
374 }
375
376 #else
377
378 /* sane hardware needs no mapping */
379 #define map_8250_in_reg(up, offset) (offset)
380 #define map_8250_out_reg(up, offset) (offset)
381
382 #endif
383
384 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
385 {
386 offset = map_8250_in_reg(p, offset) << p->regshift;
387 outb(p->hub6 - 1 + offset, p->iobase);
388 return inb(p->iobase + 1);
389 }
390
391 static void hub6_serial_out(struct uart_port *p, int offset, int value)
392 {
393 offset = map_8250_out_reg(p, offset) << p->regshift;
394 outb(p->hub6 - 1 + offset, p->iobase);
395 outb(value, p->iobase + 1);
396 }
397
398 static unsigned int mem_serial_in(struct uart_port *p, int offset)
399 {
400 offset = map_8250_in_reg(p, offset) << p->regshift;
401 return readb(p->membase + offset);
402 }
403
404 static void mem_serial_out(struct uart_port *p, int offset, int value)
405 {
406 offset = map_8250_out_reg(p, offset) << p->regshift;
407 writeb(value, p->membase + offset);
408 }
409
410 static void mem32_serial_out(struct uart_port *p, int offset, int value)
411 {
412 offset = map_8250_out_reg(p, offset) << p->regshift;
413 writel(value, p->membase + offset);
414 }
415
416 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
417 {
418 offset = map_8250_in_reg(p, offset) << p->regshift;
419 return readl(p->membase + offset);
420 }
421
422 #ifdef CONFIG_SERIAL_8250_AU1X00
423 static unsigned int au_serial_in(struct uart_port *p, int offset)
424 {
425 offset = map_8250_in_reg(p, offset) << p->regshift;
426 return __raw_readl(p->membase + offset);
427 }
428
429 static void au_serial_out(struct uart_port *p, int offset, int value)
430 {
431 offset = map_8250_out_reg(p, offset) << p->regshift;
432 __raw_writel(value, p->membase + offset);
433 }
434 #endif
435
436 static unsigned int tsi_serial_in(struct uart_port *p, int offset)
437 {
438 unsigned int tmp;
439 offset = map_8250_in_reg(p, offset) << p->regshift;
440 if (offset == UART_IIR) {
441 tmp = readl(p->membase + (UART_IIR & ~3));
442 return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
443 } else
444 return readb(p->membase + offset);
445 }
446
447 static void tsi_serial_out(struct uart_port *p, int offset, int value)
448 {
449 offset = map_8250_out_reg(p, offset) << p->regshift;
450 if (!((offset == UART_IER) && (value & UART_IER_UUE)))
451 writeb(value, p->membase + offset);
452 }
453
454 static void dwapb_serial_out(struct uart_port *p, int offset, int value)
455 {
456 int save_offset = offset;
457 offset = map_8250_out_reg(p, offset) << p->regshift;
458 /* Save the LCR value so it can be re-written when a
459 * Busy Detect interrupt occurs. */
460 if (save_offset == UART_LCR) {
461 struct uart_8250_port *up = (struct uart_8250_port *)p;
462 up->lcr = value;
463 }
464 writeb(value, p->membase + offset);
465 /* Read the IER to ensure any interrupt is cleared before
466 * returning from ISR. */
467 if (save_offset == UART_TX || save_offset == UART_IER)
468 value = p->serial_in(p, UART_IER);
469 }
470
471 static unsigned int io_serial_in(struct uart_port *p, int offset)
472 {
473 offset = map_8250_in_reg(p, offset) << p->regshift;
474 return inb(p->iobase + offset);
475 }
476
477 static void io_serial_out(struct uart_port *p, int offset, int value)
478 {
479 offset = map_8250_out_reg(p, offset) << p->regshift;
480 outb(value, p->iobase + offset);
481 }
482
483 static void set_io_from_upio(struct uart_port *p)
484 {
485 struct uart_8250_port *up = (struct uart_8250_port *)p;
486 switch (p->iotype) {
487 case UPIO_HUB6:
488 p->serial_in = hub6_serial_in;
489 p->serial_out = hub6_serial_out;
490 break;
491
492 case UPIO_MEM:
493 p->serial_in = mem_serial_in;
494 p->serial_out = mem_serial_out;
495 break;
496
497 case UPIO_RM9000:
498 case UPIO_MEM32:
499 p->serial_in = mem32_serial_in;
500 p->serial_out = mem32_serial_out;
501 break;
502
503 #ifdef CONFIG_SERIAL_8250_AU1X00
504 case UPIO_AU:
505 p->serial_in = au_serial_in;
506 p->serial_out = au_serial_out;
507 break;
508 #endif
509 case UPIO_TSI:
510 p->serial_in = tsi_serial_in;
511 p->serial_out = tsi_serial_out;
512 break;
513
514 case UPIO_DWAPB:
515 p->serial_in = mem_serial_in;
516 p->serial_out = dwapb_serial_out;
517 break;
518
519 default:
520 p->serial_in = io_serial_in;
521 p->serial_out = io_serial_out;
522 break;
523 }
524 /* Remember loaded iotype */
525 up->cur_iotype = p->iotype;
526 }
527
528 static void
529 serial_out_sync(struct uart_8250_port *up, int offset, int value)
530 {
531 struct uart_port *p = &up->port;
532 switch (p->iotype) {
533 case UPIO_MEM:
534 case UPIO_MEM32:
535 #ifdef CONFIG_SERIAL_8250_AU1X00
536 case UPIO_AU:
537 #endif
538 case UPIO_DWAPB:
539 p->serial_out(p, offset, value);
540 p->serial_in(p, UART_LCR); /* safe, no side-effects */
541 break;
542 default:
543 p->serial_out(p, offset, value);
544 }
545 }
546
547 #define serial_in(up, offset) \
548 (up->port.serial_in(&(up)->port, (offset)))
549 #define serial_out(up, offset, value) \
550 (up->port.serial_out(&(up)->port, (offset), (value)))
551 /*
552 * We used to support using pause I/O for certain machines. We
553 * haven't supported this for a while, but just in case it's badly
554 * needed for certain old 386 machines, I've left these #define's
555 * in....
556 */
557 #define serial_inp(up, offset) serial_in(up, offset)
558 #define serial_outp(up, offset, value) serial_out(up, offset, value)
559
560 /* Uart divisor latch read */
561 static inline int _serial_dl_read(struct uart_8250_port *up)
562 {
563 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
564 }
565
566 /* Uart divisor latch write */
567 static inline void _serial_dl_write(struct uart_8250_port *up, int value)
568 {
569 serial_outp(up, UART_DLL, value & 0xff);
570 serial_outp(up, UART_DLM, value >> 8 & 0xff);
571 }
572
573 #if defined(CONFIG_SERIAL_8250_AU1X00)
574 /* Au1x00 haven't got a standard divisor latch */
575 static int serial_dl_read(struct uart_8250_port *up)
576 {
577 if (up->port.iotype == UPIO_AU)
578 return __raw_readl(up->port.membase + 0x28);
579 else
580 return _serial_dl_read(up);
581 }
582
583 static void serial_dl_write(struct uart_8250_port *up, int value)
584 {
585 if (up->port.iotype == UPIO_AU)
586 __raw_writel(value, up->port.membase + 0x28);
587 else
588 _serial_dl_write(up, value);
589 }
590 #elif defined(CONFIG_SERIAL_8250_RM9K)
591 static int serial_dl_read(struct uart_8250_port *up)
592 {
593 return (up->port.iotype == UPIO_RM9000) ?
594 (((__raw_readl(up->port.membase + 0x10) << 8) |
595 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
596 _serial_dl_read(up);
597 }
598
599 static void serial_dl_write(struct uart_8250_port *up, int value)
600 {
601 if (up->port.iotype == UPIO_RM9000) {
602 __raw_writel(value, up->port.membase + 0x08);
603 __raw_writel(value >> 8, up->port.membase + 0x10);
604 } else {
605 _serial_dl_write(up, value);
606 }
607 }
608 #else
609 #define serial_dl_read(up) _serial_dl_read(up)
610 #define serial_dl_write(up, value) _serial_dl_write(up, value)
611 #endif
612
613 /*
614 * For the 16C950
615 */
616 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
617 {
618 serial_out(up, UART_SCR, offset);
619 serial_out(up, UART_ICR, value);
620 }
621
622 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
623 {
624 unsigned int value;
625
626 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
627 serial_out(up, UART_SCR, offset);
628 value = serial_in(up, UART_ICR);
629 serial_icr_write(up, UART_ACR, up->acr);
630
631 return value;
632 }
633
634 /*
635 * FIFO support.
636 */
637 static void serial8250_clear_fifos(struct uart_8250_port *p)
638 {
639 if (p->capabilities & UART_CAP_FIFO) {
640 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
641 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
642 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
643 serial_outp(p, UART_FCR, 0);
644 }
645 }
646
647 /*
648 * IER sleep support. UARTs which have EFRs need the "extended
649 * capability" bit enabled. Note that on XR16C850s, we need to
650 * reset LCR to write to IER.
651 */
652 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
653 {
654 if (p->capabilities & UART_CAP_SLEEP) {
655 if (p->capabilities & UART_CAP_EFR) {
656 serial_outp(p, UART_LCR, 0xBF);
657 serial_outp(p, UART_EFR, UART_EFR_ECB);
658 serial_outp(p, UART_LCR, 0);
659 }
660 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
661 if (p->capabilities & UART_CAP_EFR) {
662 serial_outp(p, UART_LCR, 0xBF);
663 serial_outp(p, UART_EFR, 0);
664 serial_outp(p, UART_LCR, 0);
665 }
666 }
667 }
668
669 #ifdef CONFIG_SERIAL_8250_RSA
670 /*
671 * Attempts to turn on the RSA FIFO. Returns zero on failure.
672 * We set the port uart clock rate if we succeed.
673 */
674 static int __enable_rsa(struct uart_8250_port *up)
675 {
676 unsigned char mode;
677 int result;
678
679 mode = serial_inp(up, UART_RSA_MSR);
680 result = mode & UART_RSA_MSR_FIFO;
681
682 if (!result) {
683 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
684 mode = serial_inp(up, UART_RSA_MSR);
685 result = mode & UART_RSA_MSR_FIFO;
686 }
687
688 if (result)
689 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
690
691 return result;
692 }
693
694 static void enable_rsa(struct uart_8250_port *up)
695 {
696 if (up->port.type == PORT_RSA) {
697 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
698 spin_lock_irq(&up->port.lock);
699 __enable_rsa(up);
700 spin_unlock_irq(&up->port.lock);
701 }
702 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
703 serial_outp(up, UART_RSA_FRR, 0);
704 }
705 }
706
707 /*
708 * Attempts to turn off the RSA FIFO. Returns zero on failure.
709 * It is unknown why interrupts were disabled in here. However,
710 * the caller is expected to preserve this behaviour by grabbing
711 * the spinlock before calling this function.
712 */
713 static void disable_rsa(struct uart_8250_port *up)
714 {
715 unsigned char mode;
716 int result;
717
718 if (up->port.type == PORT_RSA &&
719 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
720 spin_lock_irq(&up->port.lock);
721
722 mode = serial_inp(up, UART_RSA_MSR);
723 result = !(mode & UART_RSA_MSR_FIFO);
724
725 if (!result) {
726 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
727 mode = serial_inp(up, UART_RSA_MSR);
728 result = !(mode & UART_RSA_MSR_FIFO);
729 }
730
731 if (result)
732 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
733 spin_unlock_irq(&up->port.lock);
734 }
735 }
736 #endif /* CONFIG_SERIAL_8250_RSA */
737
738 /*
739 * This is a quickie test to see how big the FIFO is.
740 * It doesn't work at all the time, more's the pity.
741 */
742 static int size_fifo(struct uart_8250_port *up)
743 {
744 unsigned char old_fcr, old_mcr, old_lcr;
745 unsigned short old_dl;
746 int count;
747
748 old_lcr = serial_inp(up, UART_LCR);
749 serial_outp(up, UART_LCR, 0);
750 old_fcr = serial_inp(up, UART_FCR);
751 old_mcr = serial_inp(up, UART_MCR);
752 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
753 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
754 serial_outp(up, UART_MCR, UART_MCR_LOOP);
755 serial_outp(up, UART_LCR, UART_LCR_DLAB);
756 old_dl = serial_dl_read(up);
757 serial_dl_write(up, 0x0001);
758 serial_outp(up, UART_LCR, 0x03);
759 for (count = 0; count < 256; count++)
760 serial_outp(up, UART_TX, count);
761 mdelay(20);/* FIXME - schedule_timeout */
762 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
763 (count < 256); count++)
764 serial_inp(up, UART_RX);
765 serial_outp(up, UART_FCR, old_fcr);
766 serial_outp(up, UART_MCR, old_mcr);
767 serial_outp(up, UART_LCR, UART_LCR_DLAB);
768 serial_dl_write(up, old_dl);
769 serial_outp(up, UART_LCR, old_lcr);
770
771 return count;
772 }
773
774 /*
775 * Read UART ID using the divisor method - set DLL and DLM to zero
776 * and the revision will be in DLL and device type in DLM. We
777 * preserve the device state across this.
778 */
779 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
780 {
781 unsigned char old_dll, old_dlm, old_lcr;
782 unsigned int id;
783
784 old_lcr = serial_inp(p, UART_LCR);
785 serial_outp(p, UART_LCR, UART_LCR_DLAB);
786
787 old_dll = serial_inp(p, UART_DLL);
788 old_dlm = serial_inp(p, UART_DLM);
789
790 serial_outp(p, UART_DLL, 0);
791 serial_outp(p, UART_DLM, 0);
792
793 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
794
795 serial_outp(p, UART_DLL, old_dll);
796 serial_outp(p, UART_DLM, old_dlm);
797 serial_outp(p, UART_LCR, old_lcr);
798
799 return id;
800 }
801
802 /*
803 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
804 * When this function is called we know it is at least a StarTech
805 * 16650 V2, but it might be one of several StarTech UARTs, or one of
806 * its clones. (We treat the broken original StarTech 16650 V1 as a
807 * 16550, and why not? Startech doesn't seem to even acknowledge its
808 * existence.)
809 *
810 * What evil have men's minds wrought...
811 */
812 static void autoconfig_has_efr(struct uart_8250_port *up)
813 {
814 unsigned int id1, id2, id3, rev;
815
816 /*
817 * Everything with an EFR has SLEEP
818 */
819 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
820
821 /*
822 * First we check to see if it's an Oxford Semiconductor UART.
823 *
824 * If we have to do this here because some non-National
825 * Semiconductor clone chips lock up if you try writing to the
826 * LSR register (which serial_icr_read does)
827 */
828
829 /*
830 * Check for Oxford Semiconductor 16C950.
831 *
832 * EFR [4] must be set else this test fails.
833 *
834 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
835 * claims that it's needed for 952 dual UART's (which are not
836 * recommended for new designs).
837 */
838 up->acr = 0;
839 serial_out(up, UART_LCR, 0xBF);
840 serial_out(up, UART_EFR, UART_EFR_ECB);
841 serial_out(up, UART_LCR, 0x00);
842 id1 = serial_icr_read(up, UART_ID1);
843 id2 = serial_icr_read(up, UART_ID2);
844 id3 = serial_icr_read(up, UART_ID3);
845 rev = serial_icr_read(up, UART_REV);
846
847 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
848
849 if (id1 == 0x16 && id2 == 0xC9 &&
850 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
851 up->port.type = PORT_16C950;
852
853 /*
854 * Enable work around for the Oxford Semiconductor 952 rev B
855 * chip which causes it to seriously miscalculate baud rates
856 * when DLL is 0.
857 */
858 if (id3 == 0x52 && rev == 0x01)
859 up->bugs |= UART_BUG_QUOT;
860 return;
861 }
862
863 /*
864 * We check for a XR16C850 by setting DLL and DLM to 0, and then
865 * reading back DLL and DLM. The chip type depends on the DLM
866 * value read back:
867 * 0x10 - XR16C850 and the DLL contains the chip revision.
868 * 0x12 - XR16C2850.
869 * 0x14 - XR16C854.
870 */
871 id1 = autoconfig_read_divisor_id(up);
872 DEBUG_AUTOCONF("850id=%04x ", id1);
873
874 id2 = id1 >> 8;
875 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
876 up->port.type = PORT_16850;
877 return;
878 }
879
880 /*
881 * It wasn't an XR16C850.
882 *
883 * We distinguish between the '654 and the '650 by counting
884 * how many bytes are in the FIFO. I'm using this for now,
885 * since that's the technique that was sent to me in the
886 * serial driver update, but I'm not convinced this works.
887 * I've had problems doing this in the past. -TYT
888 */
889 if (size_fifo(up) == 64)
890 up->port.type = PORT_16654;
891 else
892 up->port.type = PORT_16650V2;
893 }
894
895 /*
896 * We detected a chip without a FIFO. Only two fall into
897 * this category - the original 8250 and the 16450. The
898 * 16450 has a scratch register (accessible with LCR=0)
899 */
900 static void autoconfig_8250(struct uart_8250_port *up)
901 {
902 unsigned char scratch, status1, status2;
903
904 up->port.type = PORT_8250;
905
906 scratch = serial_in(up, UART_SCR);
907 serial_outp(up, UART_SCR, 0xa5);
908 status1 = serial_in(up, UART_SCR);
909 serial_outp(up, UART_SCR, 0x5a);
910 status2 = serial_in(up, UART_SCR);
911 serial_outp(up, UART_SCR, scratch);
912
913 if (status1 == 0xa5 && status2 == 0x5a)
914 up->port.type = PORT_16450;
915 }
916
917 static int broken_efr(struct uart_8250_port *up)
918 {
919 /*
920 * Exar ST16C2550 "A2" devices incorrectly detect as
921 * having an EFR, and report an ID of 0x0201. See
922 * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
923 */
924 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
925 return 1;
926
927 return 0;
928 }
929
930 /*
931 * We know that the chip has FIFOs. Does it have an EFR? The
932 * EFR is located in the same register position as the IIR and
933 * we know the top two bits of the IIR are currently set. The
934 * EFR should contain zero. Try to read the EFR.
935 */
936 static void autoconfig_16550a(struct uart_8250_port *up)
937 {
938 unsigned char status1, status2;
939 unsigned int iersave;
940
941 up->port.type = PORT_16550A;
942 up->capabilities |= UART_CAP_FIFO;
943
944 /*
945 * Check for presence of the EFR when DLAB is set.
946 * Only ST16C650V1 UARTs pass this test.
947 */
948 serial_outp(up, UART_LCR, UART_LCR_DLAB);
949 if (serial_in(up, UART_EFR) == 0) {
950 serial_outp(up, UART_EFR, 0xA8);
951 if (serial_in(up, UART_EFR) != 0) {
952 DEBUG_AUTOCONF("EFRv1 ");
953 up->port.type = PORT_16650;
954 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
955 } else {
956 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
957 }
958 serial_outp(up, UART_EFR, 0);
959 return;
960 }
961
962 /*
963 * Maybe it requires 0xbf to be written to the LCR.
964 * (other ST16C650V2 UARTs, TI16C752A, etc)
965 */
966 serial_outp(up, UART_LCR, 0xBF);
967 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
968 DEBUG_AUTOCONF("EFRv2 ");
969 autoconfig_has_efr(up);
970 return;
971 }
972
973 /*
974 * Check for a National Semiconductor SuperIO chip.
975 * Attempt to switch to bank 2, read the value of the LOOP bit
976 * from EXCR1. Switch back to bank 0, change it in MCR. Then
977 * switch back to bank 2, read it from EXCR1 again and check
978 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
979 */
980 serial_outp(up, UART_LCR, 0);
981 status1 = serial_in(up, UART_MCR);
982 serial_outp(up, UART_LCR, 0xE0);
983 status2 = serial_in(up, 0x02); /* EXCR1 */
984
985 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
986 serial_outp(up, UART_LCR, 0);
987 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
988 serial_outp(up, UART_LCR, 0xE0);
989 status2 = serial_in(up, 0x02); /* EXCR1 */
990 serial_outp(up, UART_LCR, 0);
991 serial_outp(up, UART_MCR, status1);
992
993 if ((status2 ^ status1) & UART_MCR_LOOP) {
994 unsigned short quot;
995
996 serial_outp(up, UART_LCR, 0xE0);
997
998 quot = serial_dl_read(up);
999 quot <<= 3;
1000
1001 status1 = serial_in(up, 0x04); /* EXCR2 */
1002 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
1003 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
1004 serial_outp(up, 0x04, status1);
1005
1006 serial_dl_write(up, quot);
1007
1008 serial_outp(up, UART_LCR, 0);
1009
1010 up->port.uartclk = 921600*16;
1011 up->port.type = PORT_NS16550A;
1012 up->capabilities |= UART_NATSEMI;
1013 return;
1014 }
1015 }
1016
1017 /*
1018 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1019 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1020 * Try setting it with and without DLAB set. Cheap clones
1021 * set bit 5 without DLAB set.
1022 */
1023 serial_outp(up, UART_LCR, 0);
1024 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1025 status1 = serial_in(up, UART_IIR) >> 5;
1026 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1027 serial_outp(up, UART_LCR, UART_LCR_DLAB);
1028 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1029 status2 = serial_in(up, UART_IIR) >> 5;
1030 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1031 serial_outp(up, UART_LCR, 0);
1032
1033 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1034
1035 if (status1 == 6 && status2 == 7) {
1036 up->port.type = PORT_16750;
1037 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1038 return;
1039 }
1040
1041 /*
1042 * Try writing and reading the UART_IER_UUE bit (b6).
1043 * If it works, this is probably one of the Xscale platform's
1044 * internal UARTs.
1045 * We're going to explicitly set the UUE bit to 0 before
1046 * trying to write and read a 1 just to make sure it's not
1047 * already a 1 and maybe locked there before we even start start.
1048 */
1049 iersave = serial_in(up, UART_IER);
1050 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
1051 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1052 /*
1053 * OK it's in a known zero state, try writing and reading
1054 * without disturbing the current state of the other bits.
1055 */
1056 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
1057 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1058 /*
1059 * It's an Xscale.
1060 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1061 */
1062 DEBUG_AUTOCONF("Xscale ");
1063 up->port.type = PORT_XSCALE;
1064 up->capabilities |= UART_CAP_UUE;
1065 return;
1066 }
1067 } else {
1068 /*
1069 * If we got here we couldn't force the IER_UUE bit to 0.
1070 * Log it and continue.
1071 */
1072 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1073 }
1074 serial_outp(up, UART_IER, iersave);
1075 }
1076
1077 /*
1078 * This routine is called by rs_init() to initialize a specific serial
1079 * port. It determines what type of UART chip this serial port is
1080 * using: 8250, 16450, 16550, 16550A. The important question is
1081 * whether or not this UART is a 16550A or not, since this will
1082 * determine whether or not we can use its FIFO features or not.
1083 */
1084 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1085 {
1086 unsigned char status1, scratch, scratch2, scratch3;
1087 unsigned char save_lcr, save_mcr;
1088 unsigned long flags;
1089
1090 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
1091 return;
1092
1093 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04x, 0x%p): ",
1094 serial_index(&up->port), up->port.iobase, up->port.membase);
1095
1096 /*
1097 * We really do need global IRQs disabled here - we're going to
1098 * be frobbing the chips IRQ enable register to see if it exists.
1099 */
1100 spin_lock_irqsave(&up->port.lock, flags);
1101
1102 up->capabilities = 0;
1103 up->bugs = 0;
1104
1105 if (!(up->port.flags & UPF_BUGGY_UART)) {
1106 /*
1107 * Do a simple existence test first; if we fail this,
1108 * there's no point trying anything else.
1109 *
1110 * 0x80 is used as a nonsense port to prevent against
1111 * false positives due to ISA bus float. The
1112 * assumption is that 0x80 is a non-existent port;
1113 * which should be safe since include/asm/io.h also
1114 * makes this assumption.
1115 *
1116 * Note: this is safe as long as MCR bit 4 is clear
1117 * and the device is in "PC" mode.
1118 */
1119 scratch = serial_inp(up, UART_IER);
1120 serial_outp(up, UART_IER, 0);
1121 #ifdef __i386__
1122 outb(0xff, 0x080);
1123 #endif
1124 /*
1125 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1126 * 16C754B) allow only to modify them if an EFR bit is set.
1127 */
1128 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1129 serial_outp(up, UART_IER, 0x0F);
1130 #ifdef __i386__
1131 outb(0, 0x080);
1132 #endif
1133 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1134 serial_outp(up, UART_IER, scratch);
1135 if (scratch2 != 0 || scratch3 != 0x0F) {
1136 /*
1137 * We failed; there's nothing here
1138 */
1139 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1140 scratch2, scratch3);
1141 goto out;
1142 }
1143 }
1144
1145 save_mcr = serial_in(up, UART_MCR);
1146 save_lcr = serial_in(up, UART_LCR);
1147
1148 /*
1149 * Check to see if a UART is really there. Certain broken
1150 * internal modems based on the Rockwell chipset fail this
1151 * test, because they apparently don't implement the loopback
1152 * test mode. So this test is skipped on the COM 1 through
1153 * COM 4 ports. This *should* be safe, since no board
1154 * manufacturer would be stupid enough to design a board
1155 * that conflicts with COM 1-4 --- we hope!
1156 */
1157 if (!(up->port.flags & UPF_SKIP_TEST)) {
1158 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1159 status1 = serial_inp(up, UART_MSR) & 0xF0;
1160 serial_outp(up, UART_MCR, save_mcr);
1161 if (status1 != 0x90) {
1162 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1163 status1);
1164 goto out;
1165 }
1166 }
1167
1168 /*
1169 * We're pretty sure there's a port here. Lets find out what
1170 * type of port it is. The IIR top two bits allows us to find
1171 * out if it's 8250 or 16450, 16550, 16550A or later. This
1172 * determines what we test for next.
1173 *
1174 * We also initialise the EFR (if any) to zero for later. The
1175 * EFR occupies the same register location as the FCR and IIR.
1176 */
1177 serial_outp(up, UART_LCR, 0xBF);
1178 serial_outp(up, UART_EFR, 0);
1179 serial_outp(up, UART_LCR, 0);
1180
1181 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1182 scratch = serial_in(up, UART_IIR) >> 6;
1183
1184 DEBUG_AUTOCONF("iir=%d ", scratch);
1185
1186 switch (scratch) {
1187 case 0:
1188 autoconfig_8250(up);
1189 break;
1190 case 1:
1191 up->port.type = PORT_UNKNOWN;
1192 break;
1193 case 2:
1194 up->port.type = PORT_16550;
1195 break;
1196 case 3:
1197 autoconfig_16550a(up);
1198 break;
1199 }
1200
1201 #ifdef CONFIG_SERIAL_8250_RSA
1202 /*
1203 * Only probe for RSA ports if we got the region.
1204 */
1205 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1206 int i;
1207
1208 for (i = 0 ; i < probe_rsa_count; ++i) {
1209 if (probe_rsa[i] == up->port.iobase &&
1210 __enable_rsa(up)) {
1211 up->port.type = PORT_RSA;
1212 break;
1213 }
1214 }
1215 }
1216 #endif
1217
1218 #ifdef CONFIG_SERIAL_8250_AU1X00
1219 /* if access method is AU, it is a 16550 with a quirk */
1220 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
1221 up->bugs |= UART_BUG_NOMSR;
1222 #endif
1223
1224 serial_outp(up, UART_LCR, save_lcr);
1225
1226 if (up->capabilities != uart_config[up->port.type].flags) {
1227 printk(KERN_WARNING
1228 "ttyS%d: detected caps %08x should be %08x\n",
1229 serial_index(&up->port), up->capabilities,
1230 uart_config[up->port.type].flags);
1231 }
1232
1233 up->port.fifosize = uart_config[up->port.type].fifo_size;
1234 up->capabilities = uart_config[up->port.type].flags;
1235 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1236
1237 if (up->port.type == PORT_UNKNOWN)
1238 goto out;
1239
1240 /*
1241 * Reset the UART.
1242 */
1243 #ifdef CONFIG_SERIAL_8250_RSA
1244 if (up->port.type == PORT_RSA)
1245 serial_outp(up, UART_RSA_FRR, 0);
1246 #endif
1247 serial_outp(up, UART_MCR, save_mcr);
1248 serial8250_clear_fifos(up);
1249 serial_in(up, UART_RX);
1250 if (up->capabilities & UART_CAP_UUE)
1251 serial_outp(up, UART_IER, UART_IER_UUE);
1252 else
1253 serial_outp(up, UART_IER, 0);
1254
1255 out:
1256 spin_unlock_irqrestore(&up->port.lock, flags);
1257 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1258 }
1259
1260 static void autoconfig_irq(struct uart_8250_port *up)
1261 {
1262 unsigned char save_mcr, save_ier;
1263 unsigned char save_ICP = 0;
1264 unsigned int ICP = 0;
1265 unsigned long irqs;
1266 int irq;
1267
1268 if (up->port.flags & UPF_FOURPORT) {
1269 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1270 save_ICP = inb_p(ICP);
1271 outb_p(0x80, ICP);
1272 (void) inb_p(ICP);
1273 }
1274
1275 /* forget possible initially masked and pending IRQ */
1276 probe_irq_off(probe_irq_on());
1277 save_mcr = serial_inp(up, UART_MCR);
1278 save_ier = serial_inp(up, UART_IER);
1279 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1280
1281 irqs = probe_irq_on();
1282 serial_outp(up, UART_MCR, 0);
1283 udelay(10);
1284 if (up->port.flags & UPF_FOURPORT) {
1285 serial_outp(up, UART_MCR,
1286 UART_MCR_DTR | UART_MCR_RTS);
1287 } else {
1288 serial_outp(up, UART_MCR,
1289 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1290 }
1291 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1292 (void)serial_inp(up, UART_LSR);
1293 (void)serial_inp(up, UART_RX);
1294 (void)serial_inp(up, UART_IIR);
1295 (void)serial_inp(up, UART_MSR);
1296 serial_outp(up, UART_TX, 0xFF);
1297 udelay(20);
1298 irq = probe_irq_off(irqs);
1299
1300 serial_outp(up, UART_MCR, save_mcr);
1301 serial_outp(up, UART_IER, save_ier);
1302
1303 if (up->port.flags & UPF_FOURPORT)
1304 outb_p(save_ICP, ICP);
1305
1306 up->port.irq = (irq > 0) ? irq : 0;
1307 }
1308
1309 static inline void __stop_tx(struct uart_8250_port *p)
1310 {
1311 if (p->ier & UART_IER_THRI) {
1312 p->ier &= ~UART_IER_THRI;
1313 serial_out(p, UART_IER, p->ier);
1314 }
1315 }
1316
1317 static void serial8250_stop_tx(struct uart_port *port)
1318 {
1319 struct uart_8250_port *up = (struct uart_8250_port *)port;
1320
1321 __stop_tx(up);
1322
1323 /*
1324 * We really want to stop the transmitter from sending.
1325 */
1326 if (up->port.type == PORT_16C950) {
1327 up->acr |= UART_ACR_TXDIS;
1328 serial_icr_write(up, UART_ACR, up->acr);
1329 }
1330 }
1331
1332 static void transmit_chars(struct uart_8250_port *up);
1333
1334 static void serial8250_start_tx(struct uart_port *port)
1335 {
1336 struct uart_8250_port *up = (struct uart_8250_port *)port;
1337
1338 if (!(up->ier & UART_IER_THRI)) {
1339 up->ier |= UART_IER_THRI;
1340 serial_out(up, UART_IER, up->ier);
1341
1342 if (up->bugs & UART_BUG_TXEN) {
1343 unsigned char lsr;
1344 lsr = serial_in(up, UART_LSR);
1345 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1346 if ((up->port.type == PORT_RM9000) ?
1347 (lsr & UART_LSR_THRE) :
1348 (lsr & UART_LSR_TEMT))
1349 transmit_chars(up);
1350 }
1351 }
1352
1353 /*
1354 * Re-enable the transmitter if we disabled it.
1355 */
1356 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1357 up->acr &= ~UART_ACR_TXDIS;
1358 serial_icr_write(up, UART_ACR, up->acr);
1359 }
1360 }
1361
1362 static void serial8250_stop_rx(struct uart_port *port)
1363 {
1364 struct uart_8250_port *up = (struct uart_8250_port *)port;
1365
1366 up->ier &= ~UART_IER_RLSI;
1367 up->port.read_status_mask &= ~UART_LSR_DR;
1368 serial_out(up, UART_IER, up->ier);
1369 }
1370
1371 static void serial8250_enable_ms(struct uart_port *port)
1372 {
1373 struct uart_8250_port *up = (struct uart_8250_port *)port;
1374
1375 /* no MSR capabilities */
1376 if (up->bugs & UART_BUG_NOMSR)
1377 return;
1378
1379 up->ier |= UART_IER_MSI;
1380 serial_out(up, UART_IER, up->ier);
1381 }
1382
1383 static void
1384 receive_chars(struct uart_8250_port *up, unsigned int *status)
1385 {
1386 struct tty_struct *tty = up->port.info->port.tty;
1387 unsigned char ch, lsr = *status;
1388 int max_count = 256;
1389 char flag;
1390
1391 do {
1392 if (likely(lsr & UART_LSR_DR))
1393 ch = serial_inp(up, UART_RX);
1394 else
1395 /*
1396 * Intel 82571 has a Serial Over Lan device that will
1397 * set UART_LSR_BI without setting UART_LSR_DR when
1398 * it receives a break. To avoid reading from the
1399 * receive buffer without UART_LSR_DR bit set, we
1400 * just force the read character to be 0
1401 */
1402 ch = 0;
1403
1404 flag = TTY_NORMAL;
1405 up->port.icount.rx++;
1406
1407 lsr |= up->lsr_saved_flags;
1408 up->lsr_saved_flags = 0;
1409
1410 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1411 /*
1412 * For statistics only
1413 */
1414 if (lsr & UART_LSR_BI) {
1415 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1416 up->port.icount.brk++;
1417 /*
1418 * We do the SysRQ and SAK checking
1419 * here because otherwise the break
1420 * may get masked by ignore_status_mask
1421 * or read_status_mask.
1422 */
1423 if (uart_handle_break(&up->port))
1424 goto ignore_char;
1425 } else if (lsr & UART_LSR_PE)
1426 up->port.icount.parity++;
1427 else if (lsr & UART_LSR_FE)
1428 up->port.icount.frame++;
1429 if (lsr & UART_LSR_OE)
1430 up->port.icount.overrun++;
1431
1432 /*
1433 * Mask off conditions which should be ignored.
1434 */
1435 lsr &= up->port.read_status_mask;
1436
1437 if (lsr & UART_LSR_BI) {
1438 DEBUG_INTR("handling break....");
1439 flag = TTY_BREAK;
1440 } else if (lsr & UART_LSR_PE)
1441 flag = TTY_PARITY;
1442 else if (lsr & UART_LSR_FE)
1443 flag = TTY_FRAME;
1444 }
1445 if (uart_handle_sysrq_char(&up->port, ch))
1446 goto ignore_char;
1447
1448 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1449
1450 ignore_char:
1451 lsr = serial_inp(up, UART_LSR);
1452 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1453 spin_unlock(&up->port.lock);
1454 tty_flip_buffer_push(tty);
1455 spin_lock(&up->port.lock);
1456 *status = lsr;
1457 }
1458
1459 static void transmit_chars(struct uart_8250_port *up)
1460 {
1461 struct circ_buf *xmit = &up->port.info->xmit;
1462 int count;
1463
1464 if (up->port.x_char) {
1465 serial_outp(up, UART_TX, up->port.x_char);
1466 up->port.icount.tx++;
1467 up->port.x_char = 0;
1468 return;
1469 }
1470 if (uart_tx_stopped(&up->port)) {
1471 serial8250_stop_tx(&up->port);
1472 return;
1473 }
1474 if (uart_circ_empty(xmit)) {
1475 __stop_tx(up);
1476 return;
1477 }
1478
1479 count = up->tx_loadsz;
1480 do {
1481 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1482 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1483 up->port.icount.tx++;
1484 if (uart_circ_empty(xmit))
1485 break;
1486 } while (--count > 0);
1487
1488 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1489 uart_write_wakeup(&up->port);
1490
1491 DEBUG_INTR("THRE...");
1492
1493 if (uart_circ_empty(xmit))
1494 __stop_tx(up);
1495 }
1496
1497 static unsigned int check_modem_status(struct uart_8250_port *up)
1498 {
1499 unsigned int status = serial_in(up, UART_MSR);
1500
1501 status |= up->msr_saved_flags;
1502 up->msr_saved_flags = 0;
1503 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1504 up->port.info != NULL) {
1505 if (status & UART_MSR_TERI)
1506 up->port.icount.rng++;
1507 if (status & UART_MSR_DDSR)
1508 up->port.icount.dsr++;
1509 if (status & UART_MSR_DDCD)
1510 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1511 if (status & UART_MSR_DCTS)
1512 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1513
1514 wake_up_interruptible(&up->port.info->delta_msr_wait);
1515 }
1516
1517 return status;
1518 }
1519
1520 /*
1521 * This handles the interrupt from one port.
1522 */
1523 static void serial8250_handle_port(struct uart_8250_port *up)
1524 {
1525 unsigned int status;
1526 unsigned long flags;
1527
1528 spin_lock_irqsave(&up->port.lock, flags);
1529
1530 status = serial_inp(up, UART_LSR);
1531
1532 DEBUG_INTR("status = %x...", status);
1533
1534 if (status & (UART_LSR_DR | UART_LSR_BI))
1535 receive_chars(up, &status);
1536 check_modem_status(up);
1537 if (status & UART_LSR_THRE)
1538 transmit_chars(up);
1539
1540 spin_unlock_irqrestore(&up->port.lock, flags);
1541 }
1542
1543 /*
1544 * This is the serial driver's interrupt routine.
1545 *
1546 * Arjan thinks the old way was overly complex, so it got simplified.
1547 * Alan disagrees, saying that need the complexity to handle the weird
1548 * nature of ISA shared interrupts. (This is a special exception.)
1549 *
1550 * In order to handle ISA shared interrupts properly, we need to check
1551 * that all ports have been serviced, and therefore the ISA interrupt
1552 * line has been de-asserted.
1553 *
1554 * This means we need to loop through all ports. checking that they
1555 * don't have an interrupt pending.
1556 */
1557 static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1558 {
1559 struct irq_info *i = dev_id;
1560 struct list_head *l, *end = NULL;
1561 int pass_counter = 0, handled = 0;
1562
1563 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1564
1565 spin_lock(&i->lock);
1566
1567 l = i->head;
1568 do {
1569 struct uart_8250_port *up;
1570 unsigned int iir;
1571
1572 up = list_entry(l, struct uart_8250_port, list);
1573
1574 iir = serial_in(up, UART_IIR);
1575 if (!(iir & UART_IIR_NO_INT)) {
1576 serial8250_handle_port(up);
1577
1578 handled = 1;
1579
1580 end = NULL;
1581 } else if (up->port.iotype == UPIO_DWAPB &&
1582 (iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
1583 /* The DesignWare APB UART has an Busy Detect (0x07)
1584 * interrupt meaning an LCR write attempt occured while the
1585 * UART was busy. The interrupt must be cleared by reading
1586 * the UART status register (USR) and the LCR re-written. */
1587 unsigned int status;
1588 status = *(volatile u32 *)up->port.private_data;
1589 serial_out(up, UART_LCR, up->lcr);
1590
1591 handled = 1;
1592
1593 end = NULL;
1594 } else if (end == NULL)
1595 end = l;
1596
1597 l = l->next;
1598
1599 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1600 /* If we hit this, we're dead. */
1601 printk(KERN_ERR "serial8250: too much work for "
1602 "irq%d\n", irq);
1603 break;
1604 }
1605 } while (l != end);
1606
1607 spin_unlock(&i->lock);
1608
1609 DEBUG_INTR("end.\n");
1610
1611 return IRQ_RETVAL(handled);
1612 }
1613
1614 /*
1615 * To support ISA shared interrupts, we need to have one interrupt
1616 * handler that ensures that the IRQ line has been deasserted
1617 * before returning. Failing to do this will result in the IRQ
1618 * line being stuck active, and, since ISA irqs are edge triggered,
1619 * no more IRQs will be seen.
1620 */
1621 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1622 {
1623 spin_lock_irq(&i->lock);
1624
1625 if (!list_empty(i->head)) {
1626 if (i->head == &up->list)
1627 i->head = i->head->next;
1628 list_del(&up->list);
1629 } else {
1630 BUG_ON(i->head != &up->list);
1631 i->head = NULL;
1632 }
1633 spin_unlock_irq(&i->lock);
1634 /* List empty so throw away the hash node */
1635 if (i->head == NULL) {
1636 hlist_del(&i->node);
1637 kfree(i);
1638 }
1639 }
1640
1641 static int serial_link_irq_chain(struct uart_8250_port *up)
1642 {
1643 struct hlist_head *h;
1644 struct hlist_node *n;
1645 struct irq_info *i;
1646 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1647
1648 mutex_lock(&hash_mutex);
1649
1650 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1651
1652 hlist_for_each(n, h) {
1653 i = hlist_entry(n, struct irq_info, node);
1654 if (i->irq == up->port.irq)
1655 break;
1656 }
1657
1658 if (n == NULL) {
1659 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1660 if (i == NULL) {
1661 mutex_unlock(&hash_mutex);
1662 return -ENOMEM;
1663 }
1664 spin_lock_init(&i->lock);
1665 i->irq = up->port.irq;
1666 hlist_add_head(&i->node, h);
1667 }
1668 mutex_unlock(&hash_mutex);
1669
1670 spin_lock_irq(&i->lock);
1671
1672 if (i->head) {
1673 list_add(&up->list, i->head);
1674 spin_unlock_irq(&i->lock);
1675
1676 ret = 0;
1677 } else {
1678 INIT_LIST_HEAD(&up->list);
1679 i->head = &up->list;
1680 spin_unlock_irq(&i->lock);
1681
1682 ret = request_irq(up->port.irq, serial8250_interrupt,
1683 irq_flags, "serial", i);
1684 if (ret < 0)
1685 serial_do_unlink(i, up);
1686 }
1687
1688 return ret;
1689 }
1690
1691 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1692 {
1693 struct irq_info *i;
1694 struct hlist_node *n;
1695 struct hlist_head *h;
1696
1697 mutex_lock(&hash_mutex);
1698
1699 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1700
1701 hlist_for_each(n, h) {
1702 i = hlist_entry(n, struct irq_info, node);
1703 if (i->irq == up->port.irq)
1704 break;
1705 }
1706
1707 BUG_ON(n == NULL);
1708 BUG_ON(i->head == NULL);
1709
1710 if (list_empty(i->head))
1711 free_irq(up->port.irq, i);
1712
1713 serial_do_unlink(i, up);
1714 mutex_unlock(&hash_mutex);
1715 }
1716
1717 /* Base timer interval for polling */
1718 static inline int poll_timeout(int timeout)
1719 {
1720 return timeout > 6 ? (timeout / 2 - 2) : 1;
1721 }
1722
1723 /*
1724 * This function is used to handle ports that do not have an
1725 * interrupt. This doesn't work very well for 16450's, but gives
1726 * barely passable results for a 16550A. (Although at the expense
1727 * of much CPU overhead).
1728 */
1729 static void serial8250_timeout(unsigned long data)
1730 {
1731 struct uart_8250_port *up = (struct uart_8250_port *)data;
1732 unsigned int iir;
1733
1734 iir = serial_in(up, UART_IIR);
1735 if (!(iir & UART_IIR_NO_INT))
1736 serial8250_handle_port(up);
1737 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
1738 }
1739
1740 static void serial8250_backup_timeout(unsigned long data)
1741 {
1742 struct uart_8250_port *up = (struct uart_8250_port *)data;
1743 unsigned int iir, ier = 0, lsr;
1744 unsigned long flags;
1745
1746 /*
1747 * Must disable interrupts or else we risk racing with the interrupt
1748 * based handler.
1749 */
1750 if (is_real_interrupt(up->port.irq)) {
1751 ier = serial_in(up, UART_IER);
1752 serial_out(up, UART_IER, 0);
1753 }
1754
1755 iir = serial_in(up, UART_IIR);
1756
1757 /*
1758 * This should be a safe test for anyone who doesn't trust the
1759 * IIR bits on their UART, but it's specifically designed for
1760 * the "Diva" UART used on the management processor on many HP
1761 * ia64 and parisc boxes.
1762 */
1763 spin_lock_irqsave(&up->port.lock, flags);
1764 lsr = serial_in(up, UART_LSR);
1765 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1766 spin_unlock_irqrestore(&up->port.lock, flags);
1767 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1768 (!uart_circ_empty(&up->port.info->xmit) || up->port.x_char) &&
1769 (lsr & UART_LSR_THRE)) {
1770 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1771 iir |= UART_IIR_THRI;
1772 }
1773
1774 if (!(iir & UART_IIR_NO_INT))
1775 serial8250_handle_port(up);
1776
1777 if (is_real_interrupt(up->port.irq))
1778 serial_out(up, UART_IER, ier);
1779
1780 /* Standard timer interval plus 0.2s to keep the port running */
1781 mod_timer(&up->timer,
1782 jiffies + poll_timeout(up->port.timeout) + HZ / 5);
1783 }
1784
1785 static unsigned int serial8250_tx_empty(struct uart_port *port)
1786 {
1787 struct uart_8250_port *up = (struct uart_8250_port *)port;
1788 unsigned long flags;
1789 unsigned int lsr;
1790
1791 spin_lock_irqsave(&up->port.lock, flags);
1792 lsr = serial_in(up, UART_LSR);
1793 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1794 spin_unlock_irqrestore(&up->port.lock, flags);
1795
1796 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1797 }
1798
1799 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1800 {
1801 struct uart_8250_port *up = (struct uart_8250_port *)port;
1802 unsigned int status;
1803 unsigned int ret;
1804
1805 status = check_modem_status(up);
1806
1807 ret = 0;
1808 if (status & UART_MSR_DCD)
1809 ret |= TIOCM_CAR;
1810 if (status & UART_MSR_RI)
1811 ret |= TIOCM_RNG;
1812 if (status & UART_MSR_DSR)
1813 ret |= TIOCM_DSR;
1814 if (status & UART_MSR_CTS)
1815 ret |= TIOCM_CTS;
1816 return ret;
1817 }
1818
1819 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1820 {
1821 struct uart_8250_port *up = (struct uart_8250_port *)port;
1822 unsigned char mcr = 0;
1823
1824 if (mctrl & TIOCM_RTS)
1825 mcr |= UART_MCR_RTS;
1826 if (mctrl & TIOCM_DTR)
1827 mcr |= UART_MCR_DTR;
1828 if (mctrl & TIOCM_OUT1)
1829 mcr |= UART_MCR_OUT1;
1830 if (mctrl & TIOCM_OUT2)
1831 mcr |= UART_MCR_OUT2;
1832 if (mctrl & TIOCM_LOOP)
1833 mcr |= UART_MCR_LOOP;
1834
1835 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1836
1837 serial_out(up, UART_MCR, mcr);
1838 }
1839
1840 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1841 {
1842 struct uart_8250_port *up = (struct uart_8250_port *)port;
1843 unsigned long flags;
1844
1845 spin_lock_irqsave(&up->port.lock, flags);
1846 if (break_state == -1)
1847 up->lcr |= UART_LCR_SBC;
1848 else
1849 up->lcr &= ~UART_LCR_SBC;
1850 serial_out(up, UART_LCR, up->lcr);
1851 spin_unlock_irqrestore(&up->port.lock, flags);
1852 }
1853
1854 /*
1855 * Wait for transmitter & holding register to empty
1856 */
1857 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1858 {
1859 unsigned int status, tmout = 10000;
1860
1861 /* Wait up to 10ms for the character(s) to be sent. */
1862 do {
1863 status = serial_in(up, UART_LSR);
1864
1865 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1866
1867 if (--tmout == 0)
1868 break;
1869 udelay(1);
1870 } while ((status & bits) != bits);
1871
1872 /* Wait up to 1s for flow control if necessary */
1873 if (up->port.flags & UPF_CONS_FLOW) {
1874 unsigned int tmout;
1875 for (tmout = 1000000; tmout; tmout--) {
1876 unsigned int msr = serial_in(up, UART_MSR);
1877 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1878 if (msr & UART_MSR_CTS)
1879 break;
1880 udelay(1);
1881 touch_nmi_watchdog();
1882 }
1883 }
1884 }
1885
1886 #ifdef CONFIG_CONSOLE_POLL
1887 /*
1888 * Console polling routines for writing and reading from the uart while
1889 * in an interrupt or debug context.
1890 */
1891
1892 static int serial8250_get_poll_char(struct uart_port *port)
1893 {
1894 struct uart_8250_port *up = (struct uart_8250_port *)port;
1895 unsigned char lsr = serial_inp(up, UART_LSR);
1896
1897 while (!(lsr & UART_LSR_DR))
1898 lsr = serial_inp(up, UART_LSR);
1899
1900 return serial_inp(up, UART_RX);
1901 }
1902
1903
1904 static void serial8250_put_poll_char(struct uart_port *port,
1905 unsigned char c)
1906 {
1907 unsigned int ier;
1908 struct uart_8250_port *up = (struct uart_8250_port *)port;
1909
1910 /*
1911 * First save the IER then disable the interrupts
1912 */
1913 ier = serial_in(up, UART_IER);
1914 if (up->capabilities & UART_CAP_UUE)
1915 serial_out(up, UART_IER, UART_IER_UUE);
1916 else
1917 serial_out(up, UART_IER, 0);
1918
1919 wait_for_xmitr(up, BOTH_EMPTY);
1920 /*
1921 * Send the character out.
1922 * If a LF, also do CR...
1923 */
1924 serial_out(up, UART_TX, c);
1925 if (c == 10) {
1926 wait_for_xmitr(up, BOTH_EMPTY);
1927 serial_out(up, UART_TX, 13);
1928 }
1929
1930 /*
1931 * Finally, wait for transmitter to become empty
1932 * and restore the IER
1933 */
1934 wait_for_xmitr(up, BOTH_EMPTY);
1935 serial_out(up, UART_IER, ier);
1936 }
1937
1938 #endif /* CONFIG_CONSOLE_POLL */
1939
1940 static int serial8250_startup(struct uart_port *port)
1941 {
1942 struct uart_8250_port *up = (struct uart_8250_port *)port;
1943 unsigned long flags;
1944 unsigned char lsr, iir;
1945 int retval;
1946
1947 up->capabilities = uart_config[up->port.type].flags;
1948 up->mcr = 0;
1949
1950 if (up->port.iotype != up->cur_iotype)
1951 set_io_from_upio(port);
1952
1953 if (up->port.type == PORT_16C950) {
1954 /* Wake up and initialize UART */
1955 up->acr = 0;
1956 serial_outp(up, UART_LCR, 0xBF);
1957 serial_outp(up, UART_EFR, UART_EFR_ECB);
1958 serial_outp(up, UART_IER, 0);
1959 serial_outp(up, UART_LCR, 0);
1960 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1961 serial_outp(up, UART_LCR, 0xBF);
1962 serial_outp(up, UART_EFR, UART_EFR_ECB);
1963 serial_outp(up, UART_LCR, 0);
1964 }
1965
1966 #ifdef CONFIG_SERIAL_8250_RSA
1967 /*
1968 * If this is an RSA port, see if we can kick it up to the
1969 * higher speed clock.
1970 */
1971 enable_rsa(up);
1972 #endif
1973
1974 /*
1975 * Clear the FIFO buffers and disable them.
1976 * (they will be reenabled in set_termios())
1977 */
1978 serial8250_clear_fifos(up);
1979
1980 /*
1981 * Clear the interrupt registers.
1982 */
1983 (void) serial_inp(up, UART_LSR);
1984 (void) serial_inp(up, UART_RX);
1985 (void) serial_inp(up, UART_IIR);
1986 (void) serial_inp(up, UART_MSR);
1987
1988 /*
1989 * At this point, there's no way the LSR could still be 0xff;
1990 * if it is, then bail out, because there's likely no UART
1991 * here.
1992 */
1993 if (!(up->port.flags & UPF_BUGGY_UART) &&
1994 (serial_inp(up, UART_LSR) == 0xff)) {
1995 printk(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
1996 serial_index(&up->port));
1997 return -ENODEV;
1998 }
1999
2000 /*
2001 * For a XR16C850, we need to set the trigger levels
2002 */
2003 if (up->port.type == PORT_16850) {
2004 unsigned char fctr;
2005
2006 serial_outp(up, UART_LCR, 0xbf);
2007
2008 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2009 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2010 serial_outp(up, UART_TRG, UART_TRG_96);
2011 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2012 serial_outp(up, UART_TRG, UART_TRG_96);
2013
2014 serial_outp(up, UART_LCR, 0);
2015 }
2016
2017 if (is_real_interrupt(up->port.irq)) {
2018 unsigned char iir1;
2019 /*
2020 * Test for UARTs that do not reassert THRE when the
2021 * transmitter is idle and the interrupt has already
2022 * been cleared. Real 16550s should always reassert
2023 * this interrupt whenever the transmitter is idle and
2024 * the interrupt is enabled. Delays are necessary to
2025 * allow register changes to become visible.
2026 */
2027 spin_lock_irqsave(&up->port.lock, flags);
2028 if (up->port.flags & UPF_SHARE_IRQ)
2029 disable_irq_nosync(up->port.irq);
2030
2031 wait_for_xmitr(up, UART_LSR_THRE);
2032 serial_out_sync(up, UART_IER, UART_IER_THRI);
2033 udelay(1); /* allow THRE to set */
2034 iir1 = serial_in(up, UART_IIR);
2035 serial_out(up, UART_IER, 0);
2036 serial_out_sync(up, UART_IER, UART_IER_THRI);
2037 udelay(1); /* allow a working UART time to re-assert THRE */
2038 iir = serial_in(up, UART_IIR);
2039 serial_out(up, UART_IER, 0);
2040
2041 if (up->port.flags & UPF_SHARE_IRQ)
2042 enable_irq(up->port.irq);
2043 spin_unlock_irqrestore(&up->port.lock, flags);
2044
2045 /*
2046 * If the interrupt is not reasserted, setup a timer to
2047 * kick the UART on a regular basis.
2048 */
2049 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
2050 up->bugs |= UART_BUG_THRE;
2051 pr_debug("ttyS%d - using backup timer\n",
2052 serial_index(port));
2053 }
2054 }
2055
2056 /*
2057 * The above check will only give an accurate result the first time
2058 * the port is opened so this value needs to be preserved.
2059 */
2060 if (up->bugs & UART_BUG_THRE) {
2061 up->timer.function = serial8250_backup_timeout;
2062 up->timer.data = (unsigned long)up;
2063 mod_timer(&up->timer, jiffies +
2064 poll_timeout(up->port.timeout) + HZ / 5);
2065 }
2066
2067 /*
2068 * If the "interrupt" for this port doesn't correspond with any
2069 * hardware interrupt, we use a timer-based system. The original
2070 * driver used to do this with IRQ0.
2071 */
2072 if (!is_real_interrupt(up->port.irq)) {
2073 up->timer.data = (unsigned long)up;
2074 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
2075 } else {
2076 retval = serial_link_irq_chain(up);
2077 if (retval)
2078 return retval;
2079 }
2080
2081 /*
2082 * Now, initialize the UART
2083 */
2084 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
2085
2086 spin_lock_irqsave(&up->port.lock, flags);
2087 if (up->port.flags & UPF_FOURPORT) {
2088 if (!is_real_interrupt(up->port.irq))
2089 up->port.mctrl |= TIOCM_OUT1;
2090 } else
2091 /*
2092 * Most PC uarts need OUT2 raised to enable interrupts.
2093 */
2094 if (is_real_interrupt(up->port.irq))
2095 up->port.mctrl |= TIOCM_OUT2;
2096
2097 serial8250_set_mctrl(&up->port, up->port.mctrl);
2098
2099 /* Serial over Lan (SoL) hack:
2100 Intel 8257x Gigabit ethernet chips have a
2101 16550 emulation, to be used for Serial Over Lan.
2102 Those chips take a longer time than a normal
2103 serial device to signalize that a transmission
2104 data was queued. Due to that, the above test generally
2105 fails. One solution would be to delay the reading of
2106 iir. However, this is not reliable, since the timeout
2107 is variable. So, let's just don't test if we receive
2108 TX irq. This way, we'll never enable UART_BUG_TXEN.
2109 */
2110 if (up->port.flags & UPF_NO_TXEN_TEST)
2111 goto dont_test_tx_en;
2112
2113 /*
2114 * Do a quick test to see if we receive an
2115 * interrupt when we enable the TX irq.
2116 */
2117 serial_outp(up, UART_IER, UART_IER_THRI);
2118 lsr = serial_in(up, UART_LSR);
2119 iir = serial_in(up, UART_IIR);
2120 serial_outp(up, UART_IER, 0);
2121
2122 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2123 if (!(up->bugs & UART_BUG_TXEN)) {
2124 up->bugs |= UART_BUG_TXEN;
2125 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2126 serial_index(port));
2127 }
2128 } else {
2129 up->bugs &= ~UART_BUG_TXEN;
2130 }
2131
2132 dont_test_tx_en:
2133 spin_unlock_irqrestore(&up->port.lock, flags);
2134
2135 /*
2136 * Clear the interrupt registers again for luck, and clear the
2137 * saved flags to avoid getting false values from polling
2138 * routines or the previous session.
2139 */
2140 serial_inp(up, UART_LSR);
2141 serial_inp(up, UART_RX);
2142 serial_inp(up, UART_IIR);
2143 serial_inp(up, UART_MSR);
2144 up->lsr_saved_flags = 0;
2145 up->msr_saved_flags = 0;
2146
2147 /*
2148 * Finally, enable interrupts. Note: Modem status interrupts
2149 * are set via set_termios(), which will be occurring imminently
2150 * anyway, so we don't enable them here.
2151 */
2152 up->ier = UART_IER_RLSI | UART_IER_RDI;
2153 serial_outp(up, UART_IER, up->ier);
2154
2155 if (up->port.flags & UPF_FOURPORT) {
2156 unsigned int icp;
2157 /*
2158 * Enable interrupts on the AST Fourport board
2159 */
2160 icp = (up->port.iobase & 0xfe0) | 0x01f;
2161 outb_p(0x80, icp);
2162 (void) inb_p(icp);
2163 }
2164
2165 return 0;
2166 }
2167
2168 static void serial8250_shutdown(struct uart_port *port)
2169 {
2170 struct uart_8250_port *up = (struct uart_8250_port *)port;
2171 unsigned long flags;
2172
2173 /*
2174 * Disable interrupts from this port
2175 */
2176 up->ier = 0;
2177 serial_outp(up, UART_IER, 0);
2178
2179 spin_lock_irqsave(&up->port.lock, flags);
2180 if (up->port.flags & UPF_FOURPORT) {
2181 /* reset interrupts on the AST Fourport board */
2182 inb((up->port.iobase & 0xfe0) | 0x1f);
2183 up->port.mctrl |= TIOCM_OUT1;
2184 } else
2185 up->port.mctrl &= ~TIOCM_OUT2;
2186
2187 serial8250_set_mctrl(&up->port, up->port.mctrl);
2188 spin_unlock_irqrestore(&up->port.lock, flags);
2189
2190 /*
2191 * Disable break condition and FIFOs
2192 */
2193 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2194 serial8250_clear_fifos(up);
2195
2196 #ifdef CONFIG_SERIAL_8250_RSA
2197 /*
2198 * Reset the RSA board back to 115kbps compat mode.
2199 */
2200 disable_rsa(up);
2201 #endif
2202
2203 /*
2204 * Read data port to reset things, and then unlink from
2205 * the IRQ chain.
2206 */
2207 (void) serial_in(up, UART_RX);
2208
2209 del_timer_sync(&up->timer);
2210 up->timer.function = serial8250_timeout;
2211 if (is_real_interrupt(up->port.irq))
2212 serial_unlink_irq_chain(up);
2213 }
2214
2215 static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2216 {
2217 unsigned int quot;
2218
2219 /*
2220 * Handle magic divisors for baud rates above baud_base on
2221 * SMSC SuperIO chips.
2222 */
2223 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2224 baud == (port->uartclk/4))
2225 quot = 0x8001;
2226 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2227 baud == (port->uartclk/8))
2228 quot = 0x8002;
2229 else
2230 quot = uart_get_divisor(port, baud);
2231
2232 return quot;
2233 }
2234
2235 static void
2236 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2237 struct ktermios *old)
2238 {
2239 struct uart_8250_port *up = (struct uart_8250_port *)port;
2240 unsigned char cval, fcr = 0;
2241 unsigned long flags;
2242 unsigned int baud, quot;
2243
2244 switch (termios->c_cflag & CSIZE) {
2245 case CS5:
2246 cval = UART_LCR_WLEN5;
2247 break;
2248 case CS6:
2249 cval = UART_LCR_WLEN6;
2250 break;
2251 case CS7:
2252 cval = UART_LCR_WLEN7;
2253 break;
2254 default:
2255 case CS8:
2256 cval = UART_LCR_WLEN8;
2257 break;
2258 }
2259
2260 if (termios->c_cflag & CSTOPB)
2261 cval |= UART_LCR_STOP;
2262 if (termios->c_cflag & PARENB)
2263 cval |= UART_LCR_PARITY;
2264 if (!(termios->c_cflag & PARODD))
2265 cval |= UART_LCR_EPAR;
2266 #ifdef CMSPAR
2267 if (termios->c_cflag & CMSPAR)
2268 cval |= UART_LCR_SPAR;
2269 #endif
2270
2271 /*
2272 * Ask the core to calculate the divisor for us.
2273 */
2274 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
2275 quot = serial8250_get_divisor(port, baud);
2276
2277 /*
2278 * Oxford Semi 952 rev B workaround
2279 */
2280 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2281 quot++;
2282
2283 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2284 if (baud < 2400)
2285 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2286 else
2287 fcr = uart_config[up->port.type].fcr;
2288 }
2289
2290 /*
2291 * MCR-based auto flow control. When AFE is enabled, RTS will be
2292 * deasserted when the receive FIFO contains more characters than
2293 * the trigger, or the MCR RTS bit is cleared. In the case where
2294 * the remote UART is not using CTS auto flow control, we must
2295 * have sufficient FIFO entries for the latency of the remote
2296 * UART to respond. IOW, at least 32 bytes of FIFO.
2297 */
2298 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2299 up->mcr &= ~UART_MCR_AFE;
2300 if (termios->c_cflag & CRTSCTS)
2301 up->mcr |= UART_MCR_AFE;
2302 }
2303
2304 /*
2305 * Ok, we're now changing the port state. Do it with
2306 * interrupts disabled.
2307 */
2308 spin_lock_irqsave(&up->port.lock, flags);
2309
2310 /*
2311 * Update the per-port timeout.
2312 */
2313 uart_update_timeout(port, termios->c_cflag, baud);
2314
2315 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2316 if (termios->c_iflag & INPCK)
2317 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2318 if (termios->c_iflag & (BRKINT | PARMRK))
2319 up->port.read_status_mask |= UART_LSR_BI;
2320
2321 /*
2322 * Characteres to ignore
2323 */
2324 up->port.ignore_status_mask = 0;
2325 if (termios->c_iflag & IGNPAR)
2326 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2327 if (termios->c_iflag & IGNBRK) {
2328 up->port.ignore_status_mask |= UART_LSR_BI;
2329 /*
2330 * If we're ignoring parity and break indicators,
2331 * ignore overruns too (for real raw support).
2332 */
2333 if (termios->c_iflag & IGNPAR)
2334 up->port.ignore_status_mask |= UART_LSR_OE;
2335 }
2336
2337 /*
2338 * ignore all characters if CREAD is not set
2339 */
2340 if ((termios->c_cflag & CREAD) == 0)
2341 up->port.ignore_status_mask |= UART_LSR_DR;
2342
2343 /*
2344 * CTS flow control flag and modem status interrupts
2345 */
2346 up->ier &= ~UART_IER_MSI;
2347 if (!(up->bugs & UART_BUG_NOMSR) &&
2348 UART_ENABLE_MS(&up->port, termios->c_cflag))
2349 up->ier |= UART_IER_MSI;
2350 if (up->capabilities & UART_CAP_UUE)
2351 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
2352
2353 serial_out(up, UART_IER, up->ier);
2354
2355 if (up->capabilities & UART_CAP_EFR) {
2356 unsigned char efr = 0;
2357 /*
2358 * TI16C752/Startech hardware flow control. FIXME:
2359 * - TI16C752 requires control thresholds to be set.
2360 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2361 */
2362 if (termios->c_cflag & CRTSCTS)
2363 efr |= UART_EFR_CTS;
2364
2365 serial_outp(up, UART_LCR, 0xBF);
2366 serial_outp(up, UART_EFR, efr);
2367 }
2368
2369 #ifdef CONFIG_ARCH_OMAP
2370 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2371 if (cpu_is_omap1510() && is_omap_port(up)) {
2372 if (baud == 115200) {
2373 quot = 1;
2374 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2375 } else
2376 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2377 }
2378 #endif
2379
2380 if (up->capabilities & UART_NATSEMI) {
2381 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2382 serial_outp(up, UART_LCR, 0xe0);
2383 } else {
2384 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2385 }
2386
2387 serial_dl_write(up, quot);
2388
2389 /*
2390 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2391 * is written without DLAB set, this mode will be disabled.
2392 */
2393 if (up->port.type == PORT_16750)
2394 serial_outp(up, UART_FCR, fcr);
2395
2396 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2397 up->lcr = cval; /* Save LCR */
2398 if (up->port.type != PORT_16750) {
2399 if (fcr & UART_FCR_ENABLE_FIFO) {
2400 /* emulated UARTs (Lucent Venus 167x) need two steps */
2401 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2402 }
2403 serial_outp(up, UART_FCR, fcr); /* set fcr */
2404 }
2405 serial8250_set_mctrl(&up->port, up->port.mctrl);
2406 spin_unlock_irqrestore(&up->port.lock, flags);
2407 /* Don't rewrite B0 */
2408 if (tty_termios_baud_rate(termios))
2409 tty_termios_encode_baud_rate(termios, baud, baud);
2410 }
2411
2412 static void
2413 serial8250_pm(struct uart_port *port, unsigned int state,
2414 unsigned int oldstate)
2415 {
2416 struct uart_8250_port *p = (struct uart_8250_port *)port;
2417
2418 serial8250_set_sleep(p, state != 0);
2419
2420 if (p->pm)
2421 p->pm(port, state, oldstate);
2422 }
2423
2424 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2425 {
2426 if (pt->port.iotype == UPIO_AU)
2427 return 0x100000;
2428 #ifdef CONFIG_ARCH_OMAP
2429 if (is_omap_port(pt))
2430 return 0x16 << pt->port.regshift;
2431 #endif
2432 return 8 << pt->port.regshift;
2433 }
2434
2435 /*
2436 * Resource handling.
2437 */
2438 static int serial8250_request_std_resource(struct uart_8250_port *up)
2439 {
2440 unsigned int size = serial8250_port_size(up);
2441 int ret = 0;
2442
2443 switch (up->port.iotype) {
2444 case UPIO_AU:
2445 case UPIO_TSI:
2446 case UPIO_MEM32:
2447 case UPIO_MEM:
2448 case UPIO_DWAPB:
2449 if (!up->port.mapbase)
2450 break;
2451
2452 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2453 ret = -EBUSY;
2454 break;
2455 }
2456
2457 if (up->port.flags & UPF_IOREMAP) {
2458 up->port.membase = ioremap_nocache(up->port.mapbase,
2459 size);
2460 if (!up->port.membase) {
2461 release_mem_region(up->port.mapbase, size);
2462 ret = -ENOMEM;
2463 }
2464 }
2465 break;
2466
2467 case UPIO_HUB6:
2468 case UPIO_PORT:
2469 if (!request_region(up->port.iobase, size, "serial"))
2470 ret = -EBUSY;
2471 break;
2472 }
2473 return ret;
2474 }
2475
2476 static void serial8250_release_std_resource(struct uart_8250_port *up)
2477 {
2478 unsigned int size = serial8250_port_size(up);
2479
2480 switch (up->port.iotype) {
2481 case UPIO_AU:
2482 case UPIO_TSI:
2483 case UPIO_MEM32:
2484 case UPIO_MEM:
2485 case UPIO_DWAPB:
2486 if (!up->port.mapbase)
2487 break;
2488
2489 if (up->port.flags & UPF_IOREMAP) {
2490 iounmap(up->port.membase);
2491 up->port.membase = NULL;
2492 }
2493
2494 release_mem_region(up->port.mapbase, size);
2495 break;
2496
2497 case UPIO_HUB6:
2498 case UPIO_PORT:
2499 release_region(up->port.iobase, size);
2500 break;
2501 }
2502 }
2503
2504 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2505 {
2506 unsigned long start = UART_RSA_BASE << up->port.regshift;
2507 unsigned int size = 8 << up->port.regshift;
2508 int ret = -EINVAL;
2509
2510 switch (up->port.iotype) {
2511 case UPIO_HUB6:
2512 case UPIO_PORT:
2513 start += up->port.iobase;
2514 if (request_region(start, size, "serial-rsa"))
2515 ret = 0;
2516 else
2517 ret = -EBUSY;
2518 break;
2519 }
2520
2521 return ret;
2522 }
2523
2524 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2525 {
2526 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2527 unsigned int size = 8 << up->port.regshift;
2528
2529 switch (up->port.iotype) {
2530 case UPIO_HUB6:
2531 case UPIO_PORT:
2532 release_region(up->port.iobase + offset, size);
2533 break;
2534 }
2535 }
2536
2537 static void serial8250_release_port(struct uart_port *port)
2538 {
2539 struct uart_8250_port *up = (struct uart_8250_port *)port;
2540
2541 serial8250_release_std_resource(up);
2542 if (up->port.type == PORT_RSA)
2543 serial8250_release_rsa_resource(up);
2544 }
2545
2546 static int serial8250_request_port(struct uart_port *port)
2547 {
2548 struct uart_8250_port *up = (struct uart_8250_port *)port;
2549 int ret = 0;
2550
2551 ret = serial8250_request_std_resource(up);
2552 if (ret == 0 && up->port.type == PORT_RSA) {
2553 ret = serial8250_request_rsa_resource(up);
2554 if (ret < 0)
2555 serial8250_release_std_resource(up);
2556 }
2557
2558 return ret;
2559 }
2560
2561 static void serial8250_config_port(struct uart_port *port, int flags)
2562 {
2563 struct uart_8250_port *up = (struct uart_8250_port *)port;
2564 int probeflags = PROBE_ANY;
2565 int ret;
2566
2567 /*
2568 * Find the region that we can probe for. This in turn
2569 * tells us whether we can probe for the type of port.
2570 */
2571 ret = serial8250_request_std_resource(up);
2572 if (ret < 0)
2573 return;
2574
2575 ret = serial8250_request_rsa_resource(up);
2576 if (ret < 0)
2577 probeflags &= ~PROBE_RSA;
2578
2579 if (up->port.iotype != up->cur_iotype)
2580 set_io_from_upio(port);
2581
2582 if (flags & UART_CONFIG_TYPE)
2583 autoconfig(up, probeflags);
2584 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2585 autoconfig_irq(up);
2586
2587 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2588 serial8250_release_rsa_resource(up);
2589 if (up->port.type == PORT_UNKNOWN)
2590 serial8250_release_std_resource(up);
2591 }
2592
2593 static int
2594 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2595 {
2596 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2597 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2598 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2599 ser->type == PORT_STARTECH)
2600 return -EINVAL;
2601 return 0;
2602 }
2603
2604 static const char *
2605 serial8250_type(struct uart_port *port)
2606 {
2607 int type = port->type;
2608
2609 if (type >= ARRAY_SIZE(uart_config))
2610 type = 0;
2611 return uart_config[type].name;
2612 }
2613
2614 static struct uart_ops serial8250_pops = {
2615 .tx_empty = serial8250_tx_empty,
2616 .set_mctrl = serial8250_set_mctrl,
2617 .get_mctrl = serial8250_get_mctrl,
2618 .stop_tx = serial8250_stop_tx,
2619 .start_tx = serial8250_start_tx,
2620 .stop_rx = serial8250_stop_rx,
2621 .enable_ms = serial8250_enable_ms,
2622 .break_ctl = serial8250_break_ctl,
2623 .startup = serial8250_startup,
2624 .shutdown = serial8250_shutdown,
2625 .set_termios = serial8250_set_termios,
2626 .pm = serial8250_pm,
2627 .type = serial8250_type,
2628 .release_port = serial8250_release_port,
2629 .request_port = serial8250_request_port,
2630 .config_port = serial8250_config_port,
2631 .verify_port = serial8250_verify_port,
2632 #ifdef CONFIG_CONSOLE_POLL
2633 .poll_get_char = serial8250_get_poll_char,
2634 .poll_put_char = serial8250_put_poll_char,
2635 #endif
2636 };
2637
2638 static struct uart_8250_port serial8250_ports[UART_NR];
2639
2640 static void __init serial8250_isa_init_ports(void)
2641 {
2642 struct uart_8250_port *up;
2643 static int first = 1;
2644 int i;
2645
2646 if (!first)
2647 return;
2648 first = 0;
2649
2650 for (i = 0; i < nr_uarts; i++) {
2651 struct uart_8250_port *up = &serial8250_ports[i];
2652
2653 up->port.line = i;
2654 spin_lock_init(&up->port.lock);
2655
2656 init_timer(&up->timer);
2657 up->timer.function = serial8250_timeout;
2658
2659 /*
2660 * ALPHA_KLUDGE_MCR needs to be killed.
2661 */
2662 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2663 up->mcr_force = ALPHA_KLUDGE_MCR;
2664
2665 up->port.ops = &serial8250_pops;
2666 }
2667
2668 for (i = 0, up = serial8250_ports;
2669 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2670 i++, up++) {
2671 up->port.iobase = old_serial_port[i].port;
2672 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2673 up->port.uartclk = old_serial_port[i].baud_base * 16;
2674 up->port.flags = old_serial_port[i].flags;
2675 up->port.hub6 = old_serial_port[i].hub6;
2676 up->port.membase = old_serial_port[i].iomem_base;
2677 up->port.iotype = old_serial_port[i].io_type;
2678 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2679 set_io_from_upio(&up->port);
2680 if (share_irqs)
2681 up->port.flags |= UPF_SHARE_IRQ;
2682 }
2683 }
2684
2685 static void __init
2686 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2687 {
2688 int i;
2689
2690 for (i = 0; i < nr_uarts; i++) {
2691 struct uart_8250_port *up = &serial8250_ports[i];
2692 up->cur_iotype = 0xFF;
2693 }
2694
2695 serial8250_isa_init_ports();
2696
2697 for (i = 0; i < nr_uarts; i++) {
2698 struct uart_8250_port *up = &serial8250_ports[i];
2699
2700 up->port.dev = dev;
2701 uart_add_one_port(drv, &up->port);
2702 }
2703 }
2704
2705 #ifdef CONFIG_SERIAL_8250_CONSOLE
2706
2707 static void serial8250_console_putchar(struct uart_port *port, int ch)
2708 {
2709 struct uart_8250_port *up = (struct uart_8250_port *)port;
2710
2711 wait_for_xmitr(up, UART_LSR_THRE);
2712 serial_out(up, UART_TX, ch);
2713 }
2714
2715 /*
2716 * Print a string to the serial port trying not to disturb
2717 * any possible real use of the port...
2718 *
2719 * The console_lock must be held when we get here.
2720 */
2721 static void
2722 serial8250_console_write(struct console *co, const char *s, unsigned int count)
2723 {
2724 struct uart_8250_port *up = &serial8250_ports[co->index];
2725 unsigned long flags;
2726 unsigned int ier;
2727 int locked = 1;
2728
2729 touch_nmi_watchdog();
2730
2731 local_irq_save(flags);
2732 if (up->port.sysrq) {
2733 /* serial8250_handle_port() already took the lock */
2734 locked = 0;
2735 } else if (oops_in_progress) {
2736 locked = spin_trylock(&up->port.lock);
2737 } else
2738 spin_lock(&up->port.lock);
2739
2740 /*
2741 * First save the IER then disable the interrupts
2742 */
2743 ier = serial_in(up, UART_IER);
2744
2745 if (up->capabilities & UART_CAP_UUE)
2746 serial_out(up, UART_IER, UART_IER_UUE);
2747 else
2748 serial_out(up, UART_IER, 0);
2749
2750 uart_console_write(&up->port, s, count, serial8250_console_putchar);
2751
2752 /*
2753 * Finally, wait for transmitter to become empty
2754 * and restore the IER
2755 */
2756 wait_for_xmitr(up, BOTH_EMPTY);
2757 serial_out(up, UART_IER, ier);
2758
2759 /*
2760 * The receive handling will happen properly because the
2761 * receive ready bit will still be set; it is not cleared
2762 * on read. However, modem control will not, we must
2763 * call it if we have saved something in the saved flags
2764 * while processing with interrupts off.
2765 */
2766 if (up->msr_saved_flags)
2767 check_modem_status(up);
2768
2769 if (locked)
2770 spin_unlock(&up->port.lock);
2771 local_irq_restore(flags);
2772 }
2773
2774 static int __init serial8250_console_setup(struct console *co, char *options)
2775 {
2776 struct uart_port *port;
2777 int baud = 9600;
2778 int bits = 8;
2779 int parity = 'n';
2780 int flow = 'n';
2781
2782 /*
2783 * Check whether an invalid uart number has been specified, and
2784 * if so, search for the first available port that does have
2785 * console support.
2786 */
2787 if (co->index >= nr_uarts)
2788 co->index = 0;
2789 port = &serial8250_ports[co->index].port;
2790 if (!port->iobase && !port->membase)
2791 return -ENODEV;
2792
2793 if (options)
2794 uart_parse_options(options, &baud, &parity, &bits, &flow);
2795
2796 return uart_set_options(port, co, baud, parity, bits, flow);
2797 }
2798
2799 static int serial8250_console_early_setup(void)
2800 {
2801 return serial8250_find_port_for_earlycon();
2802 }
2803
2804 static struct console serial8250_console = {
2805 .name = "ttyS",
2806 .write = serial8250_console_write,
2807 .device = uart_console_device,
2808 .setup = serial8250_console_setup,
2809 .early_setup = serial8250_console_early_setup,
2810 .flags = CON_PRINTBUFFER,
2811 .index = -1,
2812 .data = &serial8250_reg,
2813 };
2814
2815 static int __init serial8250_console_init(void)
2816 {
2817 if (nr_uarts > UART_NR)
2818 nr_uarts = UART_NR;
2819
2820 serial8250_isa_init_ports();
2821 register_console(&serial8250_console);
2822 return 0;
2823 }
2824 console_initcall(serial8250_console_init);
2825
2826 int serial8250_find_port(struct uart_port *p)
2827 {
2828 int line;
2829 struct uart_port *port;
2830
2831 for (line = 0; line < nr_uarts; line++) {
2832 port = &serial8250_ports[line].port;
2833 if (uart_match_port(p, port))
2834 return line;
2835 }
2836 return -ENODEV;
2837 }
2838
2839 #define SERIAL8250_CONSOLE &serial8250_console
2840 #else
2841 #define SERIAL8250_CONSOLE NULL
2842 #endif
2843
2844 static struct uart_driver serial8250_reg = {
2845 .owner = THIS_MODULE,
2846 .driver_name = "serial",
2847 .dev_name = "ttyS",
2848 .major = TTY_MAJOR,
2849 .minor = 64,
2850 .cons = SERIAL8250_CONSOLE,
2851 };
2852
2853 /*
2854 * early_serial_setup - early registration for 8250 ports
2855 *
2856 * Setup an 8250 port structure prior to console initialisation. Use
2857 * after console initialisation will cause undefined behaviour.
2858 */
2859 int __init early_serial_setup(struct uart_port *port)
2860 {
2861 struct uart_port *p;
2862
2863 if (port->line >= ARRAY_SIZE(serial8250_ports))
2864 return -ENODEV;
2865
2866 serial8250_isa_init_ports();
2867 p = &serial8250_ports[port->line].port;
2868 p->iobase = port->iobase;
2869 p->membase = port->membase;
2870 p->irq = port->irq;
2871 p->uartclk = port->uartclk;
2872 p->fifosize = port->fifosize;
2873 p->regshift = port->regshift;
2874 p->iotype = port->iotype;
2875 p->flags = port->flags;
2876 p->mapbase = port->mapbase;
2877 p->private_data = port->private_data;
2878 p->type = port->type;
2879 p->line = port->line;
2880
2881 set_io_from_upio(p);
2882 if (port->serial_in)
2883 p->serial_in = port->serial_in;
2884 if (port->serial_out)
2885 p->serial_out = port->serial_out;
2886
2887 return 0;
2888 }
2889
2890 /**
2891 * serial8250_suspend_port - suspend one serial port
2892 * @line: serial line number
2893 *
2894 * Suspend one serial port.
2895 */
2896 void serial8250_suspend_port(int line)
2897 {
2898 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2899 }
2900
2901 /**
2902 * serial8250_resume_port - resume one serial port
2903 * @line: serial line number
2904 *
2905 * Resume one serial port.
2906 */
2907 void serial8250_resume_port(int line)
2908 {
2909 struct uart_8250_port *up = &serial8250_ports[line];
2910
2911 if (up->capabilities & UART_NATSEMI) {
2912 unsigned char tmp;
2913
2914 /* Ensure it's still in high speed mode */
2915 serial_outp(up, UART_LCR, 0xE0);
2916
2917 tmp = serial_in(up, 0x04); /* EXCR2 */
2918 tmp &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
2919 tmp |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
2920 serial_outp(up, 0x04, tmp);
2921
2922 serial_outp(up, UART_LCR, 0);
2923 }
2924 uart_resume_port(&serial8250_reg, &up->port);
2925 }
2926
2927 /*
2928 * Register a set of serial devices attached to a platform device. The
2929 * list is terminated with a zero flags entry, which means we expect
2930 * all entries to have at least UPF_BOOT_AUTOCONF set.
2931 */
2932 static int __devinit serial8250_probe(struct platform_device *dev)
2933 {
2934 struct plat_serial8250_port *p = dev->dev.platform_data;
2935 struct uart_port port;
2936 int ret, i;
2937
2938 memset(&port, 0, sizeof(struct uart_port));
2939
2940 for (i = 0; p && p->flags != 0; p++, i++) {
2941 port.iobase = p->iobase;
2942 port.membase = p->membase;
2943 port.irq = p->irq;
2944 port.uartclk = p->uartclk;
2945 port.regshift = p->regshift;
2946 port.iotype = p->iotype;
2947 port.flags = p->flags;
2948 port.mapbase = p->mapbase;
2949 port.hub6 = p->hub6;
2950 port.private_data = p->private_data;
2951 port.type = p->type;
2952 port.serial_in = p->serial_in;
2953 port.serial_out = p->serial_out;
2954 port.dev = &dev->dev;
2955 if (share_irqs)
2956 port.flags |= UPF_SHARE_IRQ;
2957 ret = serial8250_register_port(&port);
2958 if (ret < 0) {
2959 dev_err(&dev->dev, "unable to register port at index %d "
2960 "(IO%lx MEM%llx IRQ%d): %d\n", i,
2961 p->iobase, (unsigned long long)p->mapbase,
2962 p->irq, ret);
2963 }
2964 }
2965 return 0;
2966 }
2967
2968 /*
2969 * Remove serial ports registered against a platform device.
2970 */
2971 static int __devexit serial8250_remove(struct platform_device *dev)
2972 {
2973 int i;
2974
2975 for (i = 0; i < nr_uarts; i++) {
2976 struct uart_8250_port *up = &serial8250_ports[i];
2977
2978 if (up->port.dev == &dev->dev)
2979 serial8250_unregister_port(i);
2980 }
2981 return 0;
2982 }
2983
2984 static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
2985 {
2986 int i;
2987
2988 for (i = 0; i < UART_NR; i++) {
2989 struct uart_8250_port *up = &serial8250_ports[i];
2990
2991 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
2992 uart_suspend_port(&serial8250_reg, &up->port);
2993 }
2994
2995 return 0;
2996 }
2997
2998 static int serial8250_resume(struct platform_device *dev)
2999 {
3000 int i;
3001
3002 for (i = 0; i < UART_NR; i++) {
3003 struct uart_8250_port *up = &serial8250_ports[i];
3004
3005 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3006 serial8250_resume_port(i);
3007 }
3008
3009 return 0;
3010 }
3011
3012 static struct platform_driver serial8250_isa_driver = {
3013 .probe = serial8250_probe,
3014 .remove = __devexit_p(serial8250_remove),
3015 .suspend = serial8250_suspend,
3016 .resume = serial8250_resume,
3017 .driver = {
3018 .name = "serial8250",
3019 .owner = THIS_MODULE,
3020 },
3021 };
3022
3023 /*
3024 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3025 * in the table in include/asm/serial.h
3026 */
3027 static struct platform_device *serial8250_isa_devs;
3028
3029 /*
3030 * serial8250_register_port and serial8250_unregister_port allows for
3031 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3032 * modems and PCI multiport cards.
3033 */
3034 static DEFINE_MUTEX(serial_mutex);
3035
3036 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3037 {
3038 int i;
3039
3040 /*
3041 * First, find a port entry which matches.
3042 */
3043 for (i = 0; i < nr_uarts; i++)
3044 if (uart_match_port(&serial8250_ports[i].port, port))
3045 return &serial8250_ports[i];
3046
3047 /*
3048 * We didn't find a matching entry, so look for the first
3049 * free entry. We look for one which hasn't been previously
3050 * used (indicated by zero iobase).
3051 */
3052 for (i = 0; i < nr_uarts; i++)
3053 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3054 serial8250_ports[i].port.iobase == 0)
3055 return &serial8250_ports[i];
3056
3057 /*
3058 * That also failed. Last resort is to find any entry which
3059 * doesn't have a real port associated with it.
3060 */
3061 for (i = 0; i < nr_uarts; i++)
3062 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3063 return &serial8250_ports[i];
3064
3065 return NULL;
3066 }
3067
3068 /**
3069 * serial8250_register_port - register a serial port
3070 * @port: serial port template
3071 *
3072 * Configure the serial port specified by the request. If the
3073 * port exists and is in use, it is hung up and unregistered
3074 * first.
3075 *
3076 * The port is then probed and if necessary the IRQ is autodetected
3077 * If this fails an error is returned.
3078 *
3079 * On success the port is ready to use and the line number is returned.
3080 */
3081 int serial8250_register_port(struct uart_port *port)
3082 {
3083 struct uart_8250_port *uart;
3084 int ret = -ENOSPC;
3085
3086 if (port->uartclk == 0)
3087 return -EINVAL;
3088
3089 mutex_lock(&serial_mutex);
3090
3091 uart = serial8250_find_match_or_unused(port);
3092 if (uart) {
3093 uart_remove_one_port(&serial8250_reg, &uart->port);
3094
3095 uart->port.iobase = port->iobase;
3096 uart->port.membase = port->membase;
3097 uart->port.irq = port->irq;
3098 uart->port.uartclk = port->uartclk;
3099 uart->port.fifosize = port->fifosize;
3100 uart->port.regshift = port->regshift;
3101 uart->port.iotype = port->iotype;
3102 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3103 uart->port.mapbase = port->mapbase;
3104 uart->port.private_data = port->private_data;
3105 if (port->dev)
3106 uart->port.dev = port->dev;
3107
3108 if (port->flags & UPF_FIXED_TYPE) {
3109 uart->port.type = port->type;
3110 uart->port.fifosize = uart_config[port->type].fifo_size;
3111 uart->capabilities = uart_config[port->type].flags;
3112 uart->tx_loadsz = uart_config[port->type].tx_loadsz;
3113 }
3114
3115 set_io_from_upio(&uart->port);
3116 /* Possibly override default I/O functions. */
3117 if (port->serial_in)
3118 uart->port.serial_in = port->serial_in;
3119 if (port->serial_out)
3120 uart->port.serial_out = port->serial_out;
3121
3122 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3123 if (ret == 0)
3124 ret = uart->port.line;
3125 }
3126 mutex_unlock(&serial_mutex);
3127
3128 return ret;
3129 }
3130 EXPORT_SYMBOL(serial8250_register_port);
3131
3132 /**
3133 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3134 * @line: serial line number
3135 *
3136 * Remove one serial port. This may not be called from interrupt
3137 * context. We hand the port back to the our control.
3138 */
3139 void serial8250_unregister_port(int line)
3140 {
3141 struct uart_8250_port *uart = &serial8250_ports[line];
3142
3143 mutex_lock(&serial_mutex);
3144 uart_remove_one_port(&serial8250_reg, &uart->port);
3145 if (serial8250_isa_devs) {
3146 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3147 uart->port.type = PORT_UNKNOWN;
3148 uart->port.dev = &serial8250_isa_devs->dev;
3149 uart_add_one_port(&serial8250_reg, &uart->port);
3150 } else {
3151 uart->port.dev = NULL;
3152 }
3153 mutex_unlock(&serial_mutex);
3154 }
3155 EXPORT_SYMBOL(serial8250_unregister_port);
3156
3157 static int __init serial8250_init(void)
3158 {
3159 int ret;
3160
3161 if (nr_uarts > UART_NR)
3162 nr_uarts = UART_NR;
3163
3164 printk(KERN_INFO "Serial: 8250/16550 driver, "
3165 "%d ports, IRQ sharing %sabled\n", nr_uarts,
3166 share_irqs ? "en" : "dis");
3167
3168 #ifdef CONFIG_SPARC
3169 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3170 #else
3171 serial8250_reg.nr = UART_NR;
3172 ret = uart_register_driver(&serial8250_reg);
3173 #endif
3174 if (ret)
3175 goto out;
3176
3177 serial8250_isa_devs = platform_device_alloc("serial8250",
3178 PLAT8250_DEV_LEGACY);
3179 if (!serial8250_isa_devs) {
3180 ret = -ENOMEM;
3181 goto unreg_uart_drv;
3182 }
3183
3184 ret = platform_device_add(serial8250_isa_devs);
3185 if (ret)
3186 goto put_dev;
3187
3188 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3189
3190 ret = platform_driver_register(&serial8250_isa_driver);
3191 if (ret == 0)
3192 goto out;
3193
3194 platform_device_del(serial8250_isa_devs);
3195 put_dev:
3196 platform_device_put(serial8250_isa_devs);
3197 unreg_uart_drv:
3198 #ifdef CONFIG_SPARC
3199 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3200 #else
3201 uart_unregister_driver(&serial8250_reg);
3202 #endif
3203 out:
3204 return ret;
3205 }
3206
3207 static void __exit serial8250_exit(void)
3208 {
3209 struct platform_device *isa_dev = serial8250_isa_devs;
3210
3211 /*
3212 * This tells serial8250_unregister_port() not to re-register
3213 * the ports (thereby making serial8250_isa_driver permanently
3214 * in use.)
3215 */
3216 serial8250_isa_devs = NULL;
3217
3218 platform_driver_unregister(&serial8250_isa_driver);
3219 platform_device_unregister(isa_dev);
3220
3221 #ifdef CONFIG_SPARC
3222 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3223 #else
3224 uart_unregister_driver(&serial8250_reg);
3225 #endif
3226 }
3227
3228 module_init(serial8250_init);
3229 module_exit(serial8250_exit);
3230
3231 EXPORT_SYMBOL(serial8250_suspend_port);
3232 EXPORT_SYMBOL(serial8250_resume_port);
3233
3234 MODULE_LICENSE("GPL");
3235 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
3236
3237 module_param(share_irqs, uint, 0644);
3238 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3239 " (unsafe)");
3240
3241 module_param(nr_uarts, uint, 0644);
3242 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3243
3244 #ifdef CONFIG_SERIAL_8250_RSA
3245 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3246 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3247 #endif
3248 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
3249
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