1 /*
2 * Device driver for the SYMBIOS/LSILOGIC 53C8XX and 53C1010 family
3 * of PCI-SCSI IO processors.
4 *
5 * Copyright (C) 1999-2001 Gerard Roudier <groudier@free.fr>
6 * Copyright (c) 2003-2005 Matthew Wilcox <matthew@wil.cx>
7 *
8 * This driver is derived from the Linux sym53c8xx driver.
9 * Copyright (C) 1998-2000 Gerard Roudier
10 *
11 * The sym53c8xx driver is derived from the ncr53c8xx driver that had been
12 * a port of the FreeBSD ncr driver to Linux-1.2.13.
13 *
14 * The original ncr driver has been written for 386bsd and FreeBSD by
15 * Wolfgang Stanglmeier <wolf@cologne.de>
16 * Stefan Esser <se@mi.Uni-Koeln.de>
17 * Copyright (C) 1994 Wolfgang Stanglmeier
18 *
19 * Other major contributions:
20 *
21 * NVRAM detection and reading.
22 * Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk>
23 *
24 *-----------------------------------------------------------------------------
25 *
26 * This program is free software; you can redistribute it and/or modify
27 * it under the terms of the GNU General Public License as published by
28 * the Free Software Foundation; either version 2 of the License, or
29 * (at your option) any later version.
30 *
31 * This program is distributed in the hope that it will be useful,
32 * but WITHOUT ANY WARRANTY; without even the implied warranty of
33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
34 * GNU General Public License for more details.
35 *
36 * You should have received a copy of the GNU General Public License
37 * along with this program; if not, write to the Free Software
38 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
39 */
40
41 #include <linux/slab.h>
42 #include <asm/param.h> /* for timeouts in units of HZ */
43
44 #include "sym_glue.h"
45 #include "sym_nvram.h"
46
47 #if 0
48 #define SYM_DEBUG_GENERIC_SUPPORT
49 #endif
50
51 /*
52 * Needed function prototypes.
53 */
54 static void sym_int_ma (struct sym_hcb *np);
55 static void sym_int_sir(struct sym_hcb *);
56 static struct sym_ccb *sym_alloc_ccb(struct sym_hcb *np);
57 static struct sym_ccb *sym_ccb_from_dsa(struct sym_hcb *np, u32 dsa);
58 static void sym_alloc_lcb_tags (struct sym_hcb *np, u_char tn, u_char ln);
59 static void sym_complete_error (struct sym_hcb *np, struct sym_ccb *cp);
60 static void sym_complete_ok (struct sym_hcb *np, struct sym_ccb *cp);
61 static int sym_compute_residual(struct sym_hcb *np, struct sym_ccb *cp);
62
63 /*
64 * Print a buffer in hexadecimal format with a ".\n" at end.
65 */
66 static void sym_printl_hex(u_char *p, int n)
67 {
68 while (n-- > 0)
69 printf (" %x", *p++);
70 printf (".\n");
71 }
72
73 static void sym_print_msg(struct sym_ccb *cp, char *label, u_char *msg)
74 {
75 if (label)
76 sym_print_addr(cp->cmd, "%s: ", label);
77 else
78 sym_print_addr(cp->cmd, "");
79
80 spi_print_msg(msg);
81 printf("\n");
82 }
83
84 static void sym_print_nego_msg(struct sym_hcb *np, int target, char *label, u_char *msg)
85 {
86 struct sym_tcb *tp = &np->target[target];
87 dev_info(&tp->starget->dev, "%s: ", label);
88
89 spi_print_msg(msg);
90 printf("\n");
91 }
92
93 /*
94 * Print something that tells about extended errors.
95 */
96 void sym_print_xerr(struct scsi_cmnd *cmd, int x_status)
97 {
98 if (x_status & XE_PARITY_ERR) {
99 sym_print_addr(cmd, "unrecovered SCSI parity error.\n");
100 }
101 if (x_status & XE_EXTRA_DATA) {
102 sym_print_addr(cmd, "extraneous data discarded.\n");
103 }
104 if (x_status & XE_BAD_PHASE) {
105 sym_print_addr(cmd, "illegal scsi phase (4/5).\n");
106 }
107 if (x_status & XE_SODL_UNRUN) {
108 sym_print_addr(cmd, "ODD transfer in DATA OUT phase.\n");
109 }
110 if (x_status & XE_SWIDE_OVRUN) {
111 sym_print_addr(cmd, "ODD transfer in DATA IN phase.\n");
112 }
113 }
114
115 /*
116 * Return a string for SCSI BUS mode.
117 */
118 static char *sym_scsi_bus_mode(int mode)
119 {
120 switch(mode) {
121 case SMODE_HVD: return "HVD";
122 case SMODE_SE: return "SE";
123 case SMODE_LVD: return "LVD";
124 }
125 return "??";
126 }
127
128 /*
129 * Soft reset the chip.
130 *
131 * Raising SRST when the chip is running may cause
132 * problems on dual function chips (see below).
133 * On the other hand, LVD devices need some delay
134 * to settle and report actual BUS mode in STEST4.
135 */
136 static void sym_chip_reset (struct sym_hcb *np)
137 {
138 OUTB(np, nc_istat, SRST);
139 INB(np, nc_mbox1);
140 udelay(10);
141 OUTB(np, nc_istat, 0);
142 INB(np, nc_mbox1);
143 udelay(2000); /* For BUS MODE to settle */
144 }
145
146 /*
147 * Really soft reset the chip.:)
148 *
149 * Some 896 and 876 chip revisions may hang-up if we set
150 * the SRST (soft reset) bit at the wrong time when SCRIPTS
151 * are running.
152 * So, we need to abort the current operation prior to
153 * soft resetting the chip.
154 */
155 static void sym_soft_reset (struct sym_hcb *np)
156 {
157 u_char istat = 0;
158 int i;
159
160 if (!(np->features & FE_ISTAT1) || !(INB(np, nc_istat1) & SCRUN))
161 goto do_chip_reset;
162
163 OUTB(np, nc_istat, CABRT);
164 for (i = 100000 ; i ; --i) {
165 istat = INB(np, nc_istat);
166 if (istat & SIP) {
167 INW(np, nc_sist);
168 }
169 else if (istat & DIP) {
170 if (INB(np, nc_dstat) & ABRT)
171 break;
172 }
173 udelay(5);
174 }
175 OUTB(np, nc_istat, 0);
176 if (!i)
177 printf("%s: unable to abort current chip operation, "
178 "ISTAT=0x%02x.\n", sym_name(np), istat);
179 do_chip_reset:
180 sym_chip_reset(np);
181 }
182
183 /*
184 * Start reset process.
185 *
186 * The interrupt handler will reinitialize the chip.
187 */
188 static void sym_start_reset(struct sym_hcb *np)
189 {
190 sym_reset_scsi_bus(np, 1);
191 }
192
193 int sym_reset_scsi_bus(struct sym_hcb *np, int enab_int)
194 {
195 u32 term;
196 int retv = 0;
197
198 sym_soft_reset(np); /* Soft reset the chip */
199 if (enab_int)
200 OUTW(np, nc_sien, RST);
201 /*
202 * Enable Tolerant, reset IRQD if present and
203 * properly set IRQ mode, prior to resetting the bus.
204 */
205 OUTB(np, nc_stest3, TE);
206 OUTB(np, nc_dcntl, (np->rv_dcntl & IRQM));
207 OUTB(np, nc_scntl1, CRST);
208 INB(np, nc_mbox1);
209 udelay(200);
210
211 if (!SYM_SETUP_SCSI_BUS_CHECK)
212 goto out;
213 /*
214 * Check for no terminators or SCSI bus shorts to ground.
215 * Read SCSI data bus, data parity bits and control signals.
216 * We are expecting RESET to be TRUE and other signals to be
217 * FALSE.
218 */
219 term = INB(np, nc_sstat0);
220 term = ((term & 2) << 7) + ((term & 1) << 17); /* rst sdp0 */
221 term |= ((INB(np, nc_sstat2) & 0x01) << 26) | /* sdp1 */
222 ((INW(np, nc_sbdl) & 0xff) << 9) | /* d7-0 */
223 ((INW(np, nc_sbdl) & 0xff00) << 10) | /* d15-8 */
224 INB(np, nc_sbcl); /* req ack bsy sel atn msg cd io */
225
226 if (!np->maxwide)
227 term &= 0x3ffff;
228
229 if (term != (2<<7)) {
230 printf("%s: suspicious SCSI data while resetting the BUS.\n",
231 sym_name(np));
232 printf("%s: %sdp0,d7-0,rst,req,ack,bsy,sel,atn,msg,c/d,i/o = "
233 "0x%lx, expecting 0x%lx\n",
234 sym_name(np),
235 (np->features & FE_WIDE) ? "dp1,d15-8," : "",
236 (u_long)term, (u_long)(2<<7));
237 if (SYM_SETUP_SCSI_BUS_CHECK == 1)
238 retv = 1;
239 }
240 out:
241 OUTB(np, nc_scntl1, 0);
242 return retv;
243 }
244
245 /*
246 * Select SCSI clock frequency
247 */
248 static void sym_selectclock(struct sym_hcb *np, u_char scntl3)
249 {
250 /*
251 * If multiplier not present or not selected, leave here.
252 */
253 if (np->multiplier <= 1) {
254 OUTB(np, nc_scntl3, scntl3);
255 return;
256 }
257
258 if (sym_verbose >= 2)
259 printf ("%s: enabling clock multiplier\n", sym_name(np));
260
261 OUTB(np, nc_stest1, DBLEN); /* Enable clock multiplier */
262 /*
263 * Wait for the LCKFRQ bit to be set if supported by the chip.
264 * Otherwise wait 50 micro-seconds (at least).
265 */
266 if (np->features & FE_LCKFRQ) {
267 int i = 20;
268 while (!(INB(np, nc_stest4) & LCKFRQ) && --i > 0)
269 udelay(20);
270 if (!i)
271 printf("%s: the chip cannot lock the frequency\n",
272 sym_name(np));
273 } else {
274 INB(np, nc_mbox1);
275 udelay(50+10);
276 }
277 OUTB(np, nc_stest3, HSC); /* Halt the scsi clock */
278 OUTB(np, nc_scntl3, scntl3);
279 OUTB(np, nc_stest1, (DBLEN|DBLSEL));/* Select clock multiplier */
280 OUTB(np, nc_stest3, 0x00); /* Restart scsi clock */
281 }
282
283
284 /*
285 * Determine the chip's clock frequency.
286 *
287 * This is essential for the negotiation of the synchronous
288 * transfer rate.
289 *
290 * Note: we have to return the correct value.
291 * THERE IS NO SAFE DEFAULT VALUE.
292 *
293 * Most NCR/SYMBIOS boards are delivered with a 40 Mhz clock.
294 * 53C860 and 53C875 rev. 1 support fast20 transfers but
295 * do not have a clock doubler and so are provided with a
296 * 80 MHz clock. All other fast20 boards incorporate a doubler
297 * and so should be delivered with a 40 MHz clock.
298 * The recent fast40 chips (895/896/895A/1010) use a 40 Mhz base
299 * clock and provide a clock quadrupler (160 Mhz).
300 */
301
302 /*
303 * calculate SCSI clock frequency (in KHz)
304 */
305 static unsigned getfreq (struct sym_hcb *np, int gen)
306 {
307 unsigned int ms = 0;
308 unsigned int f;
309
310 /*
311 * Measure GEN timer delay in order
312 * to calculate SCSI clock frequency
313 *
314 * This code will never execute too
315 * many loop iterations (if DELAY is
316 * reasonably correct). It could get
317 * too low a delay (too high a freq.)
318 * if the CPU is slow executing the
319 * loop for some reason (an NMI, for
320 * example). For this reason we will
321 * if multiple measurements are to be
322 * performed trust the higher delay
323 * (lower frequency returned).
324 */
325 OUTW(np, nc_sien, 0); /* mask all scsi interrupts */
326 INW(np, nc_sist); /* clear pending scsi interrupt */
327 OUTB(np, nc_dien, 0); /* mask all dma interrupts */
328 INW(np, nc_sist); /* another one, just to be sure :) */
329 /*
330 * The C1010-33 core does not report GEN in SIST,
331 * if this interrupt is masked in SIEN.
332 * I don't know yet if the C1010-66 behaves the same way.
333 */
334 if (np->features & FE_C10) {
335 OUTW(np, nc_sien, GEN);
336 OUTB(np, nc_istat1, SIRQD);
337 }
338 OUTB(np, nc_scntl3, 4); /* set pre-scaler to divide by 3 */
339 OUTB(np, nc_stime1, 0); /* disable general purpose timer */
340 OUTB(np, nc_stime1, gen); /* set to nominal delay of 1<<gen * 125us */
341 while (!(INW(np, nc_sist) & GEN) && ms++ < 100000)
342 udelay(1000/4); /* count in 1/4 of ms */
343 OUTB(np, nc_stime1, 0); /* disable general purpose timer */
344 /*
345 * Undo C1010-33 specific settings.
346 */
347 if (np->features & FE_C10) {
348 OUTW(np, nc_sien, 0);
349 OUTB(np, nc_istat1, 0);
350 }
351 /*
352 * set prescaler to divide by whatever 0 means
353 * 0 ought to choose divide by 2, but appears
354 * to set divide by 3.5 mode in my 53c810 ...
355 */
356 OUTB(np, nc_scntl3, 0);
357
358 /*
359 * adjust for prescaler, and convert into KHz
360 */
361 f = ms ? ((1 << gen) * (4340*4)) / ms : 0;
362
363 /*
364 * The C1010-33 result is biased by a factor
365 * of 2/3 compared to earlier chips.
366 */
367 if (np->features & FE_C10)
368 f = (f * 2) / 3;
369
370 if (sym_verbose >= 2)
371 printf ("%s: Delay (GEN=%d): %u msec, %u KHz\n",
372 sym_name(np), gen, ms/4, f);
373
374 return f;
375 }
376
377 static unsigned sym_getfreq (struct sym_hcb *np)
378 {
379 u_int f1, f2;
380 int gen = 8;
381
382 getfreq (np, gen); /* throw away first result */
383 f1 = getfreq (np, gen);
384 f2 = getfreq (np, gen);
385 if (f1 > f2) f1 = f2; /* trust lower result */
386 return f1;
387 }
388
389 /*
390 * Get/probe chip SCSI clock frequency
391 */
392 static void sym_getclock (struct sym_hcb *np, int mult)
393 {
394 unsigned char scntl3 = np->sv_scntl3;
395 unsigned char stest1 = np->sv_stest1;
396 unsigned f1;
397
398 np->multiplier = 1;
399 f1 = 40000;
400 /*
401 * True with 875/895/896/895A with clock multiplier selected
402 */
403 if (mult > 1 && (stest1 & (DBLEN+DBLSEL)) == DBLEN+DBLSEL) {
404 if (sym_verbose >= 2)
405 printf ("%s: clock multiplier found\n", sym_name(np));
406 np->multiplier = mult;
407 }
408
409 /*
410 * If multiplier not found or scntl3 not 7,5,3,
411 * reset chip and get frequency from general purpose timer.
412 * Otherwise trust scntl3 BIOS setting.
413 */
414 if (np->multiplier != mult || (scntl3 & 7) < 3 || !(scntl3 & 1)) {
415 OUTB(np, nc_stest1, 0); /* make sure doubler is OFF */
416 f1 = sym_getfreq (np);
417
418 if (sym_verbose)
419 printf ("%s: chip clock is %uKHz\n", sym_name(np), f1);
420
421 if (f1 < 45000) f1 = 40000;
422 else if (f1 < 55000) f1 = 50000;
423 else f1 = 80000;
424
425 if (f1 < 80000 && mult > 1) {
426 if (sym_verbose >= 2)
427 printf ("%s: clock multiplier assumed\n",
428 sym_name(np));
429 np->multiplier = mult;
430 }
431 } else {
432 if ((scntl3 & 7) == 3) f1 = 40000;
433 else if ((scntl3 & 7) == 5) f1 = 80000;
434 else f1 = 160000;
435
436 f1 /= np->multiplier;
437 }
438
439 /*
440 * Compute controller synchronous parameters.
441 */
442 f1 *= np->multiplier;
443 np->clock_khz = f1;
444 }
445
446 /*
447 * Get/probe PCI clock frequency
448 */
449 static int sym_getpciclock (struct sym_hcb *np)
450 {
451 int f = 0;
452
453 /*
454 * For now, we only need to know about the actual
455 * PCI BUS clock frequency for C1010-66 chips.
456 */
457 #if 1
458 if (np->features & FE_66MHZ) {
459 #else
460 if (1) {
461 #endif
462 OUTB(np, nc_stest1, SCLK); /* Use the PCI clock as SCSI clock */
463 f = sym_getfreq(np);
464 OUTB(np, nc_stest1, 0);
465 }
466 np->pciclk_khz = f;
467
468 return f;
469 }
470
471 /*
472 * SYMBIOS chip clock divisor table.
473 *
474 * Divisors are multiplied by 10,000,000 in order to make
475 * calculations more simple.
476 */
477 #define _5M 5000000
478 static const u32 div_10M[] = {2*_5M, 3*_5M, 4*_5M, 6*_5M, 8*_5M, 12*_5M, 16*_5M};
479
480 /*
481 * Get clock factor and sync divisor for a given
482 * synchronous factor period.
483 */
484 static int
485 sym_getsync(struct sym_hcb *np, u_char dt, u_char sfac, u_char *divp, u_char *fakp)
486 {
487 u32 clk = np->clock_khz; /* SCSI clock frequency in kHz */
488 int div = np->clock_divn; /* Number of divisors supported */
489 u32 fak; /* Sync factor in sxfer */
490 u32 per; /* Period in tenths of ns */
491 u32 kpc; /* (per * clk) */
492 int ret;
493
494 /*
495 * Compute the synchronous period in tenths of nano-seconds
496 */
497 if (dt && sfac <= 9) per = 125;
498 else if (sfac <= 10) per = 250;
499 else if (sfac == 11) per = 303;
500 else if (sfac == 12) per = 500;
501 else per = 40 * sfac;
502 ret = per;
503
504 kpc = per * clk;
505 if (dt)
506 kpc <<= 1;
507
508 /*
509 * For earliest C10 revision 0, we cannot use extra
510 * clocks for the setting of the SCSI clocking.
511 * Note that this limits the lowest sync data transfer
512 * to 5 Mega-transfers per second and may result in
513 * using higher clock divisors.
514 */
515 #if 1
516 if ((np->features & (FE_C10|FE_U3EN)) == FE_C10) {
517 /*
518 * Look for the lowest clock divisor that allows an
519 * output speed not faster than the period.
520 */
521 while (div > 0) {
522 --div;
523 if (kpc > (div_10M[div] << 2)) {
524 ++div;
525 break;
526 }
527 }
528 fak = 0; /* No extra clocks */
529 if (div == np->clock_divn) { /* Are we too fast ? */
530 ret = -1;
531 }
532 *divp = div;
533 *fakp = fak;
534 return ret;
535 }
536 #endif
537
538 /*
539 * Look for the greatest clock divisor that allows an
540 * input speed faster than the period.
541 */
542 while (div-- > 0)
543 if (kpc >= (div_10M[div] << 2)) break;
544
545 /*
546 * Calculate the lowest clock factor that allows an output
547 * speed not faster than the period, and the max output speed.
548 * If fak >= 1 we will set both XCLKH_ST and XCLKH_DT.
549 * If fak >= 2 we will also set XCLKS_ST and XCLKS_DT.
550 */
551 if (dt) {
552 fak = (kpc - 1) / (div_10M[div] << 1) + 1 - 2;
553 /* ret = ((2+fak)*div_10M[div])/np->clock_khz; */
554 } else {
555 fak = (kpc - 1) / div_10M[div] + 1 - 4;
556 /* ret = ((4+fak)*div_10M[div])/np->clock_khz; */
557 }
558
559 /*
560 * Check against our hardware limits, or bugs :).
561 */
562 if (fak > 2) {
563 fak = 2;
564 ret = -1;
565 }
566
567 /*
568 * Compute and return sync parameters.
569 */
570 *divp = div;
571 *fakp = fak;
572
573 return ret;
574 }
575
576 /*
577 * SYMBIOS chips allow burst lengths of 2, 4, 8, 16, 32, 64,
578 * 128 transfers. All chips support at least 16 transfers
579 * bursts. The 825A, 875 and 895 chips support bursts of up
580 * to 128 transfers and the 895A and 896 support bursts of up
581 * to 64 transfers. All other chips support up to 16
582 * transfers bursts.
583 *
584 * For PCI 32 bit data transfers each transfer is a DWORD.
585 * It is a QUADWORD (8 bytes) for PCI 64 bit data transfers.
586 *
587 * We use log base 2 (burst length) as internal code, with
588 * value 0 meaning "burst disabled".
589 */
590
591 /*
592 * Burst length from burst code.
593 */
594 #define burst_length(bc) (!(bc))? 0 : 1 << (bc)
595
596 /*
597 * Burst code from io register bits.
598 */
599 #define burst_code(dmode, ctest4, ctest5) \
600 (ctest4) & 0x80? 0 : (((dmode) & 0xc0) >> 6) + ((ctest5) & 0x04) + 1
601
602 /*
603 * Set initial io register bits from burst code.
604 */
605 static inline void sym_init_burst(struct sym_hcb *np, u_char bc)
606 {
607 np->rv_ctest4 &= ~0x80;
608 np->rv_dmode &= ~(0x3 << 6);
609 np->rv_ctest5 &= ~0x4;
610
611 if (!bc) {
612 np->rv_ctest4 |= 0x80;
613 }
614 else {
615 --bc;
616 np->rv_dmode |= ((bc & 0x3) << 6);
617 np->rv_ctest5 |= (bc & 0x4);
618 }
619 }
620
621 /*
622 * Save initial settings of some IO registers.
623 * Assumed to have been set by BIOS.
624 * We cannot reset the chip prior to reading the
625 * IO registers, since informations will be lost.
626 * Since the SCRIPTS processor may be running, this
627 * is not safe on paper, but it seems to work quite
628 * well. :)
629 */
630 static void sym_save_initial_setting (struct sym_hcb *np)
631 {
632 np->sv_scntl0 = INB(np, nc_scntl0) & 0x0a;
633 np->sv_scntl3 = INB(np, nc_scntl3) & 0x07;
634 np->sv_dmode = INB(np, nc_dmode) & 0xce;
635 np->sv_dcntl = INB(np, nc_dcntl) & 0xa8;
636 np->sv_ctest3 = INB(np, nc_ctest3) & 0x01;
637 np->sv_ctest4 = INB(np, nc_ctest4) & 0x80;
638 np->sv_gpcntl = INB(np, nc_gpcntl);
639 np->sv_stest1 = INB(np, nc_stest1);
640 np->sv_stest2 = INB(np, nc_stest2) & 0x20;
641 np->sv_stest4 = INB(np, nc_stest4);
642 if (np->features & FE_C10) { /* Always large DMA fifo + ultra3 */
643 np->sv_scntl4 = INB(np, nc_scntl4);
644 np->sv_ctest5 = INB(np, nc_ctest5) & 0x04;
645 }
646 else
647 np->sv_ctest5 = INB(np, nc_ctest5) & 0x24;
648 }
649
650 /*
651 * Set SCSI BUS mode.
652 * - LVD capable chips (895/895A/896/1010) report the current BUS mode
653 * through the STEST4 IO register.
654 * - For previous generation chips (825/825A/875), the user has to tell us
655 * how to check against HVD, since a 100% safe algorithm is not possible.
656 */
657 static void sym_set_bus_mode(struct sym_hcb *np, struct sym_nvram *nvram)
658 {
659 if (np->scsi_mode)
660 return;
661
662 np->scsi_mode = SMODE_SE;
663 if (np->features & (FE_ULTRA2|FE_ULTRA3))
664 np->scsi_mode = (np->sv_stest4 & SMODE);
665 else if (np->features & FE_DIFF) {
666 if (SYM_SETUP_SCSI_DIFF == 1) {
667 if (np->sv_scntl3) {
668 if (np->sv_stest2 & 0x20)
669 np->scsi_mode = SMODE_HVD;
670 } else if (nvram->type == SYM_SYMBIOS_NVRAM) {
671 if (!(INB(np, nc_gpreg) & 0x08))
672 np->scsi_mode = SMODE_HVD;
673 }
674 } else if (SYM_SETUP_SCSI_DIFF == 2)
675 np->scsi_mode = SMODE_HVD;
676 }
677 if (np->scsi_mode == SMODE_HVD)
678 np->rv_stest2 |= 0x20;
679 }
680
681 /*
682 * Prepare io register values used by sym_start_up()
683 * according to selected and supported features.
684 */
685 static int sym_prepare_setting(struct Scsi_Host *shost, struct sym_hcb *np, struct sym_nvram *nvram)
686 {
687 struct sym_data *sym_data = shost_priv(shost);
688 struct pci_dev *pdev = sym_data->pdev;
689 u_char burst_max;
690 u32 period;
691 int i;
692
693 np->maxwide = (np->features & FE_WIDE) ? 1 : 0;
694
695 /*
696 * Guess the frequency of the chip's clock.
697 */
698 if (np->features & (FE_ULTRA3 | FE_ULTRA2))
699 np->clock_khz = 160000;
700 else if (np->features & FE_ULTRA)
701 np->clock_khz = 80000;
702 else
703 np->clock_khz = 40000;
704
705 /*
706 * Get the clock multiplier factor.
707 */
708 if (np->features & FE_QUAD)
709 np->multiplier = 4;
710 else if (np->features & FE_DBLR)
711 np->multiplier = 2;
712 else
713 np->multiplier = 1;
714
715 /*
716 * Measure SCSI clock frequency for chips
717 * it may vary from assumed one.
718 */
719 if (np->features & FE_VARCLK)
720 sym_getclock(np, np->multiplier);
721
722 /*
723 * Divisor to be used for async (timer pre-scaler).
724 */
725 i = np->clock_divn - 1;
726 while (--i >= 0) {
727 if (10ul * SYM_CONF_MIN_ASYNC * np->clock_khz > div_10M[i]) {
728 ++i;
729 break;
730 }
731 }
732 np->rv_scntl3 = i+1;
733
734 /*
735 * The C1010 uses hardwired divisors for async.
736 * So, we just throw away, the async. divisor.:-)
737 */
738 if (np->features & FE_C10)
739 np->rv_scntl3 = 0;
740
741 /*
742 * Minimum synchronous period factor supported by the chip.
743 * Btw, 'period' is in tenths of nanoseconds.
744 */
745 period = (4 * div_10M[0] + np->clock_khz - 1) / np->clock_khz;
746
747 if (period <= 250) np->minsync = 10;
748 else if (period <= 303) np->minsync = 11;
749 else if (period <= 500) np->minsync = 12;
750 else np->minsync = (period + 40 - 1) / 40;
751
752 /*
753 * Check against chip SCSI standard support (SCSI-2,ULTRA,ULTRA2).
754 */
755 if (np->minsync < 25 &&
756 !(np->features & (FE_ULTRA|FE_ULTRA2|FE_ULTRA3)))
757 np->minsync = 25;
758 else if (np->minsync < 12 &&
759 !(np->features & (FE_ULTRA2|FE_ULTRA3)))
760 np->minsync = 12;
761
762 /*
763 * Maximum synchronous period factor supported by the chip.
764 */
765 period = (11 * div_10M[np->clock_divn - 1]) / (4 * np->clock_khz);
766 np->maxsync = period > 2540 ? 254 : period / 10;
767
768 /*
769 * If chip is a C1010, guess the sync limits in DT mode.
770 */
771 if ((np->features & (FE_C10|FE_ULTRA3)) == (FE_C10|FE_ULTRA3)) {
772 if (np->clock_khz == 160000) {
773 np->minsync_dt = 9;
774 np->maxsync_dt = 50;
775 np->maxoffs_dt = nvram->type ? 62 : 31;
776 }
777 }
778
779 /*
780 * 64 bit addressing (895A/896/1010) ?
781 */
782 if (np->features & FE_DAC) {
783 if (!use_dac(np))
784 np->rv_ccntl1 |= (DDAC);
785 else if (SYM_CONF_DMA_ADDRESSING_MODE == 1)
786 np->rv_ccntl1 |= (XTIMOD | EXTIBMV);
787 else if (SYM_CONF_DMA_ADDRESSING_MODE == 2)
788 np->rv_ccntl1 |= (0 | EXTIBMV);
789 }
790
791 /*
792 * Phase mismatch handled by SCRIPTS (895A/896/1010) ?
793 */
794 if (np->features & FE_NOPM)
795 np->rv_ccntl0 |= (ENPMJ);
796
797 /*
798 * C1010-33 Errata: Part Number:609-039638 (rev. 1) is fixed.
799 * In dual channel mode, contention occurs if internal cycles
800 * are used. Disable internal cycles.
801 */
802 if (pdev->device == PCI_DEVICE_ID_LSI_53C1010_33 &&
803 pdev->revision < 0x1)
804 np->rv_ccntl0 |= DILS;
805
806 /*
807 * Select burst length (dwords)
808 */
809 burst_max = SYM_SETUP_BURST_ORDER;
810 if (burst_max == 255)
811 burst_max = burst_code(np->sv_dmode, np->sv_ctest4,
812 np->sv_ctest5);
813 if (burst_max > 7)
814 burst_max = 7;
815 if (burst_max > np->maxburst)
816 burst_max = np->maxburst;
817
818 /*
819 * DEL 352 - 53C810 Rev x11 - Part Number 609-0392140 - ITEM 2.
820 * This chip and the 860 Rev 1 may wrongly use PCI cache line
821 * based transactions on LOAD/STORE instructions. So we have
822 * to prevent these chips from using such PCI transactions in
823 * this driver. The generic ncr driver that does not use
824 * LOAD/STORE instructions does not need this work-around.
825 */
826 if ((pdev->device == PCI_DEVICE_ID_NCR_53C810 &&
827 pdev->revision >= 0x10 && pdev->revision <= 0x11) ||
828 (pdev->device == PCI_DEVICE_ID_NCR_53C860 &&
829 pdev->revision <= 0x1))
830 np->features &= ~(FE_WRIE|FE_ERL|FE_ERMP);
831
832 /*
833 * Select all supported special features.
834 * If we are using on-board RAM for scripts, prefetch (PFEN)
835 * does not help, but burst op fetch (BOF) does.
836 * Disabling PFEN makes sure BOF will be used.
837 */
838 if (np->features & FE_ERL)
839 np->rv_dmode |= ERL; /* Enable Read Line */
840 if (np->features & FE_BOF)
841 np->rv_dmode |= BOF; /* Burst Opcode Fetch */
842 if (np->features & FE_ERMP)
843 np->rv_dmode |= ERMP; /* Enable Read Multiple */
844 #if 1
845 if ((np->features & FE_PFEN) && !np->ram_ba)
846 #else
847 if (np->features & FE_PFEN)
848 #endif
849 np->rv_dcntl |= PFEN; /* Prefetch Enable */
850 if (np->features & FE_CLSE)
851 np->rv_dcntl |= CLSE; /* Cache Line Size Enable */
852 if (np->features & FE_WRIE)
853 np->rv_ctest3 |= WRIE; /* Write and Invalidate */
854 if (np->features & FE_DFS)
855 np->rv_ctest5 |= DFS; /* Dma Fifo Size */
856
857 /*
858 * Select some other
859 */
860 np->rv_ctest4 |= MPEE; /* Master parity checking */
861 np->rv_scntl0 |= 0x0a; /* full arb., ena parity, par->ATN */
862
863 /*
864 * Get parity checking, host ID and verbose mode from NVRAM
865 */
866 np->myaddr = 255;
867 np->scsi_mode = 0;
868 sym_nvram_setup_host(shost, np, nvram);
869
870 /*
871 * Get SCSI addr of host adapter (set by bios?).
872 */
873 if (np->myaddr == 255) {
874 np->myaddr = INB(np, nc_scid) & 0x07;
875 if (!np->myaddr)
876 np->myaddr = SYM_SETUP_HOST_ID;
877 }
878
879 /*
880 * Prepare initial io register bits for burst length
881 */
882 sym_init_burst(np, burst_max);
883
884 sym_set_bus_mode(np, nvram);
885
886 /*
887 * Set LED support from SCRIPTS.
888 * Ignore this feature for boards known to use a
889 * specific GPIO wiring and for the 895A, 896
890 * and 1010 that drive the LED directly.
891 */
892 if ((SYM_SETUP_SCSI_LED ||
893 (nvram->type == SYM_SYMBIOS_NVRAM ||
894 (nvram->type == SYM_TEKRAM_NVRAM &&
895 pdev->device == PCI_DEVICE_ID_NCR_53C895))) &&
896 !(np->features & FE_LEDC) && !(np->sv_gpcntl & 0x01))
897 np->features |= FE_LED0;
898
899 /*
900 * Set irq mode.
901 */
902 switch(SYM_SETUP_IRQ_MODE & 3) {
903 case 2:
904 np->rv_dcntl |= IRQM;
905 break;
906 case 1:
907 np->rv_dcntl |= (np->sv_dcntl & IRQM);
908 break;
909 default:
910 break;
911 }
912
913 /*
914 * Configure targets according to driver setup.
915 * If NVRAM present get targets setup from NVRAM.
916 */
917 for (i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) {
918 struct sym_tcb *tp = &np->target[i];
919
920 tp->usrflags |= (SYM_DISC_ENABLED | SYM_TAGS_ENABLED);
921 tp->usrtags = SYM_SETUP_MAX_TAG;
922 tp->usr_width = np->maxwide;
923 tp->usr_period = 9;
924
925 sym_nvram_setup_target(tp, i, nvram);
926
927 if (!tp->usrtags)
928 tp->usrflags &= ~SYM_TAGS_ENABLED;
929 }
930
931 /*
932 * Let user know about the settings.
933 */
934 printf("%s: %s, ID %d, Fast-%d, %s, %s\n", sym_name(np),
935 sym_nvram_type(nvram), np->myaddr,
936 (np->features & FE_ULTRA3) ? 80 :
937 (np->features & FE_ULTRA2) ? 40 :
938 (np->features & FE_ULTRA) ? 20 : 10,
939 sym_scsi_bus_mode(np->scsi_mode),
940 (np->rv_scntl0 & 0xa) ? "parity checking" : "NO parity");
941 /*
942 * Tell him more on demand.
943 */
944 if (sym_verbose) {
945 printf("%s: %s IRQ line driver%s\n",
946 sym_name(np),
947 np->rv_dcntl & IRQM ? "totem pole" : "open drain",
948 np->ram_ba ? ", using on-chip SRAM" : "");
949 printf("%s: using %s firmware.\n", sym_name(np), np->fw_name);
950 if (np->features & FE_NOPM)
951 printf("%s: handling phase mismatch from SCRIPTS.\n",
952 sym_name(np));
953 }
954 /*
955 * And still more.
956 */
957 if (sym_verbose >= 2) {
958 printf ("%s: initial SCNTL3/DMODE/DCNTL/CTEST3/4/5 = "
959 "(hex) %02x/%02x/%02x/%02x/%02x/%02x\n",
960 sym_name(np), np->sv_scntl3, np->sv_dmode, np->sv_dcntl,
961 np->sv_ctest3, np->sv_ctest4, np->sv_ctest5);
962
963 printf ("%s: final SCNTL3/DMODE/DCNTL/CTEST3/4/5 = "
964 "(hex) %02x/%02x/%02x/%02x/%02x/%02x\n",
965 sym_name(np), np->rv_scntl3, np->rv_dmode, np->rv_dcntl,
966 np->rv_ctest3, np->rv_ctest4, np->rv_ctest5);
967 }
968
969 return 0;
970 }
971
972 /*
973 * Test the pci bus snoop logic :-(
974 *
975 * Has to be called with interrupts disabled.
976 */
977 #ifdef CONFIG_SCSI_SYM53C8XX_MMIO
978 static int sym_regtest(struct sym_hcb *np)
979 {
980 register volatile u32 data;
981 /*
982 * chip registers may NOT be cached.
983 * write 0xffffffff to a read only register area,
984 * and try to read it back.
985 */
986 data = 0xffffffff;
987 OUTL(np, nc_dstat, data);
988 data = INL(np, nc_dstat);
989 #if 1
990 if (data == 0xffffffff) {
991 #else
992 if ((data & 0xe2f0fffd) != 0x02000080) {
993 #endif
994 printf ("CACHE TEST FAILED: reg dstat-sstat2 readback %x.\n",
995 (unsigned) data);
996 return 0x10;
997 }
998 return 0;
999 }
1000 #else
1001 static inline int sym_regtest(struct sym_hcb *np)
1002 {
1003 return 0;
1004 }
1005 #endif
1006
1007 static int sym_snooptest(struct sym_hcb *np)
1008 {
1009 u32 sym_rd, sym_wr, sym_bk, host_rd, host_wr, pc, dstat;
1010 int i, err;
1011
1012 err = sym_regtest(np);
1013 if (err)
1014 return err;
1015 restart_test:
1016 /*
1017 * Enable Master Parity Checking as we intend
1018 * to enable it for normal operations.
1019 */
1020 OUTB(np, nc_ctest4, (np->rv_ctest4 & MPEE));
1021 /*
1022 * init
1023 */
1024 pc = SCRIPTZ_BA(np, snooptest);
1025 host_wr = 1;
1026 sym_wr = 2;
1027 /*
1028 * Set memory and register.
1029 */
1030 np->scratch = cpu_to_scr(host_wr);
1031 OUTL(np, nc_temp, sym_wr);
1032 /*
1033 * Start script (exchange values)
1034 */
1035 OUTL(np, nc_dsa, np->hcb_ba);
1036 OUTL_DSP(np, pc);
1037 /*
1038 * Wait 'til done (with timeout)
1039 */
1040 for (i=0; i<SYM_SNOOP_TIMEOUT; i++)
1041 if (INB(np, nc_istat) & (INTF|SIP|DIP))
1042 break;
1043 if (i>=SYM_SNOOP_TIMEOUT) {
1044 printf ("CACHE TEST FAILED: timeout.\n");
1045 return (0x20);
1046 }
1047 /*
1048 * Check for fatal DMA errors.
1049 */
1050 dstat = INB(np, nc_dstat);
1051 #if 1 /* Band aiding for broken hardwares that fail PCI parity */
1052 if ((dstat & MDPE) && (np->rv_ctest4 & MPEE)) {
1053 printf ("%s: PCI DATA PARITY ERROR DETECTED - "
1054 "DISABLING MASTER DATA PARITY CHECKING.\n",
1055 sym_name(np));
1056 np->rv_ctest4 &= ~MPEE;
1057 goto restart_test;
1058 }
1059 #endif
1060 if (dstat & (MDPE|BF|IID)) {
1061 printf ("CACHE TEST FAILED: DMA error (dstat=0x%02x).", dstat);
1062 return (0x80);
1063 }
1064 /*
1065 * Save termination position.
1066 */
1067 pc = INL(np, nc_dsp);
1068 /*
1069 * Read memory and register.
1070 */
1071 host_rd = scr_to_cpu(np->scratch);
1072 sym_rd = INL(np, nc_scratcha);
1073 sym_bk = INL(np, nc_temp);
1074 /*
1075 * Check termination position.
1076 */
1077 if (pc != SCRIPTZ_BA(np, snoopend)+8) {
1078 printf ("CACHE TEST FAILED: script execution failed.\n");
1079 printf ("start=%08lx, pc=%08lx, end=%08lx\n",
1080 (u_long) SCRIPTZ_BA(np, snooptest), (u_long) pc,
1081 (u_long) SCRIPTZ_BA(np, snoopend) +8);
1082 return (0x40);
1083 }
1084 /*
1085 * Show results.
1086 */
1087 if (host_wr != sym_rd) {
1088 printf ("CACHE TEST FAILED: host wrote %d, chip read %d.\n",
1089 (int) host_wr, (int) sym_rd);
1090 err |= 1;
1091 }
1092 if (host_rd != sym_wr) {
1093 printf ("CACHE TEST FAILED: chip wrote %d, host read %d.\n",
1094 (int) sym_wr, (int) host_rd);
1095 err |= 2;
1096 }
1097 if (sym_bk != sym_wr) {
1098 printf ("CACHE TEST FAILED: chip wrote %d, read back %d.\n",
1099 (int) sym_wr, (int) sym_bk);
1100 err |= 4;
1101 }
1102
1103 return err;
1104 }
1105
1106 /*
1107 * log message for real hard errors
1108 *
1109 * sym0 targ 0?: ERROR (ds:si) (so-si-sd) (sx/s3/s4) @ name (dsp:dbc).
1110 * reg: r0 r1 r2 r3 r4 r5 r6 ..... rf.
1111 *
1112 * exception register:
1113 * ds: dstat
1114 * si: sist
1115 *
1116 * SCSI bus lines:
1117 * so: control lines as driven by chip.
1118 * si: control lines as seen by chip.
1119 * sd: scsi data lines as seen by chip.
1120 *
1121 * wide/fastmode:
1122 * sx: sxfer (see the manual)
1123 * s3: scntl3 (see the manual)
1124 * s4: scntl4 (see the manual)
1125 *
1126 * current script command:
1127 * dsp: script address (relative to start of script).
1128 * dbc: first word of script command.
1129 *
1130 * First 24 register of the chip:
1131 * r0..rf
1132 */
1133 static void sym_log_hard_error(struct Scsi_Host *shost, u_short sist, u_char dstat)
1134 {
1135 struct sym_hcb *np = sym_get_hcb(shost);
1136 u32 dsp;
1137 int script_ofs;
1138 int script_size;
1139 char *script_name;
1140 u_char *script_base;
1141 int i;
1142
1143 dsp = INL(np, nc_dsp);
1144
1145 if (dsp > np->scripta_ba &&
1146 dsp <= np->scripta_ba + np->scripta_sz) {
1147 script_ofs = dsp - np->scripta_ba;
1148 script_size = np->scripta_sz;
1149 script_base = (u_char *) np->scripta0;
1150 script_name = "scripta";
1151 }
1152 else if (np->scriptb_ba < dsp &&
1153 dsp <= np->scriptb_ba + np->scriptb_sz) {
1154 script_ofs = dsp - np->scriptb_ba;
1155 script_size = np->scriptb_sz;
1156 script_base = (u_char *) np->scriptb0;
1157 script_name = "scriptb";
1158 } else {
1159 script_ofs = dsp;
1160 script_size = 0;
1161 script_base = NULL;
1162 script_name = "mem";
1163 }
1164
1165 printf ("%s:%d: ERROR (%x:%x) (%x-%x-%x) (%x/%x/%x) @ (%s %x:%08x).\n",
1166 sym_name(np), (unsigned)INB(np, nc_sdid)&0x0f, dstat, sist,
1167 (unsigned)INB(np, nc_socl), (unsigned)INB(np, nc_sbcl),
1168 (unsigned)INB(np, nc_sbdl), (unsigned)INB(np, nc_sxfer),
1169 (unsigned)INB(np, nc_scntl3),
1170 (np->features & FE_C10) ? (unsigned)INB(np, nc_scntl4) : 0,
1171 script_name, script_ofs, (unsigned)INL(np, nc_dbc));
1172
1173 if (((script_ofs & 3) == 0) &&
1174 (unsigned)script_ofs < script_size) {
1175 printf ("%s: script cmd = %08x\n", sym_name(np),
1176 scr_to_cpu((int) *(u32 *)(script_base + script_ofs)));
1177 }
1178
1179 printf("%s: regdump:", sym_name(np));
1180 for (i = 0; i < 24; i++)
1181 printf(" %02x", (unsigned)INB_OFF(np, i));
1182 printf(".\n");
1183
1184 /*
1185 * PCI BUS error.
1186 */
1187 if (dstat & (MDPE|BF))
1188 sym_log_bus_error(shost);
1189 }
1190
1191 void sym_dump_registers(struct Scsi_Host *shost)
1192 {
1193 struct sym_hcb *np = sym_get_hcb(shost);
1194 u_short sist;
1195 u_char dstat;
1196
1197 sist = INW(np, nc_sist);
1198 dstat = INB(np, nc_dstat);
1199 sym_log_hard_error(shost, sist, dstat);
1200 }
1201
1202 static struct sym_chip sym_dev_table[] = {
1203 {PCI_DEVICE_ID_NCR_53C810, 0x0f, "810", 4, 8, 4, 64,
1204 FE_ERL}
1205 ,
1206 #ifdef SYM_DEBUG_GENERIC_SUPPORT
1207 {PCI_DEVICE_ID_NCR_53C810, 0xff, "810a", 4, 8, 4, 1,
1208 FE_BOF}
1209 ,
1210 #else
1211 {PCI_DEVICE_ID_NCR_53C810, 0xff, "810a", 4, 8, 4, 1,
1212 FE_CACHE_SET|FE_LDSTR|FE_PFEN|FE_BOF}
1213 ,
1214 #endif
1215 {PCI_DEVICE_ID_NCR_53C815, 0xff, "815", 4, 8, 4, 64,
1216 FE_BOF|FE_ERL}
1217 ,
1218 {PCI_DEVICE_ID_NCR_53C825, 0x0f, "825", 6, 8, 4, 64,
1219 FE_WIDE|FE_BOF|FE_ERL|FE_DIFF}
1220 ,
1221 {PCI_DEVICE_ID_NCR_53C825, 0xff, "825a", 6, 8, 4, 2,
1222 FE_WIDE|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM|FE_DIFF}
1223 ,
1224 {PCI_DEVICE_ID_NCR_53C860, 0xff, "860", 4, 8, 5, 1,
1225 FE_ULTRA|FE_CACHE_SET|FE_BOF|FE_LDSTR|FE_PFEN}
1226 ,
1227 {PCI_DEVICE_ID_NCR_53C875, 0x01, "875", 6, 16, 5, 2,
1228 FE_WIDE|FE_ULTRA|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|
1229 FE_RAM|FE_DIFF|FE_VARCLK}
1230 ,
1231 {PCI_DEVICE_ID_NCR_53C875, 0xff, "875", 6, 16, 5, 2,
1232 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|
1233 FE_RAM|FE_DIFF|FE_VARCLK}
1234 ,
1235 {PCI_DEVICE_ID_NCR_53C875J, 0xff, "875J", 6, 16, 5, 2,
1236 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|
1237 FE_RAM|FE_DIFF|FE_VARCLK}
1238 ,
1239 {PCI_DEVICE_ID_NCR_53C885, 0xff, "885", 6, 16, 5, 2,
1240 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|
1241 FE_RAM|FE_DIFF|FE_VARCLK}
1242 ,
1243 #ifdef SYM_DEBUG_GENERIC_SUPPORT
1244 {PCI_DEVICE_ID_NCR_53C895, 0xff, "895", 6, 31, 7, 2,
1245 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|
1246 FE_RAM|FE_LCKFRQ}
1247 ,
1248 #else
1249 {PCI_DEVICE_ID_NCR_53C895, 0xff, "895", 6, 31, 7, 2,
1250 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|
1251 FE_RAM|FE_LCKFRQ}
1252 ,
1253 #endif
1254 {PCI_DEVICE_ID_NCR_53C896, 0xff, "896", 6, 31, 7, 4,
1255 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|
1256 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_LCKFRQ}
1257 ,
1258 {PCI_DEVICE_ID_LSI_53C895A, 0xff, "895a", 6, 31, 7, 4,
1259 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|
1260 FE_RAM|FE_RAM8K|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_LCKFRQ}
1261 ,
1262 {PCI_DEVICE_ID_LSI_53C875A, 0xff, "875a", 6, 31, 7, 4,
1263 FE_WIDE|FE_ULTRA|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|
1264 FE_RAM|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_LCKFRQ}
1265 ,
1266 {PCI_DEVICE_ID_LSI_53C1010_33, 0x00, "1010-33", 6, 31, 7, 8,
1267 FE_WIDE|FE_ULTRA3|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFBC|FE_LDSTR|FE_PFEN|
1268 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_CRC|
1269 FE_C10}
1270 ,
1271 {PCI_DEVICE_ID_LSI_53C1010_33, 0xff, "1010-33", 6, 31, 7, 8,
1272 FE_WIDE|FE_ULTRA3|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFBC|FE_LDSTR|FE_PFEN|
1273 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_CRC|
1274 FE_C10|FE_U3EN}
1275 ,
1276 {PCI_DEVICE_ID_LSI_53C1010_66, 0xff, "1010-66", 6, 31, 7, 8,
1277 FE_WIDE|FE_ULTRA3|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFBC|FE_LDSTR|FE_PFEN|
1278 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_66MHZ|FE_CRC|
1279 FE_C10|FE_U3EN}
1280 ,
1281 {PCI_DEVICE_ID_LSI_53C1510, 0xff, "1510d", 6, 31, 7, 4,
1282 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|
1283 FE_RAM|FE_IO256|FE_LEDC}
1284 };
1285
1286 #define sym_num_devs (ARRAY_SIZE(sym_dev_table))
1287
1288 /*
1289 * Look up the chip table.
1290 *
1291 * Return a pointer to the chip entry if found,
1292 * zero otherwise.
1293 */
1294 struct sym_chip *
1295 sym_lookup_chip_table (u_short device_id, u_char revision)
1296 {
1297 struct sym_chip *chip;
1298 int i;
1299
1300 for (i = 0; i < sym_num_devs; i++) {
1301 chip = &sym_dev_table[i];
1302 if (device_id != chip->device_id)
1303 continue;
1304 if (revision > chip->revision_id)
1305 continue;
1306 return chip;
1307 }
1308
1309 return NULL;
1310 }
1311
1312 #if SYM_CONF_DMA_ADDRESSING_MODE == 2
1313 /*
1314 * Lookup the 64 bit DMA segments map.
1315 * This is only used if the direct mapping
1316 * has been unsuccessful.
1317 */
1318 int sym_lookup_dmap(struct sym_hcb *np, u32 h, int s)
1319 {
1320 int i;
1321
1322 if (!use_dac(np))
1323 goto weird;
1324
1325 /* Look up existing mappings */
1326 for (i = SYM_DMAP_SIZE-1; i > 0; i--) {
1327 if (h == np->dmap_bah[i])
1328 return i;
1329 }
1330 /* If direct mapping is free, get it */
1331 if (!np->dmap_bah[s])
1332 goto new;
1333 /* Collision -> lookup free mappings */
1334 for (s = SYM_DMAP_SIZE-1; s > 0; s--) {
1335 if (!np->dmap_bah[s])
1336 goto new;
1337 }
1338 weird:
1339 panic("sym: ran out of 64 bit DMA segment registers");
1340 return -1;
1341 new:
1342 np->dmap_bah[s] = h;
1343 np->dmap_dirty = 1;
1344 return s;
1345 }
1346
1347 /*
1348 * Update IO registers scratch C..R so they will be
1349 * in sync. with queued CCB expectations.
1350 */
1351 static void sym_update_dmap_regs(struct sym_hcb *np)
1352 {
1353 int o, i;
1354
1355 if (!np->dmap_dirty)
1356 return;
1357 o = offsetof(struct sym_reg, nc_scrx[0]);
1358 for (i = 0; i < SYM_DMAP_SIZE; i++) {
1359 OUTL_OFF(np, o, np->dmap_bah[i]);
1360 o += 4;
1361 }
1362 np->dmap_dirty = 0;
1363 }
1364 #endif
1365
1366 /* Enforce all the fiddly SPI rules and the chip limitations */
1367 static void sym_check_goals(struct sym_hcb *np, struct scsi_target *starget,
1368 struct sym_trans *goal)
1369 {
1370 if (!spi_support_wide(starget))
1371 goal->width = 0;
1372
1373 if (!spi_support_sync(starget)) {
1374 goal->iu = 0;
1375 goal->dt = 0;
1376 goal->qas = 0;
1377 goal->offset = 0;
1378 return;
1379 }
1380
1381 if (spi_support_dt(starget)) {
1382 if (spi_support_dt_only(starget))
1383 goal->dt = 1;
1384
1385 if (goal->offset == 0)
1386 goal->dt = 0;
1387 } else {
1388 goal->dt = 0;
1389 }
1390
1391 /* Some targets fail to properly negotiate DT in SE mode */
1392 if ((np->scsi_mode != SMODE_LVD) || !(np->features & FE_U3EN))
1393 goal->dt = 0;
1394
1395 if (goal->dt) {
1396 /* all DT transfers must be wide */
1397 goal->width = 1;
1398 if (goal->offset > np->maxoffs_dt)
1399 goal->offset = np->maxoffs_dt;
1400 if (goal->period < np->minsync_dt)
1401 goal->period = np->minsync_dt;
1402 if (goal->period > np->maxsync_dt)
1403 goal->period = np->maxsync_dt;
1404 } else {
1405 goal->iu = goal->qas = 0;
1406 if (goal->offset > np->maxoffs)
1407 goal->offset = np->maxoffs;
1408 if (goal->period < np->minsync)
1409 goal->period = np->minsync;
1410 if (goal->period > np->maxsync)
1411 goal->period = np->maxsync;
1412 }
1413 }
1414
1415 /*
1416 * Prepare the next negotiation message if needed.
1417 *
1418 * Fill in the part of message buffer that contains the
1419 * negotiation and the nego_status field of the CCB.
1420 * Returns the size of the message in bytes.
1421 */
1422 static int sym_prepare_nego(struct sym_hcb *np, struct sym_ccb *cp, u_char *msgptr)
1423 {
1424 struct sym_tcb *tp = &np->target[cp->target];
1425 struct scsi_target *starget = tp->starget;
1426 struct sym_trans *goal = &tp->tgoal;
1427 int msglen = 0;
1428 int nego;
1429
1430 sym_check_goals(np, starget, goal);
1431
1432 /*
1433 * Many devices implement PPR in a buggy way, so only use it if we
1434 * really want to.
1435 */
1436 if (goal->renego == NS_PPR || (goal->offset &&
1437 (goal->iu || goal->dt || goal->qas || (goal->period < 0xa)))) {
1438 nego = NS_PPR;
1439 } else if (goal->renego == NS_WIDE || goal->width) {
1440 nego = NS_WIDE;
1441 } else if (goal->renego == NS_SYNC || goal->offset) {
1442 nego = NS_SYNC;
1443 } else {
1444 goal->check_nego = 0;
1445 nego = 0;
1446 }
1447
1448 switch (nego) {
1449 case NS_SYNC:
1450 msglen += spi_populate_sync_msg(msgptr + msglen, goal->period,
1451 goal->offset);
1452 break;
1453 case NS_WIDE:
1454 msglen += spi_populate_width_msg(msgptr + msglen, goal->width);
1455 break;
1456 case NS_PPR:
1457 msglen += spi_populate_ppr_msg(msgptr + msglen, goal->period,
1458 goal->offset, goal->width,
1459 (goal->iu ? PPR_OPT_IU : 0) |
1460 (goal->dt ? PPR_OPT_DT : 0) |
1461 (goal->qas ? PPR_OPT_QAS : 0));
1462 break;
1463 }
1464
1465 cp->nego_status = nego;
1466
1467 if (nego) {
1468 tp->nego_cp = cp; /* Keep track a nego will be performed */
1469 if (DEBUG_FLAGS & DEBUG_NEGO) {
1470 sym_print_nego_msg(np, cp->target,
1471 nego == NS_SYNC ? "sync msgout" :
1472 nego == NS_WIDE ? "wide msgout" :
1473 "ppr msgout", msgptr);
1474 }
1475 }
1476
1477 return msglen;
1478 }
1479
1480 /*
1481 * Insert a job into the start queue.
1482 */
1483 void sym_put_start_queue(struct sym_hcb *np, struct sym_ccb *cp)
1484 {
1485 u_short qidx;
1486
1487 #ifdef SYM_CONF_IARB_SUPPORT
1488 /*
1489 * If the previously queued CCB is not yet done,
1490 * set the IARB hint. The SCRIPTS will go with IARB
1491 * for this job when starting the previous one.
1492 * We leave devices a chance to win arbitration by
1493 * not using more than 'iarb_max' consecutive
1494 * immediate arbitrations.
1495 */
1496 if (np->last_cp && np->iarb_count < np->iarb_max) {
1497 np->last_cp->host_flags |= HF_HINT_IARB;
1498 ++np->iarb_count;
1499 }
1500 else
1501 np->iarb_count = 0;
1502 np->last_cp = cp;
1503 #endif
1504
1505 #if SYM_CONF_DMA_ADDRESSING_MODE == 2
1506 /*
1507 * Make SCRIPTS aware of the 64 bit DMA
1508 * segment registers not being up-to-date.
1509 */
1510 if (np->dmap_dirty)
1511 cp->host_xflags |= HX_DMAP_DIRTY;
1512 #endif
1513
1514 /*
1515 * Insert first the idle task and then our job.
1516 * The MBs should ensure proper ordering.
1517 */
1518 qidx = np->squeueput + 2;
1519 if (qidx >= MAX_QUEUE*2) qidx = 0;
1520
1521 np->squeue [qidx] = cpu_to_scr(np->idletask_ba);
1522 MEMORY_WRITE_BARRIER();
1523 np->squeue [np->squeueput] = cpu_to_scr(cp->ccb_ba);
1524
1525 np->squeueput = qidx;
1526
1527 if (DEBUG_FLAGS & DEBUG_QUEUE)
1528 scmd_printk(KERN_DEBUG, cp->cmd, "queuepos=%d\n",
1529 np->squeueput);
1530
1531 /*
1532 * Script processor may be waiting for reselect.
1533 * Wake it up.
1534 */
1535 MEMORY_WRITE_BARRIER();
1536 OUTB(np, nc_istat, SIGP|np->istat_sem);
1537 }
1538
1539 #ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING
1540 /*
1541 * Start next ready-to-start CCBs.
1542 */
1543 void sym_start_next_ccbs(struct sym_hcb *np, struct sym_lcb *lp, int maxn)
1544 {
1545 SYM_QUEHEAD *qp;
1546 struct sym_ccb *cp;
1547
1548 /*
1549 * Paranoia, as usual. :-)
1550 */
1551 assert(!lp->started_tags || !lp->started_no_tag);
1552
1553 /*
1554 * Try to start as many commands as asked by caller.
1555 * Prevent from having both tagged and untagged
1556 * commands queued to the device at the same time.
1557 */
1558 while (maxn--) {
1559 qp = sym_remque_head(&lp->waiting_ccbq);
1560 if (!qp)
1561 break;
1562 cp = sym_que_entry(qp, struct sym_ccb, link2_ccbq);
1563 if (cp->tag != NO_TAG) {
1564 if (lp->started_no_tag ||
1565 lp->started_tags >= lp->started_max) {
1566 sym_insque_head(qp, &lp->waiting_ccbq);
1567 break;
1568 }
1569 lp->itlq_tbl[cp->tag] = cpu_to_scr(cp->ccb_ba);
1570 lp->head.resel_sa =
1571 cpu_to_scr(SCRIPTA_BA(np, resel_tag));
1572 ++lp->started_tags;
1573 } else {
1574 if (lp->started_no_tag || lp->started_tags) {
1575 sym_insque_head(qp, &lp->waiting_ccbq);
1576 break;
1577 }
1578 lp->head.itl_task_sa = cpu_to_scr(cp->ccb_ba);
1579 lp->head.resel_sa =
1580 cpu_to_scr(SCRIPTA_BA(np, resel_no_tag));
1581 ++lp->started_no_tag;
1582 }
1583 cp->started = 1;
1584 sym_insque_tail(qp, &lp->started_ccbq);
1585 sym_put_start_queue(np, cp);
1586 }
1587 }
1588 #endif /* SYM_OPT_HANDLE_DEVICE_QUEUEING */
1589
1590 /*
1591 * The chip may have completed jobs. Look at the DONE QUEUE.
1592 *
1593 * On paper, memory read barriers may be needed here to
1594 * prevent out of order LOADs by the CPU from having
1595 * prefetched stale data prior to DMA having occurred.
1596 */
1597 static int sym_wakeup_done (struct sym_hcb *np)
1598 {
1599 struct sym_ccb *cp;
1600 int i, n;
1601 u32 dsa;
1602
1603 n = 0;
1604 i = np->dqueueget;
1605
1606 /* MEMORY_READ_BARRIER(); */
1607 while (1) {
1608 dsa = scr_to_cpu(np->dqueue[i]);
1609 if (!dsa)
1610 break;
1611 np->dqueue[i] = 0;
1612 if ((i = i+2) >= MAX_QUEUE*2)
1613 i = 0;
1614
1615 cp = sym_ccb_from_dsa(np, dsa);
1616 if (cp) {
1617 MEMORY_READ_BARRIER();
1618 sym_complete_ok (np, cp);
1619 ++n;
1620 }
1621 else
1622 printf ("%s: bad DSA (%x) in done queue.\n",
1623 sym_name(np), (u_int) dsa);
1624 }
1625 np->dqueueget = i;
1626
1627 return n;
1628 }
1629
1630 /*
1631 * Complete all CCBs queued to the COMP queue.
1632 *
1633 * These CCBs are assumed:
1634 * - Not to be referenced either by devices or
1635 * SCRIPTS-related queues and datas.
1636 * - To have to be completed with an error condition
1637 * or requeued.
1638 *
1639 * The device queue freeze count is incremented
1640 * for each CCB that does not prevent this.
1641 * This function is called when all CCBs involved
1642 * in error handling/recovery have been reaped.
1643 */
1644 static void sym_flush_comp_queue(struct sym_hcb *np, int cam_status)
1645 {
1646 SYM_QUEHEAD *qp;
1647 struct sym_ccb *cp;
1648
1649 while ((qp = sym_remque_head(&np->comp_ccbq)) != NULL) {
1650 struct scsi_cmnd *cmd;
1651 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq);
1652 sym_insque_tail(&cp->link_ccbq, &np->busy_ccbq);
1653 /* Leave quiet CCBs waiting for resources */
1654 if (cp->host_status == HS_WAIT)
1655 continue;
1656 cmd = cp->cmd;
1657 if (cam_status)
1658 sym_set_cam_status(cmd, cam_status);
1659 #ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING
1660 if (sym_get_cam_status(cmd) == DID_SOFT_ERROR) {
1661 struct sym_tcb *tp = &np->target[cp->target];
1662 struct sym_lcb *lp = sym_lp(tp, cp->lun);
1663 if (lp) {
1664 sym_remque(&cp->link2_ccbq);
1665 sym_insque_tail(&cp->link2_ccbq,
1666 &lp->waiting_ccbq);
1667 if (cp->started) {
1668 if (cp->tag != NO_TAG)
1669 --lp->started_tags;
1670 else
1671 --lp->started_no_tag;
1672 }
1673 }
1674 cp->started = 0;
1675 continue;
1676 }
1677 #endif
1678 sym_free_ccb(np, cp);
1679 sym_xpt_done(np, cmd);
1680 }
1681 }
1682
1683 /*
1684 * Complete all active CCBs with error.
1685 * Used on CHIP/SCSI RESET.
1686 */
1687 static void sym_flush_busy_queue (struct sym_hcb *np, int cam_status)
1688 {
1689 /*
1690 * Move all active CCBs to the COMP queue
1691 * and flush this queue.
1692 */
1693 sym_que_splice(&np->busy_ccbq, &np->comp_ccbq);
1694 sym_que_init(&np->busy_ccbq);
1695 sym_flush_comp_queue(np, cam_status);
1696 }
1697
1698 /*
1699 * Start chip.
1700 *
1701 * 'reason' means:
1702 * 0: initialisation.
1703 * 1: SCSI BUS RESET delivered or received.
1704 * 2: SCSI BUS MODE changed.
1705 */
1706 void sym_start_up(struct Scsi_Host *shost, int reason)
1707 {
1708 struct sym_data *sym_data = shost_priv(shost);
1709 struct pci_dev *pdev = sym_data->pdev;
1710 struct sym_hcb *np = sym_data->ncb;
1711 int i;
1712 u32 phys;
1713
1714 /*
1715 * Reset chip if asked, otherwise just clear fifos.
1716 */
1717 if (reason == 1)
1718 sym_soft_reset(np);
1719 else {
1720 OUTB(np, nc_stest3, TE|CSF);
1721 OUTONB(np, nc_ctest3, CLF);
1722 }
1723
1724 /*
1725 * Clear Start Queue
1726 */
1727 phys = np->squeue_ba;
1728 for (i = 0; i < MAX_QUEUE*2; i += 2) {
1729 np->squeue[i] = cpu_to_scr(np->idletask_ba);
1730 np->squeue[i+1] = cpu_to_scr(phys + (i+2)*4);
1731 }
1732 np->squeue[MAX_QUEUE*2-1] = cpu_to_scr(phys);
1733
1734 /*
1735 * Start at first entry.
1736 */
1737 np->squeueput = 0;
1738
1739 /*
1740 * Clear Done Queue
1741 */
1742 phys = np->dqueue_ba;
1743 for (i = 0; i < MAX_QUEUE*2; i += 2) {
1744 np->dqueue[i] = 0;
1745 np->dqueue[i+1] = cpu_to_scr(phys + (i+2)*4);
1746 }
1747 np->dqueue[MAX_QUEUE*2-1] = cpu_to_scr(phys);
1748
1749 /*
1750 * Start at first entry.
1751 */
1752 np->dqueueget = 0;
1753
1754 /*
1755 * Install patches in scripts.
1756 * This also let point to first position the start
1757 * and done queue pointers used from SCRIPTS.
1758 */
1759 np->fw_patch(shost);
1760
1761 /*
1762 * Wakeup all pending jobs.
1763 */
1764 sym_flush_busy_queue(np, DID_RESET);
1765
1766 /*
1767 * Init chip.
1768 */
1769 OUTB(np, nc_istat, 0x00); /* Remove Reset, abort */
1770 INB(np, nc_mbox1);
1771 udelay(2000); /* The 895 needs time for the bus mode to settle */
1772
1773 OUTB(np, nc_scntl0, np->rv_scntl0 | 0xc0);
1774 /* full arb., ena parity, par->ATN */
1775 OUTB(np, nc_scntl1, 0x00); /* odd parity, and remove CRST!! */
1776
1777 sym_selectclock(np, np->rv_scntl3); /* Select SCSI clock */
1778
1779 OUTB(np, nc_scid , RRE|np->myaddr); /* Adapter SCSI address */
1780 OUTW(np, nc_respid, 1ul<<np->myaddr); /* Id to respond to */
1781 OUTB(np, nc_istat , SIGP ); /* Signal Process */
1782 OUTB(np, nc_dmode , np->rv_dmode); /* Burst length, dma mode */
1783 OUTB(np, nc_ctest5, np->rv_ctest5); /* Large fifo + large burst */
1784
1785 OUTB(np, nc_dcntl , NOCOM|np->rv_dcntl); /* Protect SFBR */
1786 OUTB(np, nc_ctest3, np->rv_ctest3); /* Write and invalidate */
1787 OUTB(np, nc_ctest4, np->rv_ctest4); /* Master parity checking */
1788
1789 /* Extended Sreq/Sack filtering not supported on the C10 */
1790 if (np->features & FE_C10)
1791 OUTB(np, nc_stest2, np->rv_stest2);
1792 else
1793 OUTB(np, nc_stest2, EXT|np->rv_stest2);
1794
1795 OUTB(np, nc_stest3, TE); /* TolerANT enable */
1796 OUTB(np, nc_stime0, 0x0c); /* HTH disabled STO 0.25 sec */
1797
1798 /*
1799 * For now, disable AIP generation on C1010-66.
1800 */
1801 if (pdev->device == PCI_DEVICE_ID_LSI_53C1010_66)
1802 OUTB(np, nc_aipcntl1, DISAIP);
1803
1804 /*
1805 * C10101 rev. 0 errata.
1806 * Errant SGE's when in narrow. Write bits 4 & 5 of
1807 * STEST1 register to disable SGE. We probably should do
1808 * that from SCRIPTS for each selection/reselection, but
1809 * I just don't want. :)
1810 */
1811 if (pdev->device == PCI_DEVICE_ID_LSI_53C1010_33 &&
1812 pdev->revision < 1)
1813 OUTB(np, nc_stest1, INB(np, nc_stest1) | 0x30);
1814
1815 /*
1816 * DEL 441 - 53C876 Rev 5 - Part Number 609-0392787/2788 - ITEM 2.
1817 * Disable overlapped arbitration for some dual function devices,
1818 * regardless revision id (kind of post-chip-design feature. ;-))
1819 */
1820 if (pdev->device == PCI_DEVICE_ID_NCR_53C875)
1821 OUTB(np, nc_ctest0, (1<<5));
1822 else if (pdev->device == PCI_DEVICE_ID_NCR_53C896)
1823 np->rv_ccntl0 |= DPR;
1824
1825 /*
1826 * Write CCNTL0/CCNTL1 for chips capable of 64 bit addressing
1827 * and/or hardware phase mismatch, since only such chips
1828 * seem to support those IO registers.
1829 */
1830 if (np->features & (FE_DAC|FE_NOPM)) {
1831 OUTB(np, nc_ccntl0, np->rv_ccntl0);
1832 OUTB(np, nc_ccntl1, np->rv_ccntl1);
1833 }
1834
1835 #if SYM_CONF_DMA_ADDRESSING_MODE == 2
1836 /*
1837 * Set up scratch C and DRS IO registers to map the 32 bit
1838 * DMA address range our data structures are located in.
1839 */
1840 if (use_dac(np)) {
1841 np->dmap_bah[0] = 0; /* ??? */
1842 OUTL(np, nc_scrx[0], np->dmap_bah[0]);
1843 OUTL(np, nc_drs, np->dmap_bah[0]);
1844 }
1845 #endif
1846
1847 /*
1848 * If phase mismatch handled by scripts (895A/896/1010),
1849 * set PM jump addresses.
1850 */
1851 if (np->features & FE_NOPM) {
1852 OUTL(np, nc_pmjad1, SCRIPTB_BA(np, pm_handle));
1853 OUTL(np, nc_pmjad2, SCRIPTB_BA(np, pm_handle));
1854 }
1855
1856 /*
1857 * Enable GPIO0 pin for writing if LED support from SCRIPTS.
1858 * Also set GPIO5 and clear GPIO6 if hardware LED control.
1859 */
1860 if (np->features & FE_LED0)
1861 OUTB(np, nc_gpcntl, INB(np, nc_gpcntl) & ~0x01);
1862 else if (np->features & FE_LEDC)
1863 OUTB(np, nc_gpcntl, (INB(np, nc_gpcntl) & ~0x41) | 0x20);
1864
1865 /*
1866 * enable ints
1867 */
1868 OUTW(np, nc_sien , STO|HTH|MA|SGE|UDC|RST|PAR);
1869 OUTB(np, nc_dien , MDPE|BF|SSI|SIR|IID);
1870
1871 /*
1872 * For 895/6 enable SBMC interrupt and save current SCSI bus mode.
1873 * Try to eat the spurious SBMC interrupt that may occur when
1874 * we reset the chip but not the SCSI BUS (at initialization).
1875 */
1876 if (np->features & (FE_ULTRA2|FE_ULTRA3)) {
1877 OUTONW(np, nc_sien, SBMC);
1878 if (reason == 0) {
1879 INB(np, nc_mbox1);
1880 mdelay(100);
1881 INW(np, nc_sist);
1882 }
1883 np->scsi_mode = INB(np, nc_stest4) & SMODE;
1884 }
1885
1886 /*
1887 * Fill in target structure.
1888 * Reinitialize usrsync.
1889 * Reinitialize usrwide.
1890 * Prepare sync negotiation according to actual SCSI bus mode.
1891 */
1892 for (i=0;i<SYM_CONF_MAX_TARGET;i++) {
1893 struct sym_tcb *tp = &np->target[i];
1894
1895 tp->to_reset = 0;
1896 tp->head.sval = 0;
1897 tp->head.wval = np->rv_scntl3;
1898 tp->head.uval = 0;
1899 if (tp->lun0p)
1900 tp->lun0p->to_clear = 0;
1901 if (tp->lunmp) {
1902 int ln;
1903
1904 for (ln = 1; ln < SYM_CONF_MAX_LUN; ln++)
1905 if (tp->lunmp[ln])
1906 tp->lunmp[ln]->to_clear = 0;
1907 }
1908 }
1909
1910 /*
1911 * Download SCSI SCRIPTS to on-chip RAM if present,
1912 * and start script processor.
1913 * We do the download preferently from the CPU.
1914 * For platforms that may not support PCI memory mapping,
1915 * we use simple SCRIPTS that performs MEMORY MOVEs.
1916 */
1917 phys = SCRIPTA_BA(np, init);
1918 if (np->ram_ba) {
1919 if (sym_verbose >= 2)
1920 printf("%s: Downloading SCSI SCRIPTS.\n", sym_name(np));
1921 memcpy_toio(np->s.ramaddr, np->scripta0, np->scripta_sz);
1922 if (np->features & FE_RAM8K) {
1923 memcpy_toio(np->s.ramaddr + 4096, np->scriptb0, np->scriptb_sz);
1924 phys = scr_to_cpu(np->scr_ram_seg);
1925 OUTL(np, nc_mmws, phys);
1926 OUTL(np, nc_mmrs, phys);
1927 OUTL(np, nc_sfs, phys);
1928 phys = SCRIPTB_BA(np, start64);
1929 }
1930 }
1931
1932 np->istat_sem = 0;
1933
1934 OUTL(np, nc_dsa, np->hcb_ba);
1935 OUTL_DSP(np, phys);
1936
1937 /*
1938 * Notify the XPT about the RESET condition.
1939 */
1940 if (reason != 0)
1941 sym_xpt_async_bus_reset(np);
1942 }
1943
1944 /*
1945 * Switch trans mode for current job and its target.
1946 */
1947 static void sym_settrans(struct sym_hcb *np, int target, u_char opts, u_char ofs,
1948 u_char per, u_char wide, u_char div, u_char fak)
1949 {
1950 SYM_QUEHEAD *qp;
1951 u_char sval, wval, uval;
1952 struct sym_tcb *tp = &np->target[target];
1953
1954 assert(target == (INB(np, nc_sdid) & 0x0f));
1955
1956 sval = tp->head.sval;
1957 wval = tp->head.wval;
1958 uval = tp->head.uval;
1959
1960 #if 0
1961 printf("XXXX sval=%x wval=%x uval=%x (%x)\n",
1962 sval, wval, uval, np->rv_scntl3);
1963 #endif
1964 /*
1965 * Set the offset.
1966 */
1967 if (!(np->features & FE_C10))
1968 sval = (sval & ~0x1f) | ofs;
1969 else
1970 sval = (sval & ~0x3f) | ofs;
1971
1972 /*
1973 * Set the sync divisor and extra clock factor.
1974 */
1975 if (ofs != 0) {
1976 wval = (wval & ~0x70) | ((div+1) << 4);
1977 if (!(np->features & FE_C10))
1978 sval = (sval & ~0xe0) | (fak << 5);
1979 else {
1980 uval = uval & ~(XCLKH_ST|XCLKH_DT|XCLKS_ST|XCLKS_DT);
1981 if (fak >= 1) uval |= (XCLKH_ST|XCLKH_DT);
1982 if (fak >= 2) uval |= (XCLKS_ST|XCLKS_DT);
1983 }
1984 }
1985
1986 /*
1987 * Set the bus width.
1988 */
1989 wval = wval & ~EWS;
1990 if (wide != 0)
1991 wval |= EWS;
1992
1993 /*
1994 * Set misc. ultra enable bits.
1995 */
1996 if (np->features & FE_C10) {
1997 uval = uval & ~(U3EN|AIPCKEN);
1998 if (opts) {
1999 assert(np->features & FE_U3EN);
2000 uval |= U3EN;
2001 }
2002 } else {
2003 wval = wval & ~ULTRA;
2004 if (per <= 12) wval |= ULTRA;
2005 }
2006
2007 /*
2008 * Stop there if sync parameters are unchanged.
2009 */
2010 if (tp->head.sval == sval &&
2011 tp->head.wval == wval &&
2012 tp->head.uval == uval)
2013 return;
2014 tp->head.sval = sval;
2015 tp->head.wval = wval;
2016 tp->head.uval = uval;
2017
2018 /*
2019 * Disable extended Sreq/Sack filtering if per < 50.
2020 * Not supported on the C1010.
2021 */
2022 if (per < 50 && !(np->features & FE_C10))
2023 OUTOFFB(np, nc_stest2, EXT);
2024
2025 /*
2026 * set actual value and sync_status
2027 */
2028 OUTB(np, nc_sxfer, tp->head.sval);
2029 OUTB(np, nc_scntl3, tp->head.wval);
2030
2031 if (np->features & FE_C10) {
2032 OUTB(np, nc_scntl4, tp->head.uval);
2033 }
2034
2035 /*
2036 * patch ALL busy ccbs of this target.
2037 */
2038 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) {
2039 struct sym_ccb *cp;
2040 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq);
2041 if (cp->target != target)
2042 continue;
2043 cp->phys.select.sel_scntl3 = tp->head.wval;
2044 cp->phys.select.sel_sxfer = tp->head.sval;
2045 if (np->features & FE_C10) {
2046 cp->phys.select.sel_scntl4 = tp->head.uval;
2047 }
2048 }
2049 }
2050
2051 static void sym_announce_transfer_rate(struct sym_tcb *tp)
2052 {
2053 struct scsi_target *starget = tp->starget;
2054
2055 if (tp->tprint.period != spi_period(starget) ||
2056 tp->tprint.offset != spi_offset(starget) ||
2057 tp->tprint.width != spi_width(starget) ||
2058 tp->tprint.iu != spi_iu(starget) ||
2059 tp->tprint.dt != spi_dt(starget) ||
2060 tp->tprint.qas != spi_qas(starget) ||
2061 !tp->tprint.check_nego) {
2062 tp->tprint.period = spi_period(starget);
2063 tp->tprint.offset = spi_offset(starget);
2064 tp->tprint.width = spi_width(starget);
2065 tp->tprint.iu = spi_iu(starget);
2066 tp->tprint.dt = spi_dt(starget);
2067 tp->tprint.qas = spi_qas(starget);
2068 tp->tprint.check_nego = 1;
2069
2070 spi_display_xfer_agreement(starget);
2071 }
2072 }
2073
2074 /*
2075 * We received a WDTR.
2076 * Let everything be aware of the changes.
2077 */
2078 static void sym_setwide(struct sym_hcb *np, int target, u_char wide)
2079 {
2080 struct sym_tcb *tp = &np->target[target];
2081 struct scsi_target *starget = tp->starget;
2082
2083 sym_settrans(np, target, 0, 0, 0, wide, 0, 0);
2084
2085 if (wide)
2086 tp->tgoal.renego = NS_WIDE;
2087 else
2088 tp->tgoal.renego = 0;
2089 tp->tgoal.check_nego = 0;
2090 tp->tgoal.width = wide;
2091 spi_offset(starget) = 0;
2092 spi_period(starget) = 0;
2093 spi_width(starget) = wide;
2094 spi_iu(starget) = 0;
2095 spi_dt(starget) = 0;
2096 spi_qas(starget) = 0;
2097
2098 if (sym_verbose >= 3)
2099 sym_announce_transfer_rate(tp);
2100 }
2101
2102 /*
2103 * We received a SDTR.
2104 * Let everything be aware of the changes.
2105 */
2106 static void
2107 sym_setsync(struct sym_hcb *np, int target,
2108 u_char ofs, u_char per, u_char div, u_char fak)
2109 {
2110 struct sym_tcb *tp = &np->target[target];
2111 struct scsi_target *starget = tp->starget;
2112 u_char wide = (tp->head.wval & EWS) ? BUS_16_BIT : BUS_8_BIT;
2113
2114 sym_settrans(np, target, 0, ofs, per, wide, div, fak);
2115
2116 if (wide)
2117 tp->tgoal.renego = NS_WIDE;
2118 else if (ofs)
2119 tp->tgoal.renego = NS_SYNC;
2120 else
2121 tp->tgoal.renego = 0;
2122 spi_period(starget) = per;
2123 spi_offset(starget) = ofs;
2124 spi_iu(starget) = spi_dt(starget) = spi_qas(starget) = 0;
2125
2126 if (!tp->tgoal.dt && !tp->tgoal.iu && !tp->tgoal.qas) {
2127 tp->tgoal.period = per;
2128 tp->tgoal.offset = ofs;
2129 tp->tgoal.check_nego = 0;
2130 }
2131
2132 sym_announce_transfer_rate(tp);
2133 }
2134
2135 /*
2136 * We received a PPR.
2137 * Let everything be aware of the changes.
2138 */
2139 static void
2140 sym_setpprot(struct sym_hcb *np, int target, u_char opts, u_char ofs,
2141 u_char per, u_char wide, u_char div, u_char fak)
2142 {
2143 struct sym_tcb *tp = &np->target[target];
2144 struct scsi_target *starget = tp->starget;
2145
2146 sym_settrans(np, target, opts, ofs, per, wide, div, fak);
2147
2148 if (wide || ofs)
2149 tp->tgoal.renego = NS_PPR;
2150 else
2151 tp->tgoal.renego = 0;
2152 spi_width(starget) = tp->tgoal.width = wide;
2153 spi_period(starget) = tp->tgoal.period = per;
2154 spi_offset(starget) = tp->tgoal.offset = ofs;
2155 spi_iu(starget) = tp->tgoal.iu = !!(opts & PPR_OPT_IU);
2156 spi_dt(starget) = tp->tgoal.dt = !!(opts & PPR_OPT_DT);
2157 spi_qas(starget) = tp->tgoal.qas = !!(opts & PPR_OPT_QAS);
2158 tp->tgoal.check_nego = 0;
2159
2160 sym_announce_transfer_rate(tp);
2161 }
2162
2163 /*
2164 * generic recovery from scsi interrupt
2165 *
2166 * The doc says that when the chip gets an SCSI interrupt,
2167 * it tries to stop in an orderly fashion, by completing
2168 * an instruction fetch that had started or by flushing
2169 * the DMA fifo for a write to memory that was executing.
2170 * Such a fashion is not enough to know if the instruction
2171 * that was just before the current DSP value has been
2172 * executed or not.
2173 *
2174 * There are some small SCRIPTS sections that deal with
2175 * the start queue and the done queue that may break any
2176 * assomption from the C code if we are interrupted
2177 * inside, so we reset if this happens. Btw, since these
2178 * SCRIPTS sections are executed while the SCRIPTS hasn't
2179 * started SCSI operations, it is very unlikely to happen.
2180 *
2181 * All the driver data structures are supposed to be
2182 * allocated from the same 4 GB memory window, so there
2183 * is a 1 to 1 relationship between DSA and driver data
2184 * structures. Since we are careful :) to invalidate the
2185 * DSA when we complete a command or when the SCRIPTS
2186 * pushes a DSA into a queue, we can trust it when it
2187 * points to a CCB.
2188 */
2189 static void sym_recover_scsi_int (struct sym_hcb *np, u_char hsts)
2190 {
2191 u32 dsp = INL(np, nc_dsp);
2192 u32 dsa = INL(np, nc_dsa);
2193 struct sym_ccb *cp = sym_ccb_from_dsa(np, dsa);
2194
2195 /*
2196 * If we haven't been interrupted inside the SCRIPTS
2197 * critical pathes, we can safely restart the SCRIPTS
2198 * and trust the DSA value if it matches a CCB.
2199 */
2200 if ((!(dsp > SCRIPTA_BA(np, getjob_begin) &&
2201 dsp < SCRIPTA_BA(np, getjob_end) + 1)) &&
2202 (!(dsp > SCRIPTA_BA(np, ungetjob) &&
2203 dsp < SCRIPTA_BA(np, reselect) + 1)) &&
2204 (!(dsp > SCRIPTB_BA(np, sel_for_abort) &&
2205 dsp < SCRIPTB_BA(np, sel_for_abort_1) + 1)) &&
2206 (!(dsp > SCRIPTA_BA(np, done) &&
2207 dsp < SCRIPTA_BA(np, done_end) + 1))) {
2208 OUTB(np, nc_ctest3, np->rv_ctest3 | CLF); /* clear dma fifo */
2209 OUTB(np, nc_stest3, TE|CSF); /* clear scsi fifo */
2210 /*
2211 * If we have a CCB, let the SCRIPTS call us back for
2212 * the handling of the error with SCRATCHA filled with
2213 * STARTPOS. This way, we will be able to freeze the
2214 * device queue and requeue awaiting IOs.
2215 */
2216 if (cp) {
2217 cp->host_status = hsts;
2218 OUTL_DSP(np, SCRIPTA_BA(np, complete_error));
2219 }
2220 /*
2221 * Otherwise just restart the SCRIPTS.
2222 */
2223 else {
2224 OUTL(np, nc_dsa, 0xffffff);
2225 OUTL_DSP(np, SCRIPTA_BA(np, start));
2226 }
2227 }
2228 else
2229 goto reset_all;
2230
2231 return;
2232
2233 reset_all:
2234 sym_start_reset(np);
2235 }
2236
2237 /*
2238 * chip exception handler for selection timeout
2239 */
2240 static void sym_int_sto (struct sym_hcb *np)
2241 {
2242 u32 dsp = INL(np, nc_dsp);
2243
2244 if (DEBUG_FLAGS & DEBUG_TINY) printf ("T");
2245
2246 if (dsp == SCRIPTA_BA(np, wf_sel_done) + 8)
2247 sym_recover_scsi_int(np, HS_SEL_TIMEOUT);
2248 else
2249 sym_start_reset(np);
2250 }
2251
2252 /*
2253 * chip exception handler for unexpected disconnect
2254 */
2255 static void sym_int_udc (struct sym_hcb *np)
2256 {
2257 printf ("%s: unexpected disconnect\n", sym_name(np));
2258 sym_recover_scsi_int(np, HS_UNEXPECTED);
2259 }
2260
2261 /*
2262 * chip exception handler for SCSI bus mode change
2263 *
2264 * spi2-r12 11.2.3 says a transceiver mode change must
2265 * generate a reset event and a device that detects a reset
2266 * event shall initiate a hard reset. It says also that a
2267 * device that detects a mode change shall set data transfer
2268 * mode to eight bit asynchronous, etc...
2269 * So, just reinitializing all except chip should be enough.
2270 */
2271 static void sym_int_sbmc(struct Scsi_Host *shost)
2272 {
2273 struct sym_hcb *np = sym_get_hcb(shost);
2274 u_char scsi_mode = INB(np, nc_stest4) & SMODE;
2275
2276 /*
2277 * Notify user.
2278 */
2279 printf("%s: SCSI BUS mode change from %s to %s.\n", sym_name(np),
2280 sym_scsi_bus_mode(np->scsi_mode), sym_scsi_bus_mode(scsi_mode));
2281
2282 /*
2283 * Should suspend command processing for a few seconds and
2284 * reinitialize all except the chip.
2285 */
2286 sym_start_up(shost, 2);
2287 }
2288
2289 /*
2290 * chip exception handler for SCSI parity error.
2291 *
2292 * When the chip detects a SCSI parity error and is
2293 * currently executing a (CH)MOV instruction, it does
2294 * not interrupt immediately, but tries to finish the
2295 * transfer of the current scatter entry before
2296 * interrupting. The following situations may occur:
2297 *
2298 * - The complete scatter entry has been transferred
2299 * without the device having changed phase.
2300 * The chip will then interrupt with the DSP pointing
2301 * to the instruction that follows the MOV.
2302 *
2303 * - A phase mismatch occurs before the MOV finished
2304 * and phase errors are to be handled by the C code.
2305 * The chip will then interrupt with both PAR and MA
2306 * conditions set.
2307 *
2308 * - A phase mismatch occurs before the MOV finished and
2309 * phase errors are to be handled by SCRIPTS.
2310 * The chip will load the DSP with the phase mismatch
2311 * JUMP address and interrupt the host processor.
2312 */
2313 static void sym_int_par (struct sym_hcb *np, u_short sist)
2314 {
2315 u_char hsts = INB(np, HS_PRT);
2316 u32 dsp = INL(np, nc_dsp);
2317 u32 dbc = INL(np, nc_dbc);
2318 u32 dsa = INL(np, nc_dsa);
2319 u_char sbcl = INB(np, nc_sbcl);
2320 u_char cmd = dbc >> 24;
2321 int phase = cmd & 7;
2322 struct sym_ccb *cp = sym_ccb_from_dsa(np, dsa);
2323
2324 if (printk_ratelimit())
2325 printf("%s: SCSI parity error detected: SCR1=%d DBC=%x SBCL=%x\n",
2326 sym_name(np), hsts, dbc, sbcl);
2327
2328 /*
2329 * Check that the chip is connected to the SCSI BUS.
2330 */
2331 if (!(INB(np, nc_scntl1) & ISCON)) {
2332 sym_recover_scsi_int(np, HS_UNEXPECTED);
2333 return;
2334 }
2335
2336 /*
2337 * If the nexus is not clearly identified, reset the bus.
2338 * We will try to do better later.
2339 */
2340 if (!cp)
2341 goto reset_all;
2342
2343 /*
2344 * Check instruction was a MOV, direction was INPUT and
2345 * ATN is asserted.
2346 */
2347 if ((cmd & 0xc0) || !(phase & 1) || !(sbcl & 0x8))
2348 goto reset_all;
2349
2350 /*
2351 * Keep track of the parity error.
2352 */
2353 OUTONB(np, HF_PRT, HF_EXT_ERR);
2354 cp->xerr_status |= XE_PARITY_ERR;
2355
2356 /*
2357 * Prepare the message to send to the device.
2358 */
2359 np->msgout[0] = (phase == 7) ? M_PARITY : M_ID_ERROR;
2360
2361 /*
2362 * If the old phase was DATA IN phase, we have to deal with
2363 * the 3 situations described above.
2364 * For other input phases (MSG IN and STATUS), the device
2365 * must resend the whole thing that failed parity checking
2366 * or signal error. So, jumping to dispatcher should be OK.
2367 */
2368 if (phase == 1 || phase == 5) {
2369 /* Phase mismatch handled by SCRIPTS */
2370 if (dsp == SCRIPTB_BA(np, pm_handle))
2371 OUTL_DSP(np, dsp);
2372 /* Phase mismatch handled by the C code */
2373 else if (sist & MA)
2374 sym_int_ma (np);
2375 /* No phase mismatch occurred */
2376 else {
2377 sym_set_script_dp (np, cp, dsp);
2378 OUTL_DSP(np, SCRIPTA_BA(np, dispatch));
2379 }
2380 }
2381 else if (phase == 7) /* We definitely cannot handle parity errors */
2382 #if 1 /* in message-in phase due to the relection */
2383 goto reset_all; /* path and various message anticipations. */
2384 #else
2385 OUTL_DSP(np, SCRIPTA_BA(np, clrack));
2386 #endif
2387 else
2388 OUTL_DSP(np, SCRIPTA_BA(np, dispatch));
2389 return;
2390
2391 reset_all:
2392 sym_start_reset(np);
2393 return;
2394 }
2395
2396 /*
2397 * chip exception handler for phase errors.
2398 *
2399 * We have to construct a new transfer descriptor,
2400 * to transfer the rest of the current block.
2401 */
2402 static void sym_int_ma (struct sym_hcb *np)
2403 {
2404 u32 dbc;
2405 u32 rest;
2406 u32 dsp;
2407 u32 dsa;
2408 u32 nxtdsp;
2409 u32 *vdsp;
2410 u32 oadr, olen;
2411 u32 *tblp;
2412 u32 newcmd;
2413 u_int delta;
2414 u_char cmd;
2415 u_char hflags, hflags0;
2416 struct sym_pmc *pm;
2417 struct sym_ccb *cp;
2418
2419 dsp = INL(np, nc_dsp);
2420 dbc = INL(np, nc_dbc);
2421 dsa = INL(np, nc_dsa);
2422
2423 cmd = dbc >> 24;
2424 rest = dbc & 0xffffff;
2425 delta = 0;
2426
2427 /*
2428 * locate matching cp if any.
2429 */
2430 cp = sym_ccb_from_dsa(np, dsa);
2431
2432 /*
2433 * Donnot take into account dma fifo and various buffers in
2434 * INPUT phase since the chip flushes everything before
2435 * raising the MA interrupt for interrupted INPUT phases.
2436 * For DATA IN phase, we will check for the SWIDE later.
2437 */
2438 if ((cmd & 7) != 1 && (cmd & 7) != 5) {
2439 u_char ss0, ss2;
2440
2441 if (np->features & FE_DFBC)
2442 delta = INW(np, nc_dfbc);
2443 else {
2444 u32 dfifo;
2445
2446 /*
2447 * Read DFIFO, CTEST[4-6] using 1 PCI bus ownership.
2448 */
2449 dfifo = INL(np, nc_dfifo);
2450
2451 /*
2452 * Calculate remaining bytes in DMA fifo.
2453 * (CTEST5 = dfifo >> 16)
2454 */
2455 if (dfifo & (DFS << 16))
2456 delta = ((((dfifo >> 8) & 0x300) |
2457 (dfifo & 0xff)) - rest) & 0x3ff;
2458 else
2459 delta = ((dfifo & 0xff) - rest) & 0x7f;
2460 }
2461
2462 /*
2463 * The data in the dma fifo has not been transfered to
2464 * the target -> add the amount to the rest
2465 * and clear the data.
2466 * Check the sstat2 register in case of wide transfer.
2467 */
2468 rest += delta;
2469 ss0 = INB(np, nc_sstat0);
2470 if (ss0 & OLF) rest++;
2471 if (!(np->features & FE_C10))
2472 if (ss0 & ORF) rest++;
2473 if (cp && (cp->phys.select.sel_scntl3 & EWS)) {
2474 ss2 = INB(np, nc_sstat2);
2475 if (ss2 & OLF1) rest++;
2476 if (!(np->features & FE_C10))
2477 if (ss2 & ORF1) rest++;
2478 }
2479
2480 /*
2481 * Clear fifos.
2482 */
2483 OUTB(np, nc_ctest3, np->rv_ctest3 | CLF); /* dma fifo */
2484 OUTB(np, nc_stest3, TE|CSF); /* scsi fifo */
2485 }
2486
2487 /*
2488 * log the information
2489 */
2490 if (DEBUG_FLAGS & (DEBUG_TINY|DEBUG_PHASE))
2491 printf ("P%x%x RL=%d D=%d ", cmd&7, INB(np, nc_sbcl)&7,
2492 (unsigned) rest, (unsigned) delta);
2493
2494 /*
2495 * try to find the interrupted script command,
2496 * and the address at which to continue.
2497 */
2498 vdsp = NULL;
2499 nxtdsp = 0;
2500 if (dsp > np->scripta_ba &&
2501 dsp <= np->scripta_ba + np->scripta_sz) {
2502 vdsp = (u32 *)((char*)np->scripta0 + (dsp-np->scripta_ba-8));
2503 nxtdsp = dsp;
2504 }
2505 else if (dsp > np->scriptb_ba &&
2506 dsp <= np->scriptb_ba + np->scriptb_sz) {
2507 vdsp = (u32 *)((char*)np->scriptb0 + (dsp-np->scriptb_ba-8));
2508 nxtdsp = dsp;
2509 }
2510
2511 /*
2512 * log the information
2513 */
2514 if (DEBUG_FLAGS & DEBUG_PHASE) {
2515 printf ("\nCP=%p DSP=%x NXT=%x VDSP=%p CMD=%x ",
2516 cp, (unsigned)dsp, (unsigned)nxtdsp, vdsp, cmd);
2517 }
2518
2519 if (!vdsp) {
2520 printf ("%s: interrupted SCRIPT address not found.\n",
2521 sym_name (np));
2522 goto reset_all;
2523 }
2524
2525 if (!cp) {
2526 printf ("%s: SCSI phase error fixup: CCB already dequeued.\n",
2527 sym_name (np));
2528 goto reset_all;
2529 }
2530
2531 /*
2532 * get old startaddress and old length.
2533 */
2534 oadr = scr_to_cpu(vdsp[1]);
2535
2536 if (cmd & 0x10) { /* Table indirect */
2537 tblp = (u32 *) ((char*) &cp->phys + oadr);
2538 olen = scr_to_cpu(tblp[0]);
2539 oadr = scr_to_cpu(tblp[1]);
2540 } else {
2541 tblp = (u32 *) 0;
2542 olen = scr_to_cpu(vdsp[0]) & 0xffffff;
2543 }
2544
2545 if (DEBUG_FLAGS & DEBUG_PHASE) {
2546 printf ("OCMD=%x\nTBLP=%p OLEN=%x OADR=%x\n",
2547 (unsigned) (scr_to_cpu(vdsp[0]) >> 24),
2548 tblp,
2549 (unsigned) olen,
2550 (unsigned) oadr);
2551 }
2552
2553 /*
2554 * check cmd against assumed interrupted script command.
2555 * If dt data phase, the MOVE instruction hasn't bit 4 of
2556 * the phase.
2557 */
2558 if (((cmd & 2) ? cmd : (cmd & ~4)) != (scr_to_cpu(vdsp[0]) >> 24)) {
2559 sym_print_addr(cp->cmd,
2560 "internal error: cmd=%02x != %02x=(vdsp[0] >> 24)\n",
2561 cmd, scr_to_cpu(vdsp[0]) >> 24);
2562
2563 goto reset_all;
2564 }
2565
2566 /*
2567 * if old phase not dataphase, leave here.
2568 */
2569 if (cmd & 2) {
2570 sym_print_addr(cp->cmd,
2571 "phase change %x-%x %d@%08x resid=%d.\n",
2572 cmd&7, INB(np, nc_sbcl)&7, (unsigned)olen,
2573 (unsigned)oadr, (unsigned)rest);
2574 goto unexpected_phase;
2575 }
2576
2577 /*
2578 * Choose the correct PM save area.
2579 *
2580 * Look at the PM_SAVE SCRIPT if you want to understand
2581 * this stuff. The equivalent code is implemented in
2582 * SCRIPTS for the 895A, 896 and 1010 that are able to
2583 * handle PM from the SCRIPTS processor.
2584 */
2585 hflags0 = INB(np, HF_PRT);
2586 hflags = hflags0;
2587
2588 if (hflags & (HF_IN_PM0 | HF_IN_PM1 | HF_DP_SAVED)) {
2589 if (hflags & HF_IN_PM0)
2590 nxtdsp = scr_to_cpu(cp->phys.pm0.ret);
2591 else if (hflags & HF_IN_PM1)
2592 nxtdsp = scr_to_cpu(cp->phys.pm1.ret);
2593
2594 if (hflags & HF_DP_SAVED)
2595 hflags ^= HF_ACT_PM;
2596 }
2597
2598 if (!(hflags & HF_ACT_PM)) {
2599 pm = &cp->phys.pm0;
2600 newcmd = SCRIPTA_BA(np, pm0_data);
2601 }
2602 else {
2603 pm = &cp->phys.pm1;
2604 newcmd = SCRIPTA_BA(np, pm1_data);
2605 }
2606
2607 hflags &= ~(HF_IN_PM0 | HF_IN_PM1 | HF_DP_SAVED);
2608 if (hflags != hflags0)
2609 OUTB(np, HF_PRT, hflags);
2610
2611 /*
2612 * fillin the phase mismatch context
2613 */
2614 pm->sg.addr = cpu_to_scr(oadr + olen - rest);
2615 pm->sg.size = cpu_to_scr(rest);
2616 pm->ret = cpu_to_scr(nxtdsp);
2617
2618 /*
2619 * If we have a SWIDE,
2620 * - prepare the address to write the SWIDE from SCRIPTS,
2621 * - compute the SCRIPTS address to restart from,
2622 * - move current data pointer context by one byte.
2623 */
2624 nxtdsp = SCRIPTA_BA(np, dispatch);
2625 if ((cmd & 7) == 1 && cp && (cp->phys.select.sel_scntl3 & EWS) &&
2626 (INB(np, nc_scntl2) & WSR)) {
2627 u32 tmp;
2628
2629 /*
2630 * Set up the table indirect for the MOVE
2631 * of the residual byte and adjust the data
2632 * pointer context.
2633 */
2634 tmp = scr_to_cpu(pm->sg.addr);
2635 cp->phys.wresid.addr = cpu_to_scr(tmp);
2636 pm->sg.addr = cpu_to_scr(tmp + 1);
2637 tmp = scr_to_cpu(pm->sg.size);
2638 cp->phys.wresid.size = cpu_to_scr((tmp&0xff000000) | 1);
2639 pm->sg.size = cpu_to_scr(tmp - 1);
2640
2641 /*
2642 * If only the residual byte is to be moved,
2643 * no PM context is needed.
2644 */
2645 if ((tmp&0xffffff) == 1)
2646 newcmd = pm->ret;
2647
2648 /*
2649 * Prepare the address of SCRIPTS that will
2650 * move the residual byte to memory.
2651 */
2652 nxtdsp = SCRIPTB_BA(np, wsr_ma_helper);
2653 }
2654
2655 if (DEBUG_FLAGS & DEBUG_PHASE) {
2656 sym_print_addr(cp->cmd, "PM %x %x %x / %x %x %x.\n",
2657 hflags0, hflags, newcmd,
2658 (unsigned)scr_to_cpu(pm->sg.addr),
2659 (unsigned)scr_to_cpu(pm->sg.size),
2660 (unsigned)scr_to_cpu(pm->ret));
2661 }
2662
2663 /*
2664 * Restart the SCRIPTS processor.
2665 */
2666 sym_set_script_dp (np, cp, newcmd);
2667 OUTL_DSP(np, nxtdsp);
2668 return;
2669
2670 /*
2671 * Unexpected phase changes that occurs when the current phase
2672 * is not a DATA IN or DATA OUT phase are due to error conditions.
2673 * Such event may only happen when the SCRIPTS is using a
2674 * multibyte SCSI MOVE.
2675 *
2676 * Phase change Some possible cause
2677 *
2678 * COMMAND --> MSG IN SCSI parity error detected by target.
2679 * COMMAND --> STATUS Bad command or refused by target.
2680 * MSG OUT --> MSG IN Message rejected by target.
2681 * MSG OUT --> COMMAND Bogus target that discards extended
2682 * negotiation messages.
2683 *
2684 * The code below does not care of the new phase and so
2685 * trusts the target. Why to annoy it ?
2686 * If the interrupted phase is COMMAND phase, we restart at
2687 * dispatcher.
2688 * If a target does not get all the messages after selection,
2689 * the code assumes blindly that the target discards extended
2690 * messages and clears the negotiation status.
2691 * If the target does not want all our response to negotiation,
2692 * we force a SIR_NEGO_PROTO interrupt (it is a hack that avoids
2693 * bloat for such a should_not_happen situation).
2694 * In all other situation, we reset the BUS.
2695 * Are these assumptions reasonnable ? (Wait and see ...)
2696 */
2697 unexpected_phase:
2698 dsp -= 8;
2699 nxtdsp = 0;
2700
2701 switch (cmd & 7) {
2702 case 2: /* COMMAND phase */
2703 nxtdsp = SCRIPTA_BA(np, dispatch);
2704 break;
2705 #if 0
2706 case 3: /* STATUS phase */
2707 nxtdsp = SCRIPTA_BA(np, dispatch);
2708 break;
2709 #endif
2710 case 6: /* MSG OUT phase */
2711 /*
2712 * If the device may want to use untagged when we want
2713 * tagged, we prepare an IDENTIFY without disc. granted,
2714 * since we will not be able to handle reselect.
2715 * Otherwise, we just don't care.
2716 */
2717 if (dsp == SCRIPTA_BA(np, send_ident)) {
2718 if (cp->tag != NO_TAG && olen - rest <= 3) {
2719 cp->host_status = HS_BUSY;
2720 np->msgout[0] = IDENTIFY(0, cp->lun);
2721 nxtdsp = SCRIPTB_BA(np, ident_break_atn);
2722 }
2723 else
2724 nxtdsp = SCRIPTB_BA(np, ident_break);
2725 }
2726 else if (dsp == SCRIPTB_BA(np, send_wdtr) ||
2727 dsp == SCRIPTB_BA(np, send_sdtr) ||
2728 dsp == SCRIPTB_BA(np, send_ppr)) {
2729 nxtdsp = SCRIPTB_BA(np, nego_bad_phase);
2730 if (dsp == SCRIPTB_BA(np, send_ppr)) {
2731 struct scsi_device *dev = cp->cmd->device;
2732 dev->ppr = 0;
2733 }
2734 }
2735 break;
2736 #if 0
2737 case 7: /* MSG IN phase */
2738 nxtdsp = SCRIPTA_BA(np, clrack);
2739 break;
2740 #endif
2741 }
2742
2743 if (nxtdsp) {
2744 OUTL_DSP(np, nxtdsp);
2745 return;
2746 }
2747
2748 reset_all:
2749 sym_start_reset(np);
2750 }
2751
2752 /*
2753 * chip interrupt handler
2754 *
2755 * In normal situations, interrupt conditions occur one at
2756 * a time. But when something bad happens on the SCSI BUS,
2757 * the chip may raise several interrupt flags before
2758 * stopping and interrupting the CPU. The additionnal
2759 * interrupt flags are stacked in some extra registers
2760 * after the SIP and/or DIP flag has been raised in the
2761 * ISTAT. After the CPU has read the interrupt condition
2762 * flag from SIST or DSTAT, the chip unstacks the other
2763 * interrupt flags and sets the corresponding bits in
2764 * SIST or DSTAT. Since the chip starts stacking once the
2765 * SIP or DIP flag is set, there is a small window of time
2766 * where the stacking does not occur.
2767 *
2768 * Typically, multiple interrupt conditions may happen in
2769 * the following situations:
2770 *
2771 * - SCSI parity error + Phase mismatch (PAR|MA)
2772 * When an parity error is detected in input phase
2773 * and the device switches to msg-in phase inside a
2774 * block MOV.
2775 * - SCSI parity error + Unexpected disconnect (PAR|UDC)
2776 * When a stupid device does not want to handle the
2777 * recovery of an SCSI parity error.
2778 * - Some combinations of STO, PAR, UDC, ...
2779 * When using non compliant SCSI stuff, when user is
2780 * doing non compliant hot tampering on the BUS, when
2781 * something really bad happens to a device, etc ...
2782 *
2783 * The heuristic suggested by SYMBIOS to handle
2784 * multiple interrupts is to try unstacking all
2785 * interrupts conditions and to handle them on some
2786 * priority based on error severity.
2787 * This will work when the unstacking has been
2788 * successful, but we cannot be 100 % sure of that,
2789 * since the CPU may have been faster to unstack than
2790 * the chip is able to stack. Hmmm ... But it seems that
2791 * such a situation is very unlikely to happen.
2792 *
2793 * If this happen, for example STO caught by the CPU
2794 * then UDC happenning before the CPU have restarted
2795 * the SCRIPTS, the driver may wrongly complete the
2796 * same command on UDC, since the SCRIPTS didn't restart
2797 * and the DSA still points to the same command.
2798 * We avoid this situation by setting the DSA to an
2799 * invalid value when the CCB is completed and before
2800 * restarting the SCRIPTS.
2801 *
2802 * Another issue is that we need some section of our
2803 * recovery procedures to be somehow uninterruptible but
2804 * the SCRIPTS processor does not provides such a
2805 * feature. For this reason, we handle recovery preferently
2806 * from the C code and check against some SCRIPTS critical
2807 * sections from the C code.
2808 *
2809 * Hopefully, the interrupt handling of the driver is now
2810 * able to resist to weird BUS error conditions, but donnot
2811 * ask me for any guarantee that it will never fail. :-)
2812 * Use at your own decision and risk.
2813 */
2814
2815 irqreturn_t sym_interrupt(struct Scsi_Host *shost)
2816 {
2817 struct sym_data *sym_data = shost_priv(shost);
2818 struct sym_hcb *np = sym_data->ncb;
2819 struct pci_dev *pdev = sym_data->pdev;
2820 u_char istat, istatc;
2821 u_char dstat;
2822 u_short sist;
2823
2824 /*
2825 * interrupt on the fly ?
2826 * (SCRIPTS may still be running)
2827 *
2828 * A `dummy read' is needed to ensure that the
2829 * clear of the INTF flag reaches the device
2830 * and that posted writes are flushed to memory
2831 * before the scanning of the DONE queue.
2832 * Note that SCRIPTS also (dummy) read to memory
2833 * prior to deliver the INTF interrupt condition.
2834 */
2835 istat = INB(np, nc_istat);
2836 if (istat & INTF) {
2837 OUTB(np, nc_istat, (istat & SIGP) | INTF | np->istat_sem);
2838 istat |= INB(np, nc_istat); /* DUMMY READ */
2839 if (DEBUG_FLAGS & DEBUG_TINY) printf ("F ");
2840 sym_wakeup_done(np);
2841 }
2842
2843 if (!(istat & (SIP|DIP)))
2844 return (istat & INTF) ? IRQ_HANDLED : IRQ_NONE;
2845
2846 #if 0 /* We should never get this one */
2847 if (istat & CABRT)
2848 OUTB(np, nc_istat, CABRT);
2849 #endif
2850
2851 /*
2852 * PAR and MA interrupts may occur at the same time,
2853 * and we need to know of both in order to handle
2854 * this situation properly. We try to unstack SCSI
2855 * interrupts for that reason. BTW, I dislike a LOT
2856 * such a loop inside the interrupt routine.
2857 * Even if DMA interrupt stacking is very unlikely to
2858 * happen, we also try unstacking these ones, since
2859 * this has no performance impact.
2860 */
2861 sist = 0;
2862 dstat = 0;
2863 istatc = istat;
2864 do {
2865 if (istatc & SIP)
2866 sist |= INW(np, nc_sist);
2867 if (istatc & DIP)
2868 dstat |= INB(np, nc_dstat);
2869 istatc = INB(np, nc_istat);
2870 istat |= istatc;
2871
2872 /* Prevent deadlock waiting on a condition that may
2873 * never clear. */
2874 if (unlikely(sist == 0xffff && dstat == 0xff)) {
2875 if (pci_channel_offline(pdev))
2876 return IRQ_NONE;
2877 }
2878 } while (istatc & (SIP|DIP));
2879
2880 if (DEBUG_FLAGS & DEBUG_TINY)
2881 printf ("<%d|%x:%x|%x:%x>",
2882 (int)INB(np, nc_scr0),
2883 dstat,sist,
2884 (unsigned)INL(np, nc_dsp),
2885 (unsigned)INL(np, nc_dbc));
2886 /*
2887 * On paper, a memory read barrier may be needed here to
2888 * prevent out of order LOADs by the CPU from having
2889 * prefetched stale data prior to DMA having occurred.
2890 * And since we are paranoid ... :)
2891 */
2892 MEMORY_READ_BARRIER();
2893
2894 /*
2895 * First, interrupts we want to service cleanly.
2896 *
2897 * Phase mismatch (MA) is the most frequent interrupt
2898 * for chip earlier than the 896 and so we have to service
2899 * it as quickly as possible.
2900 * A SCSI parity error (PAR) may be combined with a phase
2901 * mismatch condition (MA).
2902 * Programmed interrupts (SIR) are used to call the C code
2903 * from SCRIPTS.
2904 * The single step interrupt (SSI) is not used in this
2905 * driver.
2906 */
2907 if (!(sist & (STO|GEN|HTH|SGE|UDC|SBMC|RST)) &&
2908 !(dstat & (MDPE|BF|ABRT|IID))) {
2909 if (sist & PAR) sym_int_par (np, sist);
2910 else if (sist & MA) sym_int_ma (np);
2911 else if (dstat & SIR) sym_int_sir(np);
2912 else if (dstat & SSI) OUTONB_STD();
2913 else goto unknown_int;
2914 return IRQ_HANDLED;
2915 }
2916
2917 /*
2918 * Now, interrupts that donnot happen in normal
2919 * situations and that we may need to recover from.
2920 *
2921 * On SCSI RESET (RST), we reset everything.
2922 * On SCSI BUS MODE CHANGE (SBMC), we complete all
2923 * active CCBs with RESET status, prepare all devices
2924 * for negotiating again and restart the SCRIPTS.
2925 * On STO and UDC, we complete the CCB with the corres-
2926 * ponding status and restart the SCRIPTS.
2927 */
2928 if (sist & RST) {
2929 printf("%s: SCSI BUS reset detected.\n", sym_name(np));
2930 sym_start_up(shost, 1);
2931 return IRQ_HANDLED;
2932 }
2933
2934 OUTB(np, nc_ctest3, np->rv_ctest3 | CLF); /* clear dma fifo */
2935 OUTB(np, nc_stest3, TE|CSF); /* clear scsi fifo */
2936
2937 if (!(sist & (GEN|HTH|SGE)) &&
2938 !(dstat & (MDPE|BF|ABRT|IID))) {
2939 if (sist & SBMC) sym_int_sbmc(shost);
2940 else if (sist & STO) sym_int_sto (np);
2941 else if (sist & UDC) sym_int_udc (np);
2942 else goto unknown_int;
2943 return IRQ_HANDLED;
2944 }
2945
2946 /*
2947 * Now, interrupts we are not able to recover cleanly.
2948 *
2949 * Log message for hard errors.
2950 * Reset everything.
2951 */
2952
2953 sym_log_hard_error(shost, sist, dstat);
2954
2955 if ((sist & (GEN|HTH|SGE)) ||
2956 (dstat & (MDPE|BF|ABRT|IID))) {
2957 sym_start_reset(np);
2958 return IRQ_HANDLED;
2959 }
2960
2961 unknown_int:
2962 /*
2963 * We just miss the cause of the interrupt. :(
2964 * Print a message. The timeout will do the real work.
2965 */
2966 printf( "%s: unknown interrupt(s) ignored, "
2967 "ISTAT=0x%x DSTAT=0x%x SIST=0x%x\n",
2968 sym_name(np), istat, dstat, sist);
2969 return IRQ_NONE;
2970 }
2971
2972 /*
2973 * Dequeue from the START queue all CCBs that match
2974 * a given target/lun/task condition (-1 means all),
2975 * and move them from the BUSY queue to the COMP queue
2976 * with DID_SOFT_ERROR status condition.
2977 * This function is used during error handling/recovery.
2978 * It is called with SCRIPTS not running.
2979 */
2980 static int
2981 sym_dequeue_from_squeue(struct sym_hcb *np, int i, int target, int lun, int task)
2982 {
2983 int j;
2984 struct sym_ccb *cp;
2985
2986 /*
2987 * Make sure the starting index is within range.
2988 */
2989 assert((i >= 0) && (i < 2*MAX_QUEUE));
2990
2991 /*
2992 * Walk until end of START queue and dequeue every job
2993 * that matches the target/lun/task condition.
2994 */
2995 j = i;
2996 while (i != np->squeueput) {
2997 cp = sym_ccb_from_dsa(np, scr_to_cpu(np->squeue[i]));
2998 assert(cp);
2999 #ifdef SYM_CONF_IARB_SUPPORT
3000 /* Forget hints for IARB, they may be no longer relevant */
3001 cp->host_flags &= ~HF_HINT_IARB;
3002 #endif
3003 if ((target == -1 || cp->target == target) &&
3004 (lun == -1 || cp->lun == lun) &&
3005 (task == -1 || cp->tag == task)) {
3006 sym_set_cam_status(cp->cmd, DID_SOFT_ERROR);
3007 sym_remque(&cp->link_ccbq);
3008 sym_insque_tail(&cp->link_ccbq, &np->comp_ccbq);
3009 }
3010 else {
3011 if (i != j)
3012 np->squeue[j] = np->squeue[i];
3013 if ((j += 2) >= MAX_QUEUE*2) j = 0;
3014 }
3015 if ((i += 2) >= MAX_QUEUE*2) i = 0;
3016 }
3017 if (i != j) /* Copy back the idle task if needed */
3018 np->squeue[j] = np->squeue[i];
3019 np->squeueput = j; /* Update our current start queue pointer */
3020
3021 return (i - j) / 2;
3022 }
3023
3024 /*
3025 * chip handler for bad SCSI status condition
3026 *
3027 * In case of bad SCSI status, we unqueue all the tasks
3028 * currently queued to the controller but not yet started
3029 * and then restart the SCRIPTS processor immediately.
3030 *
3031 * QUEUE FULL and BUSY conditions are handled the same way.
3032 * Basically all the not yet started tasks are requeued in
3033 * device queue and the queue is frozen until a completion.
3034 *
3035 * For CHECK CONDITION and COMMAND TERMINATED status, we use
3036 * the CCB of the failed command to prepare a REQUEST SENSE
3037 * SCSI command and queue it to the controller queue.
3038 *
3039 * SCRATCHA is assumed to have been loaded with STARTPOS
3040 * before the SCRIPTS called the C code.
3041 */
3042 static void sym_sir_bad_scsi_status(struct sym_hcb *np, int num, struct sym_ccb *cp)
3043 {
3044 u32 startp;
3045 u_char s_status = cp->ssss_status;
3046 u_char h_flags = cp->host_flags;
3047 int msglen;
3048 int i;
3049
3050 /*
3051 * Compute the index of the next job to start from SCRIPTS.
3052 */
3053 i = (INL(np, nc_scratcha) - np->squeue_ba) / 4;
3054
3055 /*
3056 * The last CCB queued used for IARB hint may be
3057 * no longer relevant. Forget it.
3058 */
3059 #ifdef SYM_CONF_IARB_SUPPORT
3060 if (np->last_cp)
3061 np->last_cp = 0;
3062 #endif
3063
3064 /*
3065 * Now deal with the SCSI status.
3066 */
3067 switch(s_status) {
3068 case S_BUSY:
3069 case S_QUEUE_FULL:
3070 if (sym_verbose >= 2) {
3071 sym_print_addr(cp->cmd, "%s\n",
3072 s_status == S_BUSY ? "BUSY" : "QUEUE FULL\n");
3073 }
3074 default: /* S_INT, S_INT_COND_MET, S_CONFLICT */
3075 sym_complete_error (np, cp);
3076 break;
3077 case S_TERMINATED:
3078 case S_CHECK_COND:
3079 /*
3080 * If we get an SCSI error when requesting sense, give up.
3081 */
3082 if (h_flags & HF_SENSE) {
3083 sym_complete_error (np, cp);
3084 break;
3085 }
3086
3087 /*
3088 * Dequeue all queued CCBs for that device not yet started,
3089 * and restart the SCRIPTS processor immediately.
3090 */
3091 sym_dequeue_from_squeue(np, i, cp->target, cp->lun, -1);
3092 OUTL_DSP(np, SCRIPTA_BA(np, start));
3093
3094 /*
3095 * Save some info of the actual IO.
3096 * Compute the data residual.
3097 */
3098 cp->sv_scsi_status = cp->ssss_status;
3099 cp->sv_xerr_status = cp->xerr_status;
3100 cp->sv_resid = sym_compute_residual(np, cp);
3101
3102 /*
3103 * Prepare all needed data structures for
3104 * requesting sense data.
3105 */
3106
3107 cp->scsi_smsg2[0] = IDENTIFY(0, cp->lun);
3108 msglen = 1;
3109
3110 /*
3111 * If we are currently using anything different from
3112 * async. 8 bit data transfers with that target,
3113 * start a negotiation, since the device may want
3114 * to report us a UNIT ATTENTION condition due to
3115 * a cause we currently ignore, and we donnot want
3116 * to be stuck with WIDE and/or SYNC data transfer.
3117 *
3118 * cp->nego_status is filled by sym_prepare_nego().
3119 */
3120 cp->nego_status = 0;
3121 msglen += sym_prepare_nego(np, cp, &cp->scsi_smsg2[msglen]);
3122 /*
3123 * Message table indirect structure.
3124 */
3125 cp->phys.smsg.addr = CCB_BA(cp, scsi_smsg2);
3126 cp->phys.smsg.size = cpu_to_scr(msglen);
3127
3128 /*
3129 * sense command
3130 */
3131 cp->phys.cmd.addr = CCB_BA(cp, sensecmd);
3132 cp->phys.cmd.size = cpu_to_scr(6);
3133
3134 /*
3135 * patch requested size into sense command
3136 */
3137 cp->sensecmd[0] = REQUEST_SENSE;
3138 cp->sensecmd[1] = 0;
3139 if (cp->cmd->device->scsi_level <= SCSI_2 && cp->lun <= 7)
3140 cp->sensecmd[1] = cp->lun << 5;
3141 cp->sensecmd[4] = SYM_SNS_BBUF_LEN;
3142 cp->data_len = SYM_SNS_BBUF_LEN;
3143
3144 /*
3145 * sense data
3146 */
3147 memset(cp->sns_bbuf, 0, SYM_SNS_BBUF_LEN);
3148 cp->phys.sense.addr = CCB_BA(cp, sns_bbuf);
3149 cp->phys.sense.size = cpu_to_scr(SYM_SNS_BBUF_LEN);
3150
3151 /*
3152 * requeue the command.
3153 */
3154 startp = SCRIPTB_BA(np, sdata_in);
3155
3156 cp->phys.head.savep = cpu_to_scr(startp);
3157 cp->phys.head.lastp = cpu_to_scr(startp);
3158 cp->startp = cpu_to_scr(startp);
3159 cp->goalp = cpu_to_scr(startp + 16);
3160
3161 cp->host_xflags = 0;
3162 cp->host_status = cp->nego_status ? HS_NEGOTIATE : HS_BUSY;
3163 cp->ssss_status = S_ILLEGAL;
3164 cp->host_flags = (HF_SENSE|HF_DATA_IN);
3165 cp->xerr_status = 0;
3166 cp->extra_bytes = 0;
3167
3168 cp->phys.head.go.start = cpu_to_scr(SCRIPTA_BA(np, select));
3169
3170 /*
3171 * Requeue the command.
3172 */
3173 sym_put_start_queue(np, cp);
3174
3175 /*
3176 * Give back to upper layer everything we have dequeued.
3177 */
3178 sym_flush_comp_queue(np, 0);
3179 break;
3180 }
3181 }
3182
3183 /*
3184 * After a device has accepted some management message
3185 * as BUS DEVICE RESET, ABORT TASK, etc ..., or when
3186 * a device signals a UNIT ATTENTION condition, some
3187 * tasks are thrown away by the device. We are required
3188 * to reflect that on our tasks list since the device
3189 * will never complete these tasks.
3190 *
3191 * This function move from the BUSY queue to the COMP
3192 * queue all disconnected CCBs for a given target that
3193 * match the following criteria:
3194 * - lun=-1 means any logical UNIT otherwise a given one.
3195 * - task=-1 means any task, otherwise a given one.
3196 */
3197 int sym_clear_tasks(struct sym_hcb *np, int cam_status, int target, int lun, int task)
3198 {
3199 SYM_QUEHEAD qtmp, *qp;
3200 int i = 0;
3201 struct sym_ccb *cp;
3202
3203 /*
3204 * Move the entire BUSY queue to our temporary queue.
3205 */
3206 sym_que_init(&qtmp);
3207 sym_que_splice(&np->busy_ccbq, &qtmp);
3208 sym_que_init(&np->busy_ccbq);
3209
3210 /*
3211 * Put all CCBs that matches our criteria into
3212 * the COMP queue and put back other ones into
3213 * the BUSY queue.
3214 */
3215 while ((qp = sym_remque_head(&qtmp)) != NULL) {
3216 struct scsi_cmnd *cmd;
3217 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq);
3218 cmd = cp->cmd;
3219 if (cp->host_status != HS_DISCONNECT ||
3220 cp->target != target ||
3221 (lun != -1 && cp->lun != lun) ||
3222 (task != -1 &&
3223 (cp->tag != NO_TAG && cp->scsi_smsg[2] != task))) {
3224 sym_insque_tail(&cp->link_ccbq, &np->busy_ccbq);
3225 continue;
3226 }
3227 sym_insque_tail(&cp->link_ccbq, &np->comp_ccbq);
3228
3229 /* Preserve the software timeout condition */
3230 if (sym_get_cam_status(cmd) != DID_TIME_OUT)
3231 sym_set_cam_status(cmd, cam_status);
3232 ++i;
3233 #if 0
3234 printf("XXXX TASK @%p CLEARED\n", cp);
3235 #endif
3236 }
3237 return i;
3238 }
3239
3240 /*
3241 * chip handler for TASKS recovery
3242 *
3243 * We cannot safely abort a command, while the SCRIPTS
3244 * processor is running, since we just would be in race
3245 * with it.
3246 *
3247 * As long as we have tasks to abort, we keep the SEM
3248 * bit set in the ISTAT. When this bit is set, the
3249 * SCRIPTS processor interrupts (SIR_SCRIPT_STOPPED)
3250 * each time it enters the scheduler.
3251 *
3252 * If we have to reset a target, clear tasks of a unit,
3253 * or to perform the abort of a disconnected job, we
3254 * restart the SCRIPTS for selecting the target. Once
3255 * selected, the SCRIPTS interrupts (SIR_TARGET_SELECTED).
3256 * If it loses arbitration, the SCRIPTS will interrupt again
3257 * the next time it will enter its scheduler, and so on ...
3258 *
3259 * On SIR_TARGET_SELECTED, we scan for the more
3260 * appropriate thing to do:
3261 *
3262 * - If nothing, we just sent a M_ABORT message to the
3263 * target to get rid of the useless SCSI bus ownership.
3264 * According to the specs, no tasks shall be affected.
3265 * - If the target is to be reset, we send it a M_RESET
3266 * message.
3267 * - If a logical UNIT is to be cleared , we send the
3268 * IDENTIFY(lun) + M_ABORT.
3269 * - If an untagged task is to be aborted, we send the
3270 * IDENTIFY(lun) + M_ABORT.
3271 * - If a tagged task is to be aborted, we send the
3272 * IDENTIFY(lun) + task attributes + M_ABORT_TAG.
3273 *
3274 * Once our 'kiss of death' :) message has been accepted
3275 * by the target, the SCRIPTS interrupts again
3276 * (SIR_ABORT_SENT). On this interrupt, we complete
3277 * all the CCBs that should have been aborted by the
3278 * target according to our message.
3279 */
3280 static void sym_sir_task_recovery(struct sym_hcb *np, int num)
3281 {
3282 SYM_QUEHEAD *qp;
3283 struct sym_ccb *cp;
3284 struct sym_tcb *tp = NULL; /* gcc isn't quite smart enough yet */
3285 struct scsi_target *starget;
3286 int target=-1, lun=-1, task;
3287 int i, k;
3288
3289 switch(num) {
3290 /*
3291 * The SCRIPTS processor stopped before starting
3292 * the next command in order to allow us to perform
3293 * some task recovery.
3294 */
3295 case SIR_SCRIPT_STOPPED:
3296 /*
3297 * Do we have any target to reset or unit to clear ?
3298 */
3299 for (i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) {
3300 tp = &np->target[i];
3301 if (tp->to_reset ||
3302 (tp->lun0p && tp->lun0p->to_clear)) {
3303 target = i;
3304 break;
3305 }
3306 if (!tp->lunmp)
3307 continue;
3308 for (k = 1 ; k < SYM_CONF_MAX_LUN ; k++) {
3309 if (tp->lunmp[k] && tp->lunmp[k]->to_clear) {
3310 target = i;
3311 break;
3312 }
3313 }
3314 if (target != -1)
3315 break;
3316 }
3317
3318 /*
3319 * If not, walk the busy queue for any
3320 * disconnected CCB to be aborted.
3321 */
3322 if (target == -1) {
3323 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) {
3324 cp = sym_que_entry(qp,struct sym_ccb,link_ccbq);
3325 if (cp->host_status != HS_DISCONNECT)
3326 continue;
3327 if (cp->to_abort) {
3328 target = cp->target;
3329 break;
3330 }
3331 }
3332 }
3333
3334 /*
3335 * If some target is to be selected,
3336 * prepare and start the selection.
3337 */
3338 if (target != -1) {
3339 tp = &np->target[target];
3340 np->abrt_sel.sel_id = target;
3341 np->abrt_sel.sel_scntl3 = tp->head.wval;
3342 np->abrt_sel.sel_sxfer = tp->head.sval;
3343 OUTL(np, nc_dsa, np->hcb_ba);
3344 OUTL_DSP(np, SCRIPTB_BA(np, sel_for_abort));
3345 return;
3346 }
3347
3348 /*
3349 * Now look for a CCB to abort that haven't started yet.
3350 * Btw, the SCRIPTS processor is still stopped, so
3351 * we are not in race.
3352 */
3353 i = 0;
3354 cp = NULL;
3355 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) {
3356 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq);
3357 if (cp->host_status != HS_BUSY &&
3358 cp->host_status != HS_NEGOTIATE)
3359 continue;
3360 if (!cp->to_abort)
3361 continue;
3362 #ifdef SYM_CONF_IARB_SUPPORT
3363 /*
3364 * If we are using IMMEDIATE ARBITRATION, we donnot
3365 * want to cancel the last queued CCB, since the
3366 * SCRIPTS may have anticipated the selection.
3367 */
3368 if (cp == np->last_cp) {
3369 cp->to_abort = 0;
3370 continue;
3371 }
3372 #endif
3373 i = 1; /* Means we have found some */
3374 break;
3375 }
3376 if (!i) {
3377 /*
3378 * We are done, so we donnot need
3379 * to synchronize with the SCRIPTS anylonger.
3380 * Remove the SEM flag from the ISTAT.
3381 */
3382 np->istat_sem = 0;
3383 OUTB(np, nc_istat, SIGP);
3384 break;
3385 }
3386 /*
3387 * Compute index of next position in the start
3388 * queue the SCRIPTS intends to start and dequeue
3389 * all CCBs for that device that haven't been started.
3390 */
3391 i = (INL(np, nc_scratcha) - np->squeue_ba) / 4;
3392 i = sym_dequeue_from_squeue(np, i, cp->target, cp->lun, -1);
3393
3394 /*
3395 * Make sure at least our IO to abort has been dequeued.
3396 */
3397 #ifndef SYM_OPT_HANDLE_DEVICE_QUEUEING
3398 assert(i && sym_get_cam_status(cp->cmd) == DID_SOFT_ERROR);
3399 #else
3400 sym_remque(&cp->link_ccbq);
3401 sym_insque_tail(&cp->link_ccbq, &np->comp_ccbq);
3402 #endif
3403 /*
3404 * Keep track in cam status of the reason of the abort.
3405 */
3406 if (cp->to_abort == 2)
3407 sym_set_cam_status(cp->cmd, DID_TIME_OUT);
3408 else
3409 sym_set_cam_status(cp->cmd, DID_ABORT);
3410
3411 /*
3412 * Complete with error everything that we have dequeued.
3413 */
3414 sym_flush_comp_queue(np, 0);
3415 break;
3416 /*
3417 * The SCRIPTS processor has selected a target
3418 * we may have some manual recovery to perform for.
3419 */
3420 case SIR_TARGET_SELECTED:
3421 target = INB(np, nc_sdid) & 0xf;
3422 tp = &np->target[target];
3423
3424 np->abrt_tbl.addr = cpu_to_scr(vtobus(np->abrt_msg));
3425
3426 /*
3427 * If the target is to be reset, prepare a
3428 * M_RESET message and clear the to_reset flag
3429 * since we donnot expect this operation to fail.
3430 */
3431 if (tp->to_reset) {
3432 np->abrt_msg[0] = M_RESET;
3433 np->abrt_tbl.size = 1;
3434 tp->to_reset = 0;
3435 break;
3436 }
3437
3438 /*
3439 * Otherwise, look for some logical unit to be cleared.
3440 */
3441 if (tp->lun0p && tp->lun0p->to_clear)
3442 lun = 0;
3443 else if (tp->lunmp) {
3444 for (k = 1 ; k < SYM_CONF_MAX_LUN ; k++) {
3445 if (tp->lunmp[k] && tp->lunmp[k]->to_clear) {
3446 lun = k;
3447 break;
3448 }
3449 }
3450 }
3451
3452 /*
3453 * If a logical unit is to be cleared, prepare
3454 * an IDENTIFY(lun) + ABORT MESSAGE.
3455 */
3456 if (lun != -1) {
3457 struct sym_lcb *lp = sym_lp(tp, lun);
3458 lp->to_clear = 0; /* We don't expect to fail here */
3459 np->abrt_msg[0] = IDENTIFY(0, lun);
3460 np->abrt_msg[1] = M_ABORT;
3461 np->abrt_tbl.size = 2;
3462 break;
3463 }
3464
3465 /*
3466 * Otherwise, look for some disconnected job to
3467 * abort for this target.
3468 */
3469 i = 0;
3470 cp = NULL;
3471 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) {
3472 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq);
3473 if (cp->host_status != HS_DISCONNECT)
3474 continue;
3475 if (cp->target != target)
3476 continue;
3477 if (!cp->to_abort)
3478 continue;
3479 i = 1; /* Means we have some */
3480 break;
3481 }
3482
3483 /*
3484 * If we have none, probably since the device has
3485 * completed the command before we won abitration,
3486 * send a M_ABORT message without IDENTIFY.
3487 * According to the specs, the device must just
3488 * disconnect the BUS and not abort any task.
3489 */
3490 if (!i) {
3491 np->abrt_msg[0] = M_ABORT;
3492 np->abrt_tbl.size = 1;
3493 break;
3494 }
3495
3496 /*
3497 * We have some task to abort.
3498 * Set the IDENTIFY(lun)
3499 */
3500 np->abrt_msg[0] = IDENTIFY(0, cp->lun);
3501
3502 /*
3503 * If we want to abort an untagged command, we
3504 * will send a IDENTIFY + M_ABORT.
3505 * Otherwise (tagged command), we will send
3506 * a IDENTITFY + task attributes + ABORT TAG.
3507 */
3508 if (cp->tag == NO_TAG) {
3509 np->abrt_msg[1] = M_ABORT;
3510 np->abrt_tbl.size = 2;
3511 } else {
3512 np->abrt_msg[1] = cp->scsi_smsg[1];
3513 np->abrt_msg[2] = cp->scsi_smsg[2];
3514 np->abrt_msg[3] = M_ABORT_TAG;
3515 np->abrt_tbl.size = 4;
3516 }
3517 /*
3518 * Keep track of software timeout condition, since the
3519 * peripheral driver may not count retries on abort
3520 * conditions not due to timeout.
3521 */
3522 if (cp->to_abort == 2)
3523 sym_set_cam_status(cp->cmd, DID_TIME_OUT);
3524 cp->to_abort = 0; /* We donnot expect to fail here */
3525 break;
3526
3527 /*
3528 * The target has accepted our message and switched
3529 * to BUS FREE phase as we expected.
3530 */
3531 case SIR_ABORT_SENT:
3532 target = INB(np, nc_sdid) & 0xf;
3533 tp = &np->target[target];
3534 starget = tp->starget;
3535
3536 /*
3537 ** If we didn't abort anything, leave here.
3538 */
3539 if (np->abrt_msg[0] == M_ABORT)
3540 break;
3541
3542 /*
3543 * If we sent a M_RESET, then a hardware reset has
3544 * been performed by the target.
3545 * - Reset everything to async 8 bit