1 /*
2 * QLogic iSCSI HBA Driver
3 * Copyright (c) 2003-2006 QLogic Corporation
4 *
5 * See LICENSE.qla4xxx for copyright and licensing details.
6 */
7
8 #ifndef _QLA4X_FW_H
9 #define _QLA4X_FW_H
10
11
12 #define MAX_PRST_DEV_DB_ENTRIES 64
13 #define MIN_DISC_DEV_DB_ENTRY MAX_PRST_DEV_DB_ENTRIES
14 #define MAX_DEV_DB_ENTRIES 512
15
16 /*************************************************************************
17 *
18 * ISP 4010 I/O Register Set Structure and Definitions
19 *
20 *************************************************************************/
21
22 struct port_ctrl_stat_regs {
23 __le32 ext_hw_conf; /* 0x50 R/W */
24 __le32 rsrvd0; /* 0x54 */
25 __le32 port_ctrl; /* 0x58 */
26 __le32 port_status; /* 0x5c */
27 __le32 rsrvd1[32]; /* 0x60-0xdf */
28 __le32 gp_out; /* 0xe0 */
29 __le32 gp_in; /* 0xe4 */
30 __le32 rsrvd2[5]; /* 0xe8-0xfb */
31 __le32 port_err_status; /* 0xfc */
32 };
33
34 struct host_mem_cfg_regs {
35 __le32 rsrvd0[12]; /* 0x50-0x79 */
36 __le32 req_q_out; /* 0x80 */
37 __le32 rsrvd1[31]; /* 0x84-0xFF */
38 };
39
40 /* remote register set (access via PCI memory read/write) */
41 struct isp_reg {
42 #define MBOX_REG_COUNT 8
43 __le32 mailbox[MBOX_REG_COUNT];
44
45 __le32 flash_address; /* 0x20 */
46 __le32 flash_data;
47 __le32 ctrl_status;
48
49 union {
50 struct {
51 __le32 nvram;
52 __le32 reserved1[2]; /* 0x30 */
53 } __attribute__ ((packed)) isp4010;
54 struct {
55 __le32 intr_mask;
56 __le32 nvram; /* 0x30 */
57 __le32 semaphore;
58 } __attribute__ ((packed)) isp4022;
59 } u1;
60
61 __le32 req_q_in; /* SCSI Request Queue Producer Index */
62 __le32 rsp_q_out; /* SCSI Completion Queue Consumer Index */
63
64 __le32 reserved2[4]; /* 0x40 */
65
66 union {
67 struct {
68 __le32 ext_hw_conf; /* 0x50 */
69 __le32 flow_ctrl;
70 __le32 port_ctrl;
71 __le32 port_status;
72
73 __le32 reserved3[8]; /* 0x60 */
74
75 __le32 req_q_out; /* 0x80 */
76
77 __le32 reserved4[23]; /* 0x84 */
78
79 __le32 gp_out; /* 0xe0 */
80 __le32 gp_in;
81
82 __le32 reserved5[5];
83
84 __le32 port_err_status; /* 0xfc */
85 } __attribute__ ((packed)) isp4010;
86 struct {
87 union {
88 struct port_ctrl_stat_regs p0;
89 struct host_mem_cfg_regs p1;
90 };
91 } __attribute__ ((packed)) isp4022;
92 } u2;
93 }; /* 256 x100 */
94
95
96 /* Semaphore Defines for 4010 */
97 #define QL4010_DRVR_SEM_BITS 0x00000030
98 #define QL4010_GPIO_SEM_BITS 0x000000c0
99 #define QL4010_SDRAM_SEM_BITS 0x00000300
100 #define QL4010_PHY_SEM_BITS 0x00000c00
101 #define QL4010_NVRAM_SEM_BITS 0x00003000
102 #define QL4010_FLASH_SEM_BITS 0x0000c000
103
104 #define QL4010_DRVR_SEM_MASK 0x00300000
105 #define QL4010_GPIO_SEM_MASK 0x00c00000
106 #define QL4010_SDRAM_SEM_MASK 0x03000000
107 #define QL4010_PHY_SEM_MASK 0x0c000000
108 #define QL4010_NVRAM_SEM_MASK 0x30000000
109 #define QL4010_FLASH_SEM_MASK 0xc0000000
110
111 /* Semaphore Defines for 4022 */
112 #define QL4022_RESOURCE_MASK_BASE_CODE 0x7
113 #define QL4022_RESOURCE_BITS_BASE_CODE 0x4
114
115
116 #define QL4022_DRVR_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (1+16))
117 #define QL4022_DDR_RAM_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (4+16))
118 #define QL4022_PHY_GIO_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (7+16))
119 #define QL4022_NVRAM_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (10+16))
120 #define QL4022_FLASH_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (13+16))
121
122
123
124 /* Page # defines for 4022 */
125 #define PORT_CTRL_STAT_PAGE 0 /* 4022 */
126 #define HOST_MEM_CFG_PAGE 1 /* 4022 */
127 #define LOCAL_RAM_CFG_PAGE 2 /* 4022 */
128 #define PROT_STAT_PAGE 3 /* 4022 */
129
130 /* Register Mask - sets corresponding mask bits in the upper word */
131 static inline uint32_t set_rmask(uint32_t val)
132 {
133 return (val & 0xffff) | (val << 16);
134 }
135
136
137 static inline uint32_t clr_rmask(uint32_t val)
138 {
139 return 0 | (val << 16);
140 }
141
142 /* ctrl_status definitions */
143 #define CSR_SCSI_PAGE_SELECT 0x00000003
144 #define CSR_SCSI_INTR_ENABLE 0x00000004 /* 4010 */
145 #define CSR_SCSI_RESET_INTR 0x00000008
146 #define CSR_SCSI_COMPLETION_INTR 0x00000010
147 #define CSR_SCSI_PROCESSOR_INTR 0x00000020
148 #define CSR_INTR_RISC 0x00000040
149 #define CSR_BOOT_ENABLE 0x00000080
150 #define CSR_NET_PAGE_SELECT 0x00000300 /* 4010 */
151 #define CSR_FUNC_NUM 0x00000700 /* 4022 */
152 #define CSR_NET_RESET_INTR 0x00000800 /* 4010 */
153 #define CSR_FORCE_SOFT_RESET 0x00002000 /* 4022 */
154 #define CSR_FATAL_ERROR 0x00004000
155 #define CSR_SOFT_RESET 0x00008000
156 #define ISP_CONTROL_FN_MASK CSR_FUNC_NUM
157 #define ISP_CONTROL_FN0_SCSI 0x0500
158 #define ISP_CONTROL_FN1_SCSI 0x0700
159
160 #define INTR_PENDING (CSR_SCSI_COMPLETION_INTR |\
161 CSR_SCSI_PROCESSOR_INTR |\
162 CSR_SCSI_RESET_INTR)
163
164 /* ISP InterruptMask definitions */
165 #define IMR_SCSI_INTR_ENABLE 0x00000004 /* 4022 */
166
167 /* ISP 4022 nvram definitions */
168 #define NVR_WRITE_ENABLE 0x00000010 /* 4022 */
169
170 /* ISP port_status definitions */
171
172 /* ISP Semaphore definitions */
173
174 /* ISP General Purpose Output definitions */
175 #define GPOR_TOPCAT_RESET 0x00000004
176
177 /* shadow registers (DMA'd from HA to system memory. read only) */
178 struct shadow_regs {
179 /* SCSI Request Queue Consumer Index */
180 __le32 req_q_out; /* 0 x0 R */
181
182 /* SCSI Completion Queue Producer Index */
183 __le32 rsp_q_in; /* 4 x4 R */
184 }; /* 8 x8 */
185
186
187 /* External hardware configuration register */
188 union external_hw_config_reg {
189 struct {
190 /* FIXME: Do we even need this? All values are
191 * referred to by 16 bit quantities. Platform and
192 * endianess issues. */
193 __le32 bReserved0:1;
194 __le32 bSDRAMProtectionMethod:2;
195 __le32 bSDRAMBanks:1;
196 __le32 bSDRAMChipWidth:1;
197 __le32 bSDRAMChipSize:2;
198 __le32 bParityDisable:1;
199 __le32 bExternalMemoryType:1;
200 __le32 bFlashBIOSWriteEnable:1;
201 __le32 bFlashUpperBankSelect:1;
202 __le32 bWriteBurst:2;
203 __le32 bReserved1:3;
204 __le32 bMask:16;
205 };
206 uint32_t Asuint32_t;
207 };
208
209 /*************************************************************************
210 *
211 * Mailbox Commands Structures and Definitions
212 *
213 *************************************************************************/
214
215 /* Mailbox command definitions */
216 #define MBOX_CMD_ABOUT_FW 0x0009
217 #define MBOX_CMD_PING 0x000B
218 #define MBOX_CMD_LUN_RESET 0x0016
219 #define MBOX_CMD_GET_MANAGEMENT_DATA 0x001E
220 #define MBOX_CMD_GET_FW_STATUS 0x001F
221 #define MBOX_CMD_SET_ISNS_SERVICE 0x0021
222 #define ISNS_DISABLE 0
223 #define ISNS_ENABLE 1
224 #define MBOX_CMD_COPY_FLASH 0x0024
225 #define MBOX_CMD_WRITE_FLASH 0x0025
226 #define MBOX_CMD_READ_FLASH 0x0026
227 #define MBOX_CMD_CLEAR_DATABASE_ENTRY 0x0031
228 #define MBOX_CMD_CONN_CLOSE_SESS_LOGOUT 0x0056
229 #define LOGOUT_OPTION_CLOSE_SESSION 0x01
230 #define LOGOUT_OPTION_RELOGIN 0x02
231 #define MBOX_CMD_EXECUTE_IOCB_A64 0x005A
232 #define MBOX_CMD_INITIALIZE_FIRMWARE 0x0060
233 #define MBOX_CMD_GET_INIT_FW_CTRL_BLOCK 0x0061
234 #define MBOX_CMD_REQUEST_DATABASE_ENTRY 0x0062
235 #define MBOX_CMD_SET_DATABASE_ENTRY 0x0063
236 #define MBOX_CMD_GET_DATABASE_ENTRY 0x0064
237 #define DDB_DS_UNASSIGNED 0x00
238 #define DDB_DS_NO_CONNECTION_ACTIVE 0x01
239 #define DDB_DS_SESSION_ACTIVE 0x04
240 #define DDB_DS_SESSION_FAILED 0x06
241 #define DDB_DS_LOGIN_IN_PROCESS 0x07
242 #define MBOX_CMD_GET_FW_STATE 0x0069
243 #define MBOX_CMD_GET_INIT_FW_CTRL_BLOCK_DEFAULTS 0x006A
244 #define MBOX_CMD_RESTORE_FACTORY_DEFAULTS 0x0087
245 #define MBOX_CMD_SET_ACB 0x0088
246 #define MBOX_CMD_GET_ACB 0x0089
247 #define MBOX_CMD_DISABLE_ACB 0x008A
248 #define MBOX_CMD_GET_IPV6_NEIGHBOR_CACHE 0x008B
249 #define MBOX_CMD_GET_IPV6_DEST_CACHE 0x008C
250 #define MBOX_CMD_GET_IPV6_DEF_ROUTER_LIST 0x008D
251 #define MBOX_CMD_GET_IPV6_LCL_PREFIX_LIST 0x008E
252 #define MBOX_CMD_SET_IPV6_NEIGHBOR_CACHE 0x0090
253 #define MBOX_CMD_GET_IP_ADDR_STATE 0x0091
254 #define MBOX_CMD_SEND_IPV6_ROUTER_SOL 0x0092
255 #define MBOX_CMD_GET_DB_ENTRY_CURRENT_IP_ADDR 0x0093
256
257 /* Mailbox 1 */
258 #define FW_STATE_READY 0x0000
259 #define FW_STATE_CONFIG_WAIT 0x0001
260 #define FW_STATE_WAIT_LOGIN 0x0002
261 #define FW_STATE_ERROR 0x0004
262 #define FW_STATE_DHCP_IN_PROGRESS 0x0008
263
264 /* Mailbox 3 */
265 #define FW_ADDSTATE_OPTICAL_MEDIA 0x0001
266 #define FW_ADDSTATE_DHCP_ENABLED 0x0002
267 #define FW_ADDSTATE_LINK_UP 0x0010
268 #define FW_ADDSTATE_ISNS_SVC_ENABLED 0x0020
269 #define MBOX_CMD_GET_DATABASE_ENTRY_DEFAULTS 0x006B
270 #define MBOX_CMD_CONN_OPEN_SESS_LOGIN 0x0074
271 #define MBOX_CMD_GET_CRASH_RECORD 0x0076 /* 4010 only */
272 #define MBOX_CMD_GET_CONN_EVENT_LOG 0x0077
273
274 /* Mailbox status definitions */
275 #define MBOX_COMPLETION_STATUS 4
276 #define MBOX_STS_BUSY 0x0007
277 #define MBOX_STS_INTERMEDIATE_COMPLETION 0x1000
278 #define MBOX_STS_COMMAND_COMPLETE 0x4000
279 #define MBOX_STS_COMMAND_ERROR 0x4005
280
281 #define MBOX_ASYNC_EVENT_STATUS 8
282 #define MBOX_ASTS_SYSTEM_ERROR 0x8002
283 #define MBOX_ASTS_REQUEST_TRANSFER_ERROR 0x8003
284 #define MBOX_ASTS_RESPONSE_TRANSFER_ERROR 0x8004
285 #define MBOX_ASTS_PROTOCOL_STATISTIC_ALARM 0x8005
286 #define MBOX_ASTS_SCSI_COMMAND_PDU_REJECTED 0x8006
287 #define MBOX_ASTS_LINK_UP 0x8010
288 #define MBOX_ASTS_LINK_DOWN 0x8011
289 #define MBOX_ASTS_DATABASE_CHANGED 0x8014
290 #define MBOX_ASTS_UNSOLICITED_PDU_RECEIVED 0x8015
291 #define MBOX_ASTS_SELF_TEST_FAILED 0x8016
292 #define MBOX_ASTS_LOGIN_FAILED 0x8017
293 #define MBOX_ASTS_DNS 0x8018
294 #define MBOX_ASTS_HEARTBEAT 0x8019
295 #define MBOX_ASTS_NVRAM_INVALID 0x801A
296 #define MBOX_ASTS_MAC_ADDRESS_CHANGED 0x801B
297 #define MBOX_ASTS_IP_ADDRESS_CHANGED 0x801C
298 #define MBOX_ASTS_DHCP_LEASE_EXPIRED 0x801D
299 #define MBOX_ASTS_DHCP_LEASE_ACQUIRED 0x801F
300 #define MBOX_ASTS_ISNS_UNSOLICITED_PDU_RECEIVED 0x8021
301 #define MBOX_ASTS_DUPLICATE_IP 0x8025
302 #define MBOX_ASTS_ARP_COMPLETE 0x8026
303 #define MBOX_ASTS_SUBNET_STATE_CHANGE 0x8027
304 #define MBOX_ASTS_RESPONSE_QUEUE_FULL 0x8028
305 #define MBOX_ASTS_IP_ADDR_STATE_CHANGED 0x8029
306 #define MBOX_ASTS_IPV6_PREFIX_EXPIRED 0x802B
307 #define MBOX_ASTS_IPV6_ND_PREFIX_IGNORED 0x802C
308 #define MBOX_ASTS_IPV6_LCL_PREFIX_IGNORED 0x802D
309 #define MBOX_ASTS_ICMPV6_ERROR_MSG_RCVD 0x802E
310
311 #define ISNS_EVENT_DATA_RECEIVED 0x0000
312 #define ISNS_EVENT_CONNECTION_OPENED 0x0001
313 #define ISNS_EVENT_CONNECTION_FAILED 0x0002
314 #define MBOX_ASTS_IPSEC_SYSTEM_FATAL_ERROR 0x8022
315 #define MBOX_ASTS_SUBNET_STATE_CHANGE 0x8027
316
317 /*************************************************************************/
318
319 /* Host Adapter Initialization Control Block (from host) */
320 struct addr_ctrl_blk {
321 uint8_t version; /* 00 */
322 uint8_t control; /* 01 */
323
324 uint16_t fw_options; /* 02-03 */
325 #define FWOPT_HEARTBEAT_ENABLE 0x1000
326 #define FWOPT_SESSION_MODE 0x0040
327 #define FWOPT_INITIATOR_MODE 0x0020
328 #define FWOPT_TARGET_MODE 0x0010
329
330 uint16_t exec_throttle; /* 04-05 */
331 uint8_t zio_count; /* 06 */
332 uint8_t res0; /* 07 */
333 uint16_t eth_mtu_size; /* 08-09 */
334 uint16_t add_fw_options; /* 0A-0B */
335
336 uint8_t hb_interval; /* 0C */
337 uint8_t inst_num; /* 0D */
338 uint16_t res1; /* 0E-0F */
339 uint16_t rqq_consumer_idx; /* 10-11 */
340 uint16_t compq_producer_idx; /* 12-13 */
341 uint16_t rqq_len; /* 14-15 */
342 uint16_t compq_len; /* 16-17 */
343 uint32_t rqq_addr_lo; /* 18-1B */
344 uint32_t rqq_addr_hi; /* 1C-1F */
345 uint32_t compq_addr_lo; /* 20-23 */
346 uint32_t compq_addr_hi; /* 24-27 */
347 uint32_t shdwreg_addr_lo; /* 28-2B */
348 uint32_t shdwreg_addr_hi; /* 2C-2F */
349
350 uint16_t iscsi_opts; /* 30-31 */
351 uint16_t ipv4_tcp_opts; /* 32-33 */
352 uint16_t ipv4_ip_opts; /* 34-35 */
353
354 uint16_t iscsi_max_pdu_size; /* 36-37 */
355 uint8_t ipv4_tos; /* 38 */
356 uint8_t ipv4_ttl; /* 39 */
357 uint8_t acb_version; /* 3A */
358 uint8_t res2; /* 3B */
359 uint16_t def_timeout; /* 3C-3D */
360 uint16_t iscsi_fburst_len; /* 3E-3F */
361 uint16_t iscsi_def_time2wait; /* 40-41 */
362 uint16_t iscsi_def_time2retain; /* 42-43 */
363 uint16_t iscsi_max_outstnd_r2t; /* 44-45 */
364 uint16_t conn_ka_timeout; /* 46-47 */
365 uint16_t ipv4_port; /* 48-49 */
366 uint16_t iscsi_max_burst_len; /* 4A-4B */
367 uint32_t res5; /* 4C-4F */
368 uint8_t ipv4_addr[4]; /* 50-53 */
369 uint16_t ipv4_vlan_tag; /* 54-55 */
370 uint8_t ipv4_addr_state; /* 56 */
371 uint8_t ipv4_cacheid; /* 57 */
372 uint8_t res6[8]; /* 58-5F */
373 uint8_t ipv4_subnet[4]; /* 60-63 */
374 uint8_t res7[12]; /* 64-6F */
375 uint8_t ipv4_gw_addr[4]; /* 70-73 */
376 uint8_t res8[0xc]; /* 74-7F */
377 uint8_t pri_dns_srvr_ip[4];/* 80-83 */
378 uint8_t sec_dns_srvr_ip[4];/* 84-87 */
379 uint16_t min_eph_port; /* 88-89 */
380 uint16_t max_eph_port; /* 8A-8B */
381 uint8_t res9[4]; /* 8C-8F */
382 uint8_t iscsi_alias[32];/* 90-AF */
383 uint8_t res9_1[0x16]; /* B0-C5 */
384 uint16_t tgt_portal_grp;/* C6-C7 */
385 uint8_t abort_timer; /* C8 */
386 uint8_t ipv4_tcp_wsf; /* C9 */
387 uint8_t res10[6]; /* CA-CF */
388 uint8_t ipv4_sec_ip_addr[4]; /* D0-D3 */
389 uint8_t ipv4_dhcp_vid_len; /* D4 */
390 uint8_t ipv4_dhcp_vid[11]; /* D5-DF */
391 uint8_t res11[20]; /* E0-F3 */
392 uint8_t ipv4_dhcp_alt_cid_len; /* F4 */
393 uint8_t ipv4_dhcp_alt_cid[11]; /* F5-FF */
394 uint8_t iscsi_name[224]; /* 100-1DF */
395 uint8_t res12[32]; /* 1E0-1FF */
396 uint32_t cookie; /* 200-203 */
397 uint16_t ipv6_port; /* 204-205 */
398 uint16_t ipv6_opts; /* 206-207 */
399 uint16_t ipv6_addtl_opts; /* 208-209 */
400 uint16_t ipv6_tcp_opts; /* 20A-20B */
401 uint8_t ipv6_tcp_wsf; /* 20C */
402 uint16_t ipv6_flow_lbl; /* 20D-20F */
403 uint8_t ipv6_gw_addr[16]; /* 210-21F */
404 uint16_t ipv6_vlan_tag; /* 220-221 */
405 uint8_t ipv6_lnk_lcl_addr_state;/* 222 */
406 uint8_t ipv6_addr0_state; /* 223 */
407 uint8_t ipv6_addr1_state; /* 224 */
408 uint8_t ipv6_gw_state; /* 225 */
409 uint8_t ipv6_traffic_class; /* 226 */
410 uint8_t ipv6_hop_limit; /* 227 */
411 uint8_t ipv6_if_id[8]; /* 228-22F */
412 uint8_t ipv6_addr0[16]; /* 230-23F */
413 uint8_t ipv6_addr1[16]; /* 240-24F */
414 uint32_t ipv6_nd_reach_time; /* 250-253 */
415 uint32_t ipv6_nd_rexmit_timer; /* 254-257 */
416 uint32_t ipv6_nd_stale_timeout; /* 258-25B */
417 uint8_t ipv6_dup_addr_detect_count; /* 25C */
418 uint8_t ipv6_cache_id; /* 25D */
419 uint8_t res13[18]; /* 25E-26F */
420 uint32_t ipv6_gw_advrt_mtu; /* 270-273 */
421 uint8_t res14[140]; /* 274-2FF */
422 };
423
424 struct init_fw_ctrl_blk {
425 struct addr_ctrl_blk pri;
426 struct addr_ctrl_blk sec;
427 };
428
429 /*************************************************************************/
430
431 struct dev_db_entry {
432 uint16_t options; /* 00-01 */
433 #define DDB_OPT_DISC_SESSION 0x10
434 #define DDB_OPT_TARGET 0x02 /* device is a target */
435
436 uint16_t exec_throttle; /* 02-03 */
437 uint16_t exec_count; /* 04-05 */
438 uint16_t res0; /* 06-07 */
439 uint16_t iscsi_options; /* 08-09 */
440 uint16_t tcp_options; /* 0A-0B */
441 uint16_t ip_options; /* 0C-0D */
442 uint16_t iscsi_max_rcv_data_seg_len; /* 0E-0F */
443 uint32_t res1; /* 10-13 */
444 uint16_t iscsi_max_snd_data_seg_len; /* 14-15 */
445 uint16_t iscsi_first_burst_len; /* 16-17 */
446 uint16_t iscsi_def_time2wait; /* 18-19 */
447 uint16_t iscsi_def_time2retain; /* 1A-1B */
448 uint16_t iscsi_max_outsnd_r2t; /* 1C-1D */
449 uint16_t ka_timeout; /* 1E-1F */
450 uint8_t isid[6]; /* 20-25 big-endian, must be converted
451 * to little-endian */
452 uint16_t tsid; /* 26-27 */
453 uint16_t port; /* 28-29 */
454 uint16_t iscsi_max_burst_len; /* 2A-2B */
455 uint16_t def_timeout; /* 2C-2D */
456 uint16_t res2; /* 2E-2F */
457 uint8_t ip_addr[0x10]; /* 30-3F */
458 uint8_t iscsi_alias[0x20]; /* 40-5F */
459 uint8_t tgt_addr[0x20]; /* 60-7F */
460 uint16_t mss; /* 80-81 */
461 uint16_t res3; /* 82-83 */
462 uint16_t lcl_port; /* 84-85 */
463 uint8_t ipv4_tos; /* 86 */
464 uint16_t ipv6_flow_lbl; /* 87-89 */
465 uint8_t res4[0x36]; /* 8A-BF */
466 uint8_t iscsi_name[0xE0]; /* C0-19F : xxzzy Make this a
467 * pointer to a string so we
468 * don't have to reserve soooo
469 * much RAM */
470 uint8_t ipv6_addr[0x10];/* 1A0-1AF */
471 uint8_t res5[0x10]; /* 1B0-1BF */
472 uint16_t ddb_link; /* 1C0-1C1 */
473 uint16_t chap_tbl_idx; /* 1C2-1C3 */
474 uint16_t tgt_portal_grp; /* 1C4-1C5 */
475 uint8_t tcp_xmt_wsf; /* 1C6 */
476 uint8_t tcp_rcv_wsf; /* 1C7 */
477 uint32_t stat_sn; /* 1C8-1CB */
478 uint32_t exp_stat_sn; /* 1CC-1CF */
479 uint8_t res6[0x30]; /* 1D0-1FF */
480 };
481
482 /*************************************************************************/
483
484 /* Flash definitions */
485
486 #define FLASH_OFFSET_SYS_INFO 0x02000000
487 #define FLASH_DEFAULTBLOCKSIZE 0x20000
488 #define FLASH_EOF_OFFSET (FLASH_DEFAULTBLOCKSIZE-8) /* 4 bytes
489 * for EOF
490 * signature */
491
492 struct sys_info_phys_addr {
493 uint8_t address[6]; /* 00-05 */
494 uint8_t filler[2]; /* 06-07 */
495 };
496
497 struct flash_sys_info {
498 uint32_t cookie; /* 00-03 */
499 uint32_t physAddrCount; /* 04-07 */
500 struct sys_info_phys_addr physAddr[4]; /* 08-27 */
501 uint8_t vendorId[128]; /* 28-A7 */
502 uint8_t productId[128]; /* A8-127 */
503 uint32_t serialNumber; /* 128-12B */
504
505 /* PCI Configuration values */
506 uint32_t pciDeviceVendor; /* 12C-12F */
507 uint32_t pciDeviceId; /* 130-133 */
508 uint32_t pciSubsysVendor; /* 134-137 */
509 uint32_t pciSubsysId; /* 138-13B */
510
511 /* This validates version 1. */
512 uint32_t crumbs; /* 13C-13F */
513
514 uint32_t enterpriseNumber; /* 140-143 */
515
516 uint32_t mtu; /* 144-147 */
517 uint32_t reserved0; /* 148-14b */
518 uint32_t crumbs2; /* 14c-14f */
519 uint8_t acSerialNumber[16]; /* 150-15f */
520 uint32_t crumbs3; /* 160-16f */
521
522 /* Leave this last in the struct so it is declared invalid if
523 * any new items are added.
524 */
525 uint32_t reserved1[39]; /* 170-1ff */
526 }; /* 200 */
527
528 struct crash_record {
529 uint16_t fw_major_version; /* 00 - 01 */
530 uint16_t fw_minor_version; /* 02 - 03 */
531 uint16_t fw_patch_version; /* 04 - 05 */
532 uint16_t fw_build_version; /* 06 - 07 */
533
534 uint8_t build_date[16]; /* 08 - 17 */
535 uint8_t build_time[16]; /* 18 - 27 */
536 uint8_t build_user[16]; /* 28 - 37 */
537 uint8_t card_serial_num[16]; /* 38 - 47 */
538
539 uint32_t time_of_crash_in_secs; /* 48 - 4B */
540 uint32_t time_of_crash_in_ms; /* 4C - 4F */
541
542 uint16_t out_RISC_sd_num_frames; /* 50 - 51 */
543 uint16_t OAP_sd_num_words; /* 52 - 53 */
544 uint16_t IAP_sd_num_frames; /* 54 - 55 */
545 uint16_t in_RISC_sd_num_words; /* 56 - 57 */
546
547 uint8_t reserved1[28]; /* 58 - 7F */
548
549 uint8_t out_RISC_reg_dump[256]; /* 80 -17F */
550 uint8_t in_RISC_reg_dump[256]; /*180 -27F */
551 uint8_t in_out_RISC_stack_dump[0]; /*280 - ??? */
552 };
553
554 struct conn_event_log_entry {
555 #define MAX_CONN_EVENT_LOG_ENTRIES 100
556 uint32_t timestamp_sec; /* 00 - 03 seconds since boot */
557 uint32_t timestamp_ms; /* 04 - 07 milliseconds since boot */
558 uint16_t device_index; /* 08 - 09 */
559 uint16_t fw_conn_state; /* 0A - 0B */
560 uint8_t event_type; /* 0C - 0C */
561 uint8_t error_code; /* 0D - 0D */
562 uint16_t error_code_detail; /* 0E - 0F */
563 uint8_t num_consecutive_events; /* 10 - 10 */
564 uint8_t rsvd[3]; /* 11 - 13 */
565 };
566
567 /*************************************************************************
568 *
569 * IOCB Commands Structures and Definitions
570 *
571 *************************************************************************/
572 #define IOCB_MAX_CDB_LEN 16 /* Bytes in a CBD */
573 #define IOCB_MAX_SENSEDATA_LEN 32 /* Bytes of sense data */
574
575 /* IOCB header structure */
576 struct qla4_header {
577 uint8_t entryType;
578 #define ET_STATUS 0x03
579 #define ET_MARKER 0x04
580 #define ET_CONT_T1 0x0A
581 #define ET_STATUS_CONTINUATION 0x10
582 #define ET_CMND_T3 0x19
583 #define ET_PASSTHRU0 0x3A
584 #define ET_PASSTHRU_STATUS 0x3C
585
586 uint8_t entryStatus;
587 uint8_t systemDefined;
588 uint8_t entryCount;
589
590 /* SyetemDefined definition */
591 };
592
593 /* Generic queue entry structure*/
594 struct queue_entry {
595 uint8_t data[60];
596 uint32_t signature;
597
598 };
599
600 /* 64 bit addressing segment counts*/
601
602 #define COMMAND_SEG_A64 1
603 #define CONTINUE_SEG_A64 5
604
605 /* 64 bit addressing segment definition*/
606
607 struct data_seg_a64 {
608 struct {
609 uint32_t addrLow;
610 uint32_t addrHigh;
611
612 } base;
613
614 uint32_t count;
615
616 };
617
618 /* Command Type 3 entry structure*/
619
620 struct command_t3_entry {
621 struct qla4_header hdr; /* 00-03 */
622
623 uint32_t handle; /* 04-07 */
624 uint16_t target; /* 08-09 */
625 uint16_t connection_id; /* 0A-0B */
626
627 uint8_t control_flags; /* 0C */
628
629 /* data direction (bits 5-6) */
630 #define CF_WRITE 0x20
631 #define CF_READ 0x40
632 #define CF_NO_DATA 0x00
633
634 /* task attributes (bits 2-0) */
635 #define CF_HEAD_TAG 0x03
636 #define CF_ORDERED_TAG 0x02
637 #define CF_SIMPLE_TAG 0x01
638
639 /* STATE FLAGS FIELD IS A PLACE HOLDER. THE FW WILL SET BITS
640 * IN THIS FIELD AS THE COMMAND IS PROCESSED. WHEN THE IOCB IS
641 * CHANGED TO AN IOSB THIS FIELD WILL HAVE THE STATE FLAGS SET
642 * PROPERLY.
643 */
644 uint8_t state_flags; /* 0D */
645 uint8_t cmdRefNum; /* 0E */
646 uint8_t reserved1; /* 0F */
647 uint8_t cdb[IOCB_MAX_CDB_LEN]; /* 10-1F */
648 struct scsi_lun lun; /* FCP LUN (BE). */
649 uint32_t cmdSeqNum; /* 28-2B */
650 uint16_t timeout; /* 2C-2D */
651 uint16_t dataSegCnt; /* 2E-2F */
652 uint32_t ttlByteCnt; /* 30-33 */
653 struct data_seg_a64 dataseg[COMMAND_SEG_A64]; /* 34-3F */
654
655 };
656
657
658 /* Continuation Type 1 entry structure*/
659 struct continuation_t1_entry {
660 struct qla4_header hdr;
661
662 struct data_seg_a64 dataseg[CONTINUE_SEG_A64];
663
664 };
665
666 /* Parameterize for 64 or 32 bits */
667 #define COMMAND_SEG COMMAND_SEG_A64
668 #define CONTINUE_SEG CONTINUE_SEG_A64
669
670 #define ET_COMMAND ET_CMND_T3
671 #define ET_CONTINUE ET_CONT_T1
672
673 /* Marker entry structure*/
674 struct qla4_marker_entry {
675 struct qla4_header hdr; /* 00-03 */
676
677 uint32_t system_defined; /* 04-07 */
678 uint16_t target; /* 08-09 */
679 uint16_t modifier; /* 0A-0B */
680 #define MM_LUN_RESET 0
681
682 uint16_t flags; /* 0C-0D */
683 uint16_t reserved1; /* 0E-0F */
684 struct scsi_lun lun; /* FCP LUN (BE). */
685 uint64_t reserved2; /* 18-1F */
686 uint64_t reserved3; /* 20-27 */
687 uint64_t reserved4; /* 28-2F */
688 uint64_t reserved5; /* 30-37 */
689 uint64_t reserved6; /* 38-3F */
690 };
691
692 /* Status entry structure*/
693 struct status_entry {
694 struct qla4_header hdr; /* 00-03 */
695
696 uint32_t handle; /* 04-07 */
697
698 uint8_t scsiStatus; /* 08 */
699 #define SCSI_CHECK_CONDITION 0x02
700
701 uint8_t iscsiFlags; /* 09 */
702 #define ISCSI_FLAG_RESIDUAL_UNDER 0x02
703 #define ISCSI_FLAG_RESIDUAL_OVER 0x04
704
705 uint8_t iscsiResponse; /* 0A */
706
707 uint8_t completionStatus; /* 0B */
708 #define SCS_COMPLETE 0x00
709 #define SCS_INCOMPLETE 0x01
710 #define SCS_RESET_OCCURRED 0x04
711 #define SCS_ABORTED 0x05
712 #define SCS_TIMEOUT 0x06
713 #define SCS_DATA_OVERRUN 0x07
714 #define SCS_DATA_UNDERRUN 0x15
715 #define SCS_QUEUE_FULL 0x1C
716 #define SCS_DEVICE_UNAVAILABLE 0x28
717 #define SCS_DEVICE_LOGGED_OUT 0x29
718
719 uint8_t reserved1; /* 0C */
720
721 /* state_flags MUST be at the same location as state_flags in
722 * the Command_T3/4_Entry */
723 uint8_t state_flags; /* 0D */
724
725 uint16_t senseDataByteCnt; /* 0E-0F */
726 uint32_t residualByteCnt; /* 10-13 */
727 uint32_t bidiResidualByteCnt; /* 14-17 */
728 uint32_t expSeqNum; /* 18-1B */
729 uint32_t maxCmdSeqNum; /* 1C-1F */
730 uint8_t senseData[IOCB_MAX_SENSEDATA_LEN]; /* 20-3F */
731
732 };
733
734 struct passthru0 {
735 struct qla4_header hdr; /* 00-03 */
736 uint32_t handle; /* 04-07 */
737 uint16_t target; /* 08-09 */
738 uint16_t connectionID; /* 0A-0B */
739 #define ISNS_DEFAULT_SERVER_CONN_ID ((uint16_t)0x8000)
740
741 uint16_t controlFlags; /* 0C-0D */
742 #define PT_FLAG_ETHERNET_FRAME 0x8000
743 #define PT_FLAG_ISNS_PDU 0x8000
744 #define PT_FLAG_SEND_BUFFER 0x0200
745 #define PT_FLAG_WAIT_4_RESPONSE 0x0100
746
747 uint16_t timeout; /* 0E-0F */
748 #define PT_DEFAULT_TIMEOUT 30 /* seconds */
749
750 struct data_seg_a64 outDataSeg64; /* 10-1B */
751 uint32_t res1; /* 1C-1F */
752 struct data_seg_a64 inDataSeg64; /* 20-2B */
753 uint8_t res2[20]; /* 2C-3F */
754 };
755
756 struct passthru_status {
757 struct qla4_header hdr; /* 00-03 */
758 uint32_t handle; /* 04-07 */
759 uint16_t target; /* 08-09 */
760 uint16_t connectionID; /* 0A-0B */
761
762 uint8_t completionStatus; /* 0C */
763 #define PASSTHRU_STATUS_COMPLETE 0x01
764
765 uint8_t residualFlags; /* 0D */
766
767 uint16_t timeout; /* 0E-0F */
768 uint16_t portNumber; /* 10-11 */
769 uint8_t res1[10]; /* 12-1B */
770 uint32_t outResidual; /* 1C-1F */
771 uint8_t res2[12]; /* 20-2B */
772 uint32_t inResidual; /* 2C-2F */
773 uint8_t res4[16]; /* 30-3F */
774 };
775
776 #endif /* _QLA4X_FW_H */
777
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