1 /*
2 * Core routines and tables shareable across OS platforms.
3 *
4 * Copyright (c) 1994-2002 Justin T. Gibbs.
5 * Copyright (c) 2000-2002 Adaptec Inc.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
22 *
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
26 *
27 * NO WARRANTY
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGES.
39 *
40 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.c#134 $
41 *
42 * $FreeBSD$
43 */
44
45 #ifdef __linux__
46 #include "aic7xxx_osm.h"
47 #include "aic7xxx_inline.h"
48 #include "aicasm/aicasm_insformat.h"
49 #else
50 #include <dev/aic7xxx/aic7xxx_osm.h>
51 #include <dev/aic7xxx/aic7xxx_inline.h>
52 #include <dev/aic7xxx/aicasm/aicasm_insformat.h>
53 #endif
54
55 /****************************** Softc Data ************************************/
56 struct ahc_softc_tailq ahc_tailq = TAILQ_HEAD_INITIALIZER(ahc_tailq);
57
58 /***************************** Lookup Tables **********************************/
59 char *ahc_chip_names[] =
60 {
61 "NONE",
62 "aic7770",
63 "aic7850",
64 "aic7855",
65 "aic7859",
66 "aic7860",
67 "aic7870",
68 "aic7880",
69 "aic7895",
70 "aic7895C",
71 "aic7890/91",
72 "aic7896/97",
73 "aic7892",
74 "aic7899"
75 };
76 static const u_int num_chip_names = NUM_ELEMENTS(ahc_chip_names);
77
78 /*
79 * Hardware error codes.
80 */
81 struct ahc_hard_error_entry {
82 uint8_t errno;
83 char *errmesg;
84 };
85
86 static struct ahc_hard_error_entry ahc_hard_errors[] = {
87 { ILLHADDR, "Illegal Host Access" },
88 { ILLSADDR, "Illegal Sequencer Address referrenced" },
89 { ILLOPCODE, "Illegal Opcode in sequencer program" },
90 { SQPARERR, "Sequencer Parity Error" },
91 { DPARERR, "Data-path Parity Error" },
92 { MPARERR, "Scratch or SCB Memory Parity Error" },
93 { PCIERRSTAT, "PCI Error detected" },
94 { CIOPARERR, "CIOBUS Parity Error" },
95 };
96 static const u_int num_errors = NUM_ELEMENTS(ahc_hard_errors);
97
98 static struct ahc_phase_table_entry ahc_phase_table[] =
99 {
100 { P_DATAOUT, MSG_NOOP, "in Data-out phase" },
101 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" },
102 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" },
103 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" },
104 { P_COMMAND, MSG_NOOP, "in Command phase" },
105 { P_MESGOUT, MSG_NOOP, "in Message-out phase" },
106 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" },
107 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" },
108 { P_BUSFREE, MSG_NOOP, "while idle" },
109 { 0, MSG_NOOP, "in unknown phase" }
110 };
111
112 /*
113 * In most cases we only wish to itterate over real phases, so
114 * exclude the last element from the count.
115 */
116 static const u_int num_phases = NUM_ELEMENTS(ahc_phase_table) - 1;
117
118 /*
119 * Valid SCSIRATE values. (p. 3-17)
120 * Provides a mapping of tranfer periods in ns to the proper value to
121 * stick in the scsixfer reg.
122 */
123 static struct ahc_syncrate ahc_syncrates[] =
124 {
125 /* ultra2 fast/ultra period rate */
126 { 0x42, 0x000, 9, "80.0" },
127 { 0x03, 0x000, 10, "40.0" },
128 { 0x04, 0x000, 11, "33.0" },
129 { 0x05, 0x100, 12, "20.0" },
130 { 0x06, 0x110, 15, "16.0" },
131 { 0x07, 0x120, 18, "13.4" },
132 { 0x08, 0x000, 25, "10.0" },
133 { 0x19, 0x010, 31, "8.0" },
134 { 0x1a, 0x020, 37, "6.67" },
135 { 0x1b, 0x030, 43, "5.7" },
136 { 0x1c, 0x040, 50, "5.0" },
137 { 0x00, 0x050, 56, "4.4" },
138 { 0x00, 0x060, 62, "4.0" },
139 { 0x00, 0x070, 68, "3.6" },
140 { 0x00, 0x000, 0, NULL }
141 };
142
143 /* Our Sequencer Program */
144 #include "aic7xxx_seq.h"
145
146 /**************************** Function Declarations ***************************/
147 static void ahc_force_renegotiation(struct ahc_softc *ahc,
148 struct ahc_devinfo *devinfo);
149 static struct ahc_tmode_tstate*
150 ahc_alloc_tstate(struct ahc_softc *ahc,
151 u_int scsi_id, char channel);
152 #ifdef AHC_TARGET_MODE
153 static void ahc_free_tstate(struct ahc_softc *ahc,
154 u_int scsi_id, char channel, int force);
155 #endif
156 static struct ahc_syncrate*
157 ahc_devlimited_syncrate(struct ahc_softc *ahc,
158 struct ahc_initiator_tinfo *,
159 u_int *period,
160 u_int *ppr_options,
161 role_t role);
162 static void ahc_update_pending_scbs(struct ahc_softc *ahc);
163 static void ahc_fetch_devinfo(struct ahc_softc *ahc,
164 struct ahc_devinfo *devinfo);
165 static void ahc_scb_devinfo(struct ahc_softc *ahc,
166 struct ahc_devinfo *devinfo,
167 struct scb *scb);
168 static void ahc_assert_atn(struct ahc_softc *ahc);
169 static void ahc_setup_initiator_msgout(struct ahc_softc *ahc,
170 struct ahc_devinfo *devinfo,
171 struct scb *scb);
172 static void ahc_build_transfer_msg(struct ahc_softc *ahc,
173 struct ahc_devinfo *devinfo);
174 static void ahc_construct_sdtr(struct ahc_softc *ahc,
175 struct ahc_devinfo *devinfo,
176 u_int period, u_int offset);
177 static void ahc_construct_wdtr(struct ahc_softc *ahc,
178 struct ahc_devinfo *devinfo,
179 u_int bus_width);
180 static void ahc_construct_ppr(struct ahc_softc *ahc,
181 struct ahc_devinfo *devinfo,
182 u_int period, u_int offset,
183 u_int bus_width, u_int ppr_options);
184 static void ahc_clear_msg_state(struct ahc_softc *ahc);
185 static void ahc_handle_proto_violation(struct ahc_softc *ahc);
186 static void ahc_handle_message_phase(struct ahc_softc *ahc);
187 typedef enum {
188 AHCMSG_1B,
189 AHCMSG_2B,
190 AHCMSG_EXT
191 } ahc_msgtype;
192 static int ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type,
193 u_int msgval, int full);
194 static int ahc_parse_msg(struct ahc_softc *ahc,
195 struct ahc_devinfo *devinfo);
196 static int ahc_handle_msg_reject(struct ahc_softc *ahc,
197 struct ahc_devinfo *devinfo);
198 static void ahc_handle_ign_wide_residue(struct ahc_softc *ahc,
199 struct ahc_devinfo *devinfo);
200 static void ahc_reinitialize_dataptrs(struct ahc_softc *ahc);
201 static void ahc_handle_devreset(struct ahc_softc *ahc,
202 struct ahc_devinfo *devinfo,
203 cam_status status, char *message,
204 int verbose_level);
205 #ifdef AHC_TARGET_MODE
206 static void ahc_setup_target_msgin(struct ahc_softc *ahc,
207 struct ahc_devinfo *devinfo,
208 struct scb *scb);
209 #endif
210
211 static bus_dmamap_callback_t ahc_dmamap_cb;
212 static void ahc_build_free_scb_list(struct ahc_softc *ahc);
213 static int ahc_init_scbdata(struct ahc_softc *ahc);
214 static void ahc_fini_scbdata(struct ahc_softc *ahc);
215 static void ahc_qinfifo_requeue(struct ahc_softc *ahc,
216 struct scb *prev_scb,
217 struct scb *scb);
218 static int ahc_qinfifo_count(struct ahc_softc *ahc);
219 static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *ahc,
220 u_int prev, u_int scbptr);
221 static void ahc_add_curscb_to_free_list(struct ahc_softc *ahc);
222 static u_int ahc_rem_wscb(struct ahc_softc *ahc,
223 u_int scbpos, u_int prev);
224 static void ahc_reset_current_bus(struct ahc_softc *ahc);
225 #ifdef AHC_DUMP_SEQ
226 static void ahc_dumpseq(struct ahc_softc *ahc);
227 #endif
228 static int ahc_loadseq(struct ahc_softc *ahc);
229 static int ahc_check_patch(struct ahc_softc *ahc,
230 struct patch **start_patch,
231 u_int start_instr, u_int *skip_addr);
232 static void ahc_download_instr(struct ahc_softc *ahc,
233 u_int instrptr, uint8_t *dconsts);
234 #ifdef AHC_TARGET_MODE
235 static void ahc_queue_lstate_event(struct ahc_softc *ahc,
236 struct ahc_tmode_lstate *lstate,
237 u_int initiator_id,
238 u_int event_type,
239 u_int event_arg);
240 static void ahc_update_scsiid(struct ahc_softc *ahc,
241 u_int targid_mask);
242 static int ahc_handle_target_cmd(struct ahc_softc *ahc,
243 struct target_cmd *cmd);
244 #endif
245 /************************* Sequencer Execution Control ************************/
246 /*
247 * Restart the sequencer program from address zero
248 */
249 void
250 ahc_restart(struct ahc_softc *ahc)
251 {
252
253 ahc_pause(ahc);
254
255 /* No more pending messages. */
256 ahc_clear_msg_state(ahc);
257
258 ahc_outb(ahc, SCSISIGO, 0); /* De-assert BSY */
259 ahc_outb(ahc, MSG_OUT, MSG_NOOP); /* No message to send */
260 ahc_outb(ahc, SXFRCTL1, ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
261 ahc_outb(ahc, LASTPHASE, P_BUSFREE);
262 ahc_outb(ahc, SAVED_SCSIID, 0xFF);
263 ahc_outb(ahc, SAVED_LUN, 0xFF);
264
265 /*
266 * Ensure that the sequencer's idea of TQINPOS
267 * matches our own. The sequencer increments TQINPOS
268 * only after it sees a DMA complete and a reset could
269 * occur before the increment leaving the kernel to believe
270 * the command arrived but the sequencer to not.
271 */
272 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
273
274 /* Always allow reselection */
275 ahc_outb(ahc, SCSISEQ,
276 ahc_inb(ahc, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP));
277 if ((ahc->features & AHC_CMD_CHAN) != 0) {
278 /* Ensure that no DMA operations are in progress */
279 ahc_outb(ahc, CCSCBCNT, 0);
280 ahc_outb(ahc, CCSGCTL, 0);
281 ahc_outb(ahc, CCSCBCTL, 0);
282 }
283 /*
284 * If we were in the process of DMA'ing SCB data into
285 * an SCB, replace that SCB on the free list. This prevents
286 * an SCB leak.
287 */
288 if ((ahc_inb(ahc, SEQ_FLAGS2) & SCB_DMA) != 0) {
289 ahc_add_curscb_to_free_list(ahc);
290 ahc_outb(ahc, SEQ_FLAGS2,
291 ahc_inb(ahc, SEQ_FLAGS2) & ~SCB_DMA);
292 }
293 ahc_outb(ahc, MWI_RESIDUAL, 0);
294 ahc_outb(ahc, SEQCTL, ahc->seqctl);
295 ahc_outb(ahc, SEQADDR0, 0);
296 ahc_outb(ahc, SEQADDR1, 0);
297 ahc_unpause(ahc);
298 }
299
300 /************************* Input/Output Queues ********************************/
301 void
302 ahc_run_qoutfifo(struct ahc_softc *ahc)
303 {
304 struct scb *scb;
305 u_int scb_index;
306
307 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
308 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) {
309
310 scb_index = ahc->qoutfifo[ahc->qoutfifonext];
311 if ((ahc->qoutfifonext & 0x03) == 0x03) {
312 u_int modnext;
313
314 /*
315 * Clear 32bits of QOUTFIFO at a time
316 * so that we don't clobber an incoming
317 * byte DMA to the array on architectures
318 * that only support 32bit load and store
319 * operations.
320 */
321 modnext = ahc->qoutfifonext & ~0x3;
322 *((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL;
323 ahc_dmamap_sync(ahc, ahc->shared_data_dmat,
324 ahc->shared_data_dmamap,
325 /*offset*/modnext, /*len*/4,
326 BUS_DMASYNC_PREREAD);
327 }
328 ahc->qoutfifonext++;
329
330 scb = ahc_lookup_scb(ahc, scb_index);
331 if (scb == NULL) {
332 printf("%s: WARNING no command for scb %d "
333 "(cmdcmplt)\nQOUTPOS = %d\n",
334 ahc_name(ahc), scb_index,
335 (ahc->qoutfifonext - 1) & 0xFF);
336 continue;
337 }
338
339 /*
340 * Save off the residual
341 * if there is one.
342 */
343 ahc_update_residual(ahc, scb);
344 ahc_done(ahc, scb);
345 }
346 }
347
348 void
349 ahc_run_untagged_queues(struct ahc_softc *ahc)
350 {
351 int i;
352
353 for (i = 0; i < 16; i++)
354 ahc_run_untagged_queue(ahc, &ahc->untagged_queues[i]);
355 }
356
357 void
358 ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue)
359 {
360 struct scb *scb;
361
362 if (ahc->untagged_queue_lock != 0)
363 return;
364
365 if ((scb = TAILQ_FIRST(queue)) != NULL
366 && (scb->flags & SCB_ACTIVE) == 0) {
367 scb->flags |= SCB_ACTIVE;
368 ahc_queue_scb(ahc, scb);
369 }
370 }
371
372 /************************* Interrupt Handling *********************************/
373 void
374 ahc_handle_brkadrint(struct ahc_softc *ahc)
375 {
376 /*
377 * We upset the sequencer :-(
378 * Lookup the error message
379 */
380 int i;
381 int error;
382
383 error = ahc_inb(ahc, ERROR);
384 for (i = 0; error != 1 && i < num_errors; i++)
385 error >>= 1;
386 printf("%s: brkadrint, %s at seqaddr = 0x%x\n",
387 ahc_name(ahc), ahc_hard_errors[i].errmesg,
388 ahc_inb(ahc, SEQADDR0) |
389 (ahc_inb(ahc, SEQADDR1) << 8));
390
391 ahc_dump_card_state(ahc);
392
393 /* Tell everyone that this HBA is no longer available */
394 ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS,
395 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN,
396 CAM_NO_HBA);
397
398 /* Disable all interrupt sources by resetting the controller */
399 ahc_shutdown(ahc);
400 }
401
402 void
403 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat)
404 {
405 struct scb *scb;
406 struct ahc_devinfo devinfo;
407
408 ahc_fetch_devinfo(ahc, &devinfo);
409
410 /*
411 * Clear the upper byte that holds SEQINT status
412 * codes and clear the SEQINT bit. We will unpause
413 * the sequencer, if appropriate, after servicing
414 * the request.
415 */
416 ahc_outb(ahc, CLRINT, CLRSEQINT);
417 switch (intstat & SEQINT_MASK) {
418 case BAD_STATUS:
419 {
420 u_int scb_index;
421 struct hardware_scb *hscb;
422
423 /*
424 * Set the default return value to 0 (don't
425 * send sense). The sense code will change
426 * this if needed.
427 */
428 ahc_outb(ahc, RETURN_1, 0);
429
430 /*
431 * The sequencer will notify us when a command
432 * has an error that would be of interest to
433 * the kernel. This allows us to leave the sequencer
434 * running in the common case of command completes
435 * without error. The sequencer will already have
436 * dma'd the SCB back up to us, so we can reference
437 * the in kernel copy directly.
438 */
439 scb_index = ahc_inb(ahc, SCB_TAG);
440 scb = ahc_lookup_scb(ahc, scb_index);
441 if (scb == NULL) {
442 ahc_print_devinfo(ahc, &devinfo);
443 printf("ahc_intr - referenced scb "
444 "not valid during seqint 0x%x scb(%d)\n",
445 intstat, scb_index);
446 ahc_dump_card_state(ahc);
447 panic("for safety");
448 goto unpause;
449 }
450
451 hscb = scb->hscb;
452
453 /* Don't want to clobber the original sense code */
454 if ((scb->flags & SCB_SENSE) != 0) {
455 /*
456 * Clear the SCB_SENSE Flag and have
457 * the sequencer do a normal command
458 * complete.
459 */
460 scb->flags &= ~SCB_SENSE;
461 ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
462 break;
463 }
464 ahc_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR);
465 /* Freeze the queue until the client sees the error. */
466 ahc_freeze_devq(ahc, scb);
467 ahc_freeze_scb(scb);
468 ahc_set_scsi_status(scb, hscb->shared_data.status.scsi_status);
469 switch (hscb->shared_data.status.scsi_status) {
470 case SCSI_STATUS_OK:
471 printf("%s: Interrupted for staus of 0???\n",
472 ahc_name(ahc));
473 break;
474 case SCSI_STATUS_CMD_TERMINATED:
475 case SCSI_STATUS_CHECK_COND:
476 {
477 struct ahc_dma_seg *sg;
478 struct scsi_sense *sc;
479 struct ahc_initiator_tinfo *targ_info;
480 struct ahc_tmode_tstate *tstate;
481 struct ahc_transinfo *tinfo;
482 #ifdef AHC_DEBUG
483 if (ahc_debug & AHC_SHOW_SENSE) {
484 ahc_print_path(ahc, scb);
485 printf("SCB %d: requests Check Status\n",
486 scb->hscb->tag);
487 }
488 #endif
489
490 if (ahc_perform_autosense(scb) == 0)
491 break;
492
493 targ_info = ahc_fetch_transinfo(ahc,
494 devinfo.channel,
495 devinfo.our_scsiid,
496 devinfo.target,
497 &tstate);
498 tinfo = &targ_info->curr;
499 sg = scb->sg_list;
500 sc = (struct scsi_sense *)(&hscb->shared_data.cdb);
501 /*
502 * Save off the residual if there is one.
503 */
504 ahc_update_residual(ahc, scb);
505 #ifdef AHC_DEBUG
506 if (ahc_debug & AHC_SHOW_SENSE) {
507 ahc_print_path(ahc, scb);
508 printf("Sending Sense\n");
509 }
510 #endif
511 sg->addr = ahc_get_sense_bufaddr(ahc, scb);
512 sg->len = ahc_get_sense_bufsize(ahc, scb);
513 sg->len |= AHC_DMA_LAST_SEG;
514
515 /* Fixup byte order */
516 sg->addr = ahc_htole32(sg->addr);
517 sg->len = ahc_htole32(sg->len);
518
519 sc->opcode = REQUEST_SENSE;
520 sc->byte2 = 0;
521 if (tinfo->protocol_version <= SCSI_REV_2
522 && SCB_GET_LUN(scb) < 8)
523 sc->byte2 = SCB_GET_LUN(scb) << 5;
524 sc->unused[0] = 0;
525 sc->unused[1] = 0;
526 sc->length = sg->len;
527 sc->control = 0;
528
529 /*
530 * We can't allow the target to disconnect.
531 * This will be an untagged transaction and
532 * having the target disconnect will make this
533 * transaction indestinguishable from outstanding
534 * tagged transactions.
535 */
536 hscb->control = 0;
537
538 /*
539 * This request sense could be because the
540 * the device lost power or in some other
541 * way has lost our transfer negotiations.
542 * Renegotiate if appropriate. Unit attention
543 * errors will be reported before any data
544 * phases occur.
545 */
546 if (ahc_get_residual(scb)
547 == ahc_get_transfer_length(scb)) {
548 ahc_update_neg_request(ahc, &devinfo,
549 tstate, targ_info,
550 AHC_NEG_IF_NON_ASYNC);
551 }
552 if (tstate->auto_negotiate & devinfo.target_mask) {
553 hscb->control |= MK_MESSAGE;
554 scb->flags &= ~SCB_NEGOTIATE;
555 scb->flags |= SCB_AUTO_NEGOTIATE;
556 }
557 hscb->cdb_len = sizeof(*sc);
558 hscb->dataptr = sg->addr;
559 hscb->datacnt = sg->len;
560 hscb->sgptr = scb->sg_list_phys | SG_FULL_RESID;
561 hscb->sgptr = ahc_htole32(hscb->sgptr);
562 scb->sg_count = 1;
563 scb->flags |= SCB_SENSE;
564 ahc_qinfifo_requeue_tail(ahc, scb);
565 ahc_outb(ahc, RETURN_1, SEND_SENSE);
566 /*
567 * Ensure we have enough time to actually
568 * retrieve the sense.
569 */
570 ahc_scb_timer_reset(scb, 5 * 1000000);
571 break;
572 }
573 default:
574 break;
575 }
576 break;
577 }
578 case NO_MATCH:
579 {
580 /* Ensure we don't leave the selection hardware on */
581 ahc_outb(ahc, SCSISEQ,
582 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
583
584 printf("%s:%c:%d: no active SCB for reconnecting "
585 "target - issuing BUS DEVICE RESET\n",
586 ahc_name(ahc), devinfo.channel, devinfo.target);
587 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
588 "ARG_1 == 0x%x ACCUM = 0x%x\n",
589 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
590 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
591 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
592 "SINDEX == 0x%x\n",
593 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
594 ahc_index_busy_tcl(ahc,
595 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
596 ahc_inb(ahc, SAVED_LUN))),
597 ahc_inb(ahc, SINDEX));
598 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
599 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
600 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
601 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
602 ahc_inb(ahc, SCB_CONTROL));
603 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
604 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
605 printf("SXFRCTL0 == 0x%x\n", ahc_inb(ahc, SXFRCTL0));
606 printf("SEQCTL == 0x%x\n", ahc_inb(ahc, SEQCTL));
607 ahc_dump_card_state(ahc);
608 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET;
609 ahc->msgout_len = 1;
610 ahc->msgout_index = 0;
611 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
612 ahc_outb(ahc, MSG_OUT, HOST_MSG);
613 ahc_assert_atn(ahc);
614 break;
615 }
616 case SEND_REJECT:
617 {
618 u_int rejbyte = ahc_inb(ahc, ACCUM);
619 printf("%s:%c:%d: Warning - unknown message received from "
620 "target (0x%x). Rejecting\n",
621 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte);
622 break;
623 }
624 case PROTO_VIOLATION:
625 {
626 ahc_handle_proto_violation(ahc);
627 break;
628 }
629 case IGN_WIDE_RES:
630 ahc_handle_ign_wide_residue(ahc, &devinfo);
631 break;
632 case PDATA_REINIT:
633 ahc_reinitialize_dataptrs(ahc);
634 break;
635 case BAD_PHASE:
636 {
637 u_int lastphase;
638
639 lastphase = ahc_inb(ahc, LASTPHASE);
640 printf("%s:%c:%d: unknown scsi bus phase %x, "
641 "lastphase = 0x%x. Attempting to continue\n",
642 ahc_name(ahc), devinfo.channel, devinfo.target,
643 lastphase, ahc_inb(ahc, SCSISIGI));
644 break;
645 }
646 case MISSED_BUSFREE:
647 {
648 u_int lastphase;
649
650 lastphase = ahc_inb(ahc, LASTPHASE);
651 printf("%s:%c:%d: Missed busfree. "
652 "Lastphase = 0x%x, Curphase = 0x%x\n",
653 ahc_name(ahc), devinfo.channel, devinfo.target,
654 lastphase, ahc_inb(ahc, SCSISIGI));
655 ahc_restart(ahc);
656 return;
657 }
658 case HOST_MSG_LOOP:
659 {
660 /*
661 * The sequencer has encountered a message phase
662 * that requires host assistance for completion.
663 * While handling the message phase(s), we will be
664 * notified by the sequencer after each byte is
665 * transfered so we can track bus phase changes.
666 *
667 * If this is the first time we've seen a HOST_MSG_LOOP
668 * interrupt, initialize the state of the host message
669 * loop.
670 */
671 if (ahc->msg_type == MSG_TYPE_NONE) {
672 struct scb *scb;
673 u_int scb_index;
674 u_int bus_phase;
675
676 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
677 if (bus_phase != P_MESGIN
678 && bus_phase != P_MESGOUT) {
679 printf("ahc_intr: HOST_MSG_LOOP bad "
680 "phase 0x%x\n",
681 bus_phase);
682 /*
683 * Probably transitioned to bus free before
684 * we got here. Just punt the message.
685 */
686 ahc_clear_intstat(ahc);
687 ahc_restart(ahc);
688 return;
689 }
690
691 scb_index = ahc_inb(ahc, SCB_TAG);
692 scb = ahc_lookup_scb(ahc, scb_index);
693 if (devinfo.role == ROLE_INITIATOR) {
694 if (scb == NULL)
695 panic("HOST_MSG_LOOP with "
696 "invalid SCB %x\n", scb_index);
697
698 if (bus_phase == P_MESGOUT)
699 ahc_setup_initiator_msgout(ahc,
700 &devinfo,
701 scb);
702 else {
703 ahc->msg_type =
704 MSG_TYPE_INITIATOR_MSGIN;
705 ahc->msgin_index = 0;
706 }
707 }
708 #ifdef AHC_TARGET_MODE
709 else {
710 if (bus_phase == P_MESGOUT) {
711 ahc->msg_type =
712 MSG_TYPE_TARGET_MSGOUT;
713 ahc->msgin_index = 0;
714 }
715 else
716 ahc_setup_target_msgin(ahc,
717 &devinfo,
718 scb);
719 }
720 #endif
721 }
722
723 ahc_handle_message_phase(ahc);
724 break;
725 }
726 case PERR_DETECTED:
727 {
728 /*
729 * If we've cleared the parity error interrupt
730 * but the sequencer still believes that SCSIPERR
731 * is true, it must be that the parity error is
732 * for the currently presented byte on the bus,
733 * and we are not in a phase (data-in) where we will
734 * eventually ack this byte. Ack the byte and
735 * throw it away in the hope that the target will
736 * take us to message out to deliver the appropriate
737 * error message.
738 */
739 if ((intstat & SCSIINT) == 0
740 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) {
741
742 if ((ahc->features & AHC_DT) == 0) {
743 u_int curphase;
744
745 /*
746 * The hardware will only let you ack bytes
747 * if the expected phase in SCSISIGO matches
748 * the current phase. Make sure this is
749 * currently the case.
750 */
751 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
752 ahc_outb(ahc, LASTPHASE, curphase);
753 ahc_outb(ahc, SCSISIGO, curphase);
754 }
755 if ((ahc_inb(ahc, SCSISIGI) & (CDI|MSGI)) == 0) {
756 int wait;
757
758 /*
759 * In a data phase. Faster to bitbucket
760 * the data than to individually ack each
761 * byte. This is also the only strategy
762 * that will work with AUTOACK enabled.
763 */
764 ahc_outb(ahc, SXFRCTL1,
765 ahc_inb(ahc, SXFRCTL1) | BITBUCKET);
766 wait = 5000;
767 while (--wait != 0) {
768 if ((ahc_inb(ahc, SCSISIGI)
769 & (CDI|MSGI)) != 0)
770 break;
771 ahc_delay(100);
772 }
773 ahc_outb(ahc, SXFRCTL1,
774 ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
775 if (wait == 0) {
776 struct scb *scb;
777 u_int scb_index;
778
779 ahc_print_devinfo(ahc, &devinfo);
780 printf("Unable to clear parity error. "
781 "Resetting bus.\n");
782 scb_index = ahc_inb(ahc, SCB_TAG);
783 scb = ahc_lookup_scb(ahc, scb_index);
784 if (scb != NULL)
785 ahc_set_transaction_status(scb,
786 CAM_UNCOR_PARITY);
787 ahc_reset_channel(ahc, devinfo.channel,
788 /*init reset*/TRUE);
789 }
790 } else {
791 ahc_inb(ahc, SCSIDATL);
792 }
793 }
794 break;
795 }
796 case DATA_OVERRUN:
797 {
798 /*
799 * When the sequencer detects an overrun, it
800 * places the controller in "BITBUCKET" mode
801 * and allows the target to complete its transfer.
802 * Unfortunately, none of the counters get updated
803 * when the controller is in this mode, so we have
804 * no way of knowing how large the overrun was.
805 */
806 u_int scbindex = ahc_inb(ahc, SCB_TAG);
807 u_int lastphase = ahc_inb(ahc, LASTPHASE);
808 u_int i;
809
810 scb = ahc_lookup_scb(ahc, scbindex);
811 for (i = 0; i < num_phases; i++) {
812 if (lastphase == ahc_phase_table[i].phase)
813 break;
814 }
815 ahc_print_path(ahc, scb);
816 printf("data overrun detected %s."
817 " Tag == 0x%x.\n",
818 ahc_phase_table[i].phasemsg,
819 scb->hscb->tag);
820 ahc_print_path(ahc, scb);
821 printf("%s seen Data Phase. Length = %ld. NumSGs = %d.\n",
822 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't",
823 ahc_get_transfer_length(scb), scb->sg_count);
824 if (scb->sg_count > 0) {
825 for (i = 0; i < scb->sg_count; i++) {
826
827 printf("sg[%d] - Addr 0x%x%x : Length %d\n",
828 i,
829 (ahc_le32toh(scb->sg_list[i].len) >> 24
830 & SG_HIGH_ADDR_BITS),
831 ahc_le32toh(scb->sg_list[i].addr),
832 ahc_le32toh(scb->sg_list[i].len)
833 & AHC_SG_LEN_MASK);
834 }
835 }
836 /*
837 * Set this and it will take effect when the
838 * target does a command complete.
839 */
840 ahc_freeze_devq(ahc, scb);
841 if ((scb->flags & SCB_SENSE) == 0) {
842 ahc_set_transaction_status(scb, CAM_DATA_RUN_ERR);
843 } else {
844 scb->flags &= ~SCB_SENSE;
845 ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
846 }
847 ahc_freeze_scb(scb);
848
849 if ((ahc->features & AHC_ULTRA2) != 0) {
850 /*
851 * Clear the channel in case we return
852 * to data phase later.
853 */
854 ahc_outb(ahc, SXFRCTL0,
855 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
856 ahc_outb(ahc, SXFRCTL0,
857 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
858 }
859 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
860 u_int dscommand1;
861
862 /* Ensure HHADDR is 0 for future DMA operations. */
863 dscommand1 = ahc_inb(ahc, DSCOMMAND1);
864 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
865 ahc_outb(ahc, HADDR, 0);
866 ahc_outb(ahc, DSCOMMAND1, dscommand1);
867 }
868 break;
869 }
870 case MKMSG_FAILED:
871 {
872 u_int scbindex;
873
874 printf("%s:%c:%d:%d: Attempt to issue message failed\n",
875 ahc_name(ahc), devinfo.channel, devinfo.target,
876 devinfo.lun);
877 scbindex = ahc_inb(ahc, SCB_TAG);
878 scb = ahc_lookup_scb(ahc, scbindex);
879 if (scb != NULL
880 && (scb->flags & SCB_RECOVERY_SCB) != 0)
881 /*
882 * Ensure that we didn't put a second instance of this
883 * SCB into the QINFIFO.
884 */
885 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
886 SCB_GET_CHANNEL(ahc, scb),
887 SCB_GET_LUN(scb), scb->hscb->tag,
888 ROLE_INITIATOR, /*status*/0,
889 SEARCH_REMOVE);
890 break;
891 }
892 case NO_FREE_SCB:
893 {
894 printf("%s: No free or disconnected SCBs\n", ahc_name(ahc));
895 ahc_dump_card_state(ahc);
896 panic("for safety");
897 break;
898 }
899 case SCB_MISMATCH:
900 {
901 u_int scbptr;
902
903 scbptr = ahc_inb(ahc, SCBPTR);
904 printf("Bogus TAG after DMA. SCBPTR %d, tag %d, our tag %d\n",
905 scbptr, ahc_inb(ahc, ARG_1),
906 ahc->scb_data->hscbs[scbptr].tag);
907 ahc_dump_card_state(ahc);
908 panic("for saftey");
909 break;
910 }
911 case OUT_OF_RANGE:
912 {
913 printf("%s: BTT calculation out of range\n", ahc_name(ahc));
914 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
915 "ARG_1 == 0x%x ACCUM = 0x%x\n",
916 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
917 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
918 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
919 "SINDEX == 0x%x\n, A == 0x%x\n",
920 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
921 ahc_index_busy_tcl(ahc,
922 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
923 ahc_inb(ahc, SAVED_LUN))),
924 ahc_inb(ahc, SINDEX),
925 ahc_inb(ahc, ACCUM));
926 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
927 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
928 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
929 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
930 ahc_inb(ahc, SCB_CONTROL));
931 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
932 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
933 ahc_dump_card_state(ahc);
934 panic("for safety");
935 break;
936 }
937 default:
938 printf("ahc_intr: seqint, "
939 "intstat == 0x%x, scsisigi = 0x%x\n",
940 intstat, ahc_inb(ahc, SCSISIGI));
941 break;
942 }
943 unpause:
944 /*
945 * The sequencer is paused immediately on
946 * a SEQINT, so we should restart it when
947 * we're done.
948 */
949 ahc_unpause(ahc);
950 }
951
952 void
953 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat)
954 {
955 u_int scb_index;
956 u_int status0;
957 u_int status;
958 struct scb *scb;
959 char cur_channel;
960 char intr_channel;
961
962 if ((ahc->features & AHC_TWIN) != 0
963 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0))
964 cur_channel = 'B';
965 else
966 cur_channel = 'A';
967 intr_channel = cur_channel;
968
969 if ((ahc->features & AHC_ULTRA2) != 0)
970 status0 = ahc_inb(ahc, SSTAT0) & IOERR;
971 else
972 status0 = 0;
973 status = ahc_inb(ahc, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
974 if (status == 0 && status0 == 0) {
975 if ((ahc->features & AHC_TWIN) != 0) {
976 /* Try the other channel */
977 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
978 status = ahc_inb(ahc, SSTAT1)
979 & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
980 intr_channel = (cur_channel == 'A') ? 'B' : 'A';
981 }
982 if (status == 0) {
983 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc));
984 ahc_outb(ahc, CLRINT, CLRSCSIINT);
985 ahc_unpause(ahc);
986 return;
987 }
988 }
989
990 /* Make sure the sequencer is in a safe location. */
991 ahc_clear_critical_section(ahc);
992
993 scb_index = ahc_inb(ahc, SCB_TAG);
994 scb = ahc_lookup_scb(ahc, scb_index);
995 if (scb != NULL
996 && (ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) != 0)
997 scb = NULL;
998
999 if ((ahc->features & AHC_ULTRA2) != 0
1000 && (status0 & IOERR) != 0) {
1001 int now_lvd;
1002
1003 now_lvd = ahc_inb(ahc, SBLKCTL) & ENAB40;
1004 printf("%s: Transceiver State Has Changed to %s mode\n",
1005 ahc_name(ahc), now_lvd ? "LVD" : "SE");
1006 ahc_outb(ahc, CLRSINT0, CLRIOERR);
1007 /*
1008 * When transitioning to SE mode, the reset line
1009 * glitches, triggering an arbitration bug in some
1010 * Ultra2 controllers. This bug is cleared when we
1011 * assert the reset line. Since a reset glitch has
1012 * already occurred with this transition and a
1013 * transceiver state change is handled just like
1014 * a bus reset anyway, asserting the reset line
1015 * ourselves is safe.
1016 */
1017 ahc_reset_channel(ahc, intr_channel,
1018 /*Initiate Reset*/now_lvd == 0);
1019 } else if ((status & SCSIRSTI) != 0) {
1020 printf("%s: Someone reset channel %c\n",
1021 ahc_name(ahc), intr_channel);
1022 if (intr_channel != cur_channel)
1023 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
1024 ahc_reset_channel(ahc, intr_channel, /*Initiate Reset*/FALSE);
1025 } else if ((status & SCSIPERR) != 0) {
1026 /*
1027 * Determine the bus phase and queue an appropriate message.
1028 * SCSIPERR is latched true as soon as a parity error
1029 * occurs. If the sequencer acked the transfer that
1030 * caused the parity error and the currently presented
1031 * transfer on the bus has correct parity, SCSIPERR will
1032 * be cleared by CLRSCSIPERR. Use this to determine if
1033 * we should look at the last phase the sequencer recorded,
1034 * or the current phase presented on the bus.
1035 */
1036 struct ahc_devinfo devinfo;
1037 u_int mesg_out;
1038 u_int curphase;
1039 u_int errorphase;
1040 u_int lastphase;
1041 u_int scsirate;
1042 u_int i;
1043 u_int sstat2;
1044 int silent;
1045
1046 lastphase = ahc_inb(ahc, LASTPHASE);
1047 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
1048 sstat2 = ahc_inb(ahc, SSTAT2);
1049 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR);
1050 /*
1051 * For all phases save DATA, the sequencer won't
1052 * automatically ack a byte that has a parity error
1053 * in it. So the only way that the current phase
1054 * could be 'data-in' is if the parity error is for
1055 * an already acked byte in the data phase. During
1056 * synchronous data-in transfers, we may actually
1057 * ack bytes before latching the current phase in
1058 * LASTPHASE, leading to the discrepancy between
1059 * curphase and lastphase.
1060 */
1061 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0
1062 || curphase == P_DATAIN || curphase == P_DATAIN_DT)
1063 errorphase = curphase;
1064 else
1065 errorphase = lastphase;
1066
1067 for (i = 0; i < num_phases; i++) {
1068 if (errorphase == ahc_phase_table[i].phase)
1069 break;
1070 }
1071 mesg_out = ahc_phase_table[i].mesg_out;
1072 silent = FALSE;
1073 if (scb != NULL) {
1074 if (SCB_IS_SILENT(scb))
1075 silent = TRUE;
1076 else
1077 ahc_print_path(ahc, scb);
1078 scb->flags |= SCB_TRANSMISSION_ERROR;
1079 } else
1080 printf("%s:%c:%d: ", ahc_name(ahc), intr_channel,
1081 SCSIID_TARGET(ahc, ahc_inb(ahc, SAVED_SCSIID)));
1082 scsirate = ahc_inb(ahc, SCSIRATE);
1083 if (silent == FALSE) {
1084 printf("parity error detected %s. "
1085 "SEQADDR(0x%x) SCSIRATE(0x%x)\n",
1086 ahc_phase_table[i].phasemsg,
1087 ahc_inw(ahc, SEQADDR0),
1088 scsirate);
1089 if ((ahc->features & AHC_DT) != 0) {
1090 if ((sstat2 & CRCVALERR) != 0)
1091 printf("\tCRC Value Mismatch\n");
1092 if ((sstat2 & CRCENDERR) != 0)
1093 printf("\tNo terminal CRC packet "
1094 "recevied\n");
1095 if ((sstat2 & CRCREQERR) != 0)
1096 printf("\tIllegal CRC packet "
1097 "request\n");
1098 if ((sstat2 & DUAL_EDGE_ERR) != 0)
1099 printf("\tUnexpected %sDT Data Phase\n",
1100 (scsirate & SINGLE_EDGE)
1101 ? "" : "non-");
1102 }
1103 }
1104
1105 if ((ahc->features & AHC_DT) != 0
1106 && (sstat2 & DUAL_EDGE_ERR) != 0) {
1107 /*
1108 * This error applies regardless of
1109 * data direction, so ignore the value
1110 * in the phase table.
1111 */
1112 mesg_out = MSG_INITIATOR_DET_ERR;
1113 }
1114
1115 /*
1116 * We've set the hardware to assert ATN if we
1117 * get a parity error on "in" phases, so all we
1118 * need to do is stuff the message buffer with
1119 * the appropriate message. "In" phases have set
1120 * mesg_out to something other than MSG_NOP.
1121 */
1122 if (mesg_out != MSG_NOOP) {
1123 if (ahc->msg_type != MSG_TYPE_NONE)
1124 ahc->send_msg_perror = TRUE;
1125 else
1126 ahc_outb(ahc, MSG_OUT, mesg_out);
1127 }
1128 /*
1129 * Force a renegotiation with this target just in
1130 * case we are out of sync for some external reason
1131 * unknown (or unreported) by the target.
1132 */
1133 ahc_fetch_devinfo(ahc, &devinfo);
1134 ahc_force_renegotiation(ahc, &devinfo);
1135
1136 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1137 ahc_unpause(ahc);
1138 } else if ((status & SELTO) != 0) {
1139 u_int scbptr;
1140
1141 /* Stop the selection */
1142 ahc_outb(ahc, SCSISEQ, 0);
1143
1144 /* No more pending messages */
1145 ahc_clear_msg_state(ahc);
1146
1147 /* Clear interrupt state */
1148 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
1149 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR);
1150
1151 /*
1152 * Although the driver does not care about the
1153 * 'Selection in Progress' status bit, the busy
1154 * LED does. SELINGO is only cleared by a sucessfull
1155 * selection, so we must manually clear it to insure
1156 * the LED turns off just incase no future successful
1157 * selections occur (e.g. no devices on the bus).
1158 */
1159 ahc_outb(ahc, CLRSINT0, CLRSELINGO);
1160
1161 scbptr = ahc_inb(ahc, WAITING_SCBH);
1162 ahc_outb(ahc, SCBPTR, scbptr);
1163 scb_index = ahc_inb(ahc, SCB_TAG);
1164
1165 scb = ahc_lookup_scb(ahc, scb_index);
1166 if (scb == NULL) {
1167 printf("%s: ahc_intr - referenced scb not "
1168 "valid during SELTO scb(%d, %d)\n",
1169 ahc_name(ahc), scbptr, scb_index);
1170 ahc_dump_card_state(ahc);
1171 } else {
1172 struct ahc_devinfo devinfo;
1173 #ifdef AHC_DEBUG
1174 if ((ahc_debug & AHC_SHOW_SELTO) != 0) {
1175 ahc_print_path(ahc, scb);
1176 printf("Saw Selection Timeout for SCB 0x%x\n",
1177 scb_index);
1178 }
1179 #endif
1180 /*
1181 * Force a renegotiation with this target just in
1182 * case the cable was pulled and will later be
1183 * re-attached. The target may forget its negotiation
1184 * settings with us should it attempt to reselect
1185 * during the interruption. The target will not issue
1186 * a unit attention in this case, so we must always
1187 * renegotiate.
1188 */
1189 ahc_scb_devinfo(ahc, &devinfo, scb);
1190 ahc_force_renegotiation(ahc, &devinfo);
1191 ahc_set_transaction_status(scb, CAM_SEL_TIMEOUT);
1192 ahc_freeze_devq(ahc, scb);
1193 }
1194 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1195 ahc_restart(ahc);
1196 } else if ((status & BUSFREE) != 0
1197 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) {
1198 struct ahc_devinfo devinfo;
1199 u_int lastphase;
1200 u_int saved_scsiid;
1201 u_int saved_lun;
1202 u_int target;
1203 u_int initiator_role_id;
1204 char channel;
1205 int printerror;
1206
1207 /*
1208 * Clear our selection hardware as soon as possible.
1209 * We may have an entry in the waiting Q for this target,
1210 * that is affected by this busfree and we don't want to
1211 * go about selecting the target while we handle the event.
1212 */
1213 ahc_outb(ahc, SCSISEQ,
1214 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
1215
1216 /*
1217 * Disable busfree interrupts and clear the busfree
1218 * interrupt status. We do this here so that several
1219 * bus transactions occur prior to clearing the SCSIINT
1220 * latch. It can take a bit for the clearing to take effect.
1221 */
1222 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
1223 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR);
1224
1225 /*
1226 * Look at what phase we were last in.
1227 * If its message out, chances are pretty good
1228 * that the busfree was in response to one of
1229 * our abort requests.
1230 */
1231 lastphase = ahc_inb(ahc, LASTPHASE);
1232 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
1233 saved_lun = ahc_inb(ahc, SAVED_LUN);
1234 target = SCSIID_TARGET(ahc, saved_scsiid);
1235 initiator_role_id = SCSIID_OUR_ID(saved_scsiid);
1236 channel = SCSIID_CHANNEL(ahc, saved_scsiid);
1237 ahc_compile_devinfo(&devinfo, initiator_role_id,
1238 target, saved_lun, channel, ROLE_INITIATOR);
1239 printerror = 1;
1240
1241 if (lastphase == P_MESGOUT) {
1242 u_int tag;
1243
1244 tag = SCB_LIST_NULL;
1245 if (ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT_TAG, TRUE)
1246 || ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT, TRUE)) {
1247 if (ahc->msgout_buf[ahc->msgout_index - 1]
1248 == MSG_ABORT_TAG)
1249 tag = scb->hscb->tag;
1250 ahc_print_path(ahc, scb);
1251 printf("SCB %d - Abort%s Completed.\n",
1252 scb->hscb->tag, tag == SCB_LIST_NULL ?
1253 "" : " Tag");
1254 ahc_abort_scbs(ahc, target, channel,
1255 saved_lun, tag,
1256 ROLE_INITIATOR,
1257 CAM_REQ_ABORTED);
1258 printerror = 0;
1259 } else if (ahc_sent_msg(ahc, AHCMSG_1B,
1260 MSG_BUS_DEV_RESET, TRUE)) {
1261 #ifdef __FreeBSD__
1262 /*
1263 * Don't mark the user's request for this BDR
1264 * as completing with CAM_BDR_SENT. CAM3
1265 * specifies CAM_REQ_CMP.
1266 */
1267 if (scb != NULL
1268 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV
1269 && ahc_match_scb(ahc, scb, target, channel,
1270 CAM_LUN_WILDCARD,
1271 SCB_LIST_NULL,
1272 ROLE_INITIATOR)) {
1273 ahc_set_transaction_status(scb, CAM_REQ_CMP);
1274 }
1275 #endif
1276 ahc_compile_devinfo(&devinfo,
1277 initiator_role_id,
1278 target,
1279 CAM_LUN_WILDCARD,
1280 channel,
1281 ROLE_INITIATOR);
1282 ahc_handle_devreset(ahc, &devinfo,
1283 CAM_BDR_SENT,
1284 "Bus Device Reset",
1285 /*verbose_level*/0);
1286 printerror = 0;
1287 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1288 MSG_EXT_PPR, FALSE)) {
1289 struct ahc_initiator_tinfo *tinfo;
1290 struct ahc_tmode_tstate *tstate;
1291
1292 /*
1293 * PPR Rejected. Try non-ppr negotiation
1294 * and retry command.
1295 */
1296 tinfo = ahc_fetch_transinfo(ahc,
1297 devinfo.channel,
1298 devinfo.our_scsiid,
1299 devinfo.target,
1300 &tstate);
1301 tinfo->curr.transport_version = 2;
1302 tinfo->goal.transport_version = 2;
1303 tinfo->goal.ppr_options = 0;
1304 ahc_qinfifo_requeue_tail(ahc, scb);
1305 printerror = 0;
1306 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1307 MSG_EXT_WDTR, FALSE)) {
1308 /*
1309 * Negotiation Rejected. Go-narrow and
1310 * retry command.
1311 */
1312 ahc_set_width(ahc, &devinfo,
1313 MSG_EXT_WDTR_BUS_8_BIT,
1314 AHC_TRANS_CUR|AHC_TRANS_GOAL,
1315 /*paused*/TRUE);
1316 ahc_qinfifo_requeue_tail(ahc, scb);
1317 printerror = 0;
1318 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1319 MSG_EXT_SDTR, FALSE)) {
1320 /*
1321 * Negotiation Rejected. Go-async and
1322 * retry command.
1323 */
1324 ahc_set_syncrate(ahc, &devinfo,
1325 /*syncrate*/NULL,
1326 /*period*/0, /*offset*/0,
1327 /*ppr_options*/0,
1328 AHC_TRANS_CUR|AHC_TRANS_GOAL,
1329 /*paused*/TRUE);
1330 ahc_qinfifo_requeue_tail(ahc, scb);
1331 printerror = 0;
1332 }
1333 }
1334 if (printerror != 0) {
1335 u_int i;
1336
1337 if (scb != NULL) {
1338 u_int tag;
1339
1340 if ((scb->hscb->control & TAG_ENB) != 0)
1341 tag = scb->hscb->tag;
1342 else
1343 tag = SCB_LIST_NULL;
1344 ahc_print_path(ahc, scb);
1345 ahc_abort_scbs(ahc, target, channel,
1346 SCB_GET_LUN(scb), tag,
1347 ROLE_INITIATOR,
1348 CAM_UNEXP_BUSFREE);
1349 } else {
1350 /*
1351 * We had not fully identified this connection,
1352 * so we cannot abort anything.
1353 */
1354 printf("%s: ", ahc_name(ahc));
1355 }
1356 for (i = 0; i < num_phases; i++) {
1357 if (lastphase == ahc_phase_table[i].phase)
1358 break;
1359 }
1360 if (lastphase != P_BUSFREE) {
1361 /*
1362 * Renegotiate with this device at the
1363 * next oportunity just in case this busfree
1364 * is due to a negotiation mismatch with the
1365 * device.
1366 */
1367 ahc_force_renegotiation(ahc, &devinfo);
1368 }
1369 printf("Unexpected busfree %s\n"
1370 "SEQADDR == 0x%x\n",
1371 ahc_phase_table[i].phasemsg,
1372 ahc_inb(ahc, SEQADDR0)
1373 | (ahc_inb(ahc, SEQADDR1) << 8));
1374 }
1375 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1376 ahc_restart(ahc);
1377 } else {
1378 printf("%s: Missing case in ahc_handle_scsiint. status = %x\n",
1379 ahc_name(ahc), status);
1380 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1381 }
1382 }
1383
1384 /*
1385 * Force renegotiation to occur the next time we initiate
1386 * a command to the current device.
1387 */
1388 static void
1389 ahc_force_renegotiation(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
1390 {
1391 struct ahc_initiator_tinfo *targ_info;
1392 struct ahc_tmode_tstate *tstate;
1393
1394 targ_info = ahc_fetch_transinfo(ahc,
1395 devinfo->channel,
1396 devinfo->our_scsiid,
1397 devinfo->target,
1398 &tstate);
1399 ahc_update_neg_request(ahc, devinfo, tstate,
1400 targ_info, AHC_NEG_IF_NON_ASYNC);
1401 }
1402
1403 #define AHC_MAX_STEPS 2000
1404 void
1405 ahc_clear_critical_section(struct ahc_softc *ahc)
1406 {
1407 int stepping;
1408 int steps;
1409 u_int simode0;
1410 u_int simode1;
1411
1412 if (ahc->num_critical_sections == 0)
1413 return;
1414
1415 stepping = FALSE;
1416 steps = 0;
1417 simode0 = 0;
1418 simode1 = 0;
1419 for (;;) {
1420 struct cs *cs;
1421 u_int seqaddr;
1422 u_int i;
1423
1424 seqaddr = ahc_inb(ahc, SEQADDR0)
1425 | (ahc_inb(ahc, SEQADDR1) << 8);
1426
1427 /*
1428 * Seqaddr represents the next instruction to execute,
1429 * so we are really executing the instruction just
1430 * before it.
1431 */
1432 if (seqaddr != 0)
1433 seqaddr -= 1;
1434 cs = ahc->critical_sections;
1435 for (i = 0; i < ahc->num_critical_sections; i++, cs++) {
1436
1437 if (cs->begin < seqaddr && cs->end >= seqaddr)
1438 break;
1439 }
1440
1441 if (i == ahc->num_critical_sections)
1442 break;
1443
1444 if (steps > AHC_MAX_STEPS) {
1445 printf("%s: Infinite loop in critical section\n",
1446 ahc_name(ahc));
1447 ahc_dump_card_state(ahc);
1448 panic("critical section loop");
1449 }
1450
1451 steps++;
1452 if (stepping == FALSE) {
1453
1454 /*
1455 * Disable all interrupt sources so that the
1456 * sequencer will not be stuck by a pausing
1457 * interrupt condition while we attempt to
1458 * leave a critical section.
1459 */
1460 simode0 = ahc_inb(ahc, SIMODE0);
1461 ahc_outb(ahc, SIMODE0, 0);
1462 simode1 = ahc_inb(ahc, SIMODE1);
1463 if ((ahc->features & AHC_DT) != 0)
1464 /*
1465 * On DT class controllers, we
1466 * use the enhanced busfree logic.
1467 * Unfortunately we cannot re-enable
1468 * busfree detection within the
1469 * current connection, so we must
1470 * leave it on while single stepping.
1471 */
1472 ahc_outb(ahc, SIMODE1, simode1 & ENBUSFREE);
1473 else
1474 ahc_outb(ahc, SIMODE1, 0);
1475 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1476 ahc_outb(ahc, SEQCTL, ahc->seqctl | STEP);
1477 stepping = TRUE;
1478 }
1479 if ((ahc->features & AHC_DT) != 0) {
1480 ahc_outb(ahc, CLRSINT1, CLRBUSFREE);
1481 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1482 }
1483 ahc_outb(ahc, HCNTRL, ahc->unpause);
1484 while (!ahc_is_paused(ahc))
1485 ahc_delay(200);
1486 }
1487 if (stepping) {
1488 ahc_outb(ahc, SIMODE0, simode0);
1489 ahc_outb(ahc, SIMODE1, simode1);
1490 ahc_outb(ahc, SEQCTL, ahc->seqctl);
1491 }
1492 }
1493
1494 /*
1495 * Clear any pending interrupt status.
1496 */
1497 void
1498 ahc_clear_intstat(struct ahc_softc *ahc)
1499 {
1500 /* Clear any interrupt conditions this may have caused */
1501 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI
1502 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG|
1503 CLRREQINIT);
1504 ahc_flush_device_writes(ahc);
1505 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO);
1506 ahc_flush_device_writes(ahc);
1507 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1508 ahc_flush_device_writes(ahc);
1509 }
1510
1511 /**************************** Debugging Routines ******************************/
1512 #ifdef AHC_DEBUG
1513 uint32_t ahc_debug = AHC_DEBUG_OPTS;
1514 #endif
1515
1516 void
1517 ahc_print_scb(struct scb *scb)
1518 {
1519 int i;
1520
1521 struct hardware_scb *hscb = scb->hscb;
1522
1523 printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n",
1524 (void *)scb,
1525 hscb->control,
1526 hscb->scsiid,
1527 hscb->lun,
1528 hscb->cdb_len);
1529 printf("Shared Data: ");
1530 for (i = 0; i < sizeof(hscb->shared_data.cdb); i++)
1531 printf("%#02x", hscb->shared_data.cdb[i]);
1532 printf(" dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n",
1533 ahc_le32toh(hscb->dataptr),
1534 ahc_le32toh(hscb->datacnt),
1535 ahc_le32toh(hscb->sgptr),
1536 hscb->tag);
1537 if (scb->sg_count > 0) {
1538 for (i = 0; i < scb->sg_count; i++) {
1539 printf("sg[%d] - Addr 0x%x%x : Length %d\n",
1540 i,
1541 (ahc_le32toh(scb->sg_list[i].len) >> 24
1542 & SG_HIGH_ADDR_BITS),
1543 ahc_le32toh(scb->sg_list[i].addr),
1544 ahc_le32toh(scb->sg_list[i].len));
1545 }
1546 }
1547 }
1548
1549 /************************* Transfer Negotiation *******************************/
1550 /*
1551 * Allocate per target mode instance (ID we respond to as a target)
1552 * transfer negotiation data structures.
1553 */
1554 static struct ahc_tmode_tstate *
1555 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel)
1556 {
1557 struct ahc_tmode_tstate *master_tstate;
1558 struct ahc_tmode_tstate *tstate;
1559 int i;
1560
1561 master_tstate = ahc->enabled_targets[ahc->our_id];
1562 if (channel == 'B') {
1563 scsi_id += 8;
1564 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8];
1565 }
1566 if (ahc->enabled_targets[scsi_id] != NULL
1567 && ahc->enabled_targets[scsi_id] != master_tstate)
1568 panic("%s: ahc_alloc_tstate - Target already allocated",
1569 ahc_name(ahc));
1570 tstate = (struct ahc_tmode_tstate*)malloc(sizeof(*tstate),
1571 M_DEVBUF, M_NOWAIT);
1572 if (tstate == NULL)
1573 return (NULL);
1574
1575 /*
1576 * If we have allocated a master tstate, copy user settings from
1577 * the master tstate (taken from SRAM or the EEPROM) for this
1578 * channel, but reset our current and goal settings to async/narrow
1579 * until an initiator talks to us.
1580 */
1581 if (master_tstate != NULL) {
1582 memcpy(tstate, master_tstate, sizeof(*tstate));
1583 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns));
1584 tstate->ultraenb = 0;
1585 for (i = 0; i < AHC_NUM_TARGETS; i++) {
1586 memset(&tstate->transinfo[i].curr, 0,
1587 sizeof(tstate->transinfo[i].curr));
1588 memset(&tstate->transinfo[i].goal, 0,
1589 sizeof(tstate->transinfo[i].goal));
1590 }
1591 } else
1592 memset(tstate, 0, sizeof(*tstate));
1593 ahc->enabled_targets[scsi_id] = tstate;
1594 return (tstate);
1595 }
1596
1597 #ifdef AHC_TARGET_MODE
1598 /*
1599 * Free per target mode instance (ID we respond to as a target)
1600 * transfer negotiation data structures.
1601 */
1602 static void
1603 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force)
1604 {
1605 struct ahc_tmode_tstate *tstate;
1606
1607 /*
1608 * Don't clean up our "master" tstate.
1609 * It has our default user settings.
1610 */
1611 if (((channel == 'B' && scsi_id == ahc->our_id_b)
1612 || (channel == 'A' && scsi_id == ahc->our_id))
1613 && force == FALSE)
1614 return;
1615
1616 if (channel == 'B')
1617 scsi_id += 8;
1618 tstate = ahc->enabled_targets[scsi_id];
1619 if (tstate != NULL)
1620 free(tstate, M_DEVBUF);
1621 ahc->enabled_targets[scsi_id] = NULL;
1622 }
1623 #endif
1624
1625 /*
1626 * Called when we have an active connection to a target on the bus,
1627 * this function finds the nearest syncrate to the input period limited
1628 * by the capabilities of the bus connectivity of and sync settings for
1629 * the target.
1630 */
1631 struct ahc_syncrate *
1632 ahc_devlimited_syncrate(struct ahc_softc *ahc,
1633 struct ahc_initiator_tinfo *tinfo,
1634 u_int *period, u_int *ppr_options, role_t role)
1635 {
1636 struct ahc_transinfo *transinfo;
1637 u_int maxsync;
1638
1639 if ((ahc->features & AHC_ULTRA2) != 0) {
1640 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0
1641 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) {
1642 maxsync = AHC_SYNCRATE_DT;
1643 } else {
1644 maxsync = AHC_SYNCRATE_ULTRA;
1645 /* Can't do DT on an SE bus */
1646 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1647 }
1648 } else if ((ahc->features & AHC_ULTRA) != 0) {
1649 maxsync = AHC_SYNCRATE_ULTRA;
1650 } else {
1651 maxsync = AHC_SYNCRATE_FAST;
1652 }
1653 /*
1654 * Never allow a value higher than our current goal
1655 * period otherwise we may allow a target initiated
1656 * negotiation to go above the limit as set by the
1657 * user. In the case of an initiator initiated
1658 * sync negotiation, we limit based on the user
1659 * setting. This allows the system to still accept
1660 * incoming negotiations even if target initiated
1661 * negotiation is not performed.
1662 */
1663 if (role == ROLE_TARGET)
1664 transinfo = &tinfo->user;
1665 else
1666 transinfo = &tinfo->goal;
1667 *ppr_options &= transinfo->ppr_options;
1668 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) {
1669 maxsync = MAX(maxsync, AHC_SYNCRATE_ULTRA2);
1670 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1671 }
1672 if (transinfo->period == 0) {
1673 *period = 0;
1674 *ppr_options = 0;
1675 return (NULL);
1676 }
1677 *period = MAX(*period, transinfo->period);
1678 return (ahc_find_syncrate(ahc, period, ppr_options, maxsync));
1679 }
1680
1681 /*
1682 * Look up the valid period to SCSIRATE conversion in our table.
1683 * Return the period and offset that should be sent to the target
1684 * if this was the beginning of an SDTR.
1685 */
1686 struct ahc_syncrate *
1687 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period,
1688 u_int *ppr_options, u_int maxsync)
1689 {
1690 struct ahc_syncrate *syncrate;
1691
1692 if ((ahc->features & AHC_DT) == 0)
1693 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1694
1695 /* Skip all DT only entries if DT is not available */
1696 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0
1697 && maxsync < AHC_SYNCRATE_ULTRA2)
1698 maxsync = AHC_SYNCRATE_ULTRA2;
1699
1700 for (syncrate = &ahc_syncrates[maxsync];
1701 syncrate->rate != NULL;
1702 syncrate++) {
1703
1704 /*
1705 * The Ultra2 table doesn't go as low
1706 * as for the Fast/Ultra cards.
1707 */
1708 if ((ahc->features & AHC_ULTRA2) != 0
1709 && (syncrate->sxfr_u2 == 0))
1710 break;
1711
1712 if (*period <= syncrate->period) {
1713 /*
1714 * When responding to a target that requests
1715 * sync, the requested rate may fall between
1716 * two rates that we can output, but still be
1717 * a rate that we can receive. Because of this,
1718 * we want to respond to the target with
1719 * the same rate that it sent to us even
1720 * if the period we use to send data to it
1721 * is lower. Only lower the response period
1722 * if we must.
1723 */
1724 if (syncrate == &ahc_syncrates[maxsync])
1725 *period = syncrate->period;
1726
1727 /*
1728 * At some speeds, we only support
1729 * ST transfers.
1730 */
1731 if ((syncrate->sxfr_u2 & ST_SXFR) != 0)
1732 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1733 break;
1734 }
1735 }
1736
1737 if ((*period == 0)
1738 || (syncrate->rate == NULL)
1739 || ((ahc->features & AHC_ULTRA2) != 0
1740 && (syncrate->sxfr_u2 == 0))) {
1741 /* Use asynchronous transfers. */
1742 *period = 0;
1743 syncrate = NULL;
1744 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1745 }
1746 return (syncrate);
1747 }
1748
1749 /*
1750 * Convert from an entry in our syncrate table to the SCSI equivalent
1751 * sync "period" factor.
1752 */
1753 u_int
1754 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync)
1755 {
1756 struct ahc_syncrate *syncrate;
1757
1758 if ((ahc->features & AHC_ULTRA2) != 0)
1759 scsirate &= SXFR_ULTRA2;
1760 else
1761 scsirate &= SXFR;
1762
1763 syncrate = &ahc_syncrates[maxsync];
1764 while (syncrate->rate != NULL) {
1765
1766 if ((ahc->features & AHC_ULTRA2) != 0) {
1767 if (syncrate->sxfr_u2 == 0)
1768 break;
1769 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2))
1770 return (syncrate->period);
1771 } else if (scsirate == (syncrate->sxfr & SXFR)) {
1772 return (syncrate->period);
1773 }
1774 syncrate++;
1775 }
1776 return (0); /* async */
1777 }
1778
1779 /*
1780 * Truncate the given synchronous offset to a value the
1781 * current adapter type and syncrate are capable of.
1782 */
1783 void
1784 ahc_validate_offset(struct ahc_softc *ahc,
1785 struct ahc_initiator_tinfo *tinfo,
1786 struct ahc_syncrate *syncrate,
1787 u_int *offset, int wide, role_t role)
1788 {
1789 u_int maxoffset;
1790
1791 /* Limit offset to what we can do */
1792 if (syncrate == NULL) {
1793 maxoffset = 0;
1794 } else if ((ahc->features & AHC_ULTRA2) != 0) {
1795 maxoffset = MAX_OFFSET_ULTRA2;
1796 } else {
1797 if (wide)
1798 maxoffset = MAX_OFFSET_16BIT;
1799 else
1800 maxoffset = MAX_OFFSET_8BIT;
1801 }
1802 *offset = MIN(*offset, maxoffset);
1803 if (tinfo != NULL) {
1804 if (role == ROLE_TARGET)
1805 *offset = MIN(*offset, tinfo->user.offset);
1806 else
1807 *offset = MIN(*offset, tinfo->goal.offset);
1808 }
1809 }
1810
1811 /*
1812 * Truncate the given transfer width parameter to a value the
1813 * current adapter type is capable of.
1814 */
1815 void
1816 ahc_validate_width(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo,
1817 u_int *bus_width, role_t role)
1818 {
1819 switch (*bus_width) {
1820 default:
1821 if (ahc->features & AHC_WIDE) {
1822 /* Respond Wide */
1823 *bus_width = MSG_EXT_WDTR_BUS_16_BIT;
1824 break;
1825 }
1826 /* FALLTHROUGH */
1827 case MSG_EXT_WDTR_BUS_8_BIT:
1828 *bus_width = MSG_EXT_WDTR_BUS_8_BIT;
1829 break;
1830 }
1831 if (tinfo != NULL) {
1832 if (role == ROLE_TARGET)
1833 *bus_width = MIN(tinfo->user.width, *bus_width);
1834 else
1835 *bus_width = MIN(tinfo->goal.width, *bus_width);
1836 }
1837 }
1838
1839 /*
1840 * Update the bitmask of targets for which the controller should
1841 * negotiate with at the next convenient oportunity. This currently
1842 * means the next time we send the initial identify messages for
1843 * a new transaction.
1844 */
1845 int
1846 ahc_update_neg_request(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
1847 struct ahc_tmode_tstate *tstate,
1848 struct ahc_initiator_tinfo *tinfo, ahc_neg_type neg_type)
1849 {
1850 u_int auto_negotiate_orig;
1851
1852 auto_negotiate_orig = tstate->auto_negotiate;
1853 if (neg_type == AHC_NEG_ALWAYS) {
1854 /*
1855 * Force our "current" settings to be
1856 * unknown so that unless a bus reset
1857 * occurs the need to renegotiate is
1858 * recorded persistently.
1859 */
1860 if ((ahc->features & AHC_WIDE) != 0)
1861 tinfo->curr.width = AHC_WIDTH_UNKNOWN;
1862 tinfo->curr.period = AHC_PERIOD_UNKNOWN;
1863 tinfo->curr.offset = AHC_OFFSET_UNKNOWN;
1864 }
1865 if (tinfo->curr.period != tinfo->goal.period
1866 || tinfo->curr.width != tinfo->goal.width
1867 || tinfo->curr.offset != tinfo->goal.offset
1868 || tinfo->curr.ppr_options != tinfo->goal.ppr_options
1869 || (neg_type == AHC_NEG_IF_NON_ASYNC
1870 && (tinfo->goal.offset != 0
1871 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT
1872 || tinfo->goal.ppr_options != 0)))
1873 tstate->auto_negotiate |= devinfo->target_mask;
1874 else
1875 tstate->auto_negotiate &= ~devinfo->target_mask;
1876
1877 return (auto_negotiate_orig != tstate->auto_negotiate);
1878 }
1879
1880 /*
1881 * Update the user/goal/curr tables of synchronous negotiation
1882 * parameters as well as, in the case of a current or active update,
1883 * any data structures on the host controller. In the case of an
1884 * active update, the specified target is currently talking to us on
1885 * the bus, so the transfer parameter update must take effect
1886 * immediately.
1887 */
1888 void
1889 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
1890 struct ahc_syncrate *syncrate, u_int period,
1891 u_int offset, u_int ppr_options, u_int type, int paused)
1892 {
1893 struct ahc_initiator_tinfo *tinfo;
1894 struct ahc_tmode_tstate *tstate;
1895 u_int old_period;
1896 u_int old_offset;
1897 u_int old_ppr;
1898 int active;
1899 int update_needed;
1900
1901 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
1902 update_needed = 0;
1903
1904 if (syncrate == NULL) {
1905 period = 0;
1906 offset = 0;
1907 }
1908
1909 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
1910 devinfo->target, &tstate);
1911
1912 if ((type & AHC_TRANS_USER) != 0) {
1913 tinfo->user.period = period;
1914 tinfo->user.offset = offset;
1915 tinfo->user.ppr_options = ppr_options;
1916 }
1917
1918 if ((type & AHC_TRANS_GOAL) != 0) {
1919 tinfo->goal.period = period;
1920 tinfo->goal.offset = offset;
1921 tinfo->goal.ppr_options = ppr_options;
1922 }
1923
1924 old_period = tinfo->curr.period;
1925 old_offset = tinfo->curr.offset;
1926 old_ppr = tinfo->curr.ppr_options;
1927
1928 if ((type & AHC_TRANS_CUR) != 0
1929 && (old_period != period
1930 || old_offset != offset
1931 || old_ppr != ppr_options)) {
1932 u_int scsirate;
1933
1934 update_needed++;
1935 scsirate = tinfo->scsirate;
1936 if ((ahc->features & AHC_ULTRA2) != 0) {
1937
1938 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC);
1939 if (syncrate != NULL) {
1940 scsirate |= syncrate->sxfr_u2;
1941 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0)
1942 scsirate |= ENABLE_CRC;
1943 else
1944 scsirate |= SINGLE_EDGE;
1945 }
1946 } else {
1947
1948 scsirate &= ~(SXFR|SOFS);
1949 /*
1950 * Ensure Ultra mode is set properly for
1951 * this target.
1952 */
1953 tstate->ultraenb &= ~devinfo->target_mask;
1954 if (syncrate != NULL) {
1955 if (syncrate->sxfr & ULTRA_SXFR) {
1956 tstate->ultraenb |=
1957 devinfo->target_mask;
1958 }
1959 scsirate |= syncrate->sxfr & SXFR;
1960 scsirate |= offset & SOFS;
1961 }
1962 if (active) {
1963 u_int sxfrctl0;
1964
1965 sxfrctl0 = ahc_inb(ahc, SXFRCTL0);
1966 sxfrctl0 &= ~FAST20;
1967 if (tstate->ultraenb & devinfo->target_mask)
1968 sxfrctl0 |= FAST20;
1969 ahc_outb(ahc, SXFRCTL0, sxfrctl0);
1970 }
1971 }
1972 if (active) {
1973 ahc_outb(ahc, SCSIRATE, scsirate);
1974 if ((ahc->features & AHC_ULTRA2) != 0)
1975 ahc_outb(ahc, SCSIOFFSET, offset);
1976 }
1977
1978 tinfo->scsirate = scsirate;
1979 tinfo->curr.period = period;
1980 tinfo->curr.offset = offset;
1981 tinfo->curr.ppr_options = ppr_options;
1982
1983 ahc_send_async(ahc, devinfo->channel, devinfo->target,
1984 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
1985 if (bootverbose) {
1986 if (offset != 0) {
1987 printf("%s: target %d synchronous at %sMHz%s, "
1988 "offset = 0x%x\n", ahc_name(ahc),
1989 devinfo->target, syncrate->rate,
1990 (ppr_options & MSG_EXT_PPR_DT_REQ)
1991 ? " DT" : "", offset);
1992 } else {
1993 printf("%s: target %d using "
1994 "asynchronous transfers\n",
1995 ahc_name(ahc), devinfo->target);
1996 }
1997 }
1998 }
1999
2000 update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
2001 tinfo, AHC_NEG_TO_GOAL);
2002
2003 if (update_needed)
2004 ahc_update_pending_scbs(ahc);
2005 }
2006
2007 /*
2008 * Update the user/goal/curr tables of wide negotiation
2009 * parameters as well as, in the case of a current or active update,
2010 * any data structures on the host controller. In the case of an
2011 * active update, the specified target is currently talking to us on
2012 * the bus, so the transfer parameter update must take effect
2013 * immediately.
2014 */
2015 void
2016 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2017 u_int width, u_int type, int paused)
2018 {
2019 struct ahc_initiator_tinfo *tinfo;
2020 struct ahc_tmode_tstate *tstate;
2021 u_int oldwidth;
2022 int active;
2023 int update_needed;
2024
2025 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
2026 update_needed = 0;
2027 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2028 devinfo->target, &tstate);
2029
2030 if ((type & AHC_TRANS_USER) != 0)
2031 tinfo->user.width = width;
2032
2033 if ((type & AHC_TRANS_GOAL) != 0)
2034 tinfo->goal.width = width;
2035
2036 oldwidth = tinfo->curr.width;
2037 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) {
2038 u_int scsirate;
2039
2040 update_needed++;
2041 scsirate = tinfo->scsirate;
2042 scsirate &= ~WIDEXFER;
2043 if (width == MSG_EXT_WDTR_BUS_16_BIT)
2044 scsirate |= WIDEXFER;
2045
2046 tinfo->scsirate = scsirate;
2047
2048 if (active)
2049 ahc_outb(ahc, SCSIRATE, scsirate);
2050
2051 tinfo->curr.width = width;
2052
2053 ahc_send_async(ahc, devinfo->channel, devinfo->target,
2054 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
2055 if (bootverbose) {
2056 printf("%s: target %d using %dbit transfers\n",
2057 ahc_name(ahc), devinfo->target,
2058 8 * (0x01 << width));
2059 }
2060 }
2061
2062 update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
2063 tinfo, AHC_NEG_TO_GOAL);
2064 if (update_needed)
2065 ahc_update_pending_scbs(ahc);
2066 }
2067
2068 /*
2069 * Update the current state of tagged queuing for a given target.
2070 */
2071 void
2072 ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2073 ahc_queue_alg alg)
2074 {
2075 ahc_platform_set_tags(ahc, devinfo, alg);
2076 ahc_send_async(ahc, devinfo->channel, devinfo->target,
2077 devinfo->lun, AC_TRANSFER_NEG, &alg);
2078 }
2079
2080 /*
2081 * When the transfer settings for a connection change, update any
2082 * in-transit SCBs to contain the new data so the hardware will
2083 * be set correctly during future (re)selections.
2084 */
2085 static void
2086 ahc_update_pending_scbs(struct ahc_softc *ahc)
2087 {
2088 struct scb *pending_scb;
2089 int pending_scb_count;
2090 int i;
2091 int paused;
2092 u_int saved_scbptr;
2093
2094 /*
2095 * Traverse the pending SCB list and ensure that all of the
2096 * SCBs there have the proper settings.
2097 */
2098 pending_scb_count = 0;
2099 LIST_FOREACH(pending_scb, &ahc->pending_scbs, pending_links) {
2100 struct ahc_devinfo devinfo;
2101 struct hardware_scb *pending_hscb;
2102 struct ahc_initiator_tinfo *tinfo;
2103 struct ahc_tmode_tstate *tstate;
2104
2105 ahc_scb_devinfo(ahc, &devinfo, pending_scb);
2106 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel,
2107 devinfo.our_scsiid,
2108 devinfo.target, &tstate);
2109 pending_hscb = pending_scb->hscb;
2110 pending_hscb->control &= ~ULTRAENB;
2111 if ((tstate->ultraenb & devinfo.target_mask) != 0)
2112 pending_hscb->control |= ULTRAENB;
2113 pending_hscb->scsirate = tinfo->scsirate;
2114 pending_hscb->scsioffset = tinfo->curr.offset;
2115 if ((tstate->auto_negotiate & devinfo.target_mask) == 0
2116 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) {
2117 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE;
2118 pending_hscb->control &= ~MK_MESSAGE;
2119 }
2120 ahc_sync_scb(ahc, pending_scb,
2121 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
2122 pending_scb_count++;
2123 }
2124
2125 if (pending_scb_count == 0)
2126 return;
2127
2128 if (ahc_is_paused(ahc)) {
2129 paused = 1;
2130 } else {
2131 paused = 0;
2132 ahc_pause(ahc);
2133 }
2134
2135 saved_scbptr = ahc_inb(ahc, SCBPTR);
2136 /* Ensure that the hscbs down on the card match the new information */
2137 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
2138 struct hardware_scb *pending_hscb;
2139 u_int control;
2140 u_int scb_tag;
2141
2142 ahc_outb(ahc, SCBPTR, i);
2143 scb_tag = ahc_inb(ahc, SCB_TAG);
2144 pending_scb = ahc_lookup_scb(ahc, scb_tag);
2145 if (pending_scb == NULL)
2146 continue;
2147
2148 pending_hscb = pending_scb->hscb;
2149 control = ahc_inb(ahc, SCB_CONTROL);
2150 control &= ~(ULTRAENB|MK_MESSAGE);
2151 control |= pending_hscb->control & (ULTRAENB|MK_MESSAGE);
2152 ahc_outb(ahc, SCB_CONTROL, control);
2153 ahc_outb(ahc, SCB_SCSIRATE, pending_hscb->scsirate);
2154 ahc_outb(ahc, SCB_SCSIOFFSET, pending_hscb->scsioffset);
2155 }
2156 ahc_outb(ahc, SCBPTR, saved_scbptr);
2157
2158 if (paused == 0)
2159 ahc_unpause(ahc);
2160 }
2161
2162 /**************************** Pathing Information *****************************/
2163 static void
2164 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2165 {
2166 u_int saved_scsiid;
2167 role_t role;
2168 int our_id;
2169
2170 if (ahc_inb(ahc, SSTAT0) & TARGET)
2171 role = ROLE_TARGET;
2172 else
2173 role = ROLE_INITIATOR;
2174
2175 if (role == ROLE_TARGET
2176 && (ahc->features & AHC_MULTI_TID) != 0
2177 && (ahc_inb(ahc, SEQ_FLAGS)
2178 & (CMDPHASE_PENDING|TARG_CMD_PENDING|NO_DISCONNECT)) != 0) {
2179 /* We were selected, so pull our id from TARGIDIN */
2180 our_id = ahc_inb(ahc, TARGIDIN) & OID;
2181 } else if ((ahc->features & AHC_ULTRA2) != 0)
2182 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
2183 else
2184 our_id = ahc_inb(ahc, SCSIID) & OID;
2185
2186 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
2187 ahc_compile_devinfo(devinfo,
2188 our_id,
2189 SCSIID_TARGET(ahc, saved_scsiid),
2190 ahc_inb(ahc, SAVED_LUN),
2191 SCSIID_CHANNEL(ahc, saved_scsiid),
2192 role);
2193 }
2194
2195 struct ahc_phase_table_entry*
2196 ahc_lookup_phase_entry(int phase)
2197 {
2198 struct ahc_phase_table_entry *entry;
2199 struct ahc_phase_table_entry *last_entry;
2200
2201 /*
2202 * num_phases doesn't include the default entry which
2203 * will be returned if the phase doesn't match.
2204 */
2205 last_entry = &ahc_phase_table[num_phases];
2206 for (entry = ahc_phase_table; entry < last_entry; entry++) {
2207 if (phase == entry->phase)
2208 break;
2209 }
2210 return (entry);
2211 }
2212
2213 void
2214 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target,
2215 u_int lun, char channel, role_t role)
2216 {
2217 devinfo->our_scsiid = our_id;
2218 devinfo->target = target;
2219 devinfo->lun = lun;
2220 devinfo->target_offset = target;
2221 devinfo->channel = channel;
2222 devinfo->role = role;
2223 if (channel == 'B')
2224 devinfo->target_offset += 8;
2225 devinfo->target_mask = (0x01 << devinfo->target_offset);
2226 }
2227
2228 void
2229 ahc_print_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2230 {
2231 printf("%s:%c:%d:%d: ", ahc_name(ahc), devinfo->channel,
2232 devinfo->target, devinfo->lun);
2233 }
2234
2235 static void
2236 ahc_scb_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2237 struct scb *scb)
2238 {
2239 role_t role;
2240 int our_id;
2241
2242 our_id = SCSIID_OUR_ID(scb->hscb->scsiid);
2243 role = ROLE_INITIATOR;
2244 if ((scb->flags & SCB_TARGET_SCB) != 0)
2245 role = ROLE_TARGET;
2246 ahc_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahc, scb),
2247 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahc, scb), role);
2248 }
2249
2250
2251 /************************ Message Phase Processing ****************************/
2252 static void
2253 ahc_assert_atn(struct ahc_softc *ahc)
2254 {
2255 u_int scsisigo;
2256
2257 scsisigo = ATNO;
2258 if ((ahc->features & AHC_DT) == 0)
2259 scsisigo |= ahc_inb(ahc, SCSISIGI);
2260 ahc_outb(ahc, SCSISIGO, scsisigo);
2261 }
2262
2263 /*
2264 * When an initiator transaction with the MK_MESSAGE flag either reconnects
2265 * or enters the initial message out phase, we are interrupted. Fill our
2266 * outgoing message buffer with the appropriate message and beging handing
2267 * the message phase(s) manually.
2268 */
2269 static void
2270 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2271 struct scb *scb)
2272 {
2273 /*
2274 * To facilitate adding multiple messages together,
2275 * each routine should increment the index and len
2276 * variables instead of setting them explicitly.
2277 */
2278 ahc->msgout_index = 0;
2279 ahc->msgout_len = 0;
2280
2281 if ((scb->flags & SCB_DEVICE_RESET) == 0
2282 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) {
2283 u_int identify_msg;
2284
2285 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb);
2286 if ((scb->hscb->control & DISCENB) != 0)
2287 identify_msg |= MSG_IDENTIFY_DISCFLAG;
2288 ahc->msgout_buf[ahc->msgout_index++] = identify_msg;
2289 ahc->msgout_len++;
2290
2291 if ((scb->hscb->control & TAG_ENB) != 0) {
2292 ahc->msgout_buf[ahc->msgout_index++] =
2293 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE);
2294 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag;
2295 ahc->msgout_len += 2;
2296 }
2297 }
2298
2299 if (scb->flags & SCB_DEVICE_RESET) {
2300 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET;
2301 ahc->msgout_len++;
2302 ahc_print_path(ahc, scb);
2303 printf("Bus Device Reset Message Sent\n");
2304 /*
2305 * Clear our selection hardware in advance of
2306 * the busfree. We may have an entry in the waiting
2307 * Q for this target, and we don't want to go about
2308 * selecting while we handle the busfree and blow it
2309 * away.
2310 */
2311 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
2312 } else if ((scb->flags & SCB_ABORT) != 0) {
2313 if ((scb->hscb->control & TAG_ENB) != 0)
2314 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG;
2315 else
2316 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT;
2317 ahc->msgout_len++;
2318 ahc_print_path(ahc, scb);
2319 printf("Abort%s Message Sent\n",
2320 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : "");
2321 /*
2322 * Clear our selection hardware in advance of
2323 * the busfree. We may have an entry in the waiting
2324 * Q for this target, and we don't want to go about
2325 * selecting while we handle the busfree and blow it
2326 * away.
2327 */
2328 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
2329 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) {
2330 ahc_build_transfer_msg(ahc, devinfo);
2331 } else {
2332 printf("ahc_intr: AWAITING_MSG for an SCB that "
2333 "does not have a waiting message\n");
2334 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid,
2335 devinfo->target_mask);
2336 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x "
2337 "SCB flags = %x", scb->hscb->tag, scb->hscb->control,
2338 ahc_inb(ahc, MSG_OUT), scb->flags);
2339 }
2340
2341 /*
2342 * Clear the MK_MESSAGE flag from the SCB so we aren't
2343 * asked to send this message again.
2344 */
2345 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE);
2346 scb->hscb->control &= ~MK_MESSAGE;
2347 ahc->msgout_index = 0;
2348 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2349 }
2350
2351 /*
2352 * Build an appropriate transfer negotiation message for the
2353 * currently active target.
2354 */
2355 static void
2356 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2357 {
2358 /*
2359 * We need to initiate transfer negotiations.
2360 * If our current and goal settings are identical,
2361 * we want to renegotiate due to a check condition.
2362 */
2363 struct ahc_initiator_tinfo *tinfo;
2364 struct ahc_tmode_tstate *tstate;
2365 struct ahc_syncrate *rate;
2366 int dowide;
2367 int dosync;
2368 int doppr;
2369 u_int period;
2370 u_int ppr_options;
2371 u_int offset;
2372
2373 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2374 devinfo->target, &tstate);
2375 /*
2376 * Filter our period based on the current connection.
2377 * If we can't perform DT transfers on this segment (not in LVD
2378 * mode for instance), then our decision to issue a PPR message
2379 * may change.
2380 */
2381 period = tinfo->goal.period;
2382 offset = tinfo->goal.offset;
2383 ppr_options = tinfo->goal.ppr_options;
2384 /* Target initiated PPR is not allowed in the SCSI spec */
2385 if (devinfo->role == ROLE_TARGET)
2386 ppr_options = 0;
2387 rate = ahc_devlimited_syncrate(ahc, tinfo, &period,
2388 &ppr_options, devinfo->role);
2389 dowide = tinfo->curr.width != tinfo->goal.width;
2390 dosync = tinfo->curr.offset != offset || tinfo->curr.period != period;
2391 /*
2392 * Only use PPR if we have options that need it, even if the device
2393 * claims to support it. There might be an expander in the way
2394 * that doesn't.
2395 */
2396 doppr = ppr_options != 0;
2397
2398 if (!dowide && !dosync && !doppr) {
2399 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT;
2400 dosync = tinfo->goal.offset != 0;
2401 }
2402
2403 if (!dowide && !dosync && !doppr) {
2404 /*
2405 * Force async with a WDTR message if we have a wide bus,
2406 * or just issue an SDTR with a 0 offset.
2407 */
2408 if ((ahc->features & AHC_WIDE) != 0)
2409 dowide = 1;
2410 else
2411 dosync = 1;
2412
2413 if (bootverbose) {
2414 ahc_print_devinfo(ahc, devinfo);
2415 printf("Ensuring async\n");
2416 }
2417 }
2418
2419 /* Target initiated PPR is not allowed in the SCSI spec */
2420 if (devinfo->role == ROLE_TARGET)
2421 doppr = 0;
2422
2423 /*
2424 * Both the PPR message and SDTR message require the
2425 * goal syncrate to be limited to what the target device
2426 * is capable of handling (based on whether an LVD->SE
2427 * expander is on the bus), so combine these two cases.
2428 * Regardless, guarantee that if we are using WDTR and SDTR
2429 * messages that WDTR comes first.
2430 */
2431 if (doppr || (dosync && !dowide)) {
2432
2433 offset = tinfo->goal.offset;
2434 ahc_validate_offset(ahc, tinfo, rate, &offset,
2435 doppr ? tinfo->goal.width
2436 : tinfo->curr.width,
2437 devinfo->role);
2438 if (doppr) {
2439 ahc_construct_ppr(ahc, devinfo, period, offset,
2440 tinfo->goal.width, ppr_options);
2441 } else {
2442 ahc_construct_sdtr(ahc, devinfo, period, offset);
2443 }
2444 } else {
2445 ahc_construct_wdtr(ahc, devinfo, tinfo->goal.width);
2446 }
2447 }
2448
2449 /*
2450 * Build a synchronous negotiation message in our message
2451 * buffer based on the input parameters.
2452 */
2453 static void
2454 ahc_construct_sdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2455 u_int period, u_int offset)
2456 {
2457 if (offset == 0)
2458 period = AHC_ASYNC_XFER_PERIOD;
2459 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2460 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN;
2461 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR;
2462 ahc->msgout_buf[ahc->msgout_index++] = period;
2463 ahc->msgout_buf[ahc->msgout_index++] = offset;
2464 ahc->msgout_len += 5;
2465 if (bootverbose) {
2466 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n",
2467 ahc_name(ahc), devinfo->channel, devinfo->target,
2468 devinfo->lun, period, offset);
2469 }
2470 }
2471
2472 /*
2473 * Build a wide negotiation message in our message
2474 * buffer based on the input parameters.
2475 */
2476 static void
2477 ahc_construct_wdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2478 u_int bus_width)
2479 {
2480 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2481 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN;
2482 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR;
2483 ahc->msgout_buf[ahc->msgout_index++] = bus_width;
2484 ahc->msgout_len += 4;
2485 if (bootverbose) {
2486 printf("(%s:%c:%d:%d): Sending WDTR %x\n",
2487 ahc_name(ahc), devinfo->channel, devinfo->target,
2488 devinfo->lun, bus_width);
2489 }
2490 }
2491
2492 /*
2493 * Build a parallel protocol request message in our message
2494 * buffer based on the input parameters.
2495 */
2496 static void
2497 ahc_construct_ppr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2498 u_int period, u_int offset, u_int bus_width,
2499 u_int ppr_options)
2500 {
2501 if (offset == 0)
2502 period = AHC_ASYNC_XFER_PERIOD;
2503 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2504 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR_LEN;
2505 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR;
2506 ahc->msgout_buf[ahc->msgout_index++] = period;
2507 ahc->msgout_buf[ahc->msgout_index++] = 0;
2508 ahc->msgout_buf[ahc->msgout_index++] = offset;
2509 ahc->msgout_buf[ahc->msgout_index++] = bus_width;
2510 ahc->msgout_buf[ahc->msgout_index++] = ppr_options;
2511 ahc->msgout_len += 8;
2512 if (bootverbose) {
2513 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, "
2514 "offset %x, ppr_options %x\n", ahc_name(ahc),
2515 devinfo->channel, devinfo->target, devinfo->lun,
2516 bus_width, period, offset, ppr_options);
2517 }
2518 }
2519
2520 /*
2521 * Clear any active message state.
2522 */
2523 static void
2524 ahc_clear_msg_state(struct ahc_softc *ahc)
2525 {
2526 ahc->msgout_len = 0;
2527 ahc->msgin_index = 0;
2528 ahc->msg_type = MSG_TYPE_NONE;
2529 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0) {
2530 /*
2531 * The target didn't care to respond to our
2532 * message request, so clear ATN.
2533 */
2534 ahc_outb(ahc, CLRSINT1, CLRATNO);
2535 }
2536 ahc_outb(ahc, MSG_OUT, MSG_NOOP);
2537 ahc_outb(ahc, SEQ_FLAGS2,
2538 ahc_inb(ahc, SEQ_FLAGS2) & ~TARGET_MSG_PENDING);
2539 }
2540
2541 static void
2542 ahc_handle_proto_violation(struct ahc_softc *ahc)
2543 {
2544 struct ahc_devinfo devinfo;
2545 struct scb *scb;
2546 u_int scbid;
2547 u_int seq_flags;
2548 u_int curphase;
2549 u_int lastphase;
2550 int found;
2551
2552 ahc_fetch_devinfo(ahc, &devinfo);
2553 scbid = ahc_inb(ahc, SCB_TAG);
2554 scb = ahc_lookup_scb(ahc, scbid);
2555 seq_flags = ahc_inb(ahc, SEQ_FLAGS);
2556 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
2557 lastphase = ahc_inb(ahc, LASTPHASE);
2558 if ((seq_flags & NOT_IDENTIFIED) != 0) {
2559
2560 /*
2561 * The reconnecting target either did not send an
2562 * identify message, or did, but we didn't find an SCB
2563 * to match.
2564 */
2565 ahc_print_devinfo(ahc, &devinfo);
2566 printf("Target did not send an IDENTIFY message. "
2567 "LASTPHASE = 0x%x.\n", lastphase);
2568 scb = NULL;
2569 } else if (scb == NULL) {
2570 /*
2571 * We don't seem to have an SCB active for this
2572 * transaction. Print an error and reset the bus.
2573 */
2574 ahc_print_devinfo(ahc, &devinfo);
2575 printf("No SCB found during protocol violation\n");
2576 goto proto_violation_reset;
2577 } else {
2578 ahc_set_transaction_status(scb, CAM_SEQUENCE_FAIL);
2579 if ((seq_flags & NO_CDB_SENT) != 0) {
2580 ahc_print_path(ahc, scb);
2581 printf("No or incomplete CDB sent to device.\n");
2582 } else if ((ahc_inb(ahc, SCB_CONTROL) & STATUS_RCVD) == 0) {
2583 /*
2584 * The target never bothered to provide status to
2585 * us prior to completing the command. Since we don't
2586 * know the disposition of this command, we must attempt
2587 * to abort it. Assert ATN and prepare to send an abort
2588 * message.
2589 */
2590 ahc_print_path(ahc, scb);
2591 printf("Completed command without status.\n");
2592 } else {
2593 ahc_print_path(ahc, scb);
2594 printf("Unknown protocol violation.\n");
2595 ahc_dump_card_state(ahc);
2596 }
2597 }
2598 if ((lastphase & ~P_DATAIN_DT) == 0
2599 || lastphase == P_COMMAND) {
2600 proto_violation_reset:
2601 /*
2602 * Target either went directly to data/command
2603 * phase or didn't respond to our ATN.
2604 * The only safe thing to do is to blow
2605 * it away with a bus reset.
2606 */
2607 found = ahc_reset_channel(ahc, 'A', TRUE);
2608 printf("%s: Issued Channel %c Bus Reset. "
2609 "%d SCBs aborted\n", ahc_name(ahc), 'A', found);
2610 } else {
2611 /*
2612 * Leave the selection hardware off in case
2613 * this abort attempt will affect yet to
2614 * be sent commands.
2615 */
2616 ahc_outb(ahc, SCSISEQ,
2617 ahc_inb(ahc, SCSISEQ) & ~ENSELO);
2618 ahc_assert_atn(ahc);
2619 ahc_outb(ahc, MSG_OUT, HOST_MSG);
2620 if (scb == NULL) {
2621 ahc_print_devinfo(ahc, &devinfo);
2622 ahc->msgout_buf[0] = MSG_ABORT_TASK;
2623 ahc->msgout_len = 1;
2624 ahc->msgout_index = 0;
2625 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2626 } else {
2627 ahc_print_path(ahc, scb);
2628 scb->flags |= SCB_ABORT;
2629 }
2630 printf("Protocol violation %s. Attempting to abort.\n",
2631 ahc_lookup_phase_entry(curphase)->phasemsg);
2632 }
2633 }
2634
2635 /*
2636 * Manual message loop handler.
2637 */
2638 static void
2639 ahc_handle_message_phase(struct ahc_softc *ahc)
2640 {
2641 struct ahc_devinfo devinfo;
2642 u_int bus_phase;
2643 int end_session;
2644
2645 ahc_fetch_devinfo(ahc, &devinfo);
2646 end_session = FALSE;
2647 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
2648
2649 reswitch:
2650 switch (ahc->msg_type) {
2651 case MSG_TYPE_INITIATOR_MSGOUT:
2652 {
2653 int lastbyte;
2654 int phasemis;
2655 int msgdone;
2656
2657 if (ahc->msgout_len == 0)
2658 panic("HOST_MSG_LOOP interrupt with no active message");
2659
2660 #ifdef AHC_DEBUG
2661 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2662 ahc_print_devinfo(ahc, &devinfo);
2663 printf("INITIATOR_MSG_OUT");
2664 }
2665 #endif
2666 phasemis = bus_phase != P_MESGOUT;
2667 if (phasemis) {
2668 #ifdef AHC_DEBUG
2669 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2670 printf(" PHASEMIS %s\n",
2671 ahc_lookup_phase_entry(bus_phase)
2672 ->phasemsg);
2673 }
2674 #endif
2675 if (bus_phase == P_MESGIN) {
2676 /*
2677 * Change gears and see if
2678 * this messages is of interest to
2679 * us or should be passed back to
2680 * the sequencer.
2681 */
2682 ahc_outb(ahc, CLRSINT1, CLRATNO);
2683 ahc->send_msg_perror = FALSE;
2684 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN;
2685 ahc->msgin_index = 0;
2686 goto reswitch;
2687 }
2688 end_session = TRUE;
2689 break;
2690 }
2691
2692 if (ahc->send_msg_perror) {
2693 ahc_outb(ahc, CLRSINT1, CLRATNO);
2694 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2695 #ifdef AHC_DEBUG
2696 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2697 printf(" byte 0x%x\n", ahc->send_msg_perror);
2698 #endif
2699 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR);
2700 break;
2701 }
2702
2703 msgdone = ahc->msgout_index == ahc->msgout_len;
2704 if (msgdone) {
2705 /*
2706 * The target has requested a retry.
2707 * Re-assert ATN, reset our message index to
2708 * 0, and try again.
2709 */
2710 ahc->msgout_index = 0;
2711 ahc_assert_atn(ahc);
2712 }
2713
2714 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1);
2715 if (lastbyte) {
2716 /* Last byte is signified by dropping ATN */
2717 ahc_outb(ahc, CLRSINT1, CLRATNO);
2718 }
2719
2720 /*
2721 * Clear our interrupt status and present
2722 * the next byte on the bus.
2723 */
2724 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2725 #ifdef AHC_DEBUG
2726 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2727 printf(" byte 0x%x\n",
2728 ahc->msgout_buf[ahc->msgout_index]);
2729 #endif
2730 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
2731 break;
2732 }
2733 case MSG_TYPE_INITIATOR_MSGIN:
2734 {
2735 int phasemis;
2736 int message_done;
2737
2738 #ifdef AHC_DEBUG
2739 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2740 ahc_print_devinfo(ahc, &devinfo);
2741 printf("INITIATOR_MSG_IN");
2742 }
2743 #endif
2744 phasemis = bus_phase != P_MESGIN;
2745 if (phasemis) {
2746 #ifdef AHC_DEBUG
2747 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2748 printf(" PHASEMIS %s\n",
2749 ahc_lookup_phase_entry(bus_phase)
2750 ->phasemsg);
2751 }
2752 #endif
2753 ahc->msgin_index = 0;
2754 if (bus_phase == P_MESGOUT
2755 && (ahc->send_msg_perror == TRUE
2756 || (ahc->msgout_len != 0
2757 && ahc->msgout_index == 0))) {
2758 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2759 goto reswitch;
2760 }
2761 end_session = TRUE;
2762 break;
2763 }
2764
2765 /* Pull the byte in without acking it */
2766 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL);
2767 #ifdef AHC_DEBUG
2768 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2769 printf(" byte 0x%x\n",
2770 ahc->msgin_buf[ahc->msgin_index]);
2771 #endif
2772
2773 message_done = ahc_parse_msg(ahc, &devinfo);
2774
2775 if (message_done) {
2776 /*
2777 * Clear our incoming message buffer in case there
2778 * is another message following this one.
2779 */
2780 ahc->msgin_index = 0;
2781
2782 /*
2783 * If this message illicited a response,
2784 * assert ATN so the target takes us to the
2785 * message out phase.
2786 */
2787 if (ahc->msgout_len != 0) {
2788 #ifdef AHC_DEBUG
2789 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2790 ahc_print_devinfo(ahc, &devinfo);
2791 printf("Asserting ATN for response\n");
2792 }
2793 #endif
2794 ahc_assert_atn(ahc);
2795 }
2796 } else
2797 ahc->msgin_index++;
2798
2799 if (message_done == MSGLOOP_TERMINATED) {
2800 end_session = TRUE;
2801 } else {
2802 /* Ack the byte */
2803 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2804 ahc_inb(ahc, SCSIDATL);
2805 }
2806 break;
2807 }
2808 case MSG_TYPE_TARGET_MSGIN:
2809 {
2810 int msgdone;
2811 int msgout_request;
2812
2813 if (ahc->msgout_len == 0)
2814 panic("Target MSGIN with no active message");
2815
2816 /*
2817 * If we interrupted a mesgout session, the initiator
2818 * will not know this until our first REQ. So, we
2819 * only honor mesgout requests after we've sent our
2820 * first byte.
2821 */
2822 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0
2823 && ahc->msgout_index > 0)
2824 msgout_request = TRUE;
2825 else
2826 msgout_request = FALSE;
2827
2828 if (msgout_request) {
2829
2830 /*
2831 * Change gears and see if
2832 * this messages is of interest to
2833 * us or should be passed back to
2834 * the sequencer.
2835 */
2836 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT;
2837 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO);
2838 ahc->msgin_index = 0;
2839 /* Dummy read to REQ for first byte */
2840 ahc_inb(ahc, SCSIDATL);
2841 ahc_outb(ahc, SXFRCTL0,
2842 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2843 break;
2844 }
2845
2846 msgdone = ahc->msgout_index == ahc->msgout_len;
2847 if (msgdone) {
2848 ahc_outb(ahc, SXFRCTL0,
2849 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
2850 end_session = TRUE;
2851 break;
2852 }
2853
2854 /*
2855 * Present the next byte on the bus.
2856 */
2857 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2858 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
2859 break;
2860 }
2861 case MSG_TYPE_TARGET_MSGOUT:
2862 {
2863 int lastbyte;
2864 int msgdone;
2865
2866 /*
2867 * The initiator signals that this is
2868 * the last byte by dropping ATN.
2869 */
2870 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0;
2871
2872 /*
2873 * Read the latched byte, but turn off SPIOEN first
2874 * so that we don't inadvertently cause a REQ for the
2875 * next byte.
2876 */
2877 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
2878 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL);
2879 msgdone = ahc_parse_msg(ahc, &devinfo);
2880 if (msgdone == MSGLOOP_TERMINATED) {
2881 /*
2882 * The message is *really* done in that it caused
2883 * us to go to bus free. The sequencer has already
2884 * been reset at this point, so pull the ejection
2885 * handle.
2886 */
2887 return;
2888 }
2889
2890 ahc->msgin_index++;
2891
2892 /*
2893 * XXX Read spec about initiator dropping ATN too soon
2894 * and use msgdone to detect it.
2895 */
2896 if (msgdone == MSGLOOP_MSGCOMPLETE) {
2897 ahc->msgin_index = 0;
2898
2899 /*
2900 * If this message illicited a response, transition
2901 * to the Message in phase and send it.
2902 */
2903 if (ahc->msgout_len != 0) {
2904 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO);
2905 ahc_outb(ahc, SXFRCTL0,
2906 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2907 ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
2908 ahc->msgin_index = 0;
2909 break;
2910 }
2911 }
2912
2913 if (lastbyte)
2914 end_session = TRUE;
2915 else {
2916 /* Ask for the next byte. */
2917 ahc_outb(ahc, SXFRCTL0,
2918 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2919 }
2920
2921 break;
2922 }
2923 default:
2924 panic("Unknown REQINIT message type");
2925 }
2926
2927 if (end_session) {
2928 ahc_clear_msg_state(ahc);
2929 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP);
2930 } else
2931 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP);
2932 }
2933
2934 /*
2935 * See if we sent a particular extended message to the target.
2936 * If "full" is true, return true only if the target saw the full
2937 * message. If "full" is false, return true if the target saw at
2938 * least the first byte of the message.
2939 */
2940 static int
2941 ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, u_int msgval, int full)
2942 {
2943 int found;
2944 u_int index;
2945
2946 found = FALSE;
2947 index = 0;
2948
2949 while (index < ahc->msgout_len) {
2950 if (ahc->msgout_buf[index] == MSG_EXTENDED) {
2951 u_int end_index;
2952
2953 end_index = index + 1 + ahc->msgout_buf[index + 1];
2954 if (ahc->msgout_buf[index+2] == msgval
2955 && type == AHCMSG_EXT) {
2956
2957 if (full) {
2958 if (ahc->msgout_index > end_index)
2959 found = TRUE;
2960 } else if (ahc->msgout_index > index)
2961 found = TRUE;
2962 }
2963 index = end_index;
2964 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_TASK
2965 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) {
2966
2967 /* Skip tag type and tag id or residue param*/
2968 index += 2;
2969 } else {
2970 /* Single byte message */
2971 if (type == AHCMSG_1B
2972 && ahc->msgout_buf[index] == msgval
2973 && ahc->msgout_index > index)
2974 found = TRUE;
2975 index++;
2976 }
2977
2978 if (found)
2979 break;
2980 }
2981 return (found);
2982 }
2983
2984 /*
2985 * Wait for a complete incoming message, parse it, and respond accordingly.
2986 */
2987 static int
2988 ahc_parse_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2989 {
2990 struct ahc_initiator_tinfo *tinfo;
2991 struct ahc_tmode_tstate *tstate;
2992 int reject;
2993 int done;
2994 int response;
2995 u_int targ_scsirate;
2996
2997 done = MSGLOOP_IN_PROG;
2998 response = FALSE;
2999 reject = FALSE;
3000 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
3001 devinfo->target, &tstate);
3002 targ_scsirate = tinfo->scsirate;
3003
3004 /*
3005 * Parse as much of the message as is available,
3006 * rejecting it if we don't support it. When
3007 * the entire message is available and has been
3008 * handled, return MSGLOOP_MSGCOMPLETE, indicating
3009 * that we have parsed an entire message.
3010 *
3011 * In the case of extended messages, we accept the length
3012 * byte outright and perform more checking once we know the
3013 * extended message type.
3014 */
3015 switch (ahc->msgin_buf[0]) {
3016 case MSG_DISCONNECT:
3017 case MSG_SAVEDATAPOINTER:
3018 case MSG_CMDCOMPLETE:
3019 case MSG_RESTOREPOINTERS:
3020 case MSG_IGN_WIDE_RESIDUE:
3021 /*
3022 * End our message loop as these are messages
3023 * the sequencer handles on its own.
3024 */
3025 done = MSGLOOP_TERMINATED;
3026 break;
3027 case MSG_MESSAGE_REJECT:
3028 response = ahc_handle_msg_reject(ahc, devinfo);
3029 /* FALLTHROUGH */
3030 case MSG_NOOP:
3031 done = MSGLOOP_MSGCOMPLETE;
3032 break;
3033 case MSG_EXTENDED:
3034 {
3035 /* Wait for enough of the message to begin validation */
3036 if (ahc->msgin_index < 2)
3037 break;
3038 switch (ahc->msgin_buf[2]) {
3039 case MSG_EXT_SDTR:
3040 {
3041 struct ahc_syncrate *syncrate;
3042 u_int period;
3043 u_int ppr_options;
3044 u_int offset;
3045 u_int saved_offset;
3046
3047 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) {
3048 reject = TRUE;
3049 break;
3050 }
3051
3052 /*
3053 * Wait until we have both args before validating
3054 * and acting on this message.
3055 *
3056 * Add one to MSG_EXT_SDTR_LEN to account for
3057 * the extended message preamble.
3058 */
3059 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1))
3060 break;
3061
3062 period = ahc->msgin_buf[3];
3063 ppr_options = 0;
3064 saved_offset = offset = ahc->msgin_buf[4];
3065 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
3066 &ppr_options,
3067 devinfo->role);
3068 ahc_validate_offset(ahc, tinfo, syncrate, &offset,
3069 targ_scsirate & WIDEXFER,
3070 devinfo->role);
3071 if (bootverbose) {
3072 printf("(%s:%c:%d:%d): Received "
3073 "SDTR period %x, offset %x\n\t"
3074 "Filtered to period %x, offset %x\n",
3075 ahc_name(ahc), devinfo->channel,
3076 devinfo->target, devinfo->lun,
3077 ahc->msgin_buf[3], saved_offset,
3078 period, offset);
3079 }
3080 ahc_set_syncrate(ahc, devinfo,
3081 syncrate, period,
3082 offset, ppr_options,
3083 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3084 /*paused*/TRUE);
3085
3086 /*
3087 * See if we initiated Sync Negotiation
3088 * and didn't have to fall down to async
3089 * transfers.
3090 */
3091 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, TRUE)) {
3092 /* We started it */
3093 if (saved_offset != offset) {
3094 /* Went too low - force async */
3095 reject = TRUE;
3096 }
3097 } else {
3098 /*
3099 * Send our own SDTR in reply
3100 */
3101 if (bootverbose
3102 && devinfo->role == ROLE_INITIATOR) {
3103 printf("(%s:%c:%d:%d): Target "
3104 "Initiated SDTR\n",
3105 ahc_name(ahc), devinfo->channel,
3106 devinfo->target, devinfo->lun);
3107 }
3108 ahc->msgout_index = 0;
3109 ahc->msgout_len = 0;
3110 ahc_construct_sdtr(ahc, devinfo,
3111 period, offset);
3112 ahc->msgout_index = 0;
3113 response = TRUE;
3114 }
3115 done = MSGLOOP_MSGCOMPLETE;
3116 break;
3117 }
3118 case MSG_EXT_WDTR:
3119 {
3120 u_int bus_width;
3121 u_int saved_width;
3122 u_int sending_reply;
3123
3124 sending_reply = FALSE;
3125 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) {
3126 reject = TRUE;
3127 break;
3128 }
3129
3130 /*
3131 * Wait until we have our arg before validating
3132 * and acting on this message.
3133 *
3134 * Add one to MSG_EXT_WDTR_LEN to account for
3135 * the extended message preamble.
3136 */
3137 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1))
3138 break;
3139
3140 bus_width = ahc->msgin_buf[3];
3141 saved_width = bus_width;
3142 ahc_validate_width(ahc, tinfo, &bus_width,
3143 devinfo->role);
3144 if (bootverbose) {
3145 printf("(%s:%c:%d:%d): Received WDTR "
3146 "%x filtered to %x\n",
3147 ahc_name(ahc), devinfo->channel,
3148 devinfo->target, devinfo->lun,
3149 saved_width, bus_width);
3150 }
3151
3152 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, TRUE)) {
3153 /*
3154 * Don't send a WDTR back to the
3155 * target, since we asked first.
3156 * If the width went higher than our
3157 * request, reject it.
3158 */
3159 if (saved_width > bus_width) {
3160 reject = TRUE;
3161 printf("(%s:%c:%d:%d): requested %dBit "
3162 "transfers. Rejecting...\n",
3163 ahc_name(ahc), devinfo->channel,
3164 devinfo->target, devinfo->lun,
3165 8 * (0x01 << bus_width));
3166 bus_width = 0;
3167 }
3168 } else {
3169 /*
3170 * Send our own WDTR in reply
3171 */
3172 if (bootverbose
3173 && devinfo->role == ROLE_INITIATOR) {
3174 printf("(%s:%c:%d:%d): Target "
3175 "Initiated WDTR\n",
3176 ahc_name(ahc), devinfo->channel,
3177 devinfo->target, devinfo->lun);
3178 }
3179 ahc->msgout_index = 0;
3180 ahc->msgout_len = 0;
3181 ahc_construct_wdtr(ahc, devinfo, bus_width);
3182 ahc->msgout_index = 0;
3183 response = TRUE;
3184 sending_reply = TRUE;
3185 }
3186 /*
3187 * After a wide message, we are async, but
3188 * some devices don't seem to honor this portion
3189 * of the spec. Force a renegotiation of the
3190 * sync component of our transfer agreement even
3191 * if our goal is async. By updating our width
3192 * after forcing the negotiation, we avoid
3193 * renegotiating for width.
3194 */
3195 ahc_update_neg_request(ahc, devinfo, tstate,
3196 tinfo, AHC_NEG_ALWAYS);
3197 ahc_set_width(ahc, devinfo, bus_width,
3198 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3199 /*paused*/TRUE);
3200 if (sending_reply == FALSE && reject == FALSE) {
3201
3202 /*
3203 * We will always have an SDTR to send.
3204 */
3205 ahc->msgout_index = 0;
3206 ahc->msgout_len = 0;
3207 ahc_build_transfer_msg(ahc, devinfo);
3208 ahc->msgout_index = 0;
3209 response = TRUE;
3210 }
3211 done = MSGLOOP_MSGCOMPLETE;
3212 break;
3213 }
3214 case MSG_EXT_PPR:
3215 {
3216 struct ahc_syncrate *syncrate;
3217 u_int period;
3218 u_int offset;
3219 u_int bus_width;
3220 u_int ppr_options;
3221 u_int saved_width;
3222 u_int saved_offset;
3223 u_int saved_ppr_options;
3224
3225 if (ahc->msgin_buf[1] != MSG_EXT_PPR_LEN) {
3226 reject = TRUE;
3227 break;
3228 }
3229
3230 /*
3231 * Wait until we have all args before validating
3232 * and acting on this message.
3233 *
3234 * Add one to MSG_EXT_PPR_LEN to account for
3235 * the extended message preamble.
3236 */
3237 if (ahc->msgin_index < (MSG_EXT_PPR_LEN + 1))
3238 break;
3239
3240 period = ahc->msgin_buf[3];
3241 offset = ahc->msgin_buf[5];
3242 bus_width = ahc->msgin_buf[6];
3243 saved_width = bus_width;
3244 ppr_options = ahc->msgin_buf[7];
3245 /*
3246 * According to the spec, a DT only
3247 * period factor with no DT option
3248 * set implies async.
3249 */
3250 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0
3251 && period == 9)
3252 offset = 0;
3253 saved_ppr_options = ppr_options;
3254 saved_offset = offset;
3255
3256 /*
3257 * Mask out any options we don't support
3258 * on any controller. Transfer options are
3259 * only available if we are negotiating wide.
3260 */
3261 ppr_options &= MSG_EXT_PPR_DT_REQ;
3262 if (bus_width == 0)
3263 ppr_options = 0;
3264
3265 ahc_validate_width(ahc, tinfo, &bus_width,
3266 devinfo->role);
3267 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
3268 &ppr_options,
3269 devinfo->role);
3270 ahc_validate_offset(ahc, tinfo, syncrate,
3271 &offset, bus_width,
3272 devinfo->role);
3273
3274 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, TRUE)) {
3275 /*
3276 * If we are unable to do any of the
3277 * requested options (we went too low),
3278 * then we'll have to reject the message.
3279 */
3280 if (saved_width > bus_width
3281 || saved_offset != offset
3282 || saved_ppr_options != ppr_options) {
3283 reject = TRUE;
3284 period = 0;
3285 offset = 0;
3286 bus_width = 0;
3287 ppr_options = 0;
3288 syncrate = NULL;
3289 }
3290 } else {
3291 if (devinfo->role != ROLE_TARGET)
3292 printf("(%s:%c:%d:%d): Target "
3293 "Initiated PPR\n",
3294 ahc_name(ahc), devinfo->channel,
3295 devinfo->target, devinfo->lun);
3296 else
3297 printf("(%s:%c:%d:%d): Initiator "
3298 "Initiated PPR\n",
3299 ahc_name(ahc), devinfo->channel,
3300 devinfo->target, devinfo->lun);
3301 ahc->msgout_index = 0;
3302 ahc->msgout_len = 0;
3303 ahc_construct_ppr(ahc, devinfo, period, offset,
3304 bus_width, ppr_options);
3305 ahc->msgout_index = 0;
3306 response = TRUE;
3307 }
3308 if (bootverbose) {
3309 printf("(%s:%c:%d:%d): Received PPR width %x, "
3310 "period %x, offset %x,options %x\n"
3311 "\tFiltered to width %x, period %x, "
3312 "offset %x, options %x\n",
3313 ahc_name(ahc), devinfo->channel,
3314 devinfo->target, devinfo->lun,
3315 saved_width, ahc->msgin_buf[3],
3316 saved_offset, saved_ppr_options,
3317 bus_width, period, offset, ppr_options);
3318 }
3319 ahc_set_width(ahc, devinfo, bus_width,
3320 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3321 /*paused*/TRUE);
3322 ahc_set_syncrate(ahc, devinfo,
3323 syncrate, period,
3324 offset, ppr_options,
3325 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3326 /*paused*/TRUE);
3327 done = MSGLOOP_MSGCOMPLETE;
3328 break;
3329 }
3330 default:
3331 /* Unknown extended message. Reject it. */
3332 reject = TRUE;
3333 break;
3334 }
3335 break;
3336 }
3337 #ifdef AHC_TARGET_MODE
3338 case MSG_BUS_DEV_RESET:
3339 ahc_handle_devreset(ahc, devinfo,
3340 CAM_BDR_SENT,
3341 "Bus Device Reset Received",
3342 /*verbose_level*/0);
3343 ahc_restart(ahc);
3344 done = MSGLOOP_TERMINATED;
3345 break;
3346 case MSG_ABORT_TAG:
3347 case MSG_ABORT:
3348 case MSG_CLEAR_QUEUE:
3349 {
3350 int tag;
3351
3352 /* Target mode messages */
3353 if (devinfo->role != ROLE_TARGET) {
3354 reject = TRUE;
3355 break;
3356 }
3357 tag = SCB_LIST_NULL;
3358 if (ahc->msgin_buf[0] == MSG_ABORT_TAG)
3359 tag = ahc_inb(ahc, INITIATOR_TAG);
3360 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
3361 devinfo->lun, tag, ROLE_TARGET,
3362 CAM_REQ_ABORTED);
3363
3364 tstate = ahc->enabled_targets[devinfo->our_scsiid];
3365 if (tstate != NULL) {
3366 struct ahc_tmode_lstate* lstate;
3367
3368 lstate = tstate->enabled_luns[devinfo->lun];
3369 if (lstate != NULL) {
3370 ahc_queue_lstate_event(ahc, lstate,
3371 devinfo->our_scsiid,
3372 ahc->msgin_buf[0],
3373 /*arg*/tag);
3374 ahc_send_lstate_events(ahc, lstate);
3375 }
3376 }
3377 ahc_restart(ahc);
3378 done = MSGLOOP_TERMINATED;
3379 break;
3380 }
3381 #endif
3382 case MSG_TERM_IO_PROC:
3383 default:
3384 reject = TRUE;
3385 break;
3386 }
3387
3388 if (reject) {
3389 /*
3390 * Setup to reject the message.
3391 */
3392 ahc->msgout_index = 0;
3393 ahc->msgout_len = 1;
3394 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT;
3395 done = MSGLOOP_MSGCOMPLETE;
3396 response = TRUE;
3397 }
3398
3399 if (done != MSGLOOP_IN_PROG && !response)
3400 /* Clear the outgoing message buffer */
3401 ahc->msgout_len = 0;
3402
3403 return (done);
3404 }
3405
3406 /*
3407 * Process a message reject message.
3408 */
3409 static int
3410 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3411 {
3412 /*
3413 * What we care about here is if we had an
3414 * outstanding SDTR or WDTR message for this
3415 * target. If we did, this is a signal that
3416 * the target is refusing negotiation.
3417 */
3418 struct scb *scb;
3419 struct ahc_initiator_tinfo *tinfo;
3420 struct ahc_tmode_tstate *tstate;
3421 u_int scb_index;
3422 u_int last_msg;
3423 int response = 0;
3424
3425 scb_index = ahc_inb(ahc, SCB_TAG);
3426 scb = ahc_lookup_scb(ahc, scb_index);
3427 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel,
3428 devinfo->our_scsiid,
3429 devinfo->target, &tstate);
3430 /* Might be necessary */
3431 last_msg = ahc_inb(ahc, LAST_MSG);
3432
3433 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) {
3434 /*
3435 * Target does not support the PPR message.
3436 * Attempt to negotiate SPI-2 style.
3437 */
3438 if (bootverbose) {
3439 printf("(%s:%c:%d:%d): PPR Rejected. "
3440 "Trying WDTR/SDTR\n",
3441 ahc_name(ahc), devinfo->channel,
3442 devinfo->target, devinfo->lun);
3443 }
3444 tinfo->goal.ppr_options = 0;
3445 tinfo->curr.transport_version = 2;
3446 tinfo->goal.transport_version = 2;
3447 ahc->msgout_index = 0;
3448 ahc->msgout_len = 0;
3449 ahc_build_transfer_msg(ahc, devinfo);
3450 ahc->msgout_index = 0;
3451 response = 1;
3452 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) {
3453
3454 /* note 8bit xfers */
3455 printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using "
3456 "8bit transfers\n", ahc_name(ahc),
3457 devinfo->channel, devinfo->target, devinfo->lun);
3458 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
3459 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3460 /*paused*/TRUE);
3461 /*
3462 * No need to clear the sync rate. If the target
3463 * did not accept the command, our syncrate is
3464 * unaffected. If the target started the negotiation,
3465 * but rejected our response, we already cleared the
3466 * sync rate before sending our WDTR.
3467 */
3468 if (tinfo->goal.offset != tinfo->curr.offset) {
3469
3470 /* Start the sync negotiation */
3471 ahc->msgout_index = 0;
3472 ahc->msgout_len = 0;
3473 ahc_build_transfer_msg(ahc, devinfo);
3474 ahc->msgout_index = 0;
3475 response = 1;
3476 }
3477 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) {
3478 /* note asynch xfers and clear flag */
3479 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0,
3480 /*offset*/0, /*ppr_options*/0,
3481 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3482 /*paused*/TRUE);
3483 printf("(%s:%c:%d:%d): refuses synchronous negotiation. "
3484 "Using asynchronous transfers\n",
3485 ahc_name(ahc), devinfo->channel,
3486 devinfo->target, devinfo->lun);
3487 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) {
3488 int tag_type;
3489 int mask;
3490
3491 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK);
3492
3493 if (tag_type == MSG_SIMPLE_TASK) {
3494 printf("(%s:%c:%d:%d): refuses tagged commands. "
3495 "Performing non-tagged I/O\n", ahc_name(ahc),
3496 devinfo->channel, devinfo->target, devinfo->lun);
3497 ahc_set_tags(ahc, devinfo, AHC_QUEUE_NONE);
3498 mask = ~0x23;
3499 } else {
3500 printf("(%s:%c:%d:%d): refuses %s tagged commands. "
3501 "Performing simple queue tagged I/O only\n",
3502 ahc_name(ahc), devinfo->channel, devinfo->target,
3503 devinfo->lun, tag_type == MSG_ORDERED_TASK
3504 ? "ordered" : "head of queue");
3505 ahc_set_tags(ahc, devinfo, AHC_QUEUE_BASIC);
3506 mask = ~0x03;
3507 }
3508
3509 /*
3510 * Resend the identify for this CCB as the target
3511 * may believe that the selection is invalid otherwise.
3512 */
3513 ahc_outb(ahc, SCB_CONTROL,
3514 ahc_inb(ahc, SCB_CONTROL) & mask);
3515 scb->hscb->control &= mask;
3516 ahc_set_transaction_tag(scb, /*enabled*/FALSE,
3517 /*type*/MSG_SIMPLE_TASK);
3518 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG);
3519 ahc_assert_atn(ahc);
3520
3521 /*
3522 * This transaction is now at the head of
3523 * the untagged queue for this target.
3524 */
3525 if ((ahc->flags & AHC_SCB_BTT) == 0) {
3526 struct scb_tailq *untagged_q;
3527
3528 untagged_q =
3529 &(ahc->untagged_queues[devinfo->target_offset]);
3530 TAILQ_INSERT_HEAD(untagged_q, scb, links.tqe);
3531 scb->flags |= SCB_UNTAGGEDQ;
3532 }
3533 ahc_busy_tcl(ahc, BUILD_TCL(scb->hscb->scsiid, devinfo->lun),
3534 scb->hscb->tag);
3535
3536 /*
3537 * Requeue all tagged commands for this target
3538 * currently in our posession so they can be
3539 * converted to untagged commands.
3540 */
3541 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
3542 SCB_GET_CHANNEL(ahc, scb),
3543 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL,
3544 ROLE_INITIATOR, CAM_REQUEUE_REQ,
3545 SEARCH_COMPLETE);
3546 } else {
3547 /*
3548 * Otherwise, we ignore it.
3549 */
3550 printf("%s:%c:%d: Message reject for %x -- ignored\n",
3551 ahc_name(ahc), devinfo->channel, devinfo->target,
3552 last_msg);
3553 }
3554 return (response);
3555 }
3556
3557 /*
3558 * Process an ingnore wide residue message.
3559 */
3560 static void
3561 ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3562 {
3563 u_int scb_index;
3564 struct scb *scb;
3565
3566 scb_index = ahc_inb(ahc, SCB_TAG);
3567 scb = ahc_lookup_scb(ahc, scb_index);
3568 /*
3569 * XXX Actually check data direction in the sequencer?
3570 * Perhaps add datadir to some spare bits in the hscb?
3571 */
3572 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0
3573 || ahc_get_transfer_dir(scb) != CAM_DIR_IN) {
3574 /*
3575 * Ignore the message if we haven't
3576 * seen an appropriate data phase yet.
3577 */
3578 } else {
3579 /*
3580 * If the residual occurred on the last
3581 * transfer and the transfer request was
3582 * expected to end on an odd count, do
3583 * nothing. Otherwise, subtract a byte
3584 * and update the residual count accordingly.
3585 */
3586 uint32_t sgptr;
3587
3588 sgptr = ahc_inb(ahc, SCB_RESIDUAL_SGPTR);
3589 if ((sgptr & SG_LIST_NULL) != 0
3590 && (ahc_inb(ahc, SCB_LUN) & SCB_XFERLEN_ODD) != 0) {
3591 /*
3592 * If the residual occurred on the last
3593 * transfer and the transfer request was
3594 * expected to end on an odd count, do
3595 * nothing.
3596 */
3597 } else {
3598 struct ahc_dma_seg *sg;
3599 uint32_t data_cnt;
3600 uint32_t data_addr;
3601 uint32_t sglen;
3602
3603 /* Pull in all of the sgptr */
3604 sgptr = ahc_inl(ahc, SCB_RESIDUAL_SGPTR);
3605 data_cnt = ahc_inl(ahc, SCB_RESIDUAL_DATACNT);
3606
3607 if ((sgptr & SG_LIST_NULL) != 0) {
3608 /*
3609 * The residual data count is not updated
3610 * for the command run to completion case.
3611 * Explicitly zero the count.
3612 */
3613 data_cnt &= ~AHC_SG_LEN_MASK;
3614 }
3615
3616 data_addr = ahc_inl(ahc, SHADDR);
3617
3618 data_cnt += 1;
3619 data_addr -= 1;
3620 sgptr &= SG_PTR_MASK;
3621
3622 sg = ahc_sg_bus_to_virt(scb, sgptr);
3623
3624 /*
3625 * The residual sg ptr points to the next S/G
3626 * to load so we must go back one.
3627 */
3628 sg--;
3629 sglen = ahc_le32toh(sg->len) & AHC_SG_LEN_MASK;
3630 if (sg != scb->sg_list
3631 && sglen < (data_cnt & AHC_SG_LEN_MASK)) {
3632
3633 sg--;
3634 sglen = ahc_le32toh(sg->len);
3635 /*
3636 * Preserve High Address and SG_LIST bits
3637 * while setting the count to 1.
3638 */
3639 data_cnt = 1 | (sglen & (~AHC_SG_LEN_MASK));
3640 data_addr = ahc_le32toh(sg->addr)
3641 + (sglen & AHC_SG_LEN_MASK) - 1;
3642
3643 /*
3644 * Increment sg so it points to the
3645 * "next" sg.
3646 */
3647 sg++;
3648 sgptr = ahc_sg_virt_to_bus(scb, sg);
3649 }
3650 ahc_outl(ahc, SCB_RESIDUAL_SGPTR, sgptr);
3651 ahc_outl(ahc, SCB_RESIDUAL_DATACNT, data_cnt);
3652 /*
3653 * Toggle the "oddness" of the transfer length
3654 * to handle this mid-transfer ignore wide
3655 * residue. This ensures that the oddness is
3656 * correct for subsequent data transfers.
3657 */
3658 ahc_outb(ahc, SCB_LUN,
3659 ahc_inb(ahc, SCB_LUN) ^ SCB_XFERLEN_ODD);
3660 }
3661 }
3662 }
3663
3664
3665 /*
3666 * Reinitialize the data pointers for the active transfer
3667 * based on its current residual.
3668 */
3669 static void
3670 ahc_reinitialize_dataptrs(struct ahc_softc *ahc)
3671 {
3672 struct scb *scb;
3673 struct ahc_dma_seg *sg;
3674 u_int scb_index;
3675 uint32_t sgptr;
3676 uint32_t resid;
3677 uint32_t dataptr;
3678
3679 scb_index = ahc_inb(ahc, SCB_TAG);
3680 scb = ahc_lookup_scb(ahc, scb_index);
3681 sgptr = (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24)
3682 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16)
3683 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8)
3684 | ahc_inb(ahc, SCB_RESIDUAL_SGPTR);
3685
3686 sgptr &= SG_PTR_MASK;
3687 sg = ahc_sg_bus_to_virt(scb, sgptr);
3688
3689 /* The residual sg_ptr always points to the next sg */
3690 sg--;
3691
3692 resid = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 2) << 16)
3693 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 1) << 8)
3694 | ahc_inb(ahc, SCB_RESIDUAL_DATACNT);
3695
3696 dataptr = ahc_le32toh(sg->addr)
3697 + (ahc_le32toh(sg->len) & AHC_SG_LEN_MASK)
3698 - resid;
3699 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
3700 u_int dscommand1;
3701
3702 dscommand1 = ahc_inb(ahc, DSCOMMAND1);
3703 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
3704 ahc_outb(ahc, HADDR,
3705 (ahc_le32toh(sg->len) >> 24) & SG_HIGH_ADDR_BITS);
3706 ahc_outb(ahc, DSCOMMAND1, dscommand1);
3707 }
3708 ahc_outb(ahc, HADDR + 3, dataptr >> 24);
3709 ahc_outb(ahc, HADDR + 2, dataptr >> 16);
3710 ahc_outb(ahc, HADDR + 1, dataptr >> 8);
3711 ahc_outb(ahc, HADDR, dataptr);
3712 ahc_outb(ahc, HCNT + 2, resid >> 16);
3713 ahc_outb(ahc, HCNT + 1, resid >> 8);
3714 ahc_outb(ahc, HCNT, resid);
3715 if ((ahc->features & AHC_ULTRA2) == 0) {
3716 ahc_outb(ahc, STCNT + 2, resid >> 16);
3717 ahc_outb(ahc, STCNT + 1, resid >> 8);
3718 ahc_outb(ahc, STCNT, resid);
3719 }
3720 }
3721
3722 /*
3723 * Handle the effects of issuing a bus device reset message.
3724 */
3725 static void
3726 ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
3727 cam_status status, char *message, int verbose_level)
3728 {
3729 #ifdef AHC_TARGET_MODE
3730 struct ahc_tmode_tstate* tstate;
3731 u_int lun;
3732 #endif
3733 int found;
3734
3735 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
3736 CAM_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role,
3737 status);
3738
3739 #ifdef AHC_TARGET_MODE
3740 /*
3741 * Send an immediate notify ccb to all target mord peripheral
3742 * drivers affected by this action.
3743 */
3744 tstate = ahc->enabled_targets[devinfo->our_scsiid];
3745 if (tstate != NULL) {
3746 for (lun = 0; lun < AHC_NUM_LUNS; lun++) {
3747 struct ahc_tmode_lstate* lstate;
3748
3749 lstate = tstate->enabled_luns[lun];
3750 if (lstate == NULL)
3751 continue;
3752
3753 ahc_queue_lstate_event(ahc, lstate, devinfo->our_scsiid,
3754 MSG_BUS_DEV_RESET, /*arg*/0);
3755 ahc_send_lstate_events(ahc, lstate);
3756 }
3757 }
3758 #endif
3759
3760 /*
3761 * Go back to async/narrow transfers and renegotiate.
3762 */
3763 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
3764 AHC_TRANS_CUR, /*paused*/TRUE);
3765 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL,
3766 /*period*/0, /*offset*/0, /*ppr_options*/0,
3767 AHC_TRANS_CUR, /*paused*/TRUE);
3768
3769 ahc_send_async(ahc, devinfo->channel, devinfo->target,
3770 CAM_LUN_WILDCARD, AC_SENT_BDR, NULL);
3771
3772 if (message != NULL
3773 && (verbose_level <= bootverbose))
3774 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc),
3775 message, devinfo->channel, devinfo->target, found);
3776 }
3777
3778 #ifdef AHC_TARGET_MODE
3779 static void
3780 ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
3781 struct scb *scb)
3782 {
3783
3784 /*
3785 * To facilitate adding multiple messages together,
3786 * each routine should increment the index and len
3787 * variables instead of setting them explicitly.
3788 */
3789 ahc->msgout_index = 0;
3790 ahc->msgout_len = 0;
3791
3792 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0)
3793 ahc_build_transfer_msg(ahc, devinfo);
3794 else
3795 panic("ahc_intr: AWAITING target message with no message");
3796
3797 ahc->msgout_index = 0;
3798 ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
3799 }
3800 #endif
3801 /**************************** Initialization **********************************/
3802 /*
3803 * Allocate a controller structure for a new device
3804 * and perform initial initializion.
3805 */
3806 struct ahc_softc *
3807 ahc_alloc(void *platform_arg, char *name)
3808 {
3809 struct ahc_softc *ahc;
3810 int i;
3811
3812 #ifndef __FreeBSD__
3813 ahc = malloc(sizeof(*ahc), M_DEVBUF, M_NOWAIT);
3814 if (!ahc) {
3815 printf("aic7xxx: cannot malloc softc!\n");
3816 free(name, M_DEVBUF);
3817 return NULL;
3818 }
3819 #else
3820 ahc = device_get_softc((device_t)platform_arg);
3821 #endif
3822 memset(ahc, 0, sizeof(*ahc));
3823 ahc->seep_config = malloc(sizeof(*ahc->seep_config),
3824 M_DEVBUF, M_NOWAIT);
3825 if (ahc->seep_config == NULL) {
3826 #ifndef __FreeBSD__
3827 free(ahc, M_DEVBUF);
3828 #endif
3829 free(name, M_DEVBUF);
3830 return (NULL);
3831 }
3832 LIST_INIT(&ahc->pending_scbs);
3833 /* We don't know our unit number until the OSM sets it */
3834 ahc->name = name;
3835 ahc->unit = -1;
3836 ahc->description = NULL;
3837 ahc->channel = 'A';
3838 ahc->channel_b = 'B';
3839 ahc->chip = AHC_NONE;
3840 ahc->features = AHC_FENONE;
3841 ahc->bugs = AHC_BUGNONE;
3842 ahc->flags = AHC_FNONE;
3843 /*
3844 * Default to all error reporting enabled with the
3845 * sequencer operating at its fastest speed.
3846 * The bus attach code may modify this.
3847 */
3848 ahc->seqctl = FASTMODE;
3849
3850 for (i = 0; i < AHC_NUM_TARGETS; i++)
3851 TAILQ_INIT(&ahc->untagged_queues[i]);
3852 if (ahc_platform_alloc(ahc, platform_arg) != 0) {
3853 ahc_free(ahc);
3854 ahc = NULL;
3855 }
3856 return (ahc);
3857 }
3858
3859 int
3860 ahc_softc_init(struct ahc_softc *ahc)
3861 {
3862
3863 /* The IRQMS bit is only valid on VL and EISA chips */
3864 if ((ahc->chip & AHC_PCI) == 0)
3865 ahc->unpause = ahc_inb(ahc, HCNTRL) & IRQMS;
3866 else
3867 ahc->unpause = 0;
3868 ahc->pause = ahc->unpause | PAUSE;
3869 /* XXX The shared scb data stuff should be deprecated */
3870 if (ahc->scb_data == NULL) {
3871 ahc->scb_data = malloc(sizeof(*ahc->scb_data),
3872 M_DEVBUF, M_NOWAIT);
3873 if (ahc->scb_data == NULL)
3874 return (ENOMEM);
3875 memset(ahc->scb_data, 0, sizeof(*ahc->scb_data));
3876 }
3877
3878 return (0);
3879 }
3880
3881 void
3882 ahc_softc_insert(struct ahc_softc *ahc)
3883 {
3884 struct ahc_softc *list_ahc;
3885
3886 #if AHC_PCI_CONFIG > 0
3887 /*
3888 * Second Function PCI devices need to inherit some
3889 * settings from function 0.
3890 */
3891 if ((ahc->chip & AHC_BUS_MASK) == AHC_PCI
3892 && (ahc->features & AHC_MULTI_FUNC) != 0) {
3893 TAILQ_FOREACH(list_ahc, &ahc_tailq, links) {
3894 ahc_dev_softc_t list_pci;
3895 ahc_dev_softc_t pci;
3896
3897 list_pci = list_ahc->dev_softc;
3898 pci = ahc->dev_softc;
3899 if (ahc_get_pci_slot(list_pci) == ahc_get_pci_slot(pci)
3900 && ahc_get_pci_bus(list_pci) == ahc_get_pci_bus(pci)) {
3901 struct ahc_softc *master;
3902 struct ahc_softc *slave;
3903
3904 if (ahc_get_pci_function(list_pci) == 0) {
3905 master = list_ahc;
3906 slave = ahc;
3907 } else {
3908 master = ahc;
3909 slave = list_ahc;
3910 }
3911 slave->flags &= ~AHC_BIOS_ENABLED;
3912 slave->flags |=
3913 master->flags & AHC_BIOS_ENABLED;
3914 slave->flags &= ~AHC_PRIMARY_CHANNEL;
3915 slave->flags |=
3916 master->flags & AHC_PRIMARY_CHANNEL;
3917 break;
3918 }
3919 }
3920 }
3921 #endif
3922
3923 /*
3924 * Insertion sort into our list of softcs.
3925 */
3926 list_ahc = TAILQ_FIRST(&ahc_tailq);
3927 while (list_ahc != NULL
3928 && ahc_softc_comp(ahc, list_ahc) <= 0)
3929 list_ahc = TAILQ_NEXT(list_ahc, links);
3930 if (list_ahc != NULL)
3931 TAILQ_INSERT_BEFORE(list_ahc, ahc, links);
3932 else
3933 TAILQ_INSERT_TAIL(&ahc_tailq, ahc, links);
3934 ahc->init_level++;
3935 }
3936
3937 /*
3938 * Verify that the passed in softc pointer is for a
3939 * controller that is still configured.
3940 */
3941 struct ahc_softc *
3942 ahc_find_softc(struct ahc_softc *ahc)
3943 {
3944 struct ahc_softc *list_ahc;
3945
3946 TAILQ_FOREACH(list_ahc, &ahc_tailq, links) {
3947 if (list_ahc == ahc)
3948 return (ahc);
3949 }
3950 return (NULL);
3951 }
3952
3953 void
3954 ahc_set_unit(struct ahc_softc *ahc, int unit)
3955 {
3956 ahc->unit = unit;
3957 }
3958
3959 void
3960 ahc_set_name(struct ahc_softc *ahc, char *name)
3961 {
3962 if (ahc->name != NULL)
3963 free(ahc->name, M_DEVBUF);
3964 ahc->name = name;
3965 }
3966
3967 void
3968 ahc_free(struct ahc_softc *ahc)
3969 {
3970 int i;
3971
3972 switch (ahc->init_level) {
3973 default:
3974 case 5:
3975 ahc_shutdown(ahc);
3976 /* FALLTHROUGH */
3977 case 4:
3978 ahc_dmamap_unload(ahc, ahc->shared_data_dmat,
3979 ahc->shared_data_dmamap);
3980 /* FALLTHROUGH */
3981 case 3:
3982 ahc_dmamem_free(ahc, ahc->shared_data_dmat, ahc->qoutfifo,
3983 ahc->shared_data_dmamap);
3984 ahc_dmamap_destroy(ahc, ahc->shared_data_dmat,
3985 ahc->shared_data_dmamap);
3986 /* FALLTHROUGH */
3987 case 2:
3988 ahc_dma_tag_destroy(ahc, ahc->shared_data_dmat);
3989 case 1:
3990 #ifndef __linux__
3991 ahc_dma_tag_destroy(ahc, ahc->buffer_dmat);
3992 #endif
3993 break;
3994 case 0:
3995 break;
3996 }
3997
3998 #ifndef __linux__
3999 ahc_dma_tag_destroy(ahc, ahc->parent_dmat);
4000 #endif
4001 ahc_platform_free(ahc);
4002 ahc_fini_scbdata(ahc);
4003 for (i = 0; i < AHC_NUM_TARGETS; i++) {
4004 struct ahc_tmode_tstate *tstate;
4005
4006 tstate = ahc->enabled_targets[i];
4007 if (tstate != NULL) {
4008 #ifdef AHC_TARGET_MODE
4009 int j;
4010
4011 for (j = 0; j < AHC_NUM_LUNS; j++) {
4012 struct ahc_tmode_lstate *lstate;
4013
4014 lstate = tstate->enabled_luns[j];
4015 if (lstate != NULL) {
4016 xpt_free_path(lstate->path);
4017 free(lstate, M_DEVBUF);
4018 }
4019 }
4020 #endif
4021 free(tstate, M_DEVBUF);
4022 }
4023 }
4024 #ifdef AHC_TARGET_MODE
4025 if (ahc->black_hole != NULL) {
4026 xpt_free_path(ahc->black_hole->path);
4027 free(ahc->black_hole, M_DEVBUF);
4028 }
4029 #endif
4030 if (ahc->name != NULL)
4031 free(ahc->name, M_DEVBUF);
4032 if (ahc->seep_config != NULL)
4033 free(ahc->seep_config, M_DEVBUF);
4034 #ifndef __FreeBSD__
4035 free(ahc, M_DEVBUF);
4036 #endif
4037 return;
4038 }
4039
4040 void
4041 ahc_shutdown(void *arg)
4042 {
4043 struct ahc_softc *ahc;
4044 int i;
4045
4046 ahc = (struct ahc_softc *)arg;
4047
4048 /* This will reset most registers to 0, but not all */
4049 ahc_reset(ahc, /*reinit*/FALSE);
4050 ahc_outb(ahc, SCSISEQ, 0);
4051 ahc_outb(ahc, SXFRCTL0, 0);
4052 ahc_outb(ahc, DSPCISTATUS, 0);
4053
4054 for (i = TARG_SCSIRATE; i < SCSICONF; i++)
4055 ahc_outb(ahc, i, 0);
4056 }
4057
4058 /*
4059 * Reset the controller and record some information about it
4060 * that is only available just after a reset. If "reinit" is
4061 * non-zero, this reset occured after initial configuration
4062 * and the caller requests that the chip be fully reinitialized
4063 * to a runable state. Chip interrupts are *not* enabled after
4064 * a reinitialization. The caller must enable interrupts via
4065 * ahc_intr_enable().
4066 */
4067 int
4068 ahc_reset(struct ahc_softc *ahc, int reinit)
4069 {
4070 u_int sblkctl;
4071 u_int sxfrctl1_a, sxfrctl1_b;
4072 int error;
4073 int wait;
4074
4075 /*
4076 * Preserve the value of the SXFRCTL1 register for all channels.
4077 * It contains settings that affect termination and we don't want
4078 * to disturb the integrity of the bus.
4079 */
4080 ahc_pause(ahc);
4081 if ((ahc_inb(ahc, HCNTRL) & CHIPRST) != 0) {
4082 /*
4083 * The chip has not been initialized since
4084 * PCI/EISA/VLB bus reset. Don't trust
4085 * "left over BIOS data".
4086 */
4087 ahc->flags |= AHC_NO_BIOS_INIT;
4088 }
4089 sxfrctl1_b = 0;
4090 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7770) {
4091 u_int sblkctl;
4092
4093 /*
4094 * Save channel B's settings in case this chip
4095 * is setup for TWIN channel operation.
4096 */
4097 sblkctl = ahc_inb(ahc, SBLKCTL);
4098 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB);
4099 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1);
4100 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB);
4101 }
4102 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1);
4103
4104 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause);
4105
4106 /*
4107 * Ensure that the reset has finished. We delay 1000us
4108 * prior to reading the register to make sure the chip
4109 * has sufficiently completed its reset to handle register
4110 * accesses.
4111 */
4112 wait = 1000;
4113 do {
4114 ahc_delay(1000);
4115 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK));
4116
4117 if (wait == 0) {
4118 printf("%s: WARNING - Failed chip reset! "
4119 "Trying to initialize anyway.\n", ahc_name(ahc));
4120 }
4121 ahc_outb(ahc, HCNTRL, ahc->pause);
4122
4123 /* Determine channel configuration */
4124 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE);
4125 /* No Twin Channel PCI cards */
4126 if ((ahc->chip & AHC_PCI) != 0)
4127 sblkctl &= ~SELBUSB;
4128 switch (sblkctl) {
4129 case 0:
4130 /* Single Narrow Channel */
4131 break;
4132 case 2:
4133 /* Wide Channel */
4134 ahc->features |= AHC_WIDE;
4135 break;
4136 case 8:
4137 /* Twin Channel */
4138 ahc->features |= AHC_TWIN;
4139 break;
4140 default:
4141 printf(" Unsupported adapter type. Ignoring\n");
4142 return(-1);
4143 }
4144
4145 /*
4146 * Reload sxfrctl1.
4147 *
4148 * We must always initialize STPWEN to 1 before we
4149 * restore the saved values. STPWEN is initialized
4150 * to a tri-state condition which can only be cleared
4151 * by turning it on.
4152 */
4153 if ((ahc->features & AHC_TWIN) != 0) {
4154 u_int sblkctl;
4155
4156 sblkctl = ahc_inb(ahc, SBLKCTL);
4157 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB);
4158 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b);
4159 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB);
4160 }
4161 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a);
4162
4163 error = 0;
4164 if (reinit != 0)
4165 /*
4166 * If a recovery action has forced a chip reset,
4167 * re-initialize the chip to our liking.
4168 */
4169 error = ahc->bus_chip_init(ahc);
4170 #ifdef AHC_DUMP_SEQ
4171 else
4172 ahc_dumpseq(ahc);
4173 #endif
4174
4175 return (error);
4176 }
4177
4178 /*
4179 * Determine the number of SCBs available on the controller
4180 */
4181 int
4182 ahc_probe_scbs(struct ahc_softc *ahc) {
4183 int i;
4184
4185 for (i = 0; i < AHC_SCB_MAX; i++) {
4186
4187 ahc_outb(ahc, SCBPTR, i);
4188 ahc_outb(ahc, SCB_BASE, i);
4189 if (ahc_inb(ahc, SCB_BASE) != i)
4190 break;
4191 ahc_outb(ahc, SCBPTR, 0);
4192 if (ahc_inb(ahc, SCB_BASE) != 0)
4193 break;
4194 }
4195 return (i);
4196 }
4197
4198 static void
4199 ahc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
4200 {
4201 dma_addr_t *baddr;
4202
4203 baddr = (dma_addr_t *)arg;
4204 *baddr = segs->ds_addr;
4205 }
4206
4207 static void
4208 ahc_build_free_scb_list(struct ahc_softc *ahc)
4209 {
4210 int scbsize;
4211 int i;
4212
4213 scbsize = 32;
4214 if ((ahc->flags & AHC_LSCBS_ENABLED) != 0)
4215 scbsize = 64;
4216
4217 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
4218 int j;
4219
4220 ahc_outb(ahc, SCBPTR, i);
4221
4222 /*
4223 * Touch all SCB bytes to avoid parity errors
4224 * should one of our debugging routines read
4225 * an otherwise uninitiatlized byte.
4226 */
4227 for (j = 0; j < scbsize; j++)
4228 ahc_outb(ahc, SCB_BASE+j, 0xFF);
4229
4230 /* Clear the control byte. */
4231 ahc_outb(ahc, SCB_CONTROL, 0);
4232
4233 /* Set the next pointer */
4234 if ((ahc->flags & AHC_PAGESCBS) != 0)
4235 ahc_outb(ahc, SCB_NEXT, i+1);
4236 else
4237 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL);
4238
4239 /* Make the tag number, SCSIID, and lun invalid */
4240 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL);
4241 ahc_outb(ahc, SCB_SCSIID, 0xFF);
4242 ahc_outb(ahc, SCB_LUN, 0xFF);
4243 }
4244
4245 if ((ahc->flags & AHC_PAGESCBS) != 0) {
4246 /* SCB 0 heads the free list. */
4247 ahc_outb(ahc, FREE_SCBH, 0);
4248 } else {
4249 /* No free list. */
4250 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL);
4251 }
4252
4253 /* Make sure that the last SCB terminates the free list */
4254 ahc_outb(ahc, SCBPTR, i-1);
4255 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL);
4256 }
4257
4258 static int
4259 ahc_init_scbdata(struct ahc_softc *ahc)
4260 {
4261 struct scb_data *scb_data;
4262
4263 scb_data = ahc->scb_data;
4264 SLIST_INIT(&scb_data->free_scbs);
4265 SLIST_INIT(&scb_data->sg_maps);
4266
4267 /* Allocate SCB resources */
4268 scb_data->scbarray =
4269 (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX_ALLOC,
4270 M_DEVBUF, M_NOWAIT);
4271 if (scb_data->scbarray == NULL)
4272 return (ENOMEM);
4273 memset(scb_data->scbarray, 0, sizeof(struct scb) * AHC_SCB_MAX_ALLOC);
4274
4275 /* Determine the number of hardware SCBs and initialize them */
4276
4277 scb_data->maxhscbs = ahc_probe_scbs(ahc);
4278 if (ahc->scb_data->maxhscbs == 0) {
4279 printf("%s: No SCB space found\n", ahc_name(ahc));
4280 return (ENXIO);
4281 }
4282
4283 /*
4284 * Create our DMA tags. These tags define the kinds of device
4285 * accessible memory allocations and memory mappings we will
4286 * need to perform during normal operation.
4287 *
4288 * Unless we need to further restrict the allocation, we rely
4289 * on the restrictions of the parent dmat, hence the common
4290 * use of MAXADDR and MAXSIZE.
4291 */
4292
4293 /* DMA tag for our hardware scb structures */
4294 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4295 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4296 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4297 /*highaddr*/BUS_SPACE_MAXADDR,
4298 /*filter*/NULL, /*filterarg*/NULL,
4299 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb),
4300 /*nsegments*/1,
4301 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4302 /*flags*/0, &scb_data->hscb_dmat) != 0) {
4303 goto error_exit;
4304 }
4305
4306 scb_data->init_level++;
4307
4308 /* Allocation for our hscbs */
4309 if (ahc_dmamem_alloc(ahc, scb_data->hscb_dmat,
4310 (void **)&scb_data->hscbs,
4311 BUS_DMA_NOWAIT, &scb_data->hscb_dmamap) != 0) {
4312 goto error_exit;
4313 }
4314
4315 scb_data->init_level++;
4316
4317 /* And permanently map them */
4318 ahc_dmamap_load(ahc, scb_data->hscb_dmat, scb_data->hscb_dmamap,
4319 scb_data->hscbs,
4320 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb),
4321 ahc_dmamap_cb, &scb_data->hscb_busaddr, /*flags*/0);
4322
4323 scb_data->init_level++;
4324
4325 /* DMA tag for our sense buffers */
4326 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4327 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4328 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4329 /*highaddr*/BUS_SPACE_MAXADDR,
4330 /*filter*/NULL, /*filterarg*/NULL,
4331 AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data),
4332 /*nsegments*/1,
4333 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4334 /*flags*/0, &scb_data->sense_dmat) != 0) {
4335 goto error_exit;
4336 }
4337
4338 scb_data->init_level++;
4339
4340 /* Allocate them */
4341 if (ahc_dmamem_alloc(ahc, scb_data->sense_dmat,
4342 (void **)&scb_data->sense,
4343 BUS_DMA_NOWAIT, &scb_data->sense_dmamap) != 0) {
4344 goto error_exit;
4345 }
4346
4347 scb_data->init_level++;
4348
4349 /* And permanently map them */
4350 ahc_dmamap_load(ahc, scb_data->sense_dmat, scb_data->sense_dmamap,
4351 scb_data->sense,
4352 AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data),
4353 ahc_dmamap_cb, &scb_data->sense_busaddr, /*flags*/0);
4354
4355 scb_data->init_level++;
4356
4357 /* DMA tag for our S/G structures. We allocate in page sized chunks */
4358 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/8,
4359 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4360 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4361 /*highaddr*/BUS_SPACE_MAXADDR,
4362 /*filter*/NULL, /*filterarg*/NULL,
4363 PAGE_SIZE, /*nsegments*/1,
4364 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4365 /*flags*/0, &scb_data->sg_dmat) != 0) {
4366 goto error_exit;
4367 }
4368
4369 scb_data->init_level++;
4370
4371 /* Perform initial CCB allocation */
4372 memset(scb_data->hscbs, 0,
4373 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb));
4374 ahc_alloc_scbs(ahc);
4375
4376 if (scb_data->numscbs == 0) {
4377 printf("%s: ahc_init_scbdata - "
4378 "Unable to allocate initial scbs\n",
4379 ahc_name(ahc));
4380 goto error_exit;
4381 }
4382
4383 /*
4384 * Reserve the next queued SCB.
4385 */
4386 ahc->next_queued_scb = ahc_get_scb(ahc);
4387
4388 /*
4389 * Note that we were successfull
4390 */
4391 return (0);
4392
4393 error_exit:
4394
4395 return (ENOMEM);
4396 }
4397
4398 static void
4399 ahc_fini_scbdata(struct ahc_softc *ahc)
4400 {
4401 struct scb_data *scb_data;
4402
4403 scb_data = ahc->scb_data;
4404 if (scb_data == NULL)
4405 return;
4406
4407 switch (scb_data->init_level) {
4408 default:
4409 case 7:
4410 {
4411 struct sg_map_node *sg_map;
4412
4413 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) {
4414 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links);
4415 ahc_dmamap_unload(ahc, scb_data->sg_dmat,
4416 sg_map->sg_dmamap);
4417 ahc_dmamem_free(ahc, scb_data->sg_dmat,
4418 sg_map->sg_vaddr,
4419 sg_map->sg_dmamap);
4420 free(sg_map, M_DEVBUF);
4421 }
4422 ahc_dma_tag_destroy(ahc, scb_data->sg_dmat);
4423 }
4424 case 6:
4425 ahc_dmamap_unload(ahc, scb_data->sense_dmat,
4426 scb_data->sense_dmamap);
4427 case 5:
4428 ahc_dmamem_free(ahc, scb_data->sense_dmat, scb_data->sense,
4429 scb_data->sense_dmamap);
4430 ahc_dmamap_destroy(ahc, scb_data->sense_dmat,
4431 scb_data->sense_dmamap);
4432 case 4:
4433 ahc_dma_tag_destroy(ahc, scb_data->sense_dmat);
4434 case 3:
4435 ahc_dmamap_unload(ahc, scb_data->hscb_dmat,
4436 scb_data->hscb_dmamap);
4437 case 2:
4438 ahc_dmamem_free(ahc, scb_data->hscb_dmat, scb_data->hscbs,
4439 scb_data->hscb_dmamap);
4440 ahc_dmamap_destroy(ahc, scb_data->hscb_dmat,
4441 scb_data->hscb_dmamap);
4442 case 1:
4443 ahc_dma_tag_destroy(ahc, scb_data->hscb_dmat);
4444 break;
4445 case 0:
4446 break;
4447 }
4448 if (scb_data->scbarray != NULL)
4449 free(scb_data->scbarray, M_DEVBUF);
4450 }
4451
4452 void
4453 ahc_alloc_scbs(struct ahc_softc *ahc)
4454 {
4455 struct scb_data *scb_data;
4456 struct scb *next_scb;
4457 struct sg_map_node *sg_map;
4458 dma_addr_t physaddr;
4459 struct ahc_dma_seg *segs;
4460 int newcount;
4461 int i;
4462
4463 scb_data = ahc->scb_data;
4464 if (scb_data->numscbs >= AHC_SCB_MAX_ALLOC)
4465 /* Can't allocate any more */
4466 return;
4467
4468 next_scb = &scb_data->scbarray[scb_data->numscbs];
4469
4470 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT);
4471
4472 if (sg_map == NULL)
4473 return;
4474
4475 /* Allocate S/G space for the next batch of SCBS */
4476 if (ahc_dmamem_alloc(ahc, scb_data->sg_dmat,
4477 (void **)&sg_map->sg_vaddr,
4478 BUS_DMA_NOWAIT, &sg_map->sg_dmamap) != 0) {
4479 free(sg_map, M_DEVBUF);
4480 return;
4481 }
4482
4483 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links);
4484
4485 ahc_dmamap_load(ahc, scb_data->sg_dmat, sg_map->sg_dmamap,
4486 sg_map->sg_vaddr, PAGE_SIZE, ahc_dmamap_cb,
4487 &sg_map->sg_physaddr, /*flags*/0);
4488
4489 segs = sg_map->sg_vaddr;
4490 physaddr = sg_map->sg_physaddr;
4491
4492 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg)));
4493 newcount = MIN(newcount, (AHC_SCB_MAX_ALLOC - scb_data->numscbs));
4494 for (i = 0; i < newcount; i++) {
4495 struct scb_platform_data *pdata;
4496 #ifndef __linux__
4497 int error;
4498 #endif
4499 pdata = (struct scb_platform_data *)malloc(sizeof(*pdata),
4500 M_DEVBUF, M_NOWAIT);
4501 if (pdata == NULL)
4502 break;
4503 next_scb->platform_data = pdata;
4504 next_scb->sg_map = sg_map;
4505 next_scb->sg_list = segs;
4506 /*
4507 * The sequencer always starts with the second entry.
4508 * The first entry is embedded in the scb.
4509 */
4510 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg);
4511 next_scb->ahc_softc = ahc;
4512 next_scb->flags = SCB_FREE;
4513 #ifndef __linux__
4514 error = ahc_dmamap_create(ahc, ahc->buffer_dmat, /*flags*/0,
4515 &next_scb->dmamap);
4516 if (error != 0)
4517 break;
4518 #endif
4519 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs];
4520 next_scb->hscb->tag = ahc->scb_data->numscbs;
4521 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs,
4522 next_scb, links.sle);
4523 segs += AHC_NSEG;
4524 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg));
4525 next_scb++;
4526 ahc->scb_data->numscbs++;
4527 }
4528 }
4529
4530 void
4531 ahc_controller_info(struct ahc_softc *ahc, char *buf)
4532 {
4533 int len;
4534
4535 len = sprintf(buf, "%s: ", ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]);
4536 buf += len;
4537 if ((ahc->features & AHC_TWIN) != 0)
4538 len = sprintf(buf, "Twin Channel, A SCSI Id=%d, "
4539 "B SCSI Id=%d, primary %c, ",
4540 ahc->our_id, ahc->our_id_b,
4541 (ahc->flags & AHC_PRIMARY_CHANNEL) + 'A');
4542 else {
4543 const char *speed;
4544 const char *type;
4545
4546 speed = "";
4547 if ((ahc->features & AHC_ULTRA) != 0) {
4548 speed = "Ultra ";
4549 } else if ((ahc->features & AHC_DT) != 0) {
4550 speed = "Ultra160 ";
4551 } else if ((ahc->features & AHC_ULTRA2) != 0) {
4552 speed = "Ultra2 ";
4553 }
4554 if ((ahc->features & AHC_WIDE) != 0) {
4555 type = "Wide";
4556 } else {
4557 type = "Single";
4558 }
4559 len = sprintf(buf, "%s%s Channel %c, SCSI Id=%d, ",
4560 speed, type, ahc->channel, ahc->our_id);
4561 }
4562 buf += len;
4563
4564 if ((ahc->flags & AHC_PAGESCBS) != 0)
4565 sprintf(buf, "%d/%d SCBs",
4566 ahc->scb_data->maxhscbs, AHC_MAX_QUEUE);
4567 else
4568 sprintf(buf, "%d SCBs", ahc->scb_data->maxhscbs);
4569 }
4570
4571 int
4572 ahc_chip_init(struct ahc_softc *ahc)
4573 {
4574 int term;
4575 int error;
4576 u_int i;
4577 u_int scsi_conf;
4578 u_int scsiseq_template;
4579 uint32_t physaddr;
4580
4581 ahc_outb(ahc, SEQ_FLAGS, 0);
4582 ahc_outb(ahc, SEQ_FLAGS2, 0);
4583
4584 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/
4585 if (ahc->features & AHC_TWIN) {
4586
4587 /*
4588 * Setup Channel B first.
4589 */
4590 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB);
4591 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0;
4592 ahc_outb(ahc, SCSIID, ahc->our_id_b);
4593 scsi_conf = ahc_inb(ahc, SCSICONF + 1);
4594 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))
4595 |term|ahc->seltime_b|ENSTIMER|ACTNEGEN);
4596 if ((ahc->features & AHC_ULTRA2) != 0)
4597 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR);
4598 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
4599 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN);
4600
4601 /* Select Channel A */
4602 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB);
4603 }
4604 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0;
4605 if ((ahc->features & AHC_ULTRA2) != 0)
4606 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id);
4607 else
4608 ahc_outb(ahc, SCSIID, ahc->our_id);
4609 scsi_conf = ahc_inb(ahc, SCSICONF);
4610 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))
4611 |term|ahc->seltime
4612 |ENSTIMER|ACTNEGEN);
4613 if ((ahc->features & AHC_ULTRA2) != 0)
4614 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR);
4615 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
4616 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN);
4617
4618 /* There are no untagged SCBs active yet. */
4619 for (i = 0; i < 16; i++) {
4620 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, 0));
4621 if ((ahc->flags & AHC_SCB_BTT) != 0) {
4622 int lun;
4623
4624 /*
4625 * The SCB based BTT allows an entry per
4626 * target and lun pair.
4627 */
4628 for (lun = 1; lun < AHC_NUM_LUNS; lun++)
4629 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, lun));
4630 }
4631 }
4632
4633 /* All of our queues are empty */
4634 for (i = 0; i < 256; i++)
4635 ahc->qoutfifo[i] = SCB_LIST_NULL;
4636 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_PREREAD);
4637
4638 for (i = 0; i < 256; i++)
4639 ahc->qinfifo[i] = SCB_LIST_NULL;
4640
4641 if ((ahc->features & AHC_MULTI_TID) != 0) {
4642 ahc_outb(ahc, TARGID, 0);
4643 ahc_outb(ahc, TARGID + 1, 0);
4644 }
4645
4646 /*
4647 * Tell the sequencer where it can find our arrays in memory.
4648 */
4649 physaddr = ahc->scb_data->hscb_busaddr;
4650 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF);
4651 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF);
4652 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF);
4653 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF);
4654
4655 physaddr = ahc->shared_data_busaddr;
4656 ahc_outb(ahc, SHARED_DATA_ADDR, physaddr & 0xFF);
4657 ahc_outb(ahc, SHARED_DATA_ADDR + 1, (physaddr >> 8) & 0xFF);
4658 ahc_outb(ahc, SHARED_DATA_ADDR + 2, (physaddr >> 16) & 0xFF);
4659 ahc_outb(ahc, SHARED_DATA_ADDR + 3, (physaddr >> 24) & 0xFF);
4660
4661 /*
4662 * Initialize the group code to command length table.
4663 * This overrides the values in TARG_SCSIRATE, so only
4664 * setup the table after we have processed that information.
4665 */
4666 ahc_outb(ahc, CMDSIZE_TABLE, 5);
4667 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9);
4668 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9);
4669 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0);
4670 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15);
4671 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11);
4672 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0);
4673 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0);
4674
4675 if ((ahc->features & AHC_HS_MAILBOX) != 0)
4676 ahc_outb(ahc, HS_MAILBOX, 0);
4677
4678 /* Tell the sequencer of our initial queue positions */
4679 if ((ahc->features & AHC_TARGETMODE) != 0) {
4680 ahc->tqinfifonext = 1;
4681 ahc_outb(ahc, KERNEL_TQINPOS, ahc->tqinfifonext - 1);
4682 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
4683 }
4684 ahc->qinfifonext = 0;
4685 ahc->qoutfifonext = 0;
4686 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
4687 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256);
4688 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
4689 ahc_outb(ahc, SNSCB_QOFF, ahc->qinfifonext);
4690 ahc_outb(ahc, SDSCB_QOFF, 0);
4691 } else {
4692 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
4693 ahc_outb(ahc, QINPOS, ahc->qinfifonext);
4694 ahc_outb(ahc, QOUTPOS, ahc->qoutfifonext);
4695 }
4696
4697 /* We don't have any waiting selections */
4698 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL);
4699
4700 /* Our disconnection list is empty too */
4701 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL);
4702
4703 /* Message out buffer starts empty */
4704 ahc_outb(ahc, MSG_OUT, MSG_NOOP);
4705
4706 /*
4707 * Setup the allowed SCSI Sequences based on operational mode.
4708 * If we are a target, we'll enalbe select in operations once
4709 * we've had a lun enabled.
4710 */
4711 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP;
4712 if ((ahc->flags & AHC_INITIATORROLE) != 0)
4713 scsiseq_template |= ENRSELI;
4714 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template);
4715
4716 /* Initialize our list of free SCBs. */
4717 ahc_build_free_scb_list(ahc);
4718
4719 /*
4720 * Tell the sequencer which SCB will be the next one it receives.
4721 */
4722 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag);
4723
4724 /*
4725 * Load the Sequencer program and Enable the adapter
4726 * in "fast" mode.
4727 */
4728 if (bootverbose)
4729 printf("%s: Downloading Sequencer Program...",
4730 ahc_name(ahc));
4731
4732 error = ahc_loadseq(ahc);
4733 if (error != 0)
4734 return (error);
4735
4736 if ((ahc->features & AHC_ULTRA2) != 0) {
4737 int wait;
4738
4739 /*
4740 * Wait for up to 500ms for our transceivers
4741 * to settle. If the adapter does not have
4742 * a cable attached, the transceivers may
4743 * never settle, so don't complain if we
4744 * fail here.
4745 */
4746 for (wait = 5000;
4747 (ahc_inb(ahc, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait;
4748 wait--)
4749 ahc_delay(100);
4750 }
4751 ahc_restart(ahc);
4752 return (0);
4753 }
4754
4755 /*
4756 * Start the board, ready for normal operation
4757 */
4758 int
4759 ahc_init(struct ahc_softc *ahc)
4760 {
4761 int max_targ;
4762 u_int i;
4763 u_int scsi_conf;
4764 u_int ultraenb;
4765 u_int discenable;
4766 u_int tagenable;
4767 size_t driver_data_size;
4768
4769 #ifdef AHC_DEBUG
4770 if ((ahc_debug & AHC_DEBUG_SEQUENCER) != 0)
4771 ahc->flags |= AHC_SEQUENCER_DEBUG;
4772 #endif
4773
4774 #ifdef AHC_PRINT_SRAM
4775 printf("Scratch Ram:");
4776 for (i = 0x20; i < 0x5f; i++) {
4777 if (((i % 8) == 0) && (i != 0)) {
4778 printf ("\n ");
4779 }
4780 printf (" 0x%x", ahc_inb(ahc, i));
4781 }
4782 if ((ahc->features & AHC_MORE_SRAM) != 0) {
4783 for (i = 0x70; i < 0x7f; i++) {
4784 if (((i % 8) == 0) && (i != 0)) {
4785 printf ("\n ");
4786 }
4787 printf (" 0x%x", ahc_inb(ahc, i));
4788 }
4789 }
4790 printf ("\n");
4791 /*
4792 * Reading uninitialized scratch ram may
4793 * generate parity errors.
4794 */
4795 ahc_outb(ahc, CLRINT, CLRPARERR);
4796 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
4797 #endif
4798 max_targ = 15;
4799
4800 /*
4801 * Assume we have a board at this stage and it has been reset.
4802 */
4803 if ((ahc->flags & AHC_USEDEFAULTS) != 0)
4804 ahc->our_id = ahc->our_id_b = 7;
4805
4806 /*
4807 * Default to allowing initiator operations.
4808 */
4809 ahc->flags |= AHC_INITIATORROLE;
4810
4811 /*
4812 * Only allow target mode features if this unit has them enabled.
4813 */
4814 if ((AHC_TMODE_ENABLE & (0x1 << ahc->unit)) == 0)
4815 ahc->features &= ~AHC_TARGETMODE;
4816
4817 #ifndef __linux__
4818 /* DMA tag for mapping buffers into device visible space. */
4819 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4820 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4821 /*lowaddr*/ahc->flags & AHC_39BIT_ADDRESSING
4822 ? (dma_addr_t)0x7FFFFFFFFFULL
4823 : BUS_SPACE_MAXADDR_32BIT,
4824 /*highaddr*/BUS_SPACE_MAXADDR,
4825 /*filter*/NULL, /*filterarg*/NULL,
4826 /*maxsize*/(AHC_NSEG - 1) * PAGE_SIZE,
4827 /*nsegments*/AHC_NSEG,
4828 /*maxsegsz*/AHC_MAXTRANSFER_SIZE,
4829 /*flags*/BUS_DMA_ALLOCNOW,
4830 &ahc->buffer_dmat) != 0) {
4831 return (ENOMEM);
4832 }
4833 #endif
4834
4835 ahc->init_level++;
4836
4837 /*
4838 * DMA tag for our command fifos and other data in system memory
4839 * the card's sequencer must be able to access. For initiator
4840 * roles, we need to allocate space for the qinfifo and qoutfifo.
4841 * The qinfifo and qoutfifo are composed of 256 1 byte elements.
4842 * When providing for the target mode role, we must additionally
4843 * provide space for the incoming target command fifo and an extra
4844 * byte to deal with a dma bug in some chip versions.
4845 */
4846 driver_data_size = 2 * 256 * sizeof(uint8_t);
4847 if ((ahc->features & AHC_TARGETMODE) != 0)
4848 driver_data_size += AHC_TMODE_CMDS * sizeof(struct target_cmd)
4849 + /*DMA WideOdd Bug Buffer*/1;
4850 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4851 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4852 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4853 /*highaddr*/BUS_SPACE_MAXADDR,
4854 /*filter*/NULL, /*filterarg*/NULL,
4855 driver_data_size,
4856 /*nsegments*/1,
4857 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4858 /*flags*/0, &ahc->shared_data_dmat) != 0) {
4859 return (ENOMEM);
4860 }
4861
4862 ahc->init_level++;
4863
4864 /* Allocation of driver data */
4865 if (ahc_dmamem_alloc(ahc, ahc->shared_data_dmat,
4866 (void **)&ahc->qoutfifo,
4867 BUS_DMA_NOWAIT, &ahc->shared_data_dmamap) != 0) {
4868 return (ENOMEM);
4869 }
4870
4871 ahc->init_level++;
4872
4873 /* And permanently map it in */
4874 ahc_dmamap_load(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap,
4875 ahc->qoutfifo, driver_data_size, ahc_dmamap_cb,
4876 &ahc->shared_data_busaddr, /*flags*/0);
4877
4878 if ((ahc->features & AHC_TARGETMODE) != 0) {
4879 ahc->targetcmds = (struct target_cmd *)ahc->qoutfifo;
4880 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[AHC_TMODE_CMDS];
4881 ahc->dma_bug_buf = ahc->shared_data_busaddr
4882 + driver_data_size - 1;
4883 /* All target command blocks start out invalid. */
4884 for (i = 0; i < AHC_TMODE_CMDS; i++)
4885 ahc->targetcmds[i].cmd_valid = 0;
4886 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_PREREAD);
4887 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[256];
4888 }
4889 ahc->qinfifo = &ahc->qoutfifo[256];
4890
4891 ahc->init_level++;
4892
4893 /* Allocate SCB data now that buffer_dmat is initialized */
4894 if (ahc->scb_data->maxhscbs == 0)
4895 if (ahc_init_scbdata(ahc) != 0)
4896 return (ENOMEM);
4897
4898 /*
4899 * Allocate a tstate to house information for our
4900 * initiator presence on the bus as well as the user
4901 * data for any target mode initiator.
4902 */
4903 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) {
4904 printf("%s: unable to allocate ahc_tmode_tstate. "
4905 "Failing attach\n", ahc_name(ahc));
4906 return (ENOMEM);
4907 }
4908
4909 if ((ahc->features & AHC_TWIN) != 0) {
4910 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) {
4911 printf("%s: unable to allocate ahc_tmode_tstate. "
4912 "Failing attach\n", ahc_name(ahc));
4913 return (ENOMEM);
4914 }
4915 }
4916
4917 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX_ALLOC) {
4918 ahc->flags |= AHC_PAGESCBS;
4919 } else {
4920 ahc->flags &= ~AHC_PAGESCBS;
4921 }
4922
4923 #ifdef AHC_DEBUG
4924 if (ahc_debug & AHC_SHOW_MISC) {
4925 printf("%s: hardware scb %u bytes; kernel scb %u bytes; "
4926 "ahc_dma %u bytes\n",
4927 ahc_name(ahc),
4928 (u_int)sizeof(struct hardware_scb),
4929 (u_int)sizeof(struct scb),
4930 (u_int)sizeof(struct ahc_dma_seg));
4931 }
4932 #endif /* AHC_DEBUG */
4933
4934 /*
4935 * Look at the information that board initialization or
4936 * the board bios has left us.
4937 */
4938 if (ahc->features & AHC_TWIN) {
4939 scsi_conf = ahc_inb(ahc, SCSICONF + 1);
4940 if ((scsi_conf & RESET_SCSI) != 0
4941 && (ahc->flags & AHC_INITIATORROLE) != 0)
4942 ahc->flags |= AHC_RESET_BUS_B;
4943 }
4944
4945 scsi_conf = ahc_inb(ahc, SCSICONF);
4946 if ((scsi_conf & RESET_SCSI) != 0
4947 && (ahc->flags & AHC_INITIATORROLE) != 0)
4948 ahc->flags |= AHC_RESET_BUS_A;
4949
4950 ultraenb = 0;
4951 tagenable = ALL_TARGETS_MASK;
4952
4953 /* Grab the disconnection disable table and invert it for our needs */
4954 if ((ahc->flags & AHC_USEDEFAULTS) != 0) {
4955 printf("%s: Host Adapter Bios disabled. Using default SCSI "
4956 "device parameters\n", ahc_name(ahc));
4957 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B|
4958 AHC_TERM_ENB_A|AHC_TERM_ENB_B;
4959 discenable = ALL_TARGETS_MASK;
4960 if ((ahc->features & AHC_ULTRA) != 0)
4961 ultraenb = ALL_TARGETS_MASK;
4962 } else {
4963 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8)
4964 | ahc_inb(ahc, DISC_DSB));
4965 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0)
4966 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8)
4967 | ahc_inb(ahc, ULTRA_ENB);
4968 }
4969
4970 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0)
4971 max_targ = 7;
4972
4973 for (i = 0; i <= max_targ; i++) {
4974 struct ahc_initiator_tinfo *tinfo;
4975 struct ahc_tmode_tstate *tstate;
4976 u_int our_id;
4977 u_int target_id;
4978 char channel;
4979
4980 channel = 'A';
4981 our_id = ahc->our_id;
4982 target_id = i;
4983 if (i > 7 && (ahc->features & AHC_TWIN) != 0) {
4984 channel = 'B';
4985 our_id = ahc->our_id_b;
4986 target_id = i % 8;
4987 }
4988 tinfo = ahc_fetch_transinfo(ahc, channel, our_id,
4989 target_id, &tstate);
4990 /* Default to async narrow across the board */
4991 memset(tinfo, 0, sizeof(*tinfo));
4992 if (ahc->flags & AHC_USEDEFAULTS) {
4993 if ((ahc->features & AHC_WIDE) != 0)
4994 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
4995
4996 /*
4997 * These will be truncated when we determine the
4998 * connection type we have with the target.
4999 */
5000 tinfo->user.period = ahc_syncrates->period;
5001 tinfo->user.offset = MAX_OFFSET;
5002 } else {
5003 u_int scsirate;
5004 uint16_t mask;
5005
5006 /* Take the settings leftover in scratch RAM. */
5007 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i);
5008 mask = (0x01 << i);
5009 if ((ahc->features & AHC_ULTRA2) != 0) {
5010 u_int offset;
5011 u_int maxsync;
5012
5013 if ((scsirate & SOFS) == 0x0F) {
5014 /*
5015 * Haven't negotiated yet,
5016 * so the format is different.
5017 */
5018 scsirate = (scsirate & SXFR) >> 4
5019 | (ultraenb & mask)
5020 ? 0x08 : 0x0
5021 | (scsirate & WIDEXFER);
5022 offset = MAX_OFFSET_ULTRA2;
5023 } else
5024 offset = ahc_inb(ahc, TARG_OFFSET + i);
5025 if ((scsirate & ~WIDEXFER) == 0 && offset != 0)
5026 /* Set to the lowest sync rate, 5MHz */
5027 scsirate |= 0x1c;
5028 maxsync = AHC_SYNCRATE_ULTRA2;
5029 if ((ahc->features & AHC_DT) != 0)
5030 maxsync = AHC_SYNCRATE_DT;
5031 tinfo->user.period =
5032 ahc_find_period(ahc, scsirate, maxsync);
5033 if (offset == 0)
5034 tinfo->user.period = 0;
5035 else
5036 tinfo->user.offset = MAX_OFFSET;
5037 if ((scsirate & SXFR_ULTRA2) <= 8/*10MHz*/
5038 && (ahc->features & AHC_DT) != 0)
5039 tinfo->user.ppr_options =
5040 MSG_EXT_PPR_DT_REQ;
5041 } else if ((scsirate & SOFS) != 0) {
5042 if ((scsirate & SXFR) == 0x40
5043 && (ultraenb & mask) != 0) {
5044 /* Treat 10MHz as a non-ultra speed */
5045 scsirate &= ~SXFR;
5046 ultraenb &= ~mask;
5047 }
5048 tinfo->user.period =
5049 ahc_find_period(ahc, scsirate,
5050 (ultraenb & mask)
5051 ? AHC_SYNCRATE_ULTRA
5052 : AHC_SYNCRATE_FAST);
5053 if (tinfo->user.period != 0)
5054 tinfo->user.offset = MAX_OFFSET;
5055 }
5056 if (tinfo->user.period == 0)
5057 tinfo->user.offset = 0;
5058 if ((scsirate & WIDEXFER) != 0
5059 && (ahc->features & AHC_WIDE) != 0)
5060 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
5061 tinfo->user.protocol_version = 4;
5062 if ((ahc->features & AHC_DT) != 0)
5063 tinfo->user.transport_version = 3;
5064 else
5065 tinfo->user.transport_version = 2;
5066 tinfo->goal.protocol_version = 2;
5067 tinfo->goal.transport_version = 2;
5068 tinfo->curr.protocol_version = 2;
5069 tinfo->curr.transport_version = 2;
5070 }
5071 tstate->ultraenb = 0;
5072 }
5073 ahc->user_discenable = discenable;
5074 ahc->user_tagenable = tagenable;
5075
5076 return (ahc->bus_chip_init(ahc));
5077 }
5078
5079 void
5080 ahc_intr_enable(struct ahc_softc *ahc, int enable)
5081 {
5082 u_int hcntrl;
5083
5084 hcntrl = ahc_inb(ahc, HCNTRL);
5085 hcntrl &= ~INTEN;
5086 ahc->pause &= ~INTEN;
5087 ahc->unpause &= ~INTEN;
5088 if (enable) {
5089 hcntrl |= INTEN;
5090 ahc->pause |= INTEN;
5091 ahc->unpause |= INTEN;
5092 }
5093 ahc_outb(ahc, HCNTRL, hcntrl);
5094 }
5095
5096 /*
5097 * Ensure that the card is paused in a location
5098 * outside of all critical sections and that all
5099 * pending work is completed prior to returning.
5100 * This routine should only be called from outside
5101 * an interrupt context.
5102 */
5103 void
5104 ahc_pause_and_flushwork(struct ahc_softc *ahc)
5105 {
5106 int intstat;
5107 int maxloops;
5108 int paused;
5109
5110 maxloops = 1000;
5111 ahc->flags |= AHC_ALL_INTERRUPTS;
5112 paused = FALSE;
5113 do {
5114 if (paused)
5115 ahc_unpause(ahc);
5116 ahc_intr(ahc);
5117 ahc_pause(ahc);
5118 paused = TRUE;
5119 ahc_outb(ahc, SCSISEQ, ahc_inb(ahc, SCSISEQ) & ~ENSELO);
5120 ahc_clear_critical_section(ahc);
5121 intstat = ahc_inb(ahc, INTSTAT);
5122 } while (--maxloops
5123 && (intstat != 0xFF || (ahc->features & AHC_REMOVABLE) == 0)
5124 && ((intstat & INT_PEND) != 0
5125 || (ahc_inb(ahc, SSTAT0) & (SELDO|SELINGO)) != 0));
5126 if (maxloops == 0) {
5127 printf("Infinite interrupt loop, INTSTAT = %x",
5128 ahc_inb(ahc, INTSTAT));
5129 }
5130 ahc_platform_flushwork(ahc);
5131 ahc->flags &= ~AHC_ALL_INTERRUPTS;
5132 }
5133
5134 int
5135 ahc_suspend(struct ahc_softc *ahc)
5136 {
5137
5138 ahc_pause_and_flushwork(ahc);
5139
5140 if (LIST_FIRST(&ahc->pending_scbs) != NULL) {
5141 ahc_unpause(ahc);
5142 return (EBUSY);
5143 }
5144
5145 #ifdef AHC_TARGET_MODE
5146 /*
5147 * XXX What about ATIOs that have not yet been serviced?
5148 * Perhaps we should just refuse to be suspended if we
5149 * are acting in a target role.
5150 */
5151 if (ahc->pending_device != NULL) {
5152 ahc_unpause(ahc);
5153 return (EBUSY);
5154 }
5155 #endif
5156 ahc_shutdown(ahc);
5157 return (0);
5158 }
5159
5160 int
5161 ahc_resume(struct ahc_softc *ahc)
5162 {
5163
5164 ahc_reset(ahc, /*reinit*/TRUE);
5165 ahc_intr_enable(ahc, TRUE);
5166 ahc_restart(ahc);
5167 return (0);
5168 }
5169
5170 /************************** Busy Target Table *********************************/
5171 /*
5172 * Return the untagged transaction id for a given target/channel lun.
5173 * Optionally, clear the entry.
5174 */
5175 u_int
5176 ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl)
5177 {
5178 u_int scbid;
5179 u_int target_offset;
5180
5181 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5182 u_int saved_scbptr;
5183
5184 saved_scbptr = ahc_inb(ahc, SCBPTR);
5185 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5186 scbid = ahc_inb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl));
5187 ahc_outb(ahc, SCBPTR, saved_scbptr);
5188 } else {
5189 target_offset = TCL_TARGET_OFFSET(tcl);
5190 scbid = ahc_inb(ahc, BUSY_TARGETS + target_offset);
5191 }
5192
5193 return (scbid);
5194 }
5195
5196 void
5197 ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl)
5198 {
5199 u_int target_offset;
5200
5201 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5202 u_int saved_scbptr;
5203
5204 saved_scbptr = ahc_inb(ahc, SCBPTR);
5205 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5206 ahc_outb(ahc, SCB_64_BTT+TCL_TARGET_OFFSET(tcl), SCB_LIST_NULL);
5207 ahc_outb(ahc, SCBPTR, saved_scbptr);
5208 } else {
5209 target_offset = TCL_TARGET_OFFSET(tcl);
5210 ahc_outb(ahc, BUSY_TARGETS + target_offset, SCB_LIST_NULL);
5211 }
5212 }
5213
5214 void
5215 ahc_busy_tcl(struct ahc_softc *ahc, u_int tcl, u_int scbid)
5216 {
5217 u_int target_offset;
5218
5219 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5220 u_int saved_scbptr;
5221
5222 saved_scbptr = ahc_inb(ahc, SCBPTR);
5223 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5224 ahc_outb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl), scbid);
5225 ahc_outb(ahc, SCBPTR, saved_scbptr);
5226 } else {
5227 target_offset = TCL_TARGET_OFFSET(tcl);
5228 ahc_outb(ahc, BUSY_TARGETS + target_offset, scbid);
5229 }
5230 }
5231
5232 /************************** SCB and SCB queue management **********************/
5233 int
5234 ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, int target,
5235 char channel, int lun, u_int tag, role_t role)
5236 {
5237 int targ = SCB_GET_TARGET(ahc, scb);
5238 char chan = SCB_GET_CHANNEL(ahc, scb);
5239 int slun = SCB_GET_LUN(scb);
5240 int match;
5241
5242 match = ((chan == channel) || (channel == ALL_CHANNELS));
5243 if (match != 0)
5244 match = ((targ == target) || (target == CAM_TARGET_WILDCARD));
5245 if (match != 0)
5246 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD));
5247 if (match != 0) {
5248 #ifdef AHC_TARGET_MODE
5249 int group;
5250
5251 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code);
5252 if (role == ROLE_INITIATOR) {
5253 match = (group != XPT_FC_GROUP_TMODE)
5254 && ((tag == scb->hscb->tag)
5255 || (tag == SCB_LIST_NULL));
5256 } else if (role == ROLE_TARGET) {
5257 match = (group == XPT_FC_GROUP_TMODE)
5258 && ((tag == scb->io_ctx->csio.tag_id)
5259 || (tag == SCB_LIST_NULL));
5260 }
5261 #else /* !AHC_TARGET_MODE */
5262 match = ((tag == scb->hscb->tag) || (tag == SCB_LIST_NULL));
5263 #endif /* AHC_TARGET_MODE */
5264 }
5265
5266 return match;
5267 }
5268
5269 void
5270 ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb)
5271 {
5272 int target;
5273 char channel;
5274 int lun;
5275
5276 target = SCB_GET_TARGET(ahc, scb);
5277 lun = SCB_GET_LUN(scb);
5278 channel = SCB_GET_CHANNEL(ahc, scb);
5279
5280 ahc_search_qinfifo(ahc, target, channel, lun,
5281 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN,
5282 CAM_REQUEUE_REQ, SEARCH_COMPLETE);
5283
5284 ahc_platform_freeze_devq(ahc, scb);
5285 }
5286
5287 void
5288 ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, struct scb *scb)
5289 {
5290 struct scb *prev_scb;
5291
5292 prev_scb = NULL;
5293 if (ahc_qinfifo_count(ahc) != 0) {
5294 u_int prev_tag;
5295 uint8_t prev_pos;
5296
5297 prev_pos = ahc->qinfifonext - 1;
5298 prev_tag = ahc->qinfifo[prev_pos];
5299 prev_scb = ahc_lookup_scb(ahc, prev_tag);
5300 }
5301 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5302 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5303 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
5304 } else {
5305 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
5306 }
5307 }
5308
5309 static void
5310 ahc_qinfifo_requeue(struct ahc_softc *ahc, struct scb *prev_scb,
5311 struct scb *scb)
5312 {
5313 if (prev_scb == NULL) {
5314 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag);
5315 } else {
5316 prev_scb->hscb->next = scb->hscb->tag;
5317 ahc_sync_scb(ahc, prev_scb,
5318 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
5319 }
5320 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag;
5321 scb->hscb->next = ahc->next_queued_scb->hscb->tag;
5322 ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
5323 }
5324
5325 static int
5326 ahc_qinfifo_count(struct ahc_softc *ahc)
5327 {
5328 uint8_t qinpos;
5329 uint8_t diff;
5330
5331 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5332 qinpos = ahc_inb(ahc, SNSCB_QOFF);
5333 ahc_outb(ahc, SNSCB_QOFF, qinpos);
5334 } else
5335 qinpos = ahc_inb(ahc, QINPOS);
5336 diff = ahc->qinfifonext - qinpos;
5337 return (diff);
5338 }
5339
5340 int
5341 ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel,
5342 int lun, u_int tag, role_t role, uint32_t status,
5343 ahc_search_action action)
5344 {
5345 struct scb *scb;
5346 struct scb *prev_scb;
5347 uint8_t qinstart;
5348 uint8_t qinpos;
5349 uint8_t qintail;
5350 uint8_t next;
5351 uint8_t prev;
5352 uint8_t curscbptr;
5353 int found;
5354 int have_qregs;
5355
5356 qintail = ahc->qinfifonext;
5357 have_qregs = (ahc->features & AHC_QUEUE_REGS) != 0;
5358 if (have_qregs) {
5359 qinstart = ahc_inb(ahc, SNSCB_QOFF);
5360 ahc_outb(ahc, SNSCB_QOFF, qinstart);
5361 } else
5362 qinstart = ahc_inb(ahc, QINPOS);
5363 qinpos = qinstart;
5364 found = 0;
5365 prev_scb = NULL;
5366
5367 if (action == SEARCH_COMPLETE) {
5368 /*
5369 * Don't attempt to run any queued untagged transactions
5370 * until we are done with the abort process.
5371 */
5372 ahc_freeze_untagged_queues(ahc);
5373 }
5374
5375 /*
5376 * Start with an empty queue. Entries that are not chosen
5377 * for removal will be re-added to the queue as we go.
5378 */
5379 ahc->qinfifonext = qinpos;
5380 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag);
5381
5382 while (qinpos != qintail) {
5383 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinpos]);
5384 if (scb == NULL) {
5385 printf("qinpos = %d, SCB index = %d\n",
5386 qinpos, ahc->qinfifo[qinpos]);
5387 panic("Loop 1\n");
5388 }
5389
5390 if (ahc_match_scb(ahc, scb, target, channel, lun, tag, role)) {
5391 /*
5392 * We found an scb that needs to be acted on.
5393 */
5394 found++;
5395 switch (action) {
5396 case SEARCH_COMPLETE:
5397 {
5398 cam_status ostat;
5399 cam_status cstat;
5400
5401 ostat = ahc_get_transaction_status(scb);
5402 if (ostat == CAM_REQ_INPROG)
5403 ahc_set_transaction_status(scb, status);
5404 cstat = ahc_get_transaction_status(scb);
5405 if (cstat != CAM_REQ_CMP)
5406 ahc_freeze_scb(scb);
5407 if ((scb->flags & SCB_ACTIVE) == 0)
5408 printf("Inactive SCB in qinfifo\n");
5409 ahc_done(ahc, scb);
5410
5411 /* FALLTHROUGH */
5412 }
5413 case SEARCH_REMOVE:
5414 break;
5415 case SEARCH_COUNT:
5416 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5417 prev_scb = scb;
5418 break;
5419 }
5420 } else {
5421 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5422 prev_scb = scb;
5423 }
5424 qinpos++;
5425 }
5426
5427 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5428 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
5429 } else {
5430 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
5431 }
5432
5433 if (action != SEARCH_COUNT
5434 && (found != 0)
5435 && (qinstart != ahc->qinfifonext)) {
5436 /*
5437 * The sequencer may be in the process of dmaing
5438 * down the SCB at the beginning of the queue.
5439 * This could be problematic if either the first,
5440 * or the second SCB is removed from the queue
5441 * (the first SCB includes a pointer to the "next"
5442 * SCB to dma). If we have removed any entries, swap
5443 * the first element in the queue with the next HSCB
5444 * so the sequencer will notice that NEXT_QUEUED_SCB
5445 * has changed during its dma attempt and will retry
5446 * the DMA.
5447 */
5448 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinstart]);
5449
5450 if (scb == NULL) {
5451 printf("found = %d, qinstart = %d, qinfifionext = %d\n",
5452 found, qinstart, ahc->qinfifonext);
5453 panic("First/Second Qinfifo fixup\n");
5454 }
5455 /*
5456 * ahc_swap_with_next_hscb forces our next pointer to
5457 * point to the reserved SCB for future commands. Save
5458 * and restore our original next pointer to maintain
5459 * queue integrity.
5460 */
5461 next = scb->hscb->next;
5462 ahc->scb_data->scbindex[scb->hscb->tag] = NULL;
5463 ahc_swap_with_next_hscb(ahc, scb);
5464 scb->hscb->next = next;
5465 ahc->qinfifo[qinstart] = scb->hscb->tag;
5466
5467 /* Tell the card about the new head of the qinfifo. */
5468 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag);
5469
5470 /* Fixup the tail "next" pointer. */
5471 qintail = ahc->qinfifonext - 1;
5472 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qintail]);
5473 scb->hscb->next = ahc->next_queued_scb->hscb->tag;
5474 }
5475
5476 /*
5477 * Search waiting for selection list.
5478 */
5479 curscbptr = ahc_inb(ahc, SCBPTR);
5480 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */
5481 prev = SCB_LIST_NULL;
5482
5483 while (next != SCB_LIST_NULL) {
5484 uint8_t scb_index;
5485
5486 ahc_outb(ahc, SCBPTR, next);
5487 scb_index = ahc_inb(ahc, SCB_TAG);
5488 if (scb_index >= ahc->scb_data->numscbs) {
5489 printf("Waiting List inconsistency. "
5490 "SCB index == %d, yet numscbs == %d.",
5491 scb_index, ahc->scb_data->numscbs);
5492 ahc_dump_card_state(ahc);
5493 panic("for safety");
5494 }
5495 scb = ahc_lookup_scb(ahc, scb_index);
5496 if (scb == NULL) {
5497 printf("scb_index = %d, next = %d\n",
5498 scb_index, next);
5499 panic("Waiting List traversal\n");
5500 }
5501 if (ahc_match_scb(ahc, scb, target, channel,
5502 lun, SCB_LIST_NULL, role)) {
5503 /*
5504 * We found an scb that needs to be acted on.
5505 */
5506 found++;
5507 switch (action) {
5508 case SEARCH_COMPLETE:
5509 {
5510 cam_status ostat;
5511 cam_status cstat;
5512
5513 ostat = ahc_get_transaction_status(scb);
5514 if (ostat == CAM_REQ_INPROG)
5515 ahc_set_transaction_status(scb,
5516 status);
5517 cstat = ahc_get_transaction_status(scb);
5518 if (cstat != CAM_REQ_CMP)
5519 ahc_freeze_scb(scb);
5520 if ((scb->flags & SCB_ACTIVE) == 0)
5521 printf("Inactive SCB in Waiting List\n");
5522 ahc_done(ahc, scb);
5523 /* FALLTHROUGH */
5524 }
5525 case SEARCH_REMOVE:
5526 next = ahc_rem_wscb(ahc, next, prev);
5527 break;
5528 case SEARCH_COUNT:
5529 prev = next;
5530 next = ahc_inb(ahc, SCB_NEXT);
5531 break;
5532 }
5533 } else {
5534
5535 prev = next;
5536 next = ahc_inb(ahc, SCB_NEXT);
5537 }
5538 }
5539 ahc_outb(ahc, SCBPTR, curscbptr);
5540
5541 found += ahc_search_untagged_queues(ahc, /*ahc_io_ctx_t*/NULL, target,
5542 channel, lun, status, action);
5543
5544 if (action == SEARCH_COMPLETE)
5545 ahc_release_untagged_queues(ahc);
5546 return (found);
5547 }
5548
5549 int
5550 ahc_search_untagged_queues(struct ahc_softc *ahc, ahc_io_ctx_t ctx,
5551 int target, char channel, int lun, uint32_t status,
5552 ahc_search_action action)
5553 {
5554 struct scb *scb;
5555 int maxtarget;
5556 int found;
5557 int i;
5558
5559 if (action == SEARCH_COMPLETE) {
5560 /*
5561 * Don't attempt to run any queued untagged transactions
5562 * until we are done with the abort process.
5563 */
5564 ahc_freeze_untagged_queues(ahc);
5565 }
5566
5567 found = 0;
5568 i = 0;
5569 if ((ahc->flags & AHC_SCB_BTT) == 0) {
5570
5571 maxtarget = 16;
5572 if (target != CAM_TARGET_WILDCARD) {
5573
5574 i = target;
5575 if (channel == 'B')
5576 i += 8;
5577 maxtarget = i + 1;
5578 }
5579 } else {
5580 maxtarget = 0;
5581 }
5582
5583 for (; i < maxtarget; i++) {
5584 struct scb_tailq *untagged_q;
5585 struct scb *next_scb;
5586
5587 untagged_q = &(ahc->untagged_queues[i]);
5588 next_scb = TAILQ_FIRST(untagged_q);
5589 while (next_scb != NULL) {
5590
5591 scb = next_scb;
5592 next_scb = TAILQ_NEXT(scb, links.tqe);
5593
5594 /*
5595 * The head of the list may be the currently
5596 * active untagged command for a device.
5597 * We're only searching for commands that
5598 * have not been started. A transaction
5599 * marked active but still in the qinfifo
5600 * is removed by the qinfifo scanning code
5601 * above.
5602 */
5603 if ((scb->flags & SCB_ACTIVE) != 0)
5604 continue;
5605
5606 if (ahc_match_scb(ahc, scb, target, channel, lun,
5607 SCB_LIST_NULL, ROLE_INITIATOR) == 0
5608 || (ctx != NULL && ctx != scb->io_ctx))
5609 continue;
5610
5611 /*
5612 * We found an scb that needs to be acted on.
5613 */
5614 found++;
5615 switch (action) {
5616 case SEARCH_COMPLETE:
5617 {
5618 cam_status ostat;
5619 cam_status cstat;
5620
5621 ostat = ahc_get_transaction_status(scb);
5622 if (ostat == CAM_REQ_INPROG)
5623 ahc_set_transaction_status(scb, status);
5624 cstat = ahc_get_transaction_status(scb);
5625 if (cstat != CAM_REQ_CMP)
5626 ahc_freeze_scb(scb);
5627 if ((scb->flags & SCB_ACTIVE) == 0)
5628 printf("Inactive SCB in untaggedQ\n");
5629 ahc_done(ahc, scb);
5630 break;
5631 }
5632 case SEARCH_REMOVE:
5633 scb->flags &= ~SCB_UNTAGGEDQ;
5634 TAILQ_REMOVE(untagged_q, scb, links.tqe);
5635 break;
5636 case SEARCH_COUNT:
5637 break;
5638 }
5639 }
5640 }
5641
5642 if (action == SEARCH_COMPLETE)
5643 ahc_release_untagged_queues(ahc);
5644 return (found);
5645 }
5646
5647 int
5648 ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel,
5649 int lun, u_int tag, int stop_on_first, int remove,
5650 int save_state)
5651 {
5652 struct scb *scbp;
5653 u_int next;
5654 u_int prev;
5655 u_int count;
5656 u_int active_scb;
5657
5658 count = 0;
5659 next = ahc_inb(ahc, DISCONNECTED_SCBH);
5660 prev = SCB_LIST_NULL;
5661
5662 if (save_state) {
5663 /* restore this when we're done */
5664 active_scb = ahc_inb(ahc, SCBPTR);
5665 } else
5666 /* Silence compiler */
5667 active_scb = SCB_LIST_NULL;
5668
5669 while (next != SCB_LIST_NULL) {
5670 u_int scb_index;
5671
5672 ahc_outb(ahc, SCBPTR, next);
5673 scb_index = ahc_inb(ahc, SCB_TAG);
5674 if (scb_index >= ahc->scb_data->numscbs) {
5675 printf("Disconnected List inconsistency. "
5676 "SCB index == %d, yet numscbs == %d.",
5677 scb_index, ahc->scb_data->numscbs);
5678 ahc_dump_card_state(ahc);
5679 panic("for safety");
5680 }
5681
5682 if (next == prev) {
5683 panic("Disconnected List Loop. "
5684 "cur SCBPTR == %x, prev SCBPTR == %x.",
5685 next, prev);
5686 }
5687 scbp = ahc_lookup_scb(ahc, scb_index);
5688 if (ahc_match_scb(ahc, scbp, target, channel, lun,
5689 tag, ROLE_INITIATOR)) {
5690 count++;
5691 if (remove) {
5692 next =
5693 ahc_rem_scb_from_disc_list(ahc, prev, next);
5694 } else {
5695 prev = next;
5696 next = ahc_inb(ahc, SCB_NEXT);
5697 }
5698 if (stop_on_first)
5699 break;
5700 } else {
5701 prev = next;
5702 next = ahc_inb(ahc, SCB_NEXT);
5703 }
5704 }
5705 if (save_state)
5706 ahc_outb(ahc, SCBPTR, active_scb);
5707 return (count);
5708 }
5709
5710 /*
5711 * Remove an SCB from the on chip list of disconnected transactions.
5712 * This is empty/unused if we are not performing SCB paging.
5713 */
5714 static u_int
5715 ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr)
5716 {
5717 u_int next;
5718
5719 ahc_outb(ahc, SCBPTR, scbptr);
5720 next = ahc_inb(ahc, SCB_NEXT);
5721
5722 ahc_outb(ahc, SCB_CONTROL, 0);
5723
5724 ahc_add_curscb_to_free_list(ahc);
5725
5726 if (prev != SCB_LIST_NULL) {
5727 ahc_outb(ahc, SCBPTR, prev);
5728 ahc_outb(ahc, SCB_NEXT, next);
5729 } else
5730 ahc_outb(ahc, DISCONNECTED_SCBH, next);
5731
5732 return (next);
5733 }
5734
5735 /*
5736 * Add the SCB as selected by SCBPTR onto the on chip list of
5737 * free hardware SCBs. This list is empty/unused if we are not
5738 * performing SCB paging.
5739 */
5740 static void
5741 ahc_add_curscb_to_free_list(struct ahc_softc *ahc)
5742 {
5743 /*
5744 * Invalidate the tag so that our abort
5745 * routines don't think it's active.
5746 */
5747 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL);
5748
5749 if ((ahc->flags & AHC_PAGESCBS) != 0) {
5750 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH));
5751 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR));
5752 }
5753 }
5754
5755 /*
5756 * Manipulate the waiting for selection list and return the
5757 * scb that follows the one that we remove.
5758 */
5759 static u_int
5760 ahc_rem_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev)
5761 {
5762 u_int curscb, next;
5763
5764 /*
5765 * Select the SCB we want to abort and
5766 * pull the next pointer out of it.
5767 */
5768 curscb = ahc_inb(ahc, SCBPTR);
5769 ahc_outb(ahc, SCBPTR, scbpos);
5770 next = ahc_inb(ahc, SCB_NEXT);
5771
5772 /* Clear the necessary fields */
5773 ahc_outb(ahc, SCB_CONTROL, 0);
5774
5775 ahc_add_curscb_to_free_list(ahc);
5776
5777 /* update the waiting list */
5778 if (prev == SCB_LIST_NULL) {
5779 /* First in the list */
5780 ahc_outb(ahc, WAITING_SCBH, next);
5781
5782 /*
5783 * Ensure we aren't attempting to perform
5784 * selection for this entry.
5785 */
5786 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
5787 } else {
5788 /*
5789 * Select the scb that pointed to us
5790 * and update its next pointer.
5791 */
5792 ahc_outb(ahc, SCBPTR, prev);
5793 ahc_outb(ahc, SCB_NEXT, next);
5794 }
5795
5796 /*
5797 * Point us back at the original scb position.
5798 */
5799 ahc_outb(ahc, SCBPTR, curscb);
5800 return next;
5801 }
5802
5803 /******************************** Error Handling ******************************/
5804 /*
5805 * Abort all SCBs that match the given description (target/channel/lun/tag),
5806 * setting their status to the passed in status if the status has not already
5807 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer
5808 * is paused before it is called.
5809 */
5810 int
5811 ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel,
5812 int lun, u_int tag, role_t role, uint32_t status)
5813 {
5814 struct scb *scbp;
5815 struct scb *scbp_next;
5816 u_int active_scb;
5817 int i, j;
5818 int maxtarget;
5819 int minlun;
5820 int maxlun;
5821
5822 int found;
5823
5824 /*
5825 * Don't attempt to run any queued untagged transactions
5826 * until we are done with the abort process.
5827 */
5828 ahc_freeze_untagged_queues(ahc);
5829
5830 /* restore this when we're done */
5831 active_scb = ahc_inb(ahc, SCBPTR);
5832
5833 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL,
5834 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE);
5835
5836 /*
5837 * Clean out the busy target table for any untagged commands.
5838 */
5839 i = 0;
5840 maxtarget = 16;
5841 if (target != CAM_TARGET_WILDCARD) {
5842 i = target;
5843 if (channel == 'B')
5844 i += 8;
5845 maxtarget = i + 1;
5846 }
5847
5848 if (lun == CAM_LUN_WILDCARD) {
5849
5850 /*
5851 * Unless we are using an SCB based
5852 * busy targets table, there is only
5853 * one table entry for all luns of
5854 * a target.
5855 */
5856 minlun = 0;
5857 maxlun = 1;
5858 if ((ahc->flags & AHC_SCB_BTT) != 0)
5859 maxlun = AHC_NUM_LUNS;
5860 } else {
5861 minlun = lun;
5862 maxlun = lun + 1;
5863 }
5864
5865 if (role != ROLE_TARGET) {
5866 for (;i < maxtarget; i++) {
5867 for (j = minlun;j < maxlun; j++) {
5868 u_int scbid;
5869 u_int tcl;
5870
5871 tcl = BUILD_TCL(i << 4, j);
5872 scbid = ahc_index_busy_tcl(ahc, tcl);
5873 scbp = ahc_lookup_scb(ahc, scbid);
5874 if (scbp == NULL
5875 || ahc_match_scb(ahc, scbp, target, channel,
5876 lun, tag, role) == 0)
5877 continue;
5878 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, j));
5879 }
5880 }
5881
5882 /*
5883 * Go through the disconnected list and remove any entries we
5884 * have queued for completion, 0'ing their control byte too.
5885 * We save the active SCB and restore it ourselves, so there
5886 * is no reason for this search to restore it too.
5887 */
5888 ahc_search_disc_list(ahc, target, channel, lun, tag,
5889 /*stop_on_first*/FALSE, /*remove*/TRUE,
5890 /*save_state*/FALSE);
5891 }
5892
5893 /*
5894 * Go through the hardware SCB array looking for commands that
5895 * were active but not on any list. In some cases, these remnants
5896 * might not still have mappings in the scbindex array (e.g. unexpected
5897 * bus free with the same scb queued for an abort). Don't hold this
5898 * against them.
5899 */
5900 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
5901 u_int scbid;
5902
5903 ahc_outb(ahc, SCBPTR, i);
5904 scbid = ahc_inb(ahc, SCB_TAG);
5905 scbp = ahc_lookup_scb(ahc, scbid);
5906 if ((scbp == NULL && scbid != SCB_LIST_NULL)
5907 || (scbp != NULL
5908 && ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)))
5909 ahc_add_curscb_to_free_list(ahc);
5910 }
5911
5912 /*
5913 * Go through the pending CCB list and look for
5914 * commands for this target that are still active.
5915 * These are other tagged commands that were
5916 * disconnected when the reset occurred.
5917 */
5918 scbp_next = LIST_FIRST(&ahc->pending_scbs);
5919 while (scbp_next != NULL) {
5920 scbp = scbp_next;
5921 scbp_next = LIST_NEXT(scbp, pending_links);
5922 if (ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) {
5923 cam_status ostat;
5924
5925 ostat = ahc_get_transaction_status(scbp);
5926 if (ostat == CAM_REQ_INPROG)
5927 ahc_set_transaction_status(scbp, status);
5928 if (ahc_get_transaction_status(scbp) != CAM_REQ_CMP)
5929 ahc_freeze_scb(scbp);
5930 if ((scbp->flags & SCB_ACTIVE) == 0)
5931 printf("Inactive SCB on pending list\n");
5932 ahc_done(ahc, scbp);
5933 found++;
5934 }
5935 }
5936 ahc_outb(ahc, SCBPTR, active_scb);
5937 ahc_platform_abort_scbs(ahc, target, channel, lun, tag, role, status);
5938 ahc_release_untagged_queues(ahc);
5939 return found;
5940 }
5941
5942 static void
5943 ahc_reset_current_bus(struct ahc_softc *ahc)
5944 {
5945 uint8_t scsiseq;
5946
5947 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST);
5948 scsiseq = ahc_inb(ahc, SCSISEQ);
5949 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO);
5950 ahc_flush_device_writes(ahc);
5951 ahc_delay(AHC_BUSRESET_DELAY);
5952 /* Turn off the bus reset */
5953 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO);
5954
5955 ahc_clear_intstat(ahc);
5956
5957 /* Re-enable reset interrupts */
5958 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST);
5959 }
5960
5961 int
5962 ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset)
5963 {
5964 struct ahc_devinfo devinfo;
5965 u_int initiator, target, max_scsiid;
5966 u_int sblkctl;
5967 u_int scsiseq;
5968 u_int simode1;
5969 int found;
5970 int restart_needed;
5971 char cur_channel;
5972
5973 ahc->pending_device = NULL;
5974
5975 ahc_compile_devinfo(&devinfo,
5976 CAM_TARGET_WILDCARD,
5977 CAM_TARGET_WILDCARD,
5978 CAM_LUN_WILDCARD,
5979 channel, ROLE_UNKNOWN);
5980 ahc_pause(ahc);
5981
5982 /* Make sure the sequencer is in a safe location. */
5983 ahc_clear_critical_section(ahc);
5984
5985 /*
5986 * Run our command complete fifos to ensure that we perform
5987 * completion processing on any commands that 'completed'
5988 * before the reset occurred.
5989 */
5990 ahc_run_qoutfifo(ahc);
5991 #ifdef AHC_TARGET_MODE
5992 /*
5993 * XXX - In Twin mode, the tqinfifo may have commands
5994 * for an unaffected channel in it. However, if
5995 * we have run out of ATIO resources to drain that
5996 * queue, we may not get them all out here. Further,
5997 * the blocked transactions for the reset channel
5998 * should just be killed off, irrespecitve of whether
5999 * we are blocked on ATIO resources. Write a routine
6000 * to compact the tqinfifo appropriately.
6001 */
6002 if ((ahc->flags & AHC_TARGETROLE) != 0) {
6003 ahc_run_tqinfifo(ahc, /*paused*/TRUE);
6004 }
6005 #endif
6006
6007 /*
6008 * Reset the bus if we are initiating this reset
6009 */
6010 sblkctl = ahc_inb(ahc, SBLKCTL);
6011 cur_channel = 'A';
6012 if ((ahc->features & AHC_TWIN) != 0
6013 && ((sblkctl & SELBUSB) != 0))
6014 cur_channel = 'B';
6015 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
6016 if (cur_channel != channel) {
6017 /* Case 1: Command for another bus is active
6018 * Stealthily reset the other bus without
6019 * upsetting the current bus.
6020 */
6021