1 /*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
10 * The bridge optimization stuff has been removed. If you really
11 * have a silly BIOS which is unable to set your host bridge right,
12 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
13 */
14
15 #include <linux/config.h>
16 #include <linux/types.h>
17 #include <linux/kernel.h>
18 #include <linux/pci.h>
19 #include <linux/init.h>
20 #include <linux/delay.h>
21
22 #undef DEBUG
23
24 /* Deal with broken BIOS'es that neglect to enable passive release,
25 which can cause problems in combination with the 82441FX/PPro MTRRs */
26 static void __devinit quirk_passive_release(struct pci_dev *dev)
27 {
28 struct pci_dev *d = NULL;
29 unsigned char dlc;
30
31 /* We have to make sure a particular bit is set in the PIIX3
32 ISA bridge, so we have to go out and find it. */
33 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
34 pci_read_config_byte(d, 0x82, &dlc);
35 if (!(dlc & 1<<1)) {
36 printk(KERN_ERR "PCI: PIIX3: Enabling Passive Release on %s\n", pci_name(d));
37 dlc |= 1<<1;
38 pci_write_config_byte(d, 0x82, dlc);
39 }
40 }
41 }
42 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release );
43
44 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
45 but VIA don't answer queries. If you happen to have good contacts at VIA
46 ask them for me please -- Alan
47
48 This appears to be BIOS not version dependent. So presumably there is a
49 chipset level fix */
50 int isa_dma_bridge_buggy; /* Exported */
51
52 static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
53 {
54 if (!isa_dma_bridge_buggy) {
55 isa_dma_bridge_buggy=1;
56 printk(KERN_INFO "Activating ISA DMA hang workarounds.\n");
57 }
58 }
59 /*
60 * Its not totally clear which chipsets are the problematic ones
61 * We know 82C586 and 82C596 variants are affected.
62 */
63 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs );
64 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs );
65 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs );
66 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs );
67 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs );
68 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs );
69 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs );
70
71 int pci_pci_problems;
72
73 /*
74 * Chipsets where PCI->PCI transfers vanish or hang
75 */
76 static void __devinit quirk_nopcipci(struct pci_dev *dev)
77 {
78 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
79 printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n");
80 pci_pci_problems |= PCIPCI_FAIL;
81 }
82 }
83 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci );
84 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci );
85
86 /*
87 * Triton requires workarounds to be used by the drivers
88 */
89 static void __devinit quirk_triton(struct pci_dev *dev)
90 {
91 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
92 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
93 pci_pci_problems |= PCIPCI_TRITON;
94 }
95 }
96 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton );
97 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton );
98 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton );
99 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton );
100
101 /*
102 * VIA Apollo KT133 needs PCI latency patch
103 * Made according to a windows driver based patch by George E. Breese
104 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
105 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
106 * the info on which Mr Breese based his work.
107 *
108 * Updated based on further information from the site and also on
109 * information provided by VIA
110 */
111 static void __devinit quirk_vialatency(struct pci_dev *dev)
112 {
113 struct pci_dev *p;
114 u8 rev;
115 u8 busarb;
116 /* Ok we have a potential problem chipset here. Now see if we have
117 a buggy southbridge */
118
119 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
120 if (p!=NULL) {
121 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
122 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
123 /* Check for buggy part revisions */
124 if (rev < 0x40 || rev > 0x42)
125 goto exit;
126 } else {
127 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
128 if (p==NULL) /* No problem parts */
129 goto exit;
130 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
131 /* Check for buggy part revisions */
132 if (rev < 0x10 || rev > 0x12)
133 goto exit;
134 }
135
136 /*
137 * Ok we have the problem. Now set the PCI master grant to
138 * occur every master grant. The apparent bug is that under high
139 * PCI load (quite common in Linux of course) you can get data
140 * loss when the CPU is held off the bus for 3 bus master requests
141 * This happens to include the IDE controllers....
142 *
143 * VIA only apply this fix when an SB Live! is present but under
144 * both Linux and Windows this isnt enough, and we have seen
145 * corruption without SB Live! but with things like 3 UDMA IDE
146 * controllers. So we ignore that bit of the VIA recommendation..
147 */
148
149 pci_read_config_byte(dev, 0x76, &busarb);
150 /* Set bit 4 and bi 5 of byte 76 to 0x01
151 "Master priority rotation on every PCI master grant */
152 busarb &= ~(1<<5);
153 busarb |= (1<<4);
154 pci_write_config_byte(dev, 0x76, busarb);
155 printk(KERN_INFO "Applying VIA southbridge workaround.\n");
156 exit:
157 pci_dev_put(p);
158 }
159 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency );
160 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency );
161 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency );
162
163 /*
164 * VIA Apollo VP3 needs ETBF on BT848/878
165 */
166 static void __devinit quirk_viaetbf(struct pci_dev *dev)
167 {
168 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
169 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
170 pci_pci_problems |= PCIPCI_VIAETBF;
171 }
172 }
173 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf );
174
175 static void __devinit quirk_vsfx(struct pci_dev *dev)
176 {
177 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
178 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
179 pci_pci_problems |= PCIPCI_VSFX;
180 }
181 }
182 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx );
183
184 /*
185 * Ali Magik requires workarounds to be used by the drivers
186 * that DMA to AGP space. Latency must be set to 0xA and triton
187 * workaround applied too
188 * [Info kindly provided by ALi]
189 */
190 static void __init quirk_alimagik(struct pci_dev *dev)
191 {
192 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
193 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
194 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
195 }
196 }
197 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik );
198 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik );
199
200 /*
201 * Natoma has some interesting boundary conditions with Zoran stuff
202 * at least
203 */
204 static void __devinit quirk_natoma(struct pci_dev *dev)
205 {
206 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
207 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
208 pci_pci_problems |= PCIPCI_NATOMA;
209 }
210 }
211 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma );
212 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma );
213 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma );
214 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma );
215 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma );
216 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma );
217
218 /*
219 * This chip can cause PCI parity errors if config register 0xA0 is read
220 * while DMAs are occurring.
221 */
222 static void __devinit quirk_citrine(struct pci_dev *dev)
223 {
224 dev->cfg_size = 0xA0;
225 }
226 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine );
227
228 /*
229 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
230 * If it's needed, re-allocate the region.
231 */
232 static void __devinit quirk_s3_64M(struct pci_dev *dev)
233 {
234 struct resource *r = &dev->resource[0];
235
236 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
237 r->start = 0;
238 r->end = 0x3ffffff;
239 }
240 }
241 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M );
242 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M );
243
244 static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region, unsigned size, int nr)
245 {
246 region &= ~(size-1);
247 if (region) {
248 struct resource *res = dev->resource + nr;
249
250 res->name = pci_name(dev);
251 res->start = region;
252 res->end = region + size - 1;
253 res->flags = IORESOURCE_IO;
254 pci_claim_resource(dev, nr);
255 }
256 }
257
258 /*
259 * ATI Northbridge setups MCE the processor if you even
260 * read somewhere between 0x3b0->0x3bb or read 0x3d3
261 */
262 static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
263 {
264 printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n");
265 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
266 request_region(0x3b0, 0x0C, "RadeonIGP");
267 request_region(0x3d3, 0x01, "RadeonIGP");
268 }
269 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce );
270
271 /*
272 * Let's make the southbridge information explicit instead
273 * of having to worry about people probing the ACPI areas,
274 * for example.. (Yes, it happens, and if you read the wrong
275 * ACPI register it will put the machine to sleep with no
276 * way of waking it up again. Bummer).
277 *
278 * ALI M7101: Two IO regions pointed to by words at
279 * 0xE0 (64 bytes of ACPI registers)
280 * 0xE2 (32 bytes of SMB registers)
281 */
282 static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
283 {
284 u16 region;
285
286 pci_read_config_word(dev, 0xE0, ®ion);
287 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES);
288 pci_read_config_word(dev, 0xE2, ®ion);
289 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1);
290 }
291 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi );
292
293 /*
294 * PIIX4 ACPI: Two IO regions pointed to by longwords at
295 * 0x40 (64 bytes of ACPI registers)
296 * 0x90 (32 bytes of SMB registers)
297 */
298 static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
299 {
300 u32 region;
301
302 pci_read_config_dword(dev, 0x40, ®ion);
303 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES);
304 pci_read_config_dword(dev, 0x90, ®ion);
305 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1);
306 }
307 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi );
308
309 /*
310 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
311 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
312 * 0x58 (64 bytes of GPIO I/O space)
313 */
314 static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
315 {
316 u32 region;
317
318 pci_read_config_dword(dev, 0x40, ®ion);
319 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES);
320
321 pci_read_config_dword(dev, 0x58, ®ion);
322 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1);
323 }
324 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi );
325 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi );
326 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi );
327 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi );
328 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi );
329 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi );
330 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi );
331 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi );
332 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi );
333
334 /*
335 * VIA ACPI: One IO region pointed to by longword at
336 * 0x48 or 0x20 (256 bytes of ACPI registers)
337 */
338 static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
339 {
340 u8 rev;
341 u32 region;
342
343 pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
344 if (rev & 0x10) {
345 pci_read_config_dword(dev, 0x48, ®ion);
346 region &= PCI_BASE_ADDRESS_IO_MASK;
347 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES);
348 }
349 }
350 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi );
351
352 /*
353 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
354 * 0x48 (256 bytes of ACPI registers)
355 * 0x70 (128 bytes of hardware monitoring register)
356 * 0x90 (16 bytes of SMB registers)
357 */
358 static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
359 {
360 u16 hm;
361 u32 smb;
362
363 quirk_vt82c586_acpi(dev);
364
365 pci_read_config_word(dev, 0x70, &hm);
366 hm &= PCI_BASE_ADDRESS_IO_MASK;
367 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1);
368
369 pci_read_config_dword(dev, 0x90, &smb);
370 smb &= PCI_BASE_ADDRESS_IO_MASK;
371 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2);
372 }
373 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi );
374
375
376 #ifdef CONFIG_X86_IO_APIC
377
378 #include <asm/io_apic.h>
379
380 /*
381 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
382 * devices to the external APIC.
383 *
384 * TODO: When we have device-specific interrupt routers,
385 * this code will go away from quirks.
386 */
387 static void __devinit quirk_via_ioapic(struct pci_dev *dev)
388 {
389 u8 tmp;
390
391 if (nr_ioapics < 1)
392 tmp = 0; /* nothing routed to external APIC */
393 else
394 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
395
396 printk(KERN_INFO "PCI: %sbling Via external APIC routing\n",
397 tmp == 0 ? "Disa" : "Ena");
398
399 /* Offset 0x58: External APIC IRQ output control */
400 pci_write_config_byte (dev, 0x58, tmp);
401 }
402 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic );
403
404 /*
405 * The AMD io apic can hang the box when an apic irq is masked.
406 * We check all revs >= B0 (yet not in the pre production!) as the bug
407 * is currently marked NoFix
408 *
409 * We have multiple reports of hangs with this chipset that went away with
410 * noapic specified. For the moment we assume its the errata. We may be wrong
411 * of course. However the advice is demonstrably good even if so..
412 */
413 static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
414 {
415 u8 rev;
416
417 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
418 if (rev >= 0x02) {
419 printk(KERN_WARNING "I/O APIC: AMD Errata #22 may be present. In the event of instability try\n");
420 printk(KERN_WARNING " : booting with the \"noapic\" option.\n");
421 }
422 }
423 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic );
424
425 static void __init quirk_ioapic_rmw(struct pci_dev *dev)
426 {
427 if (dev->devfn == 0 && dev->bus->number == 0)
428 sis_apic_bug = 1;
429 }
430 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw );
431
432 #define AMD8131_revA0 0x01
433 #define AMD8131_revB0 0x11
434 #define AMD8131_MISC 0x40
435 #define AMD8131_NIOAMODE_BIT 0
436 static void __init quirk_amd_8131_ioapic(struct pci_dev *dev)
437 {
438 unsigned char revid, tmp;
439
440 if (nr_ioapics == 0)
441 return;
442
443 pci_read_config_byte(dev, PCI_REVISION_ID, &revid);
444 if (revid == AMD8131_revA0 || revid == AMD8131_revB0) {
445 printk(KERN_INFO "Fixing up AMD8131 IOAPIC mode\n");
446 pci_read_config_byte( dev, AMD8131_MISC, &tmp);
447 tmp &= ~(1 << AMD8131_NIOAMODE_BIT);
448 pci_write_config_byte( dev, AMD8131_MISC, tmp);
449 }
450 }
451 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_APIC, quirk_amd_8131_ioapic );
452
453 #endif /* CONFIG_X86_IO_APIC */
454
455
456 /*
457 * Via 686A/B: The PCI_INTERRUPT_LINE register for the on-chip
458 * devices, USB0/1, AC97, MC97, and ACPI, has an unusual feature:
459 * when written, it makes an internal connection to the PIC.
460 * For these devices, this register is defined to be 4 bits wide.
461 * Normally this is fine. However for IO-APIC motherboards, or
462 * non-x86 architectures (yes Via exists on PPC among other places),
463 * we must mask the PCI_INTERRUPT_LINE value versus 0xf to get
464 * interrupts delivered properly.
465 *
466 * TODO: When we have device-specific interrupt routers,
467 * quirk_via_irqpic will go away from quirks.
468 */
469
470 /*
471 * FIXME: it is questionable that quirk_via_acpi
472 * is needed. It shows up as an ISA bridge, and does not
473 * support the PCI_INTERRUPT_LINE register at all. Therefore
474 * it seems like setting the pci_dev's 'irq' to the
475 * value of the ACPI SCI interrupt is only done for convenience.
476 * -jgarzik
477 */
478 static void __devinit quirk_via_acpi(struct pci_dev *d)
479 {
480 /*
481 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
482 */
483 u8 irq;
484 pci_read_config_byte(d, 0x42, &irq);
485 irq &= 0xf;
486 if (irq && (irq != 2))
487 d->irq = irq;
488 }
489 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi );
490 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi );
491
492 /*
493 * PIIX3 USB: We have to disable USB interrupts that are
494 * hardwired to PIRQD# and may be shared with an
495 * external device.
496 *
497 * Legacy Support Register (LEGSUP):
498 * bit13: USB PIRQ Enable (USBPIRQDEN),
499 * bit4: Trap/SMI On IRQ Enable (USBSMIEN).
500 *
501 * We mask out all r/wc bits, too.
502 */
503 static void __devinit quirk_piix3_usb(struct pci_dev *dev)
504 {
505 u16 legsup;
506
507 pci_read_config_word(dev, 0xc0, &legsup);
508 legsup &= 0x50ef;
509 pci_write_config_word(dev, 0xc0, legsup);
510 }
511 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_2, quirk_piix3_usb );
512 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_2, quirk_piix3_usb );
513
514 /*
515 * VIA VT82C598 has its device ID settable and many BIOSes
516 * set it to the ID of VT82C597 for backward compatibility.
517 * We need to switch it off to be able to recognize the real
518 * type of the chip.
519 */
520 static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
521 {
522 pci_write_config_byte(dev, 0xfc, 0);
523 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
524 }
525 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id );
526
527 /*
528 * CardBus controllers have a legacy base address that enables them
529 * to respond as i82365 pcmcia controllers. We don't want them to
530 * do this even if the Linux CardBus driver is not loaded, because
531 * the Linux i82365 driver does not (and should not) handle CardBus.
532 */
533 static void __devinit quirk_cardbus_legacy(struct pci_dev *dev)
534 {
535 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
536 return;
537 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
538 }
539 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy );
540
541 /*
542 * Following the PCI ordering rules is optional on the AMD762. I'm not
543 * sure what the designers were smoking but let's not inhale...
544 *
545 * To be fair to AMD, it follows the spec by default, its BIOS people
546 * who turn it off!
547 */
548 static void __devinit quirk_amd_ordering(struct pci_dev *dev)
549 {
550 u32 pcic;
551 pci_read_config_dword(dev, 0x4C, &pcic);
552 if ((pcic&6)!=6) {
553 pcic |= 6;
554 printk(KERN_WARNING "BIOS failed to enable PCI standards compliance, fixing this error.\n");
555 pci_write_config_dword(dev, 0x4C, pcic);
556 pci_read_config_dword(dev, 0x84, &pcic);
557 pcic |= (1<<23); /* Required in this mode */
558 pci_write_config_dword(dev, 0x84, pcic);
559 }
560 }
561 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering );
562
563 /*
564 * DreamWorks provided workaround for Dunord I-3000 problem
565 *
566 * This card decodes and responds to addresses not apparently
567 * assigned to it. We force a larger allocation to ensure that
568 * nothing gets put too close to it.
569 */
570 static void __devinit quirk_dunord ( struct pci_dev * dev )
571 {
572 struct resource *r = &dev->resource [1];
573 r->start = 0;
574 r->end = 0xffffff;
575 }
576 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord );
577
578 /*
579 * i82380FB mobile docking controller: its PCI-to-PCI bridge
580 * is subtractive decoding (transparent), and does indicate this
581 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
582 * instead of 0x01.
583 */
584 static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
585 {
586 dev->transparent = 1;
587 }
588 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge );
589 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge );
590
591 /*
592 * Common misconfiguration of the MediaGX/Geode PCI master that will
593 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
594 * datasheets found at http://www.national.com/ds/GX for info on what
595 * these bits do. <christer@weinigel.se>
596 */
597 static void __init quirk_mediagx_master(struct pci_dev *dev)
598 {
599 u8 reg;
600 pci_read_config_byte(dev, 0x41, ®);
601 if (reg & 2) {
602 reg &= ~2;
603 printk(KERN_INFO "PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
604 pci_write_config_byte(dev, 0x41, reg);
605 }
606 }
607 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master );
608
609 /*
610 * As per PCI spec, ignore base address registers 0-3 of the IDE controllers
611 * running in Compatible mode (bits 0 and 2 in the ProgIf for primary and
612 * secondary channels respectively). If the device reports Compatible mode
613 * but does use BAR0-3 for address decoding, we assume that firmware has
614 * programmed these BARs with standard values (0x1f0,0x3f4 and 0x170,0x374).
615 * Exceptions (if they exist) must be handled in chip/architecture specific
616 * fixups.
617 *
618 * Note: for non x86 people. You may need an arch specific quirk to handle
619 * moving IDE devices to native mode as well. Some plug in card devices power
620 * up in compatible mode and assume the BIOS will adjust them.
621 *
622 * Q: should we load the 0x1f0,0x3f4 into the registers or zap them as
623 * we do now ? We don't want is pci_enable_device to come along
624 * and assign new resources. Both approaches work for that.
625 */
626 static void __devinit quirk_ide_bases(struct pci_dev *dev)
627 {
628 struct resource *res;
629 int first_bar = 2, last_bar = 0;
630
631 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
632 return;
633
634 res = &dev->resource[0];
635
636 /* primary channel: ProgIf bit 0, BAR0, BAR1 */
637 if (!(dev->class & 1) && (res[0].flags || res[1].flags)) {
638 res[0].start = res[0].end = res[0].flags = 0;
639 res[1].start = res[1].end = res[1].flags = 0;
640 first_bar = 0;
641 last_bar = 1;
642 }
643
644 /* secondary channel: ProgIf bit 2, BAR2, BAR3 */
645 if (!(dev->class & 4) && (res[2].flags || res[3].flags)) {
646 res[2].start = res[2].end = res[2].flags = 0;
647 res[3].start = res[3].end = res[3].flags = 0;
648 last_bar = 3;
649 }
650
651 if (!last_bar)
652 return;
653
654 printk(KERN_INFO "PCI: Ignoring BAR%d-%d of IDE controller %s\n",
655 first_bar, last_bar, pci_name(dev));
656 }
657 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_ide_bases );
658
659 /*
660 * Ensure C0 rev restreaming is off. This is normally done by
661 * the BIOS but in the odd case it is not the results are corruption
662 * hence the presence of a Linux check
663 */
664 static void __init quirk_disable_pxb(struct pci_dev *pdev)
665 {
666 u16 config;
667 u8 rev;
668
669 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
670 if (rev != 0x04) /* Only C0 requires this */
671 return;
672 pci_read_config_word(pdev, 0x40, &config);
673 if (config & (1<<6)) {
674 config &= ~(1<<6);
675 pci_write_config_word(pdev, 0x40, config);
676 printk(KERN_INFO "PCI: C0 revision 450NX. Disabling PCI restreaming.\n");
677 }
678 }
679 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb );
680
681 /*
682 * VIA northbridges care about PCI_INTERRUPT_LINE
683 */
684 int via_interrupt_line_quirk;
685
686 static void __devinit quirk_via_bridge(struct pci_dev *pdev)
687 {
688 if(pdev->devfn == 0) {
689 printk(KERN_INFO "PCI: Via IRQ fixup\n");
690 via_interrupt_line_quirk = 1;
691 }
692 }
693 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_bridge );
694
695 /*
696 * Serverworks CSB5 IDE does not fully support native mode
697 */
698 static void __init quirk_svwks_csb5ide(struct pci_dev *pdev)
699 {
700 u8 prog;
701 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
702 if (prog & 5) {
703 prog &= ~5;
704 pdev->class &= ~5;
705 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
706 /* need to re-assign BARs for compat mode */
707 quirk_ide_bases(pdev);
708 }
709 }
710 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide );
711
712 /*
713 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
714 */
715 static void __init quirk_ide_samemode(struct pci_dev *pdev)
716 {
717 u8 prog;
718
719 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
720
721 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
722 printk(KERN_INFO "PCI: IDE mode mismatch; forcing legacy mode\n");
723 prog &= ~5;
724 pdev->class &= ~5;
725 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
726 /* need to re-assign BARs for compat mode */
727 quirk_ide_bases(pdev);
728 }
729 }
730 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
731
732 /* This was originally an Alpha specific thing, but it really fits here.
733 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
734 */
735 static void __init quirk_eisa_bridge(struct pci_dev *dev)
736 {
737 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
738 }
739 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge );
740
741 /*
742 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
743 * is not activated. The myth is that Asus said that they do not want the
744 * users to be irritated by just another PCI Device in the Win98 device
745 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
746 * package 2.7.0 for details)
747 *
748 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
749 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
750 * becomes necessary to do this tweak in two steps -- I've chosen the Host
751 * bridge as trigger.
752 */
753 static int __initdata asus_hides_smbus = 0;
754
755 static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
756 {
757 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
758 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
759 switch(dev->subsystem_device) {
760 case 0x8070: /* P4B */
761 case 0x8088: /* P4B533 */
762 case 0x1626: /* L3C notebook */
763 asus_hides_smbus = 1;
764 }
765 if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
766 switch(dev->subsystem_device) {
767 case 0x80b1: /* P4GE-V */
768 case 0x80b2: /* P4PE */
769 case 0x8093: /* P4B533-V */
770 asus_hides_smbus = 1;
771 }
772 if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
773 switch(dev->subsystem_device) {
774 case 0x8030: /* P4T533 */
775 asus_hides_smbus = 1;
776 }
777 if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
778 switch (dev->subsystem_device) {
779 case 0x8070: /* P4G8X Deluxe */
780 asus_hides_smbus = 1;
781 }
782 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
783 switch (dev->subsystem_device) {
784 case 0x1751: /* M2N notebook */
785 asus_hides_smbus = 1;
786 }
787 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
788 switch (dev->subsystem_device) {
789 case 0x186a: /* M6Ne notebook */
790 asus_hides_smbus = 1;
791 }
792 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
793 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
794 switch(dev->subsystem_device) {
795 case 0x088C: /* HP Compaq nc8000 */
796 case 0x0890: /* HP Compaq nc6000 */
797 asus_hides_smbus = 1;
798 }
799 if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
800 switch (dev->subsystem_device) {
801 case 0x12bc: /* HP D330L */
802 asus_hides_smbus = 1;
803 }
804 }
805 }
806 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge );
807 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge );
808 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge );
809 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge );
810 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge );
811 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge );
812 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge );
813
814 static void __init asus_hides_smbus_lpc(struct pci_dev *dev)
815 {
816 u16 val;
817
818 if (likely(!asus_hides_smbus))
819 return;
820
821 pci_read_config_word(dev, 0xF2, &val);
822 if (val & 0x8) {
823 pci_write_config_word(dev, 0xF2, val & (~0x8));
824 pci_read_config_word(dev, 0xF2, &val);
825 if (val & 0x8)
826 printk(KERN_INFO "PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
827 else
828 printk(KERN_INFO "PCI: Enabled i801 SMBus device\n");
829 }
830 }
831 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc );
832 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc );
833 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc );
834 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc );
835 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc );
836
837 /*
838 * SiS 96x south bridge: BIOS typically hides SMBus device...
839 */
840 static void __init quirk_sis_96x_smbus(struct pci_dev *dev)
841 {
842 u8 val = 0;
843 printk(KERN_INFO "Enabling SiS 96x SMBus.\n");
844 pci_read_config_byte(dev, 0x77, &val);
845 pci_write_config_byte(dev, 0x77, val & ~0x10);
846 pci_read_config_byte(dev, 0x77, &val);
847 }
848
849
850 #define UHCI_USBLEGSUP 0xc0 /* legacy support */
851 #define UHCI_USBCMD 0 /* command register */
852 #define UHCI_USBSTS 2 /* status register */
853 #define UHCI_USBINTR 4 /* interrupt register */
854 #define UHCI_USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */
855 #define UHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */
856 #define UHCI_USBCMD_GRESET (1 << 2) /* Global reset */
857 #define UHCI_USBCMD_CONFIGURE (1 << 6) /* config semaphore */
858 #define UHCI_USBSTS_HALTED (1 << 5) /* HCHalted bit */
859
860 #define OHCI_CONTROL 0x04
861 #define OHCI_CMDSTATUS 0x08
862 #define OHCI_INTRSTATUS 0x0c
863 #define OHCI_INTRENABLE 0x10
864 #define OHCI_INTRDISABLE 0x14
865 #define OHCI_OCR (1 << 3) /* ownership change request */
866 #define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
867 #define OHCI_INTR_OC (1 << 30) /* ownership change */
868
869 #define EHCI_HCC_PARAMS 0x08 /* extended capabilities */
870 #define EHCI_USBCMD 0 /* command register */
871 #define EHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */
872 #define EHCI_USBSTS 4 /* status register */
873 #define EHCI_USBSTS_HALTED (1 << 12) /* HCHalted bit */
874 #define EHCI_USBINTR 8 /* interrupt register */
875 #define EHCI_USBLEGSUP 0 /* legacy support register */
876 #define EHCI_USBLEGSUP_BIOS (1 << 16) /* BIOS semaphore */
877 #define EHCI_USBLEGSUP_OS (1 << 24) /* OS semaphore */
878 #define EHCI_USBLEGCTLSTS 4 /* legacy control/status */
879 #define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */
880
881 int usb_early_handoff __devinitdata = 0;
882 static int __init usb_handoff_early(char *str)
883 {
884 usb_early_handoff = 1;
885 return 0;
886 }
887 __setup("usb-handoff", usb_handoff_early);
888
889 static void __devinit quirk_usb_handoff_uhci(struct pci_dev *pdev)
890 {
891 unsigned long base = 0;
892 int wait_time, delta;
893 u16 val, sts;
894 int i;
895
896 for (i = 0; i < PCI_ROM_RESOURCE; i++)
897 if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) {
898 base = pci_resource_start(pdev, i);
899 break;
900 }
901
902 if (!base)
903 return;
904
905 /*
906 * stop controller
907 */
908 sts = inw(base + UHCI_USBSTS);
909 val = inw(base + UHCI_USBCMD);
910 val &= ~(u16)(UHCI_USBCMD_RUN | UHCI_USBCMD_CONFIGURE);
911 outw(val, base + UHCI_USBCMD);
912
913 /*
914 * wait while it stops if it was running
915 */
916 if ((sts & UHCI_USBSTS_HALTED) == 0)
917 {
918 wait_time = 1000;
919 delta = 100;
920
921 do {
922 outw(0x1f, base + UHCI_USBSTS);
923 udelay(delta);
924 wait_time -= delta;
925 val = inw(base + UHCI_USBSTS);
926 if (val & UHCI_USBSTS_HALTED)
927 break;
928 } while (wait_time > 0);
929 }
930
931 /*
932 * disable interrupts & legacy support
933 */
934 outw(0, base + UHCI_USBINTR);
935 outw(0x1f, base + UHCI_USBSTS);
936 pci_read_config_word(pdev, UHCI_USBLEGSUP, &val);
937 if (val & 0xbf)
938 pci_write_config_word(pdev, UHCI_USBLEGSUP, UHCI_USBLEGSUP_DEFAULT);
939
940 }
941
942 static void __devinit quirk_usb_handoff_ohci(struct pci_dev *pdev)
943 {
944 void __iomem *base;
945 int wait_time;
946
947 base = ioremap_nocache(pci_resource_start(pdev, 0),
948 pci_resource_len(pdev, 0));
949 if (base == NULL) return;
950
951 if (readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) {
952 wait_time = 500; /* 0.5 seconds */
953 writel(OHCI_INTR_OC, base + OHCI_INTRENABLE);
954 writel(OHCI_OCR, base + OHCI_CMDSTATUS);
955 while (wait_time > 0 &&
956 readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) {
957 wait_time -= 10;
958 msleep(10);
959 }
960 }
961
962 /*
963 * disable interrupts
964 */
965 writel(~(u32)0, base + OHCI_INTRDISABLE);
966 writel(~(u32)0, base + OHCI_INTRSTATUS);
967
968 iounmap(base);
969 }
970
971 static void __devinit quirk_usb_disable_ehci(struct pci_dev *pdev)
972 {
973 int wait_time, delta;
974 void __iomem *base, *op_reg_base;
975 u32 hcc_params, val, temp;
976 u8 cap_length;
977
978 base = ioremap_nocache(pci_resource_start(pdev, 0),
979 pci_resource_len(pdev, 0));
980 if (base == NULL) return;
981
982 cap_length = readb(base);
983 op_reg_base = base + cap_length;
984 hcc_params = readl(base + EHCI_HCC_PARAMS);
985 hcc_params = (hcc_params >> 8) & 0xff;
986 if (hcc_params) {
987 pci_read_config_dword(pdev,
988 hcc_params + EHCI_USBLEGSUP,
989 &val);
990 if (((val & 0xff) == 1) && (val & EHCI_USBLEGSUP_BIOS)) {
991 /*
992 * Ok, BIOS is in smm mode, try to hand off...
993 */
994 pci_read_config_dword(pdev,
995 hcc_params + EHCI_USBLEGCTLSTS,
996 &temp);
997 pci_write_config_dword(pdev,
998 hcc_params + EHCI_USBLEGCTLSTS,
999 temp | EHCI_USBLEGCTLSTS_SOOE);
1000 val |= EHCI_USBLEGSUP_OS;
1001 pci_write_config_dword(pdev,
1002 hcc_params + EHCI_USBLEGSUP,
1003 val);
1004
1005 wait_time = 500;
1006 do {
1007 msleep(10);
1008 wait_time -= 10;
1009 pci_read_config_dword(pdev,
1010 hcc_params + EHCI_USBLEGSUP,
1011 &val);
1012 } while (wait_time && (val & EHCI_USBLEGSUP_BIOS));
1013 if (!wait_time) {
1014 /*
1015 * well, possibly buggy BIOS...
1016 */
1017 printk(KERN_WARNING "EHCI early BIOS handoff "
1018 "failed (BIOS bug ?)\n");
1019 pci_write_config_dword(pdev,
1020 hcc_params + EHCI_USBLEGSUP,
1021 EHCI_USBLEGSUP_OS);
1022 pci_write_config_dword(pdev,
1023 hcc_params + EHCI_USBLEGCTLSTS,
1024 0);
1025 }
1026 }
1027 }
1028
1029 /*
1030 * halt EHCI & disable its interrupts in any case
1031 */
1032 val = readl(op_reg_base + EHCI_USBSTS);
1033 if ((val & EHCI_USBSTS_HALTED) == 0) {
1034 val = readl(op_reg_base + EHCI_USBCMD);
1035 val &= ~EHCI_USBCMD_RUN;
1036 writel(val, op_reg_base + EHCI_USBCMD);
1037
1038 wait_time = 2000;
1039 delta = 100;
1040 do {
1041 writel(0x3f, op_reg_base + EHCI_USBSTS);
1042 udelay(delta);
1043 wait_time -= delta;
1044 val = readl(op_reg_base + EHCI_USBSTS);
1045 if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) {
1046 break;
1047 }
1048 } while (wait_time > 0);
1049 }
1050 writel(0, op_reg_base + EHCI_USBINTR);
1051 writel(0x3f, op_reg_base + EHCI_USBSTS);
1052
1053 iounmap(base);
1054
1055 return;
1056 }
1057
1058
1059
1060 static void __devinit quirk_usb_early_handoff(struct pci_dev *pdev)
1061 {
1062 if (!usb_early_handoff)
1063 return;
1064
1065 if (pdev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x00)) { /* UHCI */
1066 quirk_usb_handoff_uhci(pdev);
1067 } else if (pdev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x10)) { /* OHCI */
1068 quirk_usb_handoff_ohci(pdev);
1069 } else if (pdev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x20)) { /* EHCI */
1070 quirk_usb_disable_ehci(pdev);
1071 }
1072
1073 return;
1074 }
1075 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_usb_early_handoff);
1076
1077 /*
1078 * ... This is further complicated by the fact that some SiS96x south
1079 * bridges pretend to be 85C503/5513 instead. In that case see if we
1080 * spotted a compatible north bridge to make sure.
1081 * (pci_find_device doesn't work yet)
1082 *
1083 * We can also enable the sis96x bit in the discovery register..
1084 */
1085 static int __devinitdata sis_96x_compatible = 0;
1086
1087 #define SIS_DETECT_REGISTER 0x40
1088
1089 static void __init quirk_sis_503(struct pci_dev *dev)
1090 {
1091 u8 reg;
1092 u16 devid;
1093
1094 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®);
1095 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1096 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1097 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1098 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1099 return;
1100 }
1101
1102 /* Make people aware that we changed the config.. */
1103 printk(KERN_WARNING "Uncovering SIS%x that hid as a SIS503 (compatible=%d)\n", devid, sis_96x_compatible);
1104
1105 /*
1106 * Ok, it now shows up as a 96x.. The 96x quirks are after
1107 * the 503 quirk in the quirk table, so they'll automatically
1108 * run and enable things like the SMBus device
1109 */
1110 dev->device = devid;
1111 }
1112
1113 static void __init quirk_sis_96x_compatible(struct pci_dev *dev)
1114 {
1115 sis_96x_compatible = 1;
1116 }
1117 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_645, quirk_sis_96x_compatible );
1118 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_646, quirk_sis_96x_compatible );
1119 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_648, quirk_sis_96x_compatible );
1120 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_650, quirk_sis_96x_compatible );
1121 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_651, quirk_sis_96x_compatible );
1122 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_735, quirk_sis_96x_compatible );
1123
1124 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503 );
1125
1126 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus );
1127 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus );
1128 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus );
1129 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus );
1130
1131 #ifdef CONFIG_X86_IO_APIC
1132 static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1133 {
1134 int i;
1135
1136 if ((pdev->class >> 8) != 0xff00)
1137 return;
1138
1139 /* the first BAR is the location of the IO APIC...we must
1140 * not touch this (and it's already covered by the fixmap), so
1141 * forcibly insert it into the resource tree */
1142 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1143 insert_resource(&iomem_resource, &pdev->resource[0]);
1144
1145 /* The next five BARs all seem to be rubbish, so just clean
1146 * them out */
1147 for (i=1; i < 6; i++) {
1148 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1149 }
1150
1151 }
1152 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic );
1153 #endif
1154
1155 #ifdef CONFIG_SCSI_SATA
1156 static void __devinit quirk_intel_ide_combined(struct pci_dev *pdev)
1157 {
1158 u8 prog, comb, tmp;
1159 int ich = 0;
1160
1161 /*
1162 * Narrow down to Intel SATA PCI devices.
1163 */
1164 switch (pdev->device) {
1165 /* PCI ids taken from drivers/scsi/ata_piix.c */
1166 case 0x24d1:
1167 case 0x24df:
1168 case 0x25a3:
1169 case 0x25b0:
1170 ich = 5;
1171 break;
1172 case 0x2651:
1173 case 0x2652:
1174 case 0x2653:
1175 ich = 6;
1176 break;
1177 case 0x27c0:
1178 case 0x27c4:
1179 ich = 7;
1180 break;
1181 default:
1182 /* we do not handle this PCI device */
1183 return;
1184 }
1185
1186 /*
1187 * Read combined mode register.
1188 */
1189 pci_read_config_byte(pdev, 0x90, &tmp); /* combined mode reg */
1190
1191 if (ich == 5) {
1192 tmp &= 0x6; /* interesting bits 2:1, PATA primary/secondary */
1193 if (tmp == 0x4) /* bits 10x */
1194 comb = (1 << 0); /* SATA port 0, PATA port 1 */
1195 else if (tmp == 0x6) /* bits 11x */
1196 comb = (1 << 2); /* PATA port 0, SATA port 1 */
1197 else
1198 return; /* not in combined mode */
1199 } else {
1200 WARN_ON((ich != 6) && (ich != 7));
1201 tmp &= 0x3; /* interesting bits 1:0 */
1202 if (tmp & (1 << 0))
1203 comb = (1 << 2); /* PATA port 0, SATA port 1 */
1204 else if (tmp & (1 << 1))
1205 comb = (1 << 0); /* SATA port 0, PATA port 1 */
1206 else
1207 return; /* not in combined mode */
1208 }
1209
1210 /*
1211 * Read programming interface register.
1212 * (Tells us if it's legacy or native mode)
1213 */
1214 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1215
1216 /* if SATA port is in native mode, we're ok. */
1217 if (prog & comb)
1218 return;
1219
1220 /* SATA port is in legacy mode. Reserve port so that
1221 * IDE driver does not attempt to use it. If request_region
1222 * fails, it will be obvious at boot time, so we don't bother
1223 * checking return values.
1224 */
1225 if (comb == (1 << 0))
1226 request_region(0x1f0, 8, "libata"); /* port 0 */
1227 else
1228 request_region(0x170, 8, "libata"); /* port 1 */
1229 }
1230 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_intel_ide_combined );
1231 #endif /* CONFIG_SCSI_SATA */
1232
1233
1234 int pcie_mch_quirk;
1235
1236 static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1237 {
1238 pcie_mch_quirk = 1;
1239 }
1240 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch );
1241 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch );
1242 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch );
1243
1244 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end)
1245 {
1246 while (f < end) {
1247 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
1248 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
1249 pr_debug("PCI: Calling quirk %p for %s\n", f->hook, pci_name(dev));
1250 f->hook(dev);
1251 }
1252 f++;
1253 }
1254 }
1255
1256 extern struct pci_fixup __start_pci_fixups_early[];
1257 extern struct pci_fixup __end_pci_fixups_early[];
1258 extern struct pci_fixup __start_pci_fixups_header[];
1259 extern struct pci_fixup __end_pci_fixups_header[];
1260 extern struct pci_fixup __start_pci_fixups_final[];
1261 extern struct pci_fixup __end_pci_fixups_final[];
1262 extern struct pci_fixup __start_pci_fixups_enable[];
1263 extern struct pci_fixup __end_pci_fixups_enable[];
1264
1265
1266 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
1267 {
1268 struct pci_fixup *start, *end;
1269
1270 switch(pass) {
1271 case pci_fixup_early:
1272 start = __start_pci_fixups_early;
1273 end = __end_pci_fixups_early;
1274 break;
1275
1276 case pci_fixup_header:
1277 start = __start_pci_fixups_header;
1278 end = __end_pci_fixups_header;
1279 break;
1280
1281 case pci_fixup_final:
1282 start = __start_pci_fixups_final;
1283 end = __end_pci_fixups_final;
1284 break;
1285
1286 case pci_fixup_enable:
1287 start = __start_pci_fixups_enable;
1288 end = __end_pci_fixups_enable;
1289 break;
1290
1291 default:
1292 /* stupid compiler warning, you would think with an enum... */
1293 return;
1294 }
1295 pci_do_fixups(dev, start, end);
1296 }
1297
1298 EXPORT_SYMBOL(pcie_mch_quirk);
1299 #ifdef CONFIG_HOTPLUG
1300 EXPORT_SYMBOL(pci_fixup_device);
1301 #endif
1302
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