1 /*
2 * probe.c - PCI detection and setup code
3 */
4
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
8 #include <linux/pci.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
12 #include "pci.h"
13
14 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
15 #define CARDBUS_RESERVE_BUSNR 3
16 #define PCI_CFG_SPACE_SIZE 256
17 #define PCI_CFG_SPACE_EXP_SIZE 4096
18
19 /* Ugh. Need to stop exporting this to modules. */
20 LIST_HEAD(pci_root_buses);
21 EXPORT_SYMBOL(pci_root_buses);
22
23 LIST_HEAD(pci_devices);
24
25 /*
26 * Some device drivers need know if pci is initiated.
27 * Basically, we think pci is not initiated when there
28 * is no device in list of pci_devices.
29 */
30 int no_pci_devices(void)
31 {
32 return list_empty(&pci_devices);
33 }
34
35 EXPORT_SYMBOL(no_pci_devices);
36
37 #ifdef HAVE_PCI_LEGACY
38 /**
39 * pci_create_legacy_files - create legacy I/O port and memory files
40 * @b: bus to create files under
41 *
42 * Some platforms allow access to legacy I/O port and ISA memory space on
43 * a per-bus basis. This routine creates the files and ties them into
44 * their associated read, write and mmap files from pci-sysfs.c
45 */
46 static void pci_create_legacy_files(struct pci_bus *b)
47 {
48 b->legacy_io = kzalloc(sizeof(struct bin_attribute) * 2,
49 GFP_ATOMIC);
50 if (b->legacy_io) {
51 b->legacy_io->attr.name = "legacy_io";
52 b->legacy_io->size = 0xffff;
53 b->legacy_io->attr.mode = S_IRUSR | S_IWUSR;
54 b->legacy_io->read = pci_read_legacy_io;
55 b->legacy_io->write = pci_write_legacy_io;
56 device_create_bin_file(&b->dev, b->legacy_io);
57
58 /* Allocated above after the legacy_io struct */
59 b->legacy_mem = b->legacy_io + 1;
60 b->legacy_mem->attr.name = "legacy_mem";
61 b->legacy_mem->size = 1024*1024;
62 b->legacy_mem->attr.mode = S_IRUSR | S_IWUSR;
63 b->legacy_mem->mmap = pci_mmap_legacy_mem;
64 device_create_bin_file(&b->dev, b->legacy_mem);
65 }
66 }
67
68 void pci_remove_legacy_files(struct pci_bus *b)
69 {
70 if (b->legacy_io) {
71 device_remove_bin_file(&b->dev, b->legacy_io);
72 device_remove_bin_file(&b->dev, b->legacy_mem);
73 kfree(b->legacy_io); /* both are allocated here */
74 }
75 }
76 #else /* !HAVE_PCI_LEGACY */
77 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
78 void pci_remove_legacy_files(struct pci_bus *bus) { return; }
79 #endif /* HAVE_PCI_LEGACY */
80
81 /*
82 * PCI Bus Class Devices
83 */
84 static ssize_t pci_bus_show_cpuaffinity(struct device *dev,
85 struct device_attribute *attr,
86 char *buf)
87 {
88 int ret;
89 cpumask_t cpumask;
90
91 cpumask = pcibus_to_cpumask(to_pci_bus(dev));
92 ret = cpumask_scnprintf(buf, PAGE_SIZE, cpumask);
93 if (ret < PAGE_SIZE)
94 buf[ret++] = '\n';
95 return ret;
96 }
97 DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpuaffinity, NULL);
98
99 /*
100 * PCI Bus Class
101 */
102 static void release_pcibus_dev(struct device *dev)
103 {
104 struct pci_bus *pci_bus = to_pci_bus(dev);
105
106 if (pci_bus->bridge)
107 put_device(pci_bus->bridge);
108 kfree(pci_bus);
109 }
110
111 static struct class pcibus_class = {
112 .name = "pci_bus",
113 .dev_release = &release_pcibus_dev,
114 };
115
116 static int __init pcibus_class_init(void)
117 {
118 return class_register(&pcibus_class);
119 }
120 postcore_initcall(pcibus_class_init);
121
122 /*
123 * Translate the low bits of the PCI base
124 * to the resource type
125 */
126 static inline unsigned int pci_calc_resource_flags(unsigned int flags)
127 {
128 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
129 return IORESOURCE_IO;
130
131 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
132 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
133
134 return IORESOURCE_MEM;
135 }
136
137 /*
138 * Find the extent of a PCI decode..
139 */
140 static u32 pci_size(u32 base, u32 maxbase, u32 mask)
141 {
142 u32 size = mask & maxbase; /* Find the significant bits */
143 if (!size)
144 return 0;
145
146 /* Get the lowest of them to find the decode size, and
147 from that the extent. */
148 size = (size & ~(size-1)) - 1;
149
150 /* base == maxbase can be valid only if the BAR has
151 already been programmed with all 1s. */
152 if (base == maxbase && ((base | size) & mask) != mask)
153 return 0;
154
155 return size;
156 }
157
158 static u64 pci_size64(u64 base, u64 maxbase, u64 mask)
159 {
160 u64 size = mask & maxbase; /* Find the significant bits */
161 if (!size)
162 return 0;
163
164 /* Get the lowest of them to find the decode size, and
165 from that the extent. */
166 size = (size & ~(size-1)) - 1;
167
168 /* base == maxbase can be valid only if the BAR has
169 already been programmed with all 1s. */
170 if (base == maxbase && ((base | size) & mask) != mask)
171 return 0;
172
173 return size;
174 }
175
176 static inline int is_64bit_memory(u32 mask)
177 {
178 if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
179 (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64))
180 return 1;
181 return 0;
182 }
183
184 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
185 {
186 unsigned int pos, reg, next;
187 u32 l, sz;
188 struct resource *res;
189
190 for(pos=0; pos<howmany; pos = next) {
191 u64 l64;
192 u64 sz64;
193 u32 raw_sz;
194
195 next = pos+1;
196 res = &dev->resource[pos];
197 res->name = pci_name(dev);
198 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
199 pci_read_config_dword(dev, reg, &l);
200 pci_write_config_dword(dev, reg, ~0);
201 pci_read_config_dword(dev, reg, &sz);
202 pci_write_config_dword(dev, reg, l);
203 if (!sz || sz == 0xffffffff)
204 continue;
205 if (l == 0xffffffff)
206 l = 0;
207 raw_sz = sz;
208 if ((l & PCI_BASE_ADDRESS_SPACE) ==
209 PCI_BASE_ADDRESS_SPACE_MEMORY) {
210 sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK);
211 /*
212 * For 64bit prefetchable memory sz could be 0, if the
213 * real size is bigger than 4G, so we need to check
214 * szhi for that.
215 */
216 if (!is_64bit_memory(l) && !sz)
217 continue;
218 res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
219 res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
220 } else {
221 sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
222 if (!sz)
223 continue;
224 res->start = l & PCI_BASE_ADDRESS_IO_MASK;
225 res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
226 }
227 res->end = res->start + (unsigned long) sz;
228 res->flags |= pci_calc_resource_flags(l);
229 if (is_64bit_memory(l)) {
230 u32 szhi, lhi;
231
232 pci_read_config_dword(dev, reg+4, &lhi);
233 pci_write_config_dword(dev, reg+4, ~0);
234 pci_read_config_dword(dev, reg+4, &szhi);
235 pci_write_config_dword(dev, reg+4, lhi);
236 sz64 = ((u64)szhi << 32) | raw_sz;
237 l64 = ((u64)lhi << 32) | l;
238 sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);
239 next++;
240 #if BITS_PER_LONG == 64
241 if (!sz64) {
242 res->start = 0;
243 res->end = 0;
244 res->flags = 0;
245 continue;
246 }
247 res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK;
248 res->end = res->start + sz64;
249 #else
250 if (sz64 > 0x100000000ULL) {
251 printk(KERN_ERR "PCI: Unable to handle 64-bit "
252 "BAR for device %s\n", pci_name(dev));
253 res->start = 0;
254 res->flags = 0;
255 } else if (lhi) {
256 /* 64-bit wide address, treat as disabled */
257 pci_write_config_dword(dev, reg,
258 l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK);
259 pci_write_config_dword(dev, reg+4, 0);
260 res->start = 0;
261 res->end = sz;
262 }
263 #endif
264 }
265 }
266 if (rom) {
267 dev->rom_base_reg = rom;
268 res = &dev->resource[PCI_ROM_RESOURCE];
269 res->name = pci_name(dev);
270 pci_read_config_dword(dev, rom, &l);
271 pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE);
272 pci_read_config_dword(dev, rom, &sz);
273 pci_write_config_dword(dev, rom, l);
274 if (l == 0xffffffff)
275 l = 0;
276 if (sz && sz != 0xffffffff) {
277 sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK);
278 if (sz) {
279 res->flags = (l & IORESOURCE_ROM_ENABLE) |
280 IORESOURCE_MEM | IORESOURCE_PREFETCH |
281 IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
282 res->start = l & PCI_ROM_ADDRESS_MASK;
283 res->end = res->start + (unsigned long) sz;
284 }
285 }
286 }
287 }
288
289 void __devinit pci_read_bridge_bases(struct pci_bus *child)
290 {
291 struct pci_dev *dev = child->self;
292 u8 io_base_lo, io_limit_lo;
293 u16 mem_base_lo, mem_limit_lo;
294 unsigned long base, limit;
295 struct resource *res;
296 int i;
297
298 if (!dev) /* It's a host bus, nothing to read */
299 return;
300
301 if (dev->transparent) {
302 printk(KERN_INFO "PCI: Transparent bridge - %s\n", pci_name(dev));
303 for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++)
304 child->resource[i] = child->parent->resource[i - 3];
305 }
306
307 for(i=0; i<3; i++)
308 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
309
310 res = child->resource[0];
311 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
312 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
313 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
314 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
315
316 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
317 u16 io_base_hi, io_limit_hi;
318 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
319 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
320 base |= (io_base_hi << 16);
321 limit |= (io_limit_hi << 16);
322 }
323
324 if (base <= limit) {
325 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
326 if (!res->start)
327 res->start = base;
328 if (!res->end)
329 res->end = limit + 0xfff;
330 }
331
332 res = child->resource[1];
333 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
334 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
335 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
336 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
337 if (base <= limit) {
338 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
339 res->start = base;
340 res->end = limit + 0xfffff;
341 }
342
343 res = child->resource[2];
344 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
345 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
346 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
347 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
348
349 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
350 u32 mem_base_hi, mem_limit_hi;
351 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
352 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
353
354 /*
355 * Some bridges set the base > limit by default, and some
356 * (broken) BIOSes do not initialize them. If we find
357 * this, just assume they are not being used.
358 */
359 if (mem_base_hi <= mem_limit_hi) {
360 #if BITS_PER_LONG == 64
361 base |= ((long) mem_base_hi) << 32;
362 limit |= ((long) mem_limit_hi) << 32;
363 #else
364 if (mem_base_hi || mem_limit_hi) {
365 printk(KERN_ERR "PCI: Unable to handle 64-bit address space for bridge %s\n", pci_name(dev));
366 return;
367 }
368 #endif
369 }
370 }
371 if (base <= limit) {
372 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH;
373 res->start = base;
374 res->end = limit + 0xfffff;
375 }
376 }
377
378 static struct pci_bus * pci_alloc_bus(void)
379 {
380 struct pci_bus *b;
381
382 b = kzalloc(sizeof(*b), GFP_KERNEL);
383 if (b) {
384 INIT_LIST_HEAD(&b->node);
385 INIT_LIST_HEAD(&b->children);
386 INIT_LIST_HEAD(&b->devices);
387 }
388 return b;
389 }
390
391 static struct pci_bus * __devinit
392 pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr)
393 {
394 struct pci_bus *child;
395 int i;
396
397 /*
398 * Allocate a new bus, and inherit stuff from the parent..
399 */
400 child = pci_alloc_bus();
401 if (!child)
402 return NULL;
403
404 child->self = bridge;
405 child->parent = parent;
406 child->ops = parent->ops;
407 child->sysdata = parent->sysdata;
408 child->bus_flags = parent->bus_flags;
409 child->bridge = get_device(&bridge->dev);
410
411 /* initialize some portions of the bus device, but don't register it
412 * now as the parent is not properly set up yet. This device will get
413 * registered later in pci_bus_add_devices()
414 */
415 child->dev.class = &pcibus_class;
416 sprintf(child->dev.bus_id, "%04x:%02x", pci_domain_nr(child), busnr);
417
418 /*
419 * Set up the primary, secondary and subordinate
420 * bus numbers.
421 */
422 child->number = child->secondary = busnr;
423 child->primary = parent->secondary;
424 child->subordinate = 0xff;
425
426 /* Set up default resource pointers and names.. */
427 for (i = 0; i < 4; i++) {
428 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
429 child->resource[i]->name = child->name;
430 }
431 bridge->subordinate = child;
432
433 return child;
434 }
435
436 struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
437 {
438 struct pci_bus *child;
439
440 child = pci_alloc_child_bus(parent, dev, busnr);
441 if (child) {
442 down_write(&pci_bus_sem);
443 list_add_tail(&child->node, &parent->children);
444 up_write(&pci_bus_sem);
445 }
446 return child;
447 }
448
449 static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
450 {
451 struct pci_bus *parent = child->parent;
452
453 /* Attempts to fix that up are really dangerous unless
454 we're going to re-assign all bus numbers. */
455 if (!pcibios_assign_all_busses())
456 return;
457
458 while (parent->parent && parent->subordinate < max) {
459 parent->subordinate = max;
460 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
461 parent = parent->parent;
462 }
463 }
464
465 /*
466 * If it's a bridge, configure it and scan the bus behind it.
467 * For CardBus bridges, we don't scan behind as the devices will
468 * be handled by the bridge driver itself.
469 *
470 * We need to process bridges in two passes -- first we scan those
471 * already configured by the BIOS and after we are done with all of
472 * them, we proceed to assigning numbers to the remaining buses in
473 * order to avoid overlaps between old and new bus numbers.
474 */
475 int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
476 {
477 struct pci_bus *child;
478 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
479 u32 buses, i, j = 0;
480 u16 bctl;
481
482 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
483
484 pr_debug("PCI: Scanning behind PCI bridge %s, config %06x, pass %d\n",
485 pci_name(dev), buses & 0xffffff, pass);
486
487 /* Disable MasterAbortMode during probing to avoid reporting
488 of bus errors (in some architectures) */
489 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
490 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
491 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
492
493 if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) {
494 unsigned int cmax, busnr;
495 /*
496 * Bus already configured by firmware, process it in the first
497 * pass and just note the configuration.
498 */
499 if (pass)
500 goto out;
501 busnr = (buses >> 8) & 0xFF;
502
503 /*
504 * If we already got to this bus through a different bridge,
505 * ignore it. This can happen with the i450NX chipset.
506 */
507 if (pci_find_bus(pci_domain_nr(bus), busnr)) {
508 printk(KERN_INFO "PCI: Bus %04x:%02x already known\n",
509 pci_domain_nr(bus), busnr);
510 goto out;
511 }
512
513 child = pci_add_new_bus(bus, dev, busnr);
514 if (!child)
515 goto out;
516 child->primary = buses & 0xFF;
517 child->subordinate = (buses >> 16) & 0xFF;
518 child->bridge_ctl = bctl;
519
520 cmax = pci_scan_child_bus(child);
521 if (cmax > max)
522 max = cmax;
523 if (child->subordinate > max)
524 max = child->subordinate;
525 } else {
526 /*
527 * We need to assign a number to this bus which we always
528 * do in the second pass.
529 */
530 if (!pass) {
531 if (pcibios_assign_all_busses())
532 /* Temporarily disable forwarding of the
533 configuration cycles on all bridges in
534 this bus segment to avoid possible
535 conflicts in the second pass between two
536 bridges programmed with overlapping
537 bus ranges. */
538 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
539 buses & ~0xffffff);
540 goto out;
541 }
542
543 /* Clear errors */
544 pci_write_config_word(dev, PCI_STATUS, 0xffff);
545
546 /* Prevent assigning a bus number that already exists.
547 * This can happen when a bridge is hot-plugged */
548 if (pci_find_bus(pci_domain_nr(bus), max+1))
549 goto out;
550 child = pci_add_new_bus(bus, dev, ++max);
551 buses = (buses & 0xff000000)
552 | ((unsigned int)(child->primary) << 0)
553 | ((unsigned int)(child->secondary) << 8)
554 | ((unsigned int)(child->subordinate) << 16);
555
556 /*
557 * yenta.c forces a secondary latency timer of 176.
558 * Copy that behaviour here.
559 */
560 if (is_cardbus) {
561 buses &= ~0xff000000;
562 buses |= CARDBUS_LATENCY_TIMER << 24;
563 }
564
565 /*
566 * We need to blast all three values with a single write.
567 */
568 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
569
570 if (!is_cardbus) {
571 child->bridge_ctl = bctl;
572 /*
573 * Adjust subordinate busnr in parent buses.
574 * We do this before scanning for children because
575 * some devices may not be detected if the bios
576 * was lazy.
577 */
578 pci_fixup_parent_subordinate_busnr(child, max);
579 /* Now we can scan all subordinate buses... */
580 max = pci_scan_child_bus(child);
581 /*
582 * now fix it up again since we have found
583 * the real value of max.
584 */
585 pci_fixup_parent_subordinate_busnr(child, max);
586 } else {
587 /*
588 * For CardBus bridges, we leave 4 bus numbers
589 * as cards with a PCI-to-PCI bridge can be
590 * inserted later.
591 */
592 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
593 struct pci_bus *parent = bus;
594 if (pci_find_bus(pci_domain_nr(bus),
595 max+i+1))
596 break;
597 while (parent->parent) {
598 if ((!pcibios_assign_all_busses()) &&
599 (parent->subordinate > max) &&
600 (parent->subordinate <= max+i)) {
601 j = 1;
602 }
603 parent = parent->parent;
604 }
605 if (j) {
606 /*
607 * Often, there are two cardbus bridges
608 * -- try to leave one valid bus number
609 * for each one.
610 */
611 i /= 2;
612 break;
613 }
614 }
615 max += i;
616 pci_fixup_parent_subordinate_busnr(child, max);
617 }
618 /*
619 * Set the subordinate bus number to its real value.
620 */
621 child->subordinate = max;
622 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
623 }
624
625 sprintf(child->name, (is_cardbus ? "PCI CardBus #%02x" : "PCI Bus #%02x"), child->number);
626
627 /* Has only triggered on CardBus, fixup is in yenta_socket */
628 while (bus->parent) {
629 if ((child->subordinate > bus->subordinate) ||
630 (child->number > bus->subordinate) ||
631 (child->number < bus->number) ||
632 (child->subordinate < bus->number)) {
633 pr_debug("PCI: Bus #%02x (-#%02x) is %s "
634 "hidden behind%s bridge #%02x (-#%02x)\n",
635 child->number, child->subordinate,
636 (bus->number > child->subordinate &&
637 bus->subordinate < child->number) ?
638 "wholly" : "partially",
639 bus->self->transparent ? " transparent" : "",
640 bus->number, bus->subordinate);
641 }
642 bus = bus->parent;
643 }
644
645 out:
646 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
647
648 return max;
649 }
650
651 /*
652 * Read interrupt line and base address registers.
653 * The architecture-dependent code can tweak these, of course.
654 */
655 static void pci_read_irq(struct pci_dev *dev)
656 {
657 unsigned char irq;
658
659 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
660 dev->pin = irq;
661 if (irq)
662 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
663 dev->irq = irq;
664 }
665
666 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
667
668 /**
669 * pci_setup_device - fill in class and map information of a device
670 * @dev: the device structure to fill
671 *
672 * Initialize the device structure with information about the device's
673 * vendor,class,memory and IO-space addresses,IRQ lines etc.
674 * Called at initialisation of the PCI subsystem and by CardBus services.
675 * Returns 0 on success and -1 if unknown type of device (not normal, bridge
676 * or CardBus).
677 */
678 static int pci_setup_device(struct pci_dev * dev)
679 {
680 u32 class;
681
682 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
683 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
684
685 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
686 dev->revision = class & 0xff;
687 class >>= 8; /* upper 3 bytes */
688 dev->class = class;
689 class >>= 8;
690
691 pr_debug("PCI: Found %s [%04x/%04x] %06x %02x\n", pci_name(dev),
692 dev->vendor, dev->device, class, dev->hdr_type);
693
694 /* "Unknown power state" */
695 dev->current_state = PCI_UNKNOWN;
696
697 /* Early fixups, before probing the BARs */
698 pci_fixup_device(pci_fixup_early, dev);
699 class = dev->class >> 8;
700
701 switch (dev->hdr_type) { /* header type */
702 case PCI_HEADER_TYPE_NORMAL: /* standard header */
703 if (class == PCI_CLASS_BRIDGE_PCI)
704 goto bad;
705 pci_read_irq(dev);
706 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
707 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
708 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
709
710 /*
711 * Do the ugly legacy mode stuff here rather than broken chip
712 * quirk code. Legacy mode ATA controllers have fixed
713 * addresses. These are not always echoed in BAR0-3, and
714 * BAR0-3 in a few cases contain junk!
715 */
716 if (class == PCI_CLASS_STORAGE_IDE) {
717 u8 progif;
718 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
719 if ((progif & 1) == 0) {
720 dev->resource[0].start = 0x1F0;
721 dev->resource[0].end = 0x1F7;
722 dev->resource[0].flags = LEGACY_IO_RESOURCE;
723 dev->resource[1].start = 0x3F6;
724 dev->resource[1].end = 0x3F6;
725 dev->resource[1].flags = LEGACY_IO_RESOURCE;
726 }
727 if ((progif & 4) == 0) {
728 dev->resource[2].start = 0x170;
729 dev->resource[2].end = 0x177;
730 dev->resource[2].flags = LEGACY_IO_RESOURCE;
731 dev->resource[3].start = 0x376;
732 dev->resource[3].end = 0x376;
733 dev->resource[3].flags = LEGACY_IO_RESOURCE;
734 }
735 }
736 break;
737
738 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
739 if (class != PCI_CLASS_BRIDGE_PCI)
740 goto bad;
741 /* The PCI-to-PCI bridge spec requires that subtractive
742 decoding (i.e. transparent) bridge must have programming
743 interface code of 0x01. */
744 pci_read_irq(dev);
745 dev->transparent = ((dev->class & 0xff) == 1);
746 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
747 break;
748
749 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
750 if (class != PCI_CLASS_BRIDGE_CARDBUS)
751 goto bad;
752 pci_read_irq(dev);
753 pci_read_bases(dev, 1, 0);
754 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
755 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
756 break;
757
758 default: /* unknown header */
759 printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
760 pci_name(dev), dev->hdr_type);
761 return -1;
762
763 bad:
764 printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
765 pci_name(dev), class, dev->hdr_type);
766 dev->class = PCI_CLASS_NOT_DEFINED;
767 }
768
769 /* We found a fine healthy device, go go go... */
770 return 0;
771 }
772
773 /**
774 * pci_release_dev - free a pci device structure when all users of it are finished.
775 * @dev: device that's been disconnected
776 *
777 * Will be called only by the device core when all users of this pci device are
778 * done.
779 */
780 static void pci_release_dev(struct device *dev)
781 {
782 struct pci_dev *pci_dev;
783
784 pci_dev = to_pci_dev(dev);
785 kfree(pci_dev);
786 }
787
788 static void set_pcie_port_type(struct pci_dev *pdev)
789 {
790 int pos;
791 u16 reg16;
792
793 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
794 if (!pos)
795 return;
796 pdev->is_pcie = 1;
797 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
798 pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
799 }
800
801 /**
802 * pci_cfg_space_size - get the configuration space size of the PCI device.
803 * @dev: PCI device
804 *
805 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
806 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
807 * access it. Maybe we don't have a way to generate extended config space
808 * accesses, or the device is behind a reverse Express bridge. So we try
809 * reading the dword at 0x100 which must either be 0 or a valid extended
810 * capability header.
811 */
812 int pci_cfg_space_size(struct pci_dev *dev)
813 {
814 int pos;
815 u32 status;
816
817 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
818 if (!pos) {
819 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
820 if (!pos)
821 goto fail;
822
823 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
824 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
825 goto fail;
826 }
827
828 if (pci_read_config_dword(dev, 256, &status) != PCIBIOS_SUCCESSFUL)
829 goto fail;
830 if (status == 0xffffffff)
831 goto fail;
832
833 return PCI_CFG_SPACE_EXP_SIZE;
834
835 fail:
836 return PCI_CFG_SPACE_SIZE;
837 }
838
839 static void pci_release_bus_bridge_dev(struct device *dev)
840 {
841 kfree(dev);
842 }
843
844 struct pci_dev *alloc_pci_dev(void)
845 {
846 int i;
847 struct pci_dev *dev;
848
849 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
850 if (!dev)
851 return NULL;
852
853 INIT_LIST_HEAD(&dev->global_list);
854 INIT_LIST_HEAD(&dev->bus_list);
855
856 for (i = 0; i < ARRAY_SIZE(dev->cached_capabilities); ++i)
857 dev->cached_capabilities[i] = -1;
858
859 pci_msi_init_pci_dev(dev);
860
861 return dev;
862 }
863 EXPORT_SYMBOL(alloc_pci_dev);
864
865 /*
866 * Read the config data for a PCI device, sanity-check it
867 * and fill in the dev structure...
868 */
869 static struct pci_dev * __devinit
870 pci_scan_device(struct pci_bus *bus, int devfn)
871 {
872 struct pci_dev *dev;
873 u32 l;
874 u8 hdr_type;
875 int delay = 1;
876
877 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
878 return NULL;
879
880 /* some broken boards return 0 or ~0 if a slot is empty: */
881 if (l == 0xffffffff || l == 0x00000000 ||
882 l == 0x0000ffff || l == 0xffff0000)
883 return NULL;
884
885 /* Configuration request Retry Status */
886 while (l == 0xffff0001) {
887 msleep(delay);
888 delay *= 2;
889 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
890 return NULL;
891 /* Card hasn't responded in 60 seconds? Must be stuck. */
892 if (delay > 60 * 1000) {
893 printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "
894 "responding\n", pci_domain_nr(bus),
895 bus->number, PCI_SLOT(devfn),
896 PCI_FUNC(devfn));
897 return NULL;
898 }
899 }
900
901 if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type))
902 return NULL;
903
904 dev = alloc_pci_dev();
905 if (!dev)
906 return NULL;
907
908 dev->bus = bus;
909 dev->sysdata = bus->sysdata;
910 dev->dev.parent = bus->bridge;
911 dev->dev.bus = &pci_bus_type;
912 dev->devfn = devfn;
913 dev->hdr_type = hdr_type & 0x7f;
914 dev->multifunction = !!(hdr_type & 0x80);
915 dev->vendor = l & 0xffff;
916 dev->device = (l >> 16) & 0xffff;
917 dev->cfg_size = pci_cfg_space_size(dev);
918 dev->error_state = pci_channel_io_normal;
919 set_pcie_port_type(dev);
920
921 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
922 set this higher, assuming the system even supports it. */
923 dev->dma_mask = 0xffffffff;
924 if (pci_setup_device(dev) < 0) {
925 kfree(dev);
926 return NULL;
927 }
928
929 return dev;
930 }
931
932 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
933 {
934 device_initialize(&dev->dev);
935 dev->dev.release = pci_release_dev;
936 pci_dev_get(dev);
937
938 set_dev_node(&dev->dev, pcibus_to_node(bus));
939 dev->dev.dma_mask = &dev->dma_mask;
940 dev->dev.dma_parms = &dev->dma_parms;
941 dev->dev.coherent_dma_mask = 0xffffffffull;
942
943 pci_set_dma_max_seg_size(dev, 65536);
944 pci_set_dma_seg_boundary(dev, 0xffffffff);
945
946 /* Fix up broken headers */
947 pci_fixup_device(pci_fixup_header, dev);
948
949 /*
950 * Add the device to our list of discovered devices
951 * and the bus list for fixup functions, etc.
952 */
953 INIT_LIST_HEAD(&dev->global_list);
954 down_write(&pci_bus_sem);
955 list_add_tail(&dev->bus_list, &bus->devices);
956 up_write(&pci_bus_sem);
957 }
958
959 struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn)
960 {
961 struct pci_dev *dev;
962
963 dev = pci_scan_device(bus, devfn);
964 if (!dev)
965 return NULL;
966
967 pci_device_add(dev, bus);
968
969 return dev;
970 }
971 EXPORT_SYMBOL(pci_scan_single_device);
972
973 /**
974 * pci_scan_slot - scan a PCI slot on a bus for devices.
975 * @bus: PCI bus to scan
976 * @devfn: slot number to scan (must have zero function.)
977 *
978 * Scan a PCI slot on the specified PCI bus for devices, adding
979 * discovered devices to the @bus->devices list. New devices
980 * will have an empty dev->global_list head.
981 */
982 int pci_scan_slot(struct pci_bus *bus, int devfn)
983 {
984 int func, nr = 0;
985 int scan_all_fns;
986
987 scan_all_fns = pcibios_scan_all_fns(bus, devfn);
988
989 for (func = 0; func < 8; func++, devfn++) {
990 struct pci_dev *dev;
991
992 dev = pci_scan_single_device(bus, devfn);
993 if (dev) {
994 nr++;
995
996 /*
997 * If this is a single function device,
998 * don't scan past the first function.
999 */
1000 if (!dev->multifunction) {
1001 if (func > 0) {
1002 dev->multifunction = 1;
1003 } else {
1004 break;
1005 }
1006 }
1007 } else {
1008 if (func == 0 && !scan_all_fns)
1009 break;
1010 }
1011 }
1012 return nr;
1013 }
1014
1015 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
1016 {
1017 unsigned int devfn, pass, max = bus->secondary;
1018 struct pci_dev *dev;
1019
1020 pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
1021
1022 /* Go find them, Rover! */
1023 for (devfn = 0; devfn < 0x100; devfn += 8)
1024 pci_scan_slot(bus, devfn);
1025
1026 /*
1027 * After performing arch-dependent fixup of the bus, look behind
1028 * all PCI-to-PCI bridges on this bus.
1029 */
1030 pr_debug("PCI: Fixups for bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
1031 pcibios_fixup_bus(bus);
1032 for (pass=0; pass < 2; pass++)
1033 list_for_each_entry(dev, &bus->devices, bus_list) {
1034 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1035 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1036 max = pci_scan_bridge(bus, dev, max, pass);
1037 }
1038
1039 /*
1040 * We've scanned the bus and so we know all about what's on
1041 * the other side of any bridges that may be on this bus plus
1042 * any devices.
1043 *
1044 * Return how far we've got finding sub-buses.
1045 */
1046 pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n",
1047 pci_domain_nr(bus), bus->number, max);
1048 return max;
1049 }
1050
1051 struct pci_bus * pci_create_bus(struct device *parent,
1052 int bus, struct pci_ops *ops, void *sysdata)
1053 {
1054 int error;
1055 struct pci_bus *b;
1056 struct device *dev;
1057
1058 b = pci_alloc_bus();
1059 if (!b)
1060 return NULL;
1061
1062 dev = kmalloc(sizeof(*dev), GFP_KERNEL);
1063 if (!dev){
1064 kfree(b);
1065 return NULL;
1066 }
1067
1068 b->sysdata = sysdata;
1069 b->ops = ops;
1070
1071 if (pci_find_bus(pci_domain_nr(b), bus)) {
1072 /* If we already got to this bus through a different bridge, ignore it */
1073 pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus);
1074 goto err_out;
1075 }
1076
1077 down_write(&pci_bus_sem);
1078 list_add_tail(&b->node, &pci_root_buses);
1079 up_write(&pci_bus_sem);
1080
1081 memset(dev, 0, sizeof(*dev));
1082 dev->parent = parent;
1083 dev->release = pci_release_bus_bridge_dev;
1084 sprintf(dev->bus_id, "pci%04x:%02x", pci_domain_nr(b), bus);
1085 error = device_register(dev);
1086 if (error)
1087 goto dev_reg_err;
1088 b->bridge = get_device(dev);
1089
1090 b->dev.class = &pcibus_class;
1091 b->dev.parent = b->bridge;
1092 sprintf(b->dev.bus_id, "%04x:%02x", pci_domain_nr(b), bus);
1093 error = device_register(&b->dev);
1094 if (error)
1095 goto class_dev_reg_err;
1096 error = device_create_file(&b->dev, &dev_attr_cpuaffinity);
1097 if (error)
1098 goto dev_create_file_err;
1099
1100 /* Create legacy_io and legacy_mem files for this bus */
1101 pci_create_legacy_files(b);
1102
1103 b->number = b->secondary = bus;
1104 b->resource[0] = &ioport_resource;
1105 b->resource[1] = &iomem_resource;
1106
1107 return b;
1108
1109 dev_create_file_err:
1110 device_unregister(&b->dev);
1111 class_dev_reg_err:
1112 device_unregister(dev);
1113 dev_reg_err:
1114 down_write(&pci_bus_sem);
1115 list_del(&b->node);
1116 up_write(&pci_bus_sem);
1117 err_out:
1118 kfree(dev);
1119 kfree(b);
1120 return NULL;
1121 }
1122
1123 struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
1124 int bus, struct pci_ops *ops, void *sysdata)
1125 {
1126 struct pci_bus *b;
1127
1128 b = pci_create_bus(parent, bus, ops, sysdata);
1129 if (b)
1130 b->subordinate = pci_scan_child_bus(b);
1131 return b;
1132 }
1133 EXPORT_SYMBOL(pci_scan_bus_parented);
1134
1135 #ifdef CONFIG_HOTPLUG
1136 EXPORT_SYMBOL(pci_add_new_bus);
1137 EXPORT_SYMBOL(pci_scan_slot);
1138 EXPORT_SYMBOL(pci_scan_bridge);
1139 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1140 #endif
1141
1142 static int __init pci_sort_bf_cmp(const struct pci_dev *a, const struct pci_dev *b)
1143 {
1144 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
1145 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
1146
1147 if (a->bus->number < b->bus->number) return -1;
1148 else if (a->bus->number > b->bus->number) return 1;
1149
1150 if (a->devfn < b->devfn) return -1;
1151 else if (a->devfn > b->devfn) return 1;
1152
1153 return 0;
1154 }
1155
1156 /*
1157 * Yes, this forcably breaks the klist abstraction temporarily. It
1158 * just wants to sort the klist, not change reference counts and
1159 * take/drop locks rapidly in the process. It does all this while
1160 * holding the lock for the list, so objects can't otherwise be
1161 * added/removed while we're swizzling.
1162 */
1163 static void __init pci_insertion_sort_klist(struct pci_dev *a, struct list_head *list)
1164 {
1165 struct list_head *pos;
1166 struct klist_node *n;
1167 struct device *dev;
1168 struct pci_dev *b;
1169
1170 list_for_each(pos, list) {
1171 n = container_of(pos, struct klist_node, n_node);
1172 dev = container_of(n, struct device, knode_bus);
1173 b = to_pci_dev(dev);
1174 if (pci_sort_bf_cmp(a, b) <= 0) {
1175 list_move_tail(&a->dev.knode_bus.n_node, &b->dev.knode_bus.n_node);
1176 return;
1177 }
1178 }
1179 list_move_tail(&a->dev.knode_bus.n_node, list);
1180 }
1181
1182 static void __init pci_sort_breadthfirst_klist(void)
1183 {
1184 LIST_HEAD(sorted_devices);
1185 struct list_head *pos, *tmp;
1186 struct klist_node *n;
1187 struct device *dev;
1188 struct pci_dev *pdev;
1189 struct klist *device_klist;
1190
1191 device_klist = bus_get_device_klist(&pci_bus_type);
1192
1193 spin_lock(&device_klist->k_lock);
1194 list_for_each_safe(pos, tmp, &device_klist->k_list) {
1195 n = container_of(pos, struct klist_node, n_node);
1196 dev = container_of(n, struct device, knode_bus);
1197 pdev = to_pci_dev(dev);
1198 pci_insertion_sort_klist(pdev, &sorted_devices);
1199 }
1200 list_splice(&sorted_devices, &device_klist->k_list);
1201 spin_unlock(&device_klist->k_lock);
1202 }
1203
1204 static void __init pci_insertion_sort_devices(struct pci_dev *a, struct list_head *list)
1205 {
1206 struct pci_dev *b;
1207
1208 list_for_each_entry(b, list, global_list) {
1209 if (pci_sort_bf_cmp(a, b) <= 0) {
1210 list_move_tail(&a->global_list, &b->global_list);
1211 return;
1212 }
1213 }
1214 list_move_tail(&a->global_list, list);
1215 }
1216
1217 static void __init pci_sort_breadthfirst_devices(void)
1218 {
1219 LIST_HEAD(sorted_devices);
1220 struct pci_dev *dev, *tmp;
1221
1222 down_write(&pci_bus_sem);
1223 list_for_each_entry_safe(dev, tmp, &pci_devices, global_list) {
1224 pci_insertion_sort_devices(dev, &sorted_devices);
1225 }
1226 list_splice(&sorted_devices, &pci_devices);
1227 up_write(&pci_bus_sem);
1228 }
1229
1230 void __init pci_sort_breadthfirst(void)
1231 {
1232 pci_sort_breadthfirst_devices();
1233 pci_sort_breadthfirst_klist();
1234 }
1235
1236
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