1 /*
2 * probe.c - PCI detection and setup code
3 */
4
5 #include <linux/delay.h>
6 #include <linux/init.h>
7 #include <linux/pci.h>
8 #include <linux/slab.h>
9 #include <linux/module.h>
10 #include <linux/cpumask.h>
11
12 #undef DEBUG
13
14 #ifdef DEBUG
15 #define DBG(x...) printk(x)
16 #else
17 #define DBG(x...)
18 #endif
19
20 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
21 #define CARDBUS_RESERVE_BUSNR 3
22 #define PCI_CFG_SPACE_SIZE 256
23 #define PCI_CFG_SPACE_EXP_SIZE 4096
24
25 /* Ugh. Need to stop exporting this to modules. */
26 LIST_HEAD(pci_root_buses);
27 EXPORT_SYMBOL(pci_root_buses);
28
29 LIST_HEAD(pci_devices);
30
31 #ifdef HAVE_PCI_LEGACY
32 /**
33 * pci_create_legacy_files - create legacy I/O port and memory files
34 * @b: bus to create files under
35 *
36 * Some platforms allow access to legacy I/O port and ISA memory space on
37 * a per-bus basis. This routine creates the files and ties them into
38 * their associated read, write and mmap files from pci-sysfs.c
39 */
40 static void pci_create_legacy_files(struct pci_bus *b)
41 {
42 b->legacy_io = kmalloc(sizeof(struct bin_attribute) * 2,
43 GFP_ATOMIC);
44 if (b->legacy_io) {
45 memset(b->legacy_io, 0, sizeof(struct bin_attribute) * 2);
46 b->legacy_io->attr.name = "legacy_io";
47 b->legacy_io->size = 0xffff;
48 b->legacy_io->attr.mode = S_IRUSR | S_IWUSR;
49 b->legacy_io->attr.owner = THIS_MODULE;
50 b->legacy_io->read = pci_read_legacy_io;
51 b->legacy_io->write = pci_write_legacy_io;
52 class_device_create_bin_file(&b->class_dev, b->legacy_io);
53
54 /* Allocated above after the legacy_io struct */
55 b->legacy_mem = b->legacy_io + 1;
56 b->legacy_mem->attr.name = "legacy_mem";
57 b->legacy_mem->size = 1024*1024;
58 b->legacy_mem->attr.mode = S_IRUSR | S_IWUSR;
59 b->legacy_mem->attr.owner = THIS_MODULE;
60 b->legacy_mem->mmap = pci_mmap_legacy_mem;
61 class_device_create_bin_file(&b->class_dev, b->legacy_mem);
62 }
63 }
64
65 void pci_remove_legacy_files(struct pci_bus *b)
66 {
67 class_device_remove_bin_file(&b->class_dev, b->legacy_io);
68 class_device_remove_bin_file(&b->class_dev, b->legacy_mem);
69 kfree(b->legacy_io); /* both are allocated here */
70 }
71 #else /* !HAVE_PCI_LEGACY */
72 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
73 void pci_remove_legacy_files(struct pci_bus *bus) { return; }
74 #endif /* HAVE_PCI_LEGACY */
75
76 /*
77 * PCI Bus Class Devices
78 */
79 static ssize_t pci_bus_show_cpuaffinity(struct class_device *class_dev, char *buf)
80 {
81 cpumask_t cpumask = pcibus_to_cpumask((to_pci_bus(class_dev))->number);
82 int ret;
83
84 ret = cpumask_scnprintf(buf, PAGE_SIZE, cpumask);
85 if (ret < PAGE_SIZE)
86 buf[ret++] = '\n';
87 return ret;
88 }
89 CLASS_DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpuaffinity, NULL);
90
91 /*
92 * PCI Bus Class
93 */
94 static void release_pcibus_dev(struct class_device *class_dev)
95 {
96 struct pci_bus *pci_bus = to_pci_bus(class_dev);
97
98 if (pci_bus->bridge)
99 put_device(pci_bus->bridge);
100 kfree(pci_bus);
101 }
102
103 static struct class pcibus_class = {
104 .name = "pci_bus",
105 .release = &release_pcibus_dev,
106 };
107
108 static int __init pcibus_class_init(void)
109 {
110 return class_register(&pcibus_class);
111 }
112 postcore_initcall(pcibus_class_init);
113
114 /*
115 * Translate the low bits of the PCI base
116 * to the resource type
117 */
118 static inline unsigned int pci_calc_resource_flags(unsigned int flags)
119 {
120 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
121 return IORESOURCE_IO;
122
123 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
124 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
125
126 return IORESOURCE_MEM;
127 }
128
129 /*
130 * Find the extent of a PCI decode..
131 */
132 static u32 pci_size(u32 base, u32 maxbase, unsigned long mask)
133 {
134 u32 size = mask & maxbase; /* Find the significant bits */
135 if (!size)
136 return 0;
137
138 /* Get the lowest of them to find the decode size, and
139 from that the extent. */
140 size = (size & ~(size-1)) - 1;
141
142 /* base == maxbase can be valid only if the BAR has
143 already been programmed with all 1s. */
144 if (base == maxbase && ((base | size) & mask) != mask)
145 return 0;
146
147 return size;
148 }
149
150 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
151 {
152 unsigned int pos, reg, next;
153 u32 l, sz;
154 struct resource *res;
155
156 for(pos=0; pos<howmany; pos = next) {
157 next = pos+1;
158 res = &dev->resource[pos];
159 res->name = pci_name(dev);
160 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
161 pci_read_config_dword(dev, reg, &l);
162 pci_write_config_dword(dev, reg, ~0);
163 pci_read_config_dword(dev, reg, &sz);
164 pci_write_config_dword(dev, reg, l);
165 if (!sz || sz == 0xffffffff)
166 continue;
167 if (l == 0xffffffff)
168 l = 0;
169 if ((l & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY) {
170 sz = pci_size(l, sz, PCI_BASE_ADDRESS_MEM_MASK);
171 if (!sz)
172 continue;
173 res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
174 res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
175 } else {
176 sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
177 if (!sz)
178 continue;
179 res->start = l & PCI_BASE_ADDRESS_IO_MASK;
180 res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
181 }
182 res->end = res->start + (unsigned long) sz;
183 res->flags |= pci_calc_resource_flags(l);
184 if ((l & (PCI_BASE_ADDRESS_SPACE | PCI_BASE_ADDRESS_MEM_TYPE_MASK))
185 == (PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64)) {
186 pci_read_config_dword(dev, reg+4, &l);
187 next++;
188 #if BITS_PER_LONG == 64
189 res->start |= ((unsigned long) l) << 32;
190 res->end = res->start + sz;
191 pci_write_config_dword(dev, reg+4, ~0);
192 pci_read_config_dword(dev, reg+4, &sz);
193 pci_write_config_dword(dev, reg+4, l);
194 sz = pci_size(l, sz, 0xffffffff);
195 if (sz) {
196 /* This BAR needs > 4GB? Wow. */
197 res->end |= (unsigned long)sz<<32;
198 }
199 #else
200 if (l) {
201 printk(KERN_ERR "PCI: Unable to handle 64-bit address for device %s\n", pci_name(dev));
202 res->start = 0;
203 res->flags = 0;
204 continue;
205 }
206 #endif
207 }
208 }
209 if (rom) {
210 dev->rom_base_reg = rom;
211 res = &dev->resource[PCI_ROM_RESOURCE];
212 res->name = pci_name(dev);
213 pci_read_config_dword(dev, rom, &l);
214 pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE);
215 pci_read_config_dword(dev, rom, &sz);
216 pci_write_config_dword(dev, rom, l);
217 if (l == 0xffffffff)
218 l = 0;
219 if (sz && sz != 0xffffffff) {
220 sz = pci_size(l, sz, PCI_ROM_ADDRESS_MASK);
221 if (sz) {
222 res->flags = (l & IORESOURCE_ROM_ENABLE) |
223 IORESOURCE_MEM | IORESOURCE_PREFETCH |
224 IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
225 res->start = l & PCI_ROM_ADDRESS_MASK;
226 res->end = res->start + (unsigned long) sz;
227 }
228 }
229 }
230 }
231
232 void __devinit pci_read_bridge_bases(struct pci_bus *child)
233 {
234 struct pci_dev *dev = child->self;
235 u8 io_base_lo, io_limit_lo;
236 u16 mem_base_lo, mem_limit_lo;
237 unsigned long base, limit;
238 struct resource *res;
239 int i;
240
241 if (!dev) /* It's a host bus, nothing to read */
242 return;
243
244 if (dev->transparent) {
245 printk(KERN_INFO "PCI: Transparent bridge - %s\n", pci_name(dev));
246 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++)
247 child->resource[i] = child->parent->resource[i];
248 return;
249 }
250
251 for(i=0; i<3; i++)
252 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
253
254 res = child->resource[0];
255 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
256 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
257 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
258 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
259
260 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
261 u16 io_base_hi, io_limit_hi;
262 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
263 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
264 base |= (io_base_hi << 16);
265 limit |= (io_limit_hi << 16);
266 }
267
268 if (base <= limit) {
269 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
270 res->start = base;
271 res->end = limit + 0xfff;
272 }
273
274 res = child->resource[1];
275 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
276 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
277 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
278 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
279 if (base <= limit) {
280 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
281 res->start = base;
282 res->end = limit + 0xfffff;
283 }
284
285 res = child->resource[2];
286 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
287 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
288 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
289 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
290
291 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
292 u32 mem_base_hi, mem_limit_hi;
293 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
294 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
295
296 /*
297 * Some bridges set the base > limit by default, and some
298 * (broken) BIOSes do not initialize them. If we find
299 * this, just assume they are not being used.
300 */
301 if (mem_base_hi <= mem_limit_hi) {
302 #if BITS_PER_LONG == 64
303 base |= ((long) mem_base_hi) << 32;
304 limit |= ((long) mem_limit_hi) << 32;
305 #else
306 if (mem_base_hi || mem_limit_hi) {
307 printk(KERN_ERR "PCI: Unable to handle 64-bit address space for bridge %s\n", pci_name(dev));
308 return;
309 }
310 #endif
311 }
312 }
313 if (base <= limit) {
314 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH;
315 res->start = base;
316 res->end = limit + 0xfffff;
317 }
318 }
319
320 static struct pci_bus * __devinit pci_alloc_bus(void)
321 {
322 struct pci_bus *b;
323
324 b = kmalloc(sizeof(*b), GFP_KERNEL);
325 if (b) {
326 memset(b, 0, sizeof(*b));
327 INIT_LIST_HEAD(&b->node);
328 INIT_LIST_HEAD(&b->children);
329 INIT_LIST_HEAD(&b->devices);
330 }
331 return b;
332 }
333
334 static struct pci_bus * __devinit
335 pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr)
336 {
337 struct pci_bus *child;
338 int i;
339
340 /*
341 * Allocate a new bus, and inherit stuff from the parent..
342 */
343 child = pci_alloc_bus();
344 if (!child)
345 return NULL;
346
347 child->self = bridge;
348 child->parent = parent;
349 child->ops = parent->ops;
350 child->sysdata = parent->sysdata;
351 child->bridge = get_device(&bridge->dev);
352
353 child->class_dev.class = &pcibus_class;
354 sprintf(child->class_dev.class_id, "%04x:%02x", pci_domain_nr(child), busnr);
355 class_device_register(&child->class_dev);
356 class_device_create_file(&child->class_dev, &class_device_attr_cpuaffinity);
357
358 /*
359 * Set up the primary, secondary and subordinate
360 * bus numbers.
361 */
362 child->number = child->secondary = busnr;
363 child->primary = parent->secondary;
364 child->subordinate = 0xff;
365
366 /* Set up default resource pointers and names.. */
367 for (i = 0; i < 4; i++) {
368 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
369 child->resource[i]->name = child->name;
370 }
371 bridge->subordinate = child;
372
373 return child;
374 }
375
376 struct pci_bus * __devinit pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
377 {
378 struct pci_bus *child;
379
380 child = pci_alloc_child_bus(parent, dev, busnr);
381 if (child)
382 list_add_tail(&child->node, &parent->children);
383 return child;
384 }
385
386 static void pci_enable_crs(struct pci_dev *dev)
387 {
388 u16 cap, rpctl;
389 int rpcap = pci_find_capability(dev, PCI_CAP_ID_EXP);
390 if (!rpcap)
391 return;
392
393 pci_read_config_word(dev, rpcap + PCI_CAP_FLAGS, &cap);
394 if (((cap & PCI_EXP_FLAGS_TYPE) >> 4) != PCI_EXP_TYPE_ROOT_PORT)
395 return;
396
397 pci_read_config_word(dev, rpcap + PCI_EXP_RTCTL, &rpctl);
398 rpctl |= PCI_EXP_RTCTL_CRSSVE;
399 pci_write_config_word(dev, rpcap + PCI_EXP_RTCTL, rpctl);
400 }
401
402 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus);
403
404 /*
405 * If it's a bridge, configure it and scan the bus behind it.
406 * For CardBus bridges, we don't scan behind as the devices will
407 * be handled by the bridge driver itself.
408 *
409 * We need to process bridges in two passes -- first we scan those
410 * already configured by the BIOS and after we are done with all of
411 * them, we proceed to assigning numbers to the remaining buses in
412 * order to avoid overlaps between old and new bus numbers.
413 */
414 int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass)
415 {
416 struct pci_bus *child;
417 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
418 u32 buses;
419 u16 bctl;
420
421 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
422
423 DBG("Scanning behind PCI bridge %s, config %06x, pass %d\n",
424 pci_name(dev), buses & 0xffffff, pass);
425
426 /* Disable MasterAbortMode during probing to avoid reporting
427 of bus errors (in some architectures) */
428 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
429 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
430 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
431
432 pci_enable_crs(dev);
433
434 if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) {
435 unsigned int cmax, busnr;
436 /*
437 * Bus already configured by firmware, process it in the first
438 * pass and just note the configuration.
439 */
440 if (pass)
441 return max;
442 busnr = (buses >> 8) & 0xFF;
443
444 /*
445 * If we already got to this bus through a different bridge,
446 * ignore it. This can happen with the i450NX chipset.
447 */
448 if (pci_find_bus(pci_domain_nr(bus), busnr)) {
449 printk(KERN_INFO "PCI: Bus %04x:%02x already known\n",
450 pci_domain_nr(bus), busnr);
451 return max;
452 }
453
454 child = pci_alloc_child_bus(bus, dev, busnr);
455 if (!child)
456 return max;
457 child->primary = buses & 0xFF;
458 child->subordinate = (buses >> 16) & 0xFF;
459 child->bridge_ctl = bctl;
460
461 cmax = pci_scan_child_bus(child);
462 if (cmax > max)
463 max = cmax;
464 if (child->subordinate > max)
465 max = child->subordinate;
466 } else {
467 /*
468 * We need to assign a number to this bus which we always
469 * do in the second pass.
470 */
471 if (!pass)
472 return max;
473
474 /* Clear errors */
475 pci_write_config_word(dev, PCI_STATUS, 0xffff);
476
477 child = pci_alloc_child_bus(bus, dev, ++max);
478 buses = (buses & 0xff000000)
479 | ((unsigned int)(child->primary) << 0)
480 | ((unsigned int)(child->secondary) << 8)
481 | ((unsigned int)(child->subordinate) << 16);
482
483 /*
484 * yenta.c forces a secondary latency timer of 176.
485 * Copy that behaviour here.
486 */
487 if (is_cardbus) {
488 buses &= ~0xff000000;
489 buses |= CARDBUS_LATENCY_TIMER << 24;
490 }
491
492 /*
493 * We need to blast all three values with a single write.
494 */
495 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
496
497 if (!is_cardbus) {
498 child->bridge_ctl = PCI_BRIDGE_CTL_NO_ISA;
499
500 /* Now we can scan all subordinate buses... */
501 max = pci_scan_child_bus(child);
502 } else {
503 /*
504 * For CardBus bridges, we leave 4 bus numbers
505 * as cards with a PCI-to-PCI bridge can be
506 * inserted later.
507 */
508 max += CARDBUS_RESERVE_BUSNR;
509 }
510 /*
511 * Set the subordinate bus number to its real value.
512 */
513 child->subordinate = max;
514 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
515 }
516
517 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
518
519 sprintf(child->name, (is_cardbus ? "PCI CardBus #%02x" : "PCI Bus #%02x"), child->number);
520
521 return max;
522 }
523
524 /*
525 * Read interrupt line and base address registers.
526 * The architecture-dependent code can tweak these, of course.
527 */
528 static void pci_read_irq(struct pci_dev *dev)
529 {
530 unsigned char irq;
531
532 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
533 if (irq)
534 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
535 dev->irq = irq;
536 }
537
538 /**
539 * pci_setup_device - fill in class and map information of a device
540 * @dev: the device structure to fill
541 *
542 * Initialize the device structure with information about the device's
543 * vendor,class,memory and IO-space addresses,IRQ lines etc.
544 * Called at initialisation of the PCI subsystem and by CardBus services.
545 * Returns 0 on success and -1 if unknown type of device (not normal, bridge
546 * or CardBus).
547 */
548 static int pci_setup_device(struct pci_dev * dev)
549 {
550 u32 class;
551
552 dev->slot_name = dev->dev.bus_id;
553 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
554 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
555
556 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
557 class >>= 8; /* upper 3 bytes */
558 dev->class = class;
559 class >>= 8;
560
561 DBG("Found %02x:%02x [%04x/%04x] %06x %02x\n", dev->bus->number,
562 dev->devfn, dev->vendor, dev->device, class, dev->hdr_type);
563
564 /* "Unknown power state" */
565 dev->current_state = 4;
566
567 /* Early fixups, before probing the BARs */
568 pci_fixup_device(pci_fixup_early, dev);
569 class = dev->class >> 8;
570
571 switch (dev->hdr_type) { /* header type */
572 case PCI_HEADER_TYPE_NORMAL: /* standard header */
573 if (class == PCI_CLASS_BRIDGE_PCI)
574 goto bad;
575 pci_read_irq(dev);
576 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
577 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
578 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
579 break;
580
581 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
582 if (class != PCI_CLASS_BRIDGE_PCI)
583 goto bad;
584 /* The PCI-to-PCI bridge spec requires that subtractive
585 decoding (i.e. transparent) bridge must have programming
586 interface code of 0x01. */
587 dev->transparent = ((dev->class & 0xff) == 1);
588 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
589 break;
590
591 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
592 if (class != PCI_CLASS_BRIDGE_CARDBUS)
593 goto bad;
594 pci_read_irq(dev);
595 pci_read_bases(dev, 1, 0);
596 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
597 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
598 break;
599
600 default: /* unknown header */
601 printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
602 pci_name(dev), dev->hdr_type);
603 return -1;
604
605 bad:
606 printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
607 pci_name(dev), class, dev->hdr_type);
608 dev->class = PCI_CLASS_NOT_DEFINED;
609 }
610
611 /* We found a fine healthy device, go go go... */
612 return 0;
613 }
614
615 /**
616 * pci_release_dev - free a pci device structure when all users of it are finished.
617 * @dev: device that's been disconnected
618 *
619 * Will be called only by the device core when all users of this pci device are
620 * done.
621 */
622 static void pci_release_dev(struct device *dev)
623 {
624 struct pci_dev *pci_dev;
625
626 pci_dev = to_pci_dev(dev);
627 kfree(pci_dev);
628 }
629
630 /**
631 * pci_cfg_space_size - get the configuration space size of the PCI device.
632 *
633 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
634 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
635 * access it. Maybe we don't have a way to generate extended config space
636 * accesses, or the device is behind a reverse Express bridge. So we try
637 * reading the dword at 0x100 which must either be 0 or a valid extended
638 * capability header.
639 */
640 static int pci_cfg_space_size(struct pci_dev *dev)
641 {
642 int pos;
643 u32 status;
644
645 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
646 if (!pos) {
647 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
648 if (!pos)
649 goto fail;
650
651 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
652 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
653 goto fail;
654 }
655
656 if (pci_read_config_dword(dev, 256, &status) != PCIBIOS_SUCCESSFUL)
657 goto fail;
658 if (status == 0xffffffff)
659 goto fail;
660
661 return PCI_CFG_SPACE_EXP_SIZE;
662
663 fail:
664 return PCI_CFG_SPACE_SIZE;
665 }
666
667 static void pci_release_bus_bridge_dev(struct device *dev)
668 {
669 kfree(dev);
670 }
671
672 /*
673 * Read the config data for a PCI device, sanity-check it
674 * and fill in the dev structure...
675 */
676 static struct pci_dev * __devinit
677 pci_scan_device(struct pci_bus *bus, int devfn)
678 {
679 struct pci_dev *dev;
680 u32 l;
681 u8 hdr_type;
682 int delay = 1;
683
684 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
685 return NULL;
686
687 /* some broken boards return 0 or ~0 if a slot is empty: */
688 if (l == 0xffffffff || l == 0x00000000 ||
689 l == 0x0000ffff || l == 0xffff0000)
690 return NULL;
691
692 /* Configuration request Retry Status */
693 while (l == 0xffff0001) {
694 msleep(delay);
695 delay *= 2;
696 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
697 return NULL;
698 /* Card hasn't responded in 60 seconds? Must be stuck. */
699 if (delay > 60 * 1000) {
700 printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "
701 "responding\n", pci_domain_nr(bus),
702 bus->number, PCI_SLOT(devfn),
703 PCI_FUNC(devfn));
704 return NULL;
705 }
706 }
707
708 if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type))
709 return NULL;
710
711 dev = kmalloc(sizeof(struct pci_dev), GFP_KERNEL);
712 if (!dev)
713 return NULL;
714
715 memset(dev, 0, sizeof(struct pci_dev));
716 dev->bus = bus;
717 dev->sysdata = bus->sysdata;
718 dev->dev.parent = bus->bridge;
719 dev->dev.bus = &pci_bus_type;
720 dev->devfn = devfn;
721 dev->hdr_type = hdr_type & 0x7f;
722 dev->multifunction = !!(hdr_type & 0x80);
723 dev->vendor = l & 0xffff;
724 dev->device = (l >> 16) & 0xffff;
725 dev->cfg_size = pci_cfg_space_size(dev);
726
727 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
728 set this higher, assuming the system even supports it. */
729 dev->dma_mask = 0xffffffff;
730 if (pci_setup_device(dev) < 0) {
731 kfree(dev);
732 return NULL;
733 }
734 device_initialize(&dev->dev);
735 dev->dev.release = pci_release_dev;
736 pci_dev_get(dev);
737
738 pci_name_device(dev);
739
740 dev->dev.dma_mask = &dev->dma_mask;
741 dev->dev.coherent_dma_mask = 0xffffffffull;
742
743 return dev;
744 }
745
746 struct pci_dev * __devinit
747 pci_scan_single_device(struct pci_bus *bus, int devfn)
748 {
749 struct pci_dev *dev;
750
751 dev = pci_scan_device(bus, devfn);
752 pci_scan_msi_device(dev);
753
754 if (!dev)
755 return NULL;
756
757 /* Fix up broken headers */
758 pci_fixup_device(pci_fixup_header, dev);
759
760 /*
761 * Add the device to our list of discovered devices
762 * and the bus list for fixup functions, etc.
763 */
764 INIT_LIST_HEAD(&dev->global_list);
765 list_add_tail(&dev->bus_list, &bus->devices);
766
767 return dev;
768 }
769
770 /**
771 * pci_scan_slot - scan a PCI slot on a bus for devices.
772 * @bus: PCI bus to scan
773 * @devfn: slot number to scan (must have zero function.)
774 *
775 * Scan a PCI slot on the specified PCI bus for devices, adding
776 * discovered devices to the @bus->devices list. New devices
777 * will have an empty dev->global_list head.
778 */
779 int __devinit pci_scan_slot(struct pci_bus *bus, int devfn)
780 {
781 int func, nr = 0;
782 int scan_all_fns;
783
784 scan_all_fns = pcibios_scan_all_fns(bus, devfn);
785
786 for (func = 0; func < 8; func++, devfn++) {
787 struct pci_dev *dev;
788
789 dev = pci_scan_single_device(bus, devfn);
790 if (dev) {
791 nr++;
792
793 /*
794 * If this is a single function device,
795 * don't scan past the first function.
796 */
797 if (!dev->multifunction) {
798 if (func > 0) {
799 dev->multifunction = 1;
800 } else {
801 break;
802 }
803 }
804 } else {
805 if (func == 0 && !scan_all_fns)
806 break;
807 }
808 }
809 return nr;
810 }
811
812 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
813 {
814 unsigned int devfn, pass, max = bus->secondary;
815 struct pci_dev *dev;
816
817 DBG("Scanning bus %02x\n", bus->number);
818
819 /* Go find them, Rover! */
820 for (devfn = 0; devfn < 0x100; devfn += 8)
821 pci_scan_slot(bus, devfn);
822
823 /*
824 * After performing arch-dependent fixup of the bus, look behind
825 * all PCI-to-PCI bridges on this bus.
826 */
827 DBG("Fixups for bus %02x\n", bus->number);
828 pcibios_fixup_bus(bus);
829 for (pass=0; pass < 2; pass++)
830 list_for_each_entry(dev, &bus->devices, bus_list) {
831 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
832 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
833 max = pci_scan_bridge(bus, dev, max, pass);
834 }
835
836 /*
837 * We've scanned the bus and so we know all about what's on
838 * the other side of any bridges that may be on this bus plus
839 * any devices.
840 *
841 * Return how far we've got finding sub-buses.
842 */
843 DBG("Bus scan for %02x returning with max=%02x\n", bus->number, max);
844 return max;
845 }
846
847 unsigned int __devinit pci_do_scan_bus(struct pci_bus *bus)
848 {
849 unsigned int max;
850
851 max = pci_scan_child_bus(bus);
852
853 /*
854 * Make the discovered devices available.
855 */
856 pci_bus_add_devices(bus);
857
858 return max;
859 }
860
861 struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent, int bus, struct pci_ops *ops, void *sysdata)
862 {
863 int error;
864 struct pci_bus *b;
865 struct device *dev;
866
867 b = pci_alloc_bus();
868 if (!b)
869 return NULL;
870
871 dev = kmalloc(sizeof(*dev), GFP_KERNEL);
872 if (!dev){
873 kfree(b);
874 return NULL;
875 }
876
877 b->sysdata = sysdata;
878 b->ops = ops;
879
880 if (pci_find_bus(pci_domain_nr(b), bus)) {
881 /* If we already got to this bus through a different bridge, ignore it */
882 DBG("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus);
883 goto err_out;
884 }
885 list_add_tail(&b->node, &pci_root_buses);
886
887 memset(dev, 0, sizeof(*dev));
888 dev->parent = parent;
889 dev->release = pci_release_bus_bridge_dev;
890 sprintf(dev->bus_id, "pci%04x:%02x", pci_domain_nr(b), bus);
891 error = device_register(dev);
892 if (error)
893 goto dev_reg_err;
894 b->bridge = get_device(dev);
895
896 b->class_dev.class = &pcibus_class;
897 sprintf(b->class_dev.class_id, "%04x:%02x", pci_domain_nr(b), bus);
898 error = class_device_register(&b->class_dev);
899 if (error)
900 goto class_dev_reg_err;
901 error = class_device_create_file(&b->class_dev, &class_device_attr_cpuaffinity);
902 if (error)
903 goto class_dev_create_file_err;
904
905 /* Create legacy_io and legacy_mem files for this bus */
906 pci_create_legacy_files(b);
907
908 error = sysfs_create_link(&b->class_dev.kobj, &b->bridge->kobj, "bridge");
909 if (error)
910 goto sys_create_link_err;
911
912 b->number = b->secondary = bus;
913 b->resource[0] = &ioport_resource;
914 b->resource[1] = &iomem_resource;
915
916 b->subordinate = pci_scan_child_bus(b);
917
918 pci_bus_add_devices(b);
919
920 return b;
921
922 sys_create_link_err:
923 class_device_remove_file(&b->class_dev, &class_device_attr_cpuaffinity);
924 class_dev_create_file_err:
925 class_device_unregister(&b->class_dev);
926 class_dev_reg_err:
927 device_unregister(dev);
928 dev_reg_err:
929 list_del(&b->node);
930 err_out:
931 kfree(dev);
932 kfree(b);
933 return NULL;
934 }
935 EXPORT_SYMBOL(pci_scan_bus_parented);
936
937 #ifdef CONFIG_HOTPLUG
938 EXPORT_SYMBOL(pci_add_new_bus);
939 EXPORT_SYMBOL(pci_do_scan_bus);
940 EXPORT_SYMBOL(pci_scan_slot);
941 EXPORT_SYMBOL(pci_scan_bridge);
942 EXPORT_SYMBOL(pci_scan_single_device);
943 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
944 #endif
945
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