1 /*
2 * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $
3 *
4 * PCI Bus Services, see include/linux/pci.h for further explanation.
5 *
6 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * David Mosberger-Tang
8 *
9 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/init.h>
15 #include <linux/pci.h>
16 #include <linux/pm.h>
17 #include <linux/module.h>
18 #include <linux/spinlock.h>
19 #include <linux/string.h>
20 #include <linux/log2.h>
21 #include <asm/dma.h> /* isa_dma_bridge_buggy */
22 #include "pci.h"
23
24 unsigned int pci_pm_d3_delay = 10;
25
26 #ifdef CONFIG_PCI_DOMAINS
27 int pci_domains_supported = 1;
28 #endif
29
30 #define DEFAULT_CARDBUS_IO_SIZE (256)
31 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
32 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
33 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
34 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
35
36 /**
37 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
38 * @bus: pointer to PCI bus structure to search
39 *
40 * Given a PCI bus, returns the highest PCI bus number present in the set
41 * including the given PCI bus and its list of child PCI buses.
42 */
43 unsigned char pci_bus_max_busnr(struct pci_bus* bus)
44 {
45 struct list_head *tmp;
46 unsigned char max, n;
47
48 max = bus->subordinate;
49 list_for_each(tmp, &bus->children) {
50 n = pci_bus_max_busnr(pci_bus_b(tmp));
51 if(n > max)
52 max = n;
53 }
54 return max;
55 }
56 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
57
58 #if 0
59 /**
60 * pci_max_busnr - returns maximum PCI bus number
61 *
62 * Returns the highest PCI bus number present in the system global list of
63 * PCI buses.
64 */
65 unsigned char __devinit
66 pci_max_busnr(void)
67 {
68 struct pci_bus *bus = NULL;
69 unsigned char max, n;
70
71 max = 0;
72 while ((bus = pci_find_next_bus(bus)) != NULL) {
73 n = pci_bus_max_busnr(bus);
74 if(n > max)
75 max = n;
76 }
77 return max;
78 }
79
80 #endif /* 0 */
81
82 #define PCI_FIND_CAP_TTL 48
83
84 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
85 u8 pos, int cap, int *ttl)
86 {
87 u8 id;
88
89 while ((*ttl)--) {
90 pci_bus_read_config_byte(bus, devfn, pos, &pos);
91 if (pos < 0x40)
92 break;
93 pos &= ~3;
94 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
95 &id);
96 if (id == 0xff)
97 break;
98 if (id == cap)
99 return pos;
100 pos += PCI_CAP_LIST_NEXT;
101 }
102 return 0;
103 }
104
105 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
106 u8 pos, int cap)
107 {
108 int ttl = PCI_FIND_CAP_TTL;
109
110 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
111 }
112
113 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
114 {
115 return __pci_find_next_cap(dev->bus, dev->devfn,
116 pos + PCI_CAP_LIST_NEXT, cap);
117 }
118 EXPORT_SYMBOL_GPL(pci_find_next_capability);
119
120 static int __pci_bus_find_cap_start(struct pci_bus *bus,
121 unsigned int devfn, u8 hdr_type)
122 {
123 u16 status;
124
125 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
126 if (!(status & PCI_STATUS_CAP_LIST))
127 return 0;
128
129 switch (hdr_type) {
130 case PCI_HEADER_TYPE_NORMAL:
131 case PCI_HEADER_TYPE_BRIDGE:
132 return PCI_CAPABILITY_LIST;
133 case PCI_HEADER_TYPE_CARDBUS:
134 return PCI_CB_CAPABILITY_LIST;
135 default:
136 return 0;
137 }
138
139 return 0;
140 }
141
142 /**
143 * pci_find_capability - query for devices' capabilities
144 * @dev: PCI device to query
145 * @cap: capability code
146 *
147 * Tell if a device supports a given PCI capability.
148 * Returns the address of the requested capability structure within the
149 * device's PCI configuration space or 0 in case the device does not
150 * support it. Possible values for @cap:
151 *
152 * %PCI_CAP_ID_PM Power Management
153 * %PCI_CAP_ID_AGP Accelerated Graphics Port
154 * %PCI_CAP_ID_VPD Vital Product Data
155 * %PCI_CAP_ID_SLOTID Slot Identification
156 * %PCI_CAP_ID_MSI Message Signalled Interrupts
157 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
158 * %PCI_CAP_ID_PCIX PCI-X
159 * %PCI_CAP_ID_EXP PCI Express
160 */
161 int pci_find_capability(struct pci_dev *dev, int cap)
162 {
163 int pos;
164
165 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
166 if (pos)
167 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
168
169 return pos;
170 }
171
172 /**
173 * pci_find_capability_cached - query for devices' capabilities, cached version
174 * @dev: PCI device to query
175 * @cap: capability code
176 *
177 * Tell if a device supports a given PCI capability.
178 * Returns the address of the requested capability structure within the
179 * device's PCI configuration space or 0 in case the device does not
180 * support it. Possible values for @cap:
181 *
182 * %PCI_CAP_ID_PM Power Management
183 * %PCI_CAP_ID_AGP Accelerated Graphics Port
184 * %PCI_CAP_ID_VPD Vital Product Data
185 * %PCI_CAP_ID_SLOTID Slot Identification
186 * %PCI_CAP_ID_MSI Message Signalled Interrupts
187 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
188 * %PCI_CAP_ID_PCIX PCI-X
189 * %PCI_CAP_ID_EXP PCI Express
190 */
191 int pci_find_capability_cached(struct pci_dev *dev, int cap)
192 {
193 int pos = 0;
194
195 WARN_ON_ONCE(cap <= 0 || cap > PCI_CAP_LIST_NR_ENTRIES);
196
197 if (cap <= PCI_CAP_LIST_NR_ENTRIES) {
198 const int i = cap - 1;
199 if (dev->cached_capabilities[i] == -1)
200 dev->cached_capabilities[i] = pci_find_capability(dev, cap);
201
202 pos = dev->cached_capabilities[i];
203 }
204
205 return pos;
206 }
207
208 /**
209 * pci_bus_find_capability - query for devices' capabilities
210 * @bus: the PCI bus to query
211 * @devfn: PCI device to query
212 * @cap: capability code
213 *
214 * Like pci_find_capability() but works for pci devices that do not have a
215 * pci_dev structure set up yet.
216 *
217 * Returns the address of the requested capability structure within the
218 * device's PCI configuration space or 0 in case the device does not
219 * support it.
220 */
221 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
222 {
223 int pos;
224 u8 hdr_type;
225
226 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
227
228 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
229 if (pos)
230 pos = __pci_find_next_cap(bus, devfn, pos, cap);
231
232 return pos;
233 }
234
235 /**
236 * pci_find_ext_capability - Find an extended capability
237 * @dev: PCI device to query
238 * @cap: capability code
239 *
240 * Returns the address of the requested extended capability structure
241 * within the device's PCI configuration space or 0 if the device does
242 * not support it. Possible values for @cap:
243 *
244 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
245 * %PCI_EXT_CAP_ID_VC Virtual Channel
246 * %PCI_EXT_CAP_ID_DSN Device Serial Number
247 * %PCI_EXT_CAP_ID_PWR Power Budgeting
248 */
249 int pci_find_ext_capability(struct pci_dev *dev, int cap)
250 {
251 u32 header;
252 int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */
253 int pos = 0x100;
254
255 if (dev->cfg_size <= 256)
256 return 0;
257
258 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
259 return 0;
260
261 /*
262 * If we have no capabilities, this is indicated by cap ID,
263 * cap version and next pointer all being 0.
264 */
265 if (header == 0)
266 return 0;
267
268 while (ttl-- > 0) {
269 if (PCI_EXT_CAP_ID(header) == cap)
270 return pos;
271
272 pos = PCI_EXT_CAP_NEXT(header);
273 if (pos < 0x100)
274 break;
275
276 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
277 break;
278 }
279
280 return 0;
281 }
282 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
283
284 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
285 {
286 int rc, ttl = PCI_FIND_CAP_TTL;
287 u8 cap, mask;
288
289 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
290 mask = HT_3BIT_CAP_MASK;
291 else
292 mask = HT_5BIT_CAP_MASK;
293
294 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
295 PCI_CAP_ID_HT, &ttl);
296 while (pos) {
297 rc = pci_read_config_byte(dev, pos + 3, &cap);
298 if (rc != PCIBIOS_SUCCESSFUL)
299 return 0;
300
301 if ((cap & mask) == ht_cap)
302 return pos;
303
304 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
305 pos + PCI_CAP_LIST_NEXT,
306 PCI_CAP_ID_HT, &ttl);
307 }
308
309 return 0;
310 }
311 /**
312 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
313 * @dev: PCI device to query
314 * @pos: Position from which to continue searching
315 * @ht_cap: Hypertransport capability code
316 *
317 * To be used in conjunction with pci_find_ht_capability() to search for
318 * all capabilities matching @ht_cap. @pos should always be a value returned
319 * from pci_find_ht_capability().
320 *
321 * NB. To be 100% safe against broken PCI devices, the caller should take
322 * steps to avoid an infinite loop.
323 */
324 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
325 {
326 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
327 }
328 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
329
330 /**
331 * pci_find_ht_capability - query a device's Hypertransport capabilities
332 * @dev: PCI device to query
333 * @ht_cap: Hypertransport capability code
334 *
335 * Tell if a device supports a given Hypertransport capability.
336 * Returns an address within the device's PCI configuration space
337 * or 0 in case the device does not support the request capability.
338 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
339 * which has a Hypertransport capability matching @ht_cap.
340 */
341 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
342 {
343 int pos;
344
345 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
346 if (pos)
347 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
348
349 return pos;
350 }
351 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
352
353 /**
354 * pci_find_parent_resource - return resource region of parent bus of given region
355 * @dev: PCI device structure contains resources to be searched
356 * @res: child resource record for which parent is sought
357 *
358 * For given resource region of given device, return the resource
359 * region of parent bus the given region is contained in or where
360 * it should be allocated from.
361 */
362 struct resource *
363 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
364 {
365 const struct pci_bus *bus = dev->bus;
366 int i;
367 struct resource *best = NULL;
368
369 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
370 struct resource *r = bus->resource[i];
371 if (!r)
372 continue;
373 if (res->start && !(res->start >= r->start && res->end <= r->end))
374 continue; /* Not contained */
375 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
376 continue; /* Wrong type */
377 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
378 return r; /* Exact match */
379 if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH))
380 best = r; /* Approximating prefetchable by non-prefetchable */
381 }
382 return best;
383 }
384
385 /**
386 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
387 * @dev: PCI device to have its BARs restored
388 *
389 * Restore the BAR values for a given device, so as to make it
390 * accessible by its driver.
391 */
392 static void
393 pci_restore_bars(struct pci_dev *dev)
394 {
395 int i, numres;
396
397 switch (dev->hdr_type) {
398 case PCI_HEADER_TYPE_NORMAL:
399 numres = 6;
400 break;
401 case PCI_HEADER_TYPE_BRIDGE:
402 numres = 2;
403 break;
404 case PCI_HEADER_TYPE_CARDBUS:
405 numres = 1;
406 break;
407 default:
408 /* Should never get here, but just in case... */
409 return;
410 }
411
412 for (i = 0; i < numres; i ++)
413 pci_update_resource(dev, &dev->resource[i], i);
414 }
415
416 int (*platform_pci_set_power_state)(struct pci_dev *dev, pci_power_t t);
417
418 /**
419 * pci_set_power_state - Set the power state of a PCI device
420 * @dev: PCI device to be suspended
421 * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering
422 *
423 * Transition a device to a new power state, using the Power Management
424 * Capabilities in the device's config space.
425 *
426 * RETURN VALUE:
427 * -EINVAL if trying to enter a lower state than we're already in.
428 * 0 if we're already in the requested state.
429 * -EIO if device does not support PCI PM.
430 * 0 if we can successfully change the power state.
431 */
432 int
433 pci_set_power_state(struct pci_dev *dev, pci_power_t state)
434 {
435 int pm, need_restore = 0;
436 u16 pmcsr, pmc;
437
438 /* bound the state we're entering */
439 if (state > PCI_D3hot)
440 state = PCI_D3hot;
441
442 /*
443 * If the device or the parent bridge can't support PCI PM, ignore
444 * the request if we're doing anything besides putting it into D0
445 * (which would only happen on boot).
446 */
447 if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
448 return 0;
449
450 /* find PCI PM capability in list */
451 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
452
453 /* abort if the device doesn't support PM capabilities */
454 if (!pm)
455 return -EIO;
456
457 /* Validate current state:
458 * Can enter D0 from any state, but if we can only go deeper
459 * to sleep if we're already in a low power state
460 */
461 if (state != PCI_D0 && dev->current_state > state) {
462 printk(KERN_ERR "%s(): %s: state=%d, current state=%d\n",
463 __FUNCTION__, pci_name(dev), state, dev->current_state);
464 return -EINVAL;
465 } else if (dev->current_state == state)
466 return 0; /* we're already there */
467
468
469 pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc);
470 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
471 printk(KERN_DEBUG
472 "PCI: %s has unsupported PM cap regs version (%u)\n",
473 pci_name(dev), pmc & PCI_PM_CAP_VER_MASK);
474 return -EIO;
475 }
476
477 /* check if this device supports the desired state */
478 if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1))
479 return -EIO;
480 else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2))
481 return -EIO;
482
483 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
484
485 /* If we're (effectively) in D3, force entire word to 0.
486 * This doesn't affect PME_Status, disables PME_En, and
487 * sets PowerState to 0.
488 */
489 switch (dev->current_state) {
490 case PCI_D0:
491 case PCI_D1:
492 case PCI_D2:
493 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
494 pmcsr |= state;
495 break;
496 case PCI_UNKNOWN: /* Boot-up */
497 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
498 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
499 need_restore = 1;
500 /* Fall-through: force to D0 */
501 default:
502 pmcsr = 0;
503 break;
504 }
505
506 /* enter specified state */
507 pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr);
508
509 /* Mandatory power management transition delays */
510 /* see PCI PM 1.1 5.6.1 table 18 */
511 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
512 msleep(pci_pm_d3_delay);
513 else if (state == PCI_D2 || dev->current_state == PCI_D2)
514 udelay(200);
515
516 /*
517 * Give firmware a chance to be called, such as ACPI _PRx, _PSx
518 * Firmware method after native method ?
519 */
520 if (platform_pci_set_power_state)
521 platform_pci_set_power_state(dev, state);
522
523 dev->current_state = state;
524
525 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
526 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
527 * from D3hot to D0 _may_ perform an internal reset, thereby
528 * going to "D0 Uninitialized" rather than "D0 Initialized".
529 * For example, at least some versions of the 3c905B and the
530 * 3c556B exhibit this behaviour.
531 *
532 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
533 * devices in a D3hot state at boot. Consequently, we need to
534 * restore at least the BARs so that the device will be
535 * accessible to its driver.
536 */
537 if (need_restore)
538 pci_restore_bars(dev);
539
540 return 0;
541 }
542
543 pci_power_t (*platform_pci_choose_state)(struct pci_dev *dev, pm_message_t state);
544
545 /**
546 * pci_choose_state - Choose the power state of a PCI device
547 * @dev: PCI device to be suspended
548 * @state: target sleep state for the whole system. This is the value
549 * that is passed to suspend() function.
550 *
551 * Returns PCI power state suitable for given device and given system
552 * message.
553 */
554
555 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
556 {
557 pci_power_t ret;
558
559 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
560 return PCI_D0;
561
562 if (platform_pci_choose_state) {
563 ret = platform_pci_choose_state(dev, state);
564 if (ret != PCI_POWER_ERROR)
565 return ret;
566 }
567
568 switch (state.event) {
569 case PM_EVENT_ON:
570 return PCI_D0;
571 case PM_EVENT_FREEZE:
572 case PM_EVENT_PRETHAW:
573 /* REVISIT both freeze and pre-thaw "should" use D0 */
574 case PM_EVENT_SUSPEND:
575 case PM_EVENT_HIBERNATE:
576 return PCI_D3hot;
577 default:
578 printk("Unrecognized suspend event %d\n", state.event);
579 BUG();
580 }
581 return PCI_D0;
582 }
583
584 EXPORT_SYMBOL(pci_choose_state);
585
586 static int pci_save_pcie_state(struct pci_dev *dev)
587 {
588 int pos, i = 0;
589 struct pci_cap_saved_state *save_state;
590 u16 *cap;
591 int found = 0;
592
593 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
594 if (pos <= 0)
595 return 0;
596
597 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
598 if (!save_state)
599 save_state = kzalloc(sizeof(*save_state) + sizeof(u16) * 4, GFP_KERNEL);
600 else
601 found = 1;
602 if (!save_state) {
603 dev_err(&dev->dev, "Out of memory in pci_save_pcie_state\n");
604 return -ENOMEM;
605 }
606 cap = (u16 *)&save_state->data[0];
607
608 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
609 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
610 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
611 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
612 save_state->cap_nr = PCI_CAP_ID_EXP;
613 if (!found)
614 pci_add_saved_cap(dev, save_state);
615 return 0;
616 }
617
618 static void pci_restore_pcie_state(struct pci_dev *dev)
619 {
620 int i = 0, pos;
621 struct pci_cap_saved_state *save_state;
622 u16 *cap;
623
624 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
625 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
626 if (!save_state || pos <= 0)
627 return;
628 cap = (u16 *)&save_state->data[0];
629
630 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
631 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
632 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
633 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
634 }
635
636
637 static int pci_save_pcix_state(struct pci_dev *dev)
638 {
639 int pos, i = 0;
640 struct pci_cap_saved_state *save_state;
641 u16 *cap;
642 int found = 0;
643
644 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
645 if (pos <= 0)
646 return 0;
647
648 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
649 if (!save_state)
650 save_state = kzalloc(sizeof(*save_state) + sizeof(u16), GFP_KERNEL);
651 else
652 found = 1;
653 if (!save_state) {
654 dev_err(&dev->dev, "Out of memory in pci_save_pcie_state\n");
655 return -ENOMEM;
656 }
657 cap = (u16 *)&save_state->data[0];
658
659 pci_read_config_word(dev, pos + PCI_X_CMD, &cap[i++]);
660 save_state->cap_nr = PCI_CAP_ID_PCIX;
661 if (!found)
662 pci_add_saved_cap(dev, save_state);
663 return 0;
664 }
665
666 static void pci_restore_pcix_state(struct pci_dev *dev)
667 {
668 int i = 0, pos;
669 struct pci_cap_saved_state *save_state;
670 u16 *cap;
671
672 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
673 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
674 if (!save_state || pos <= 0)
675 return;
676 cap = (u16 *)&save_state->data[0];
677
678 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
679 }
680
681
682 /**
683 * pci_save_state - save the PCI configuration space of a device before suspending
684 * @dev: - PCI device that we're dealing with
685 */
686 int
687 pci_save_state(struct pci_dev *dev)
688 {
689 int i;
690 /* XXX: 100% dword access ok here? */
691 for (i = 0; i < 16; i++)
692 pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]);
693 if ((i = pci_save_pcie_state(dev)) != 0)
694 return i;
695 if ((i = pci_save_pcix_state(dev)) != 0)
696 return i;
697 return 0;
698 }
699
700 /**
701 * pci_restore_state - Restore the saved state of a PCI device
702 * @dev: - PCI device that we're dealing with
703 */
704 int
705 pci_restore_state(struct pci_dev *dev)
706 {
707 int i;
708 u32 val;
709
710 /* PCI Express register must be restored first */
711 pci_restore_pcie_state(dev);
712
713 /*
714 * The Base Address register should be programmed before the command
715 * register(s)
716 */
717 for (i = 15; i >= 0; i--) {
718 pci_read_config_dword(dev, i * 4, &val);
719 if (val != dev->saved_config_space[i]) {
720 printk(KERN_DEBUG "PM: Writing back config space on "
721 "device %s at offset %x (was %x, writing %x)\n",
722 pci_name(dev), i,
723 val, (int)dev->saved_config_space[i]);
724 pci_write_config_dword(dev,i * 4,
725 dev->saved_config_space[i]);
726 }
727 }
728 pci_restore_pcix_state(dev);
729 pci_restore_msi_state(dev);
730
731 return 0;
732 }
733
734 static int do_pci_enable_device(struct pci_dev *dev, int bars)
735 {
736 int err;
737
738 err = pci_set_power_state(dev, PCI_D0);
739 if (err < 0 && err != -EIO)
740 return err;
741 err = pcibios_enable_device(dev, bars);
742 if (err < 0)
743 return err;
744 pci_fixup_device(pci_fixup_enable, dev);
745
746 return 0;
747 }
748
749 /**
750 * pci_reenable_device - Resume abandoned device
751 * @dev: PCI device to be resumed
752 *
753 * Note this function is a backend of pci_default_resume and is not supposed
754 * to be called by normal code, write proper resume handler and use it instead.
755 */
756 int pci_reenable_device(struct pci_dev *dev)
757 {
758 if (atomic_read(&dev->enable_cnt))
759 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
760 return 0;
761 }
762
763 static int __pci_enable_device_flags(struct pci_dev *dev,
764 resource_size_t flags)
765 {
766 int err;
767 int i, bars = 0;
768
769 if (atomic_add_return(1, &dev->enable_cnt) > 1)
770 return 0; /* already enabled */
771
772 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
773 if (dev->resource[i].flags & flags)
774 bars |= (1 << i);
775
776 err = do_pci_enable_device(dev, bars);
777 if (err < 0)
778 atomic_dec(&dev->enable_cnt);
779 return err;
780 }
781
782 /**
783 * pci_enable_device_io - Initialize a device for use with IO space
784 * @dev: PCI device to be initialized
785 *
786 * Initialize device before it's used by a driver. Ask low-level code
787 * to enable I/O resources. Wake up the device if it was suspended.
788 * Beware, this function can fail.
789 */
790 int pci_enable_device_io(struct pci_dev *dev)
791 {
792 return __pci_enable_device_flags(dev, IORESOURCE_IO);
793 }
794
795 /**
796 * pci_enable_device_mem - Initialize a device for use with Memory space
797 * @dev: PCI device to be initialized
798 *
799 * Initialize device before it's used by a driver. Ask low-level code
800 * to enable Memory resources. Wake up the device if it was suspended.
801 * Beware, this function can fail.
802 */
803 int pci_enable_device_mem(struct pci_dev *dev)
804 {
805 return __pci_enable_device_flags(dev, IORESOURCE_MEM);
806 }
807
808 /**
809 * pci_enable_device - Initialize device before it's used by a driver.
810 * @dev: PCI device to be initialized
811 *
812 * Initialize device before it's used by a driver. Ask low-level code
813 * to enable I/O and memory. Wake up the device if it was suspended.
814 * Beware, this function can fail.
815 *
816 * Note we don't actually enable the device many times if we call
817 * this function repeatedly (we just increment the count).
818 */
819 int pci_enable_device(struct pci_dev *dev)
820 {
821 return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
822 }
823
824 /*
825 * Managed PCI resources. This manages device on/off, intx/msi/msix
826 * on/off and BAR regions. pci_dev itself records msi/msix status, so
827 * there's no need to track it separately. pci_devres is initialized
828 * when a device is enabled using managed PCI device enable interface.
829 */
830 struct pci_devres {
831 unsigned int enabled:1;
832 unsigned int pinned:1;
833 unsigned int orig_intx:1;
834 unsigned int restore_intx:1;
835 u32 region_mask;
836 };
837
838 static void pcim_release(struct device *gendev, void *res)
839 {
840 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
841 struct pci_devres *this = res;
842 int i;
843
844 if (dev->msi_enabled)
845 pci_disable_msi(dev);
846 if (dev->msix_enabled)
847 pci_disable_msix(dev);
848
849 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
850 if (this->region_mask & (1 << i))
851 pci_release_region(dev, i);
852
853 if (this->restore_intx)
854 pci_intx(dev, this->orig_intx);
855
856 if (this->enabled && !this->pinned)
857 pci_disable_device(dev);
858 }
859
860 static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
861 {
862 struct pci_devres *dr, *new_dr;
863
864 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
865 if (dr)
866 return dr;
867
868 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
869 if (!new_dr)
870 return NULL;
871 return devres_get(&pdev->dev, new_dr, NULL, NULL);
872 }
873
874 static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
875 {
876 if (pci_is_managed(pdev))
877 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
878 return NULL;
879 }
880
881 /**
882 * pcim_enable_device - Managed pci_enable_device()
883 * @pdev: PCI device to be initialized
884 *
885 * Managed pci_enable_device().
886 */
887 int pcim_enable_device(struct pci_dev *pdev)
888 {
889 struct pci_devres *dr;
890 int rc;
891
892 dr = get_pci_dr(pdev);
893 if (unlikely(!dr))
894 return -ENOMEM;
895 if (dr->enabled)
896 return 0;
897
898 rc = pci_enable_device(pdev);
899 if (!rc) {
900 pdev->is_managed = 1;
901 dr->enabled = 1;
902 }
903 return rc;
904 }
905
906 /**
907 * pcim_pin_device - Pin managed PCI device
908 * @pdev: PCI device to pin
909 *
910 * Pin managed PCI device @pdev. Pinned device won't be disabled on
911 * driver detach. @pdev must have been enabled with
912 * pcim_enable_device().
913 */
914 void pcim_pin_device(struct pci_dev *pdev)
915 {
916 struct pci_devres *dr;
917
918 dr = find_pci_dr(pdev);
919 WARN_ON(!dr || !dr->enabled);
920 if (dr)
921 dr->pinned = 1;
922 }
923
924 /**
925 * pcibios_disable_device - disable arch specific PCI resources for device dev
926 * @dev: the PCI device to disable
927 *
928 * Disables architecture specific PCI resources for the device. This
929 * is the default implementation. Architecture implementations can
930 * override this.
931 */
932 void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
933
934 /**
935 * pci_disable_device - Disable PCI device after use
936 * @dev: PCI device to be disabled
937 *
938 * Signal to the system that the PCI device is not in use by the system
939 * anymore. This only involves disabling PCI bus-mastering, if active.
940 *
941 * Note we don't actually disable the device until all callers of
942 * pci_device_enable() have called pci_device_disable().
943 */
944 void
945 pci_disable_device(struct pci_dev *dev)
946 {
947 struct pci_devres *dr;
948 u16 pci_command;
949
950 dr = find_pci_dr(dev);
951 if (dr)
952 dr->enabled = 0;
953
954 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
955 return;
956
957 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
958 if (pci_command & PCI_COMMAND_MASTER) {
959 pci_command &= ~PCI_COMMAND_MASTER;
960 pci_write_config_word(dev, PCI_COMMAND, pci_command);
961 }
962 dev->is_busmaster = 0;
963
964 pcibios_disable_device(dev);
965 }
966
967 /**
968 * pcibios_set_pcie_reset_state - set reset state for device dev
969 * @dev: the PCI-E device reset
970 * @state: Reset state to enter into
971 *
972 *
973 * Sets the PCI-E reset state for the device. This is the default
974 * implementation. Architecture implementations can override this.
975 */
976 int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
977 enum pcie_reset_state state)
978 {
979 return -EINVAL;
980 }
981
982 /**
983 * pci_set_pcie_reset_state - set reset state for device dev
984 * @dev: the PCI-E device reset
985 * @state: Reset state to enter into
986 *
987 *
988 * Sets the PCI reset state for the device.
989 */
990 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
991 {
992 return pcibios_set_pcie_reset_state(dev, state);
993 }
994
995 /**
996 * pci_enable_wake - enable PCI device as wakeup event source
997 * @dev: PCI device affected
998 * @state: PCI state from which device will issue wakeup events
999 * @enable: True to enable event generation; false to disable
1000 *
1001 * This enables the device as a wakeup event source, or disables it.
1002 * When such events involves platform-specific hooks, those hooks are
1003 * called automatically by this routine.
1004 *
1005 * Devices with legacy power management (no standard PCI PM capabilities)
1006 * always require such platform hooks. Depending on the platform, devices
1007 * supporting the standard PCI PME# signal may require such platform hooks;
1008 * they always update bits in config space to allow PME# generation.
1009 *
1010 * -EIO is returned if the device can't ever be a wakeup event source.
1011 * -EINVAL is returned if the device can't generate wakeup events from
1012 * the specified PCI state. Returns zero if the operation is successful.
1013 */
1014 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable)
1015 {
1016 int pm;
1017 int status;
1018 u16 value;
1019
1020 /* Note that drivers should verify device_may_wakeup(&dev->dev)
1021 * before calling this function. Platform code should report
1022 * errors when drivers try to enable wakeup on devices that
1023 * can't issue wakeups, or on which wakeups were disabled by
1024 * userspace updating the /sys/devices.../power/wakeup file.
1025 */
1026
1027 status = call_platform_enable_wakeup(&dev->dev, enable);
1028
1029 /* find PCI PM capability in list */
1030 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1031
1032 /* If device doesn't support PM Capabilities, but caller wants to
1033 * disable wake events, it's a NOP. Otherwise fail unless the
1034 * platform hooks handled this legacy device already.
1035 */
1036 if (!pm)
1037 return enable ? status : 0;
1038
1039 /* Check device's ability to generate PME# */
1040 pci_read_config_word(dev,pm+PCI_PM_PMC,&value);
1041
1042 value &= PCI_PM_CAP_PME_MASK;
1043 value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */
1044
1045 /* Check if it can generate PME# from requested state. */
1046 if (!value || !(value & (1 << state))) {
1047 /* if it can't, revert what the platform hook changed,
1048 * always reporting the base "EINVAL, can't PME#" error
1049 */
1050 if (enable)
1051 call_platform_enable_wakeup(&dev->dev, 0);
1052 return enable ? -EINVAL : 0;
1053 }
1054
1055 pci_read_config_word(dev, pm + PCI_PM_CTRL, &value);
1056
1057 /* Clear PME_Status by writing 1 to it and enable PME# */
1058 value |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1059
1060 if (!enable)
1061 value &= ~PCI_PM_CTRL_PME_ENABLE;
1062
1063 pci_write_config_word(dev, pm + PCI_PM_CTRL, value);
1064
1065 return 0;
1066 }
1067
1068 int
1069 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
1070 {
1071 u8 pin;
1072
1073 pin = dev->pin;
1074 if (!pin)
1075 return -1;
1076 pin--;
1077 while (dev->bus->self) {
1078 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
1079 dev = dev->bus->self;
1080 }
1081 *bridge = dev;
1082 return pin;
1083 }
1084
1085 /**
1086 * pci_release_region - Release a PCI bar
1087 * @pdev: PCI device whose resources were previously reserved by pci_request_region
1088 * @bar: BAR to release
1089 *
1090 * Releases the PCI I/O and memory resources previously reserved by a
1091 * successful call to pci_request_region. Call this function only
1092 * after all use of the PCI regions has ceased.
1093 */
1094 void pci_release_region(struct pci_dev *pdev, int bar)
1095 {
1096 struct pci_devres *dr;
1097
1098 if (pci_resource_len(pdev, bar) == 0)
1099 return;
1100 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
1101 release_region(pci_resource_start(pdev, bar),
1102 pci_resource_len(pdev, bar));
1103 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
1104 release_mem_region(pci_resource_start(pdev, bar),
1105 pci_resource_len(pdev, bar));
1106
1107 dr = find_pci_dr(pdev);
1108 if (dr)
1109 dr->region_mask &= ~(1 << bar);
1110 }
1111
1112 /**
1113 * pci_request_region - Reserved PCI I/O and memory resource
1114 * @pdev: PCI device whose resources are to be reserved
1115 * @bar: BAR to be reserved
1116 * @res_name: Name to be associated with resource.
1117 *
1118 * Mark the PCI region associated with PCI device @pdev BR @bar as
1119 * being reserved by owner @res_name. Do not access any
1120 * address inside the PCI regions unless this call returns
1121 * successfully.
1122 *
1123 * Returns 0 on success, or %EBUSY on error. A warning
1124 * message is also printed on failure.
1125 */
1126 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
1127 {
1128 struct pci_devres *dr;
1129
1130 if (pci_resource_len(pdev, bar) == 0)
1131 return 0;
1132
1133 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
1134 if (!request_region(pci_resource_start(pdev, bar),
1135 pci_resource_len(pdev, bar), res_name))
1136 goto err_out;
1137 }
1138 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
1139 if (!request_mem_region(pci_resource_start(pdev, bar),
1140 pci_resource_len(pdev, bar), res_name))
1141 goto err_out;
1142 }
1143
1144 dr = find_pci_dr(pdev);
1145 if (dr)
1146 dr->region_mask |= 1 << bar;
1147
1148 return 0;
1149
1150 err_out:
1151 printk (KERN_WARNING "PCI: Unable to reserve %s region #%d:%llx@%llx "
1152 "for device %s\n",
1153 pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem",
1154 bar + 1, /* PCI BAR # */
1155 (unsigned long long)pci_resource_len(pdev, bar),
1156 (unsigned long long)pci_resource_start(pdev, bar),
1157 pci_name(pdev));
1158 return -EBUSY;
1159 }
1160
1161 /**
1162 * pci_release_selected_regions - Release selected PCI I/O and memory resources
1163 * @pdev: PCI device whose resources were previously reserved
1164 * @bars: Bitmask of BARs to be released
1165 *
1166 * Release selected PCI I/O and memory resources previously reserved.
1167 * Call this function only after all use of the PCI regions has ceased.
1168 */
1169 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
1170 {
1171 int i;
1172
1173 for (i = 0; i < 6; i++)
1174 if (bars & (1 << i))
1175 pci_release_region(pdev, i);
1176 }
1177
1178 /**
1179 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
1180 * @pdev: PCI device whose resources are to be reserved
1181 * @bars: Bitmask of BARs to be requested
1182 * @res_name: Name to be associated with resource
1183 */
1184 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
1185 const char *res_name)
1186 {
1187 int i;
1188
1189 for (i = 0; i < 6; i++)
1190 if (bars & (1 << i))
1191 if(pci_request_region(pdev, i, res_name))
1192 goto err_out;
1193 return 0;
1194
1195 err_out:
1196 while(--i >= 0)
1197 if (bars & (1 << i))
1198 pci_release_region(pdev, i);
1199
1200 return -EBUSY;
1201 }
1202
1203 /**
1204 * pci_release_regions - Release reserved PCI I/O and memory resources
1205 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
1206 *
1207 * Releases all PCI I/O and memory resources previously reserved by a
1208 * successful call to pci_request_regions. Call this function only
1209 * after all use of the PCI regions has ceased.
1210 */
1211
1212 void pci_release_regions(struct pci_dev *pdev)
1213 {
1214 pci_release_selected_regions(pdev, (1 << 6) - 1);
1215 }
1216
1217 /**
1218 * pci_request_regions - Reserved PCI I/O and memory resources
1219 * @pdev: PCI device whose resources are to be reserved
1220 * @res_name: Name to be associated with resource.
1221 *
1222 * Mark all PCI regions associated with PCI device @pdev as
1223 * being reserved by owner @res_name. Do not access any
1224 * address inside the PCI regions unless this call returns
1225 * successfully.
1226 *
1227 * Returns 0 on success, or %EBUSY on error. A warning
1228 * message is also printed on failure.
1229 */
1230 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
1231 {
1232 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
1233 }
1234
1235 /**
1236 * pci_set_master - enables bus-mastering for device dev
1237 * @dev: the PCI device to enable
1238 *
1239 * Enables bus-mastering on the device and calls pcibios_set_master()
1240 * to do the needed arch specific settings.
1241 */
1242 void
1243 pci_set_master(struct pci_dev *dev)
1244 {
1245 u16 cmd;
1246
1247 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1248 if (! (cmd & PCI_COMMAND_MASTER)) {
1249 pr_debug("PCI: Enabling bus mastering for device %s\n", pci_name(dev));
1250 cmd |= PCI_COMMAND_MASTER;
1251 pci_write_config_word(dev, PCI_COMMAND, cmd);
1252 }
1253 dev->is_busmaster = 1;
1254 pcibios_set_master(dev);
1255 }
1256
1257 #ifdef PCI_DISABLE_MWI
1258 int pci_set_mwi(struct pci_dev *dev)
1259 {
1260 return 0;
1261 }
1262
1263 int pci_try_set_mwi(struct pci_dev *dev)
1264 {
1265 return 0;
1266 }
1267
1268 void pci_clear_mwi(struct pci_dev *dev)
1269 {
1270 }
1271
1272 #else
1273
1274 #ifndef PCI_CACHE_LINE_BYTES
1275 #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
1276 #endif
1277
1278 /* This can be overridden by arch code. */
1279 /* Don't forget this is measured in 32-bit words, not bytes */
1280 u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4;
1281
1282 /**
1283 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
1284 * @dev: the PCI device for which MWI is to be enabled
1285 *
1286 * Helper function for pci_set_mwi.
1287 * Originally copied from drivers/net/acenic.c.
1288 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
1289 *
1290 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1291 */
1292 static int
1293 pci_set_cacheline_size(struct pci_dev *dev)
1294 {
1295 u8 cacheline_size;
1296
1297 if (!pci_cache_line_size)
1298 return -EINVAL; /* The system doesn't support MWI. */
1299
1300 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
1301 equal to or multiple of the right value. */
1302 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
1303 if (cacheline_size >= pci_cache_line_size &&
1304 (cacheline_size % pci_cache_line_size) == 0)
1305 return 0;
1306
1307 /* Write the correct value. */
1308 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
1309 /* Read it back. */
1310 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
1311 if (cacheline_size == pci_cache_line_size)
1312 return 0;
1313
1314 printk(KERN_DEBUG "PCI: cache line size of %d is not supported "
1315 "by device %s\n", pci_cache_line_size << 2, pci_name(dev));
1316
1317 return -EINVAL;
1318 }
1319
1320 /**
1321 * pci_set_mwi - enables memory-write-invalidate PCI transaction
1322 * @dev: the PCI device for which MWI is enabled
1323 *
1324 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1325 *
1326 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1327 */
1328 int
1329 pci_set_mwi(struct pci_dev *dev)
1330 {
1331 int rc;
1332 u16 cmd;
1333
1334 rc = pci_set_cacheline_size(dev);
1335 if (rc)
1336 return rc;
1337
1338 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1339 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
1340 pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n",
1341 pci_name(dev));
1342 cmd |= PCI_COMMAND_INVALIDATE;
1343 pci_write_config_word(dev, PCI_COMMAND, cmd);
1344 }
1345
1346 return 0;
1347 }
1348
1349 /**
1350 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
1351 * @dev: the PCI device for which MWI is enabled
1352 *
1353 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1354 * Callers are not required to check the return value.
1355 *
1356 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1357 */
1358 int pci_try_set_mwi(struct pci_dev *dev)
1359 {
1360 int rc = pci_set_mwi(dev);
1361 return rc;
1362 }
1363
1364 /**
1365 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
1366 * @dev: the PCI device to disable
1367 *
1368 * Disables PCI Memory-Write-Invalidate transaction on the device
1369 */
1370 void
1371 pci_clear_mwi(struct pci_dev *dev)
1372 {
1373 u16 cmd;
1374
1375 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1376 if (cmd & PCI_COMMAND_INVALIDATE) {
1377 cmd &= ~PCI_COMMAND_INVALIDATE;
1378 pci_write_config_word(dev, PCI_COMMAND, cmd);
1379 }
1380 }
1381 #endif /* ! PCI_DISABLE_MWI */
1382
1383 /**
1384 * pci_intx - enables/disables PCI INTx for device dev
1385 * @pdev: the PCI device to operate on
1386 * @enable: boolean: whether to enable or disable PCI INTx
1387 *
1388 * Enables/disables PCI INTx for device dev
1389 */
1390 void
1391 pci_intx(struct pci_dev *pdev, int enable)
1392 {
1393 u16 pci_command, new;
1394
1395 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
1396
1397 if (enable) {
1398 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
1399 } else {
1400 new = pci_command | PCI_COMMAND_INTX_DISABLE;
1401 }
1402
1403 if (new != pci_command) {
1404 struct pci_devres *dr;
1405
1406 pci_write_config_word(pdev, PCI_COMMAND, new);
1407
1408 dr = find_pci_dr(pdev);
1409 if (dr && !dr->restore_intx) {
1410 dr->restore_intx = 1;
1411 dr->orig_intx = !enable;
1412 }
1413 }
1414 }
1415
1416 /**
1417 * pci_msi_off - disables any msi or msix capabilities
1418 * @dev: the PCI device to operate on
1419 *
1420 * If you want to use msi see pci_enable_msi and friends.
1421 * This is a lower level primitive that allows us to disable
1422 * msi operation at the device level.
1423 */
1424 void pci_msi_off(struct pci_dev *dev)
1425 {
1426 int pos;
1427 u16 control;
1428
1429 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
1430 if (pos) {
1431 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
1432 control &= ~PCI_MSI_FLAGS_ENABLE;
1433 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
1434 }
1435 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1436 if (pos) {
1437 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
1438 control &= ~PCI_MSIX_FLAGS_ENABLE;
1439 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
1440 }
1441 }
1442
1443 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
1444 /*
1445 * These can be overridden by arch-specific implementations
1446 */
1447 int
1448 pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1449 {
1450 if (!pci_dma_supported(dev, mask))
1451 return -EIO;
1452
1453 dev->dma_mask = mask;
1454
1455 return 0;
1456 }
1457
1458 int
1459 pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1460 {
1461 if (!pci_dma_supported(dev, mask))
1462 return -EIO;
1463
1464 dev->dev.coherent_dma_mask = mask;
1465
1466 return 0;
1467 }
1468 #endif
1469
1470 #ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE
1471 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
1472 {
1473 return dma_set_max_seg_size(&dev->dev, size);
1474 }
1475 EXPORT_SYMBOL(pci_set_dma_max_seg_size);
1476 #endif
1477
1478 #ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY
1479 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
1480 {
1481 return dma_set_seg_boundary(&dev->dev, mask);
1482 }
1483 EXPORT_SYMBOL(pci_set_dma_seg_boundary);
1484 #endif
1485
1486 /**
1487 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
1488 * @dev: PCI device to query
1489 *
1490 * Returns mmrbc: maximum designed memory read count in bytes
1491 * or appropriate error value.
1492 */
1493 int pcix_get_max_mmrbc(struct pci_dev *dev)
1494 {
1495 int err, cap;
1496 u32 stat;
1497
1498 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1499 if (!cap)
1500 return -EINVAL;
1501
1502 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
1503 if (err)
1504 return -EINVAL;
1505
1506 return (stat & PCI_X_STATUS_MAX_READ) >> 12;
1507 }
1508 EXPORT_SYMBOL(pcix_get_max_mmrbc);
1509
1510 /**
1511 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
1512 * @dev: PCI device to query
1513 *
1514 * Returns mmrbc: maximum memory read count in bytes
1515 * or appropriate error value.
1516 */
1517 int pcix_get_mmrbc(struct pci_dev *dev)
1518 {
1519 int ret, cap;
1520 u32 cmd;
1521
1522 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1523 if (!cap)
1524 return -EINVAL;
1525
1526 ret = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
1527 if (!ret)
1528 ret = 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
1529
1530 return ret;
1531 }
1532 EXPORT_SYMBOL(pcix_get_mmrbc);
1533
1534 /**
1535 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
1536 * @dev: PCI device to query
1537 * @mmrbc: maximum memory read count in bytes
1538 * valid values are 512, 1024, 2048, 4096
1539 *
1540 * If possible sets maximum memory read byte count, some bridges have erratas
1541 * that prevent this.
1542 */
1543 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
1544 {
1545 int cap, err = -EINVAL;
1546 u32 stat, cmd, v, o;
1547
1548 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
1549 goto out;
1550
1551 v = ffs(mmrbc) - 10;
1552
1553 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1554 if (!cap)
1555 goto out;
1556
1557 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
1558 if (err)
1559 goto out;
1560
1561 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
1562 return -E2BIG;
1563
1564 err = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
1565 if (err)
1566 goto out;
1567
1568 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
1569 if (o != v) {
1570 if (v > o && dev->bus &&
1571 (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
1572 return -EIO;
1573
1574 cmd &= ~PCI_X_CMD_MAX_READ;
1575 cmd |= v << 2;
1576 err = pci_write_config_dword(dev, cap + PCI_X_CMD, cmd);
1577 }
1578 out:
1579 return err;
1580 }
1581 EXPORT_SYMBOL(pcix_set_mmrbc);
1582
1583 /**
1584 * pcie_get_readrq - get PCI Express read request size
1585 * @dev: PCI device to query
1586 *
1587 * Returns maximum memory read request in bytes
1588 * or appropriate error value.
1589 */
1590 int pcie_get_readrq(struct pci_dev *dev)
1591 {
1592 int ret, cap;
1593 u16 ctl;
1594
1595 cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
1596 if (!cap)
1597 return -EINVAL;
1598
1599 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
1600 if (!ret)
1601 ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
1602
1603 return ret;
1604 }
1605 EXPORT_SYMBOL(pcie_get_readrq);
1606
1607 /**
1608 * pcie_set_readrq - set PCI Express maximum memory read request
1609 * @dev: PCI device to query
1610 * @rq: maximum memory read count in bytes
1611 * valid values are 128, 256, 512, 1024, 2048, 4096
1612 *
1613 * If possible sets maximum read byte count
1614 */
1615 int pcie_set_readrq(struct pci_dev *dev, int rq)
1616 {
1617 int cap, err = -EINVAL;
1618 u16 ctl, v;
1619
1620 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
1621 goto out;
1622
1623 v = (ffs(rq) - 8) << 12;
1624
1625 cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
1626 if (!cap)
1627 goto out;
1628
1629 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
1630 if (err)
1631 goto out;
1632
1633 if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
1634 ctl &= ~PCI_EXP_DEVCTL_READRQ;
1635 ctl |= v;
1636 err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl);
1637 }
1638
1639 out:
1640 return err;
1641 }
1642 EXPORT_SYMBOL(pcie_set_readrq);
1643
1644 /**
1645 * pci_select_bars - Make BAR mask from the type of resource
1646 * @dev: the PCI device for which BAR mask is made
1647 * @flags: resource type mask to be selected
1648 *
1649 * This helper routine makes bar mask from the type of resource.
1650 */
1651 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
1652 {
1653 int i, bars = 0;
1654 for (i = 0; i < PCI_NUM_RESOURCES; i++)
1655 if (pci_resource_flags(dev, i) & flags)
1656 bars |= (1 << i);
1657 return bars;
1658 }
1659
1660 static void __devinit pci_no_domains(void)
1661 {
1662 #ifdef CONFIG_PCI_DOMAINS
1663 pci_domains_supported = 0;
1664 #endif
1665 }
1666
1667 static int __devinit pci_init(void)
1668 {
1669 struct pci_dev *dev = NULL;
1670
1671 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1672 pci_fixup_device(pci_fixup_final, dev);
1673 }
1674 return 0;
1675 }
1676
1677 static int __devinit pci_setup(char *str)
1678 {
1679 while (str) {
1680 char *k = strchr(str, ',');
1681 if (k)
1682 *k++ = 0;
1683 if (*str && (str = pcibios_setup(str)) && *str) {
1684 if (!strcmp(str, "nomsi")) {
1685 pci_no_msi();
1686 } else if (!strcmp(str, "noaer")) {
1687 pci_no_aer();
1688 } else if (!strcmp(str, "nodomains")) {
1689 pci_no_domains();
1690 } else if (!strncmp(str, "cbiosize=", 9)) {
1691 pci_cardbus_io_size = memparse(str + 9, &str);
1692 } else if (!strncmp(str, "cbmemsize=", 10)) {
1693 pci_cardbus_mem_size = memparse(str + 10, &str);
1694 } else {
1695 printk(KERN_ERR "PCI: Unknown option `%s'\n",
1696 str);
1697 }
1698 }
1699 str = k;
1700 }
1701 return 0;
1702 }
1703 early_param("pci", pci_setup);
1704
1705 device_initcall(pci_init);
1706
1707 EXPORT_SYMBOL(pci_reenable_device);
1708 EXPORT_SYMBOL(pci_enable_device_io);
1709 EXPORT_SYMBOL(pci_enable_device_mem);
1710 EXPORT_SYMBOL(pci_enable_device);
1711 EXPORT_SYMBOL(pcim_enable_device);
1712 EXPORT_SYMBOL(pcim_pin_device);
1713 EXPORT_SYMBOL(pci_disable_device);
1714 EXPORT_SYMBOL(pci_find_capability);
1715 EXPORT_SYMBOL(pci_bus_find_capability);
1716 EXPORT_SYMBOL(pci_release_regions);
1717 EXPORT_SYMBOL(pci_request_regions);
1718 EXPORT_SYMBOL(pci_release_region);
1719 EXPORT_SYMBOL(pci_request_region);
1720 EXPORT_SYMBOL(pci_release_selected_regions);
1721 EXPORT_SYMBOL(pci_request_selected_regions);
1722 EXPORT_SYMBOL(pci_set_master);
1723 EXPORT_SYMBOL(pci_set_mwi);
1724 EXPORT_SYMBOL(pci_try_set_mwi);
1725 EXPORT_SYMBOL(pci_clear_mwi);
1726 EXPORT_SYMBOL_GPL(pci_intx);
1727 EXPORT_SYMBOL(pci_set_dma_mask);
1728 EXPORT_SYMBOL(pci_set_consistent_dma_mask);
1729 EXPORT_SYMBOL(pci_assign_resource);
1730 EXPORT_SYMBOL(pci_find_parent_resource);
1731 EXPORT_SYMBOL(pci_select_bars);
1732
1733 EXPORT_SYMBOL(pci_set_power_state);
1734 EXPORT_SYMBOL(pci_save_state);
1735 EXPORT_SYMBOL(pci_restore_state);
1736 EXPORT_SYMBOL(pci_enable_wake);
1737 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
1738
1739
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