1 /*
2 * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $
3 *
4 * PCI Bus Services, see include/linux/pci.h for further explanation.
5 *
6 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * David Mosberger-Tang
8 *
9 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 */
11
12 #include <linux/delay.h>
13 #include <linux/init.h>
14 #include <linux/pci.h>
15 #include <linux/module.h>
16 #include <linux/spinlock.h>
17 #include <asm/dma.h> /* isa_dma_bridge_buggy */
18
19 #undef DEBUG
20
21 #ifdef DEBUG
22 #define DBG(x...) printk(x)
23 #else
24 #define DBG(x...)
25 #endif
26
27 /**
28 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
29 * @bus: pointer to PCI bus structure to search
30 *
31 * Given a PCI bus, returns the highest PCI bus number present in the set
32 * including the given PCI bus and its list of child PCI buses.
33 */
34 unsigned char __devinit
35 pci_bus_max_busnr(struct pci_bus* bus)
36 {
37 struct list_head *tmp;
38 unsigned char max, n;
39
40 max = bus->number;
41 list_for_each(tmp, &bus->children) {
42 n = pci_bus_max_busnr(pci_bus_b(tmp));
43 if(n > max)
44 max = n;
45 }
46 return max;
47 }
48
49 /**
50 * pci_max_busnr - returns maximum PCI bus number
51 *
52 * Returns the highest PCI bus number present in the system global list of
53 * PCI buses.
54 */
55 unsigned char __devinit
56 pci_max_busnr(void)
57 {
58 struct pci_bus *bus = NULL;
59 unsigned char max, n;
60
61 max = 0;
62 while ((bus = pci_find_next_bus(bus)) != NULL) {
63 n = pci_bus_max_busnr(bus);
64 if(n > max)
65 max = n;
66 }
67 return max;
68 }
69
70 static int __pci_bus_find_cap(struct pci_bus *bus, unsigned int devfn, u8 hdr_type, int cap)
71 {
72 u16 status;
73 u8 pos, id;
74 int ttl = 48;
75
76 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
77 if (!(status & PCI_STATUS_CAP_LIST))
78 return 0;
79
80 switch (hdr_type) {
81 case PCI_HEADER_TYPE_NORMAL:
82 case PCI_HEADER_TYPE_BRIDGE:
83 pci_bus_read_config_byte(bus, devfn, PCI_CAPABILITY_LIST, &pos);
84 break;
85 case PCI_HEADER_TYPE_CARDBUS:
86 pci_bus_read_config_byte(bus, devfn, PCI_CB_CAPABILITY_LIST, &pos);
87 break;
88 default:
89 return 0;
90 }
91 while (ttl-- && pos >= 0x40) {
92 pos &= ~3;
93 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, &id);
94 if (id == 0xff)
95 break;
96 if (id == cap)
97 return pos;
98 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_NEXT, &pos);
99 }
100 return 0;
101 }
102
103 /**
104 * pci_find_capability - query for devices' capabilities
105 * @dev: PCI device to query
106 * @cap: capability code
107 *
108 * Tell if a device supports a given PCI capability.
109 * Returns the address of the requested capability structure within the
110 * device's PCI configuration space or 0 in case the device does not
111 * support it. Possible values for @cap:
112 *
113 * %PCI_CAP_ID_PM Power Management
114 * %PCI_CAP_ID_AGP Accelerated Graphics Port
115 * %PCI_CAP_ID_VPD Vital Product Data
116 * %PCI_CAP_ID_SLOTID Slot Identification
117 * %PCI_CAP_ID_MSI Message Signalled Interrupts
118 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
119 * %PCI_CAP_ID_PCIX PCI-X
120 * %PCI_CAP_ID_EXP PCI Express
121 */
122 int pci_find_capability(struct pci_dev *dev, int cap)
123 {
124 return __pci_bus_find_cap(dev->bus, dev->devfn, dev->hdr_type, cap);
125 }
126
127 /**
128 * pci_bus_find_capability - query for devices' capabilities
129 * @bus: the PCI bus to query
130 * @devfn: PCI device to query
131 * @cap: capability code
132 *
133 * Like pci_find_capability() but works for pci devices that do not have a
134 * pci_dev structure set up yet.
135 *
136 * Returns the address of the requested capability structure within the
137 * device's PCI configuration space or 0 in case the device does not
138 * support it.
139 */
140 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
141 {
142 u8 hdr_type;
143
144 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
145
146 return __pci_bus_find_cap(bus, devfn, hdr_type & 0x7f, cap);
147 }
148
149 /**
150 * pci_find_ext_capability - Find an extended capability
151 * @dev: PCI device to query
152 * @cap: capability code
153 *
154 * Returns the address of the requested extended capability structure
155 * within the device's PCI configuration space or 0 if the device does
156 * not support it. Possible values for @cap:
157 *
158 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
159 * %PCI_EXT_CAP_ID_VC Virtual Channel
160 * %PCI_EXT_CAP_ID_DSN Device Serial Number
161 * %PCI_EXT_CAP_ID_PWR Power Budgeting
162 */
163 int pci_find_ext_capability(struct pci_dev *dev, int cap)
164 {
165 u32 header;
166 int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */
167 int pos = 0x100;
168
169 if (dev->cfg_size <= 256)
170 return 0;
171
172 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
173 return 0;
174
175 /*
176 * If we have no capabilities, this is indicated by cap ID,
177 * cap version and next pointer all being 0.
178 */
179 if (header == 0)
180 return 0;
181
182 while (ttl-- > 0) {
183 if (PCI_EXT_CAP_ID(header) == cap)
184 return pos;
185
186 pos = PCI_EXT_CAP_NEXT(header);
187 if (pos < 0x100)
188 break;
189
190 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
191 break;
192 }
193
194 return 0;
195 }
196
197 /**
198 * pci_find_parent_resource - return resource region of parent bus of given region
199 * @dev: PCI device structure contains resources to be searched
200 * @res: child resource record for which parent is sought
201 *
202 * For given resource region of given device, return the resource
203 * region of parent bus the given region is contained in or where
204 * it should be allocated from.
205 */
206 struct resource *
207 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
208 {
209 const struct pci_bus *bus = dev->bus;
210 int i;
211 struct resource *best = NULL;
212
213 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
214 struct resource *r = bus->resource[i];
215 if (!r)
216 continue;
217 if (res->start && !(res->start >= r->start && res->end <= r->end))
218 continue; /* Not contained */
219 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
220 continue; /* Wrong type */
221 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
222 return r; /* Exact match */
223 if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH))
224 best = r; /* Approximating prefetchable by non-prefetchable */
225 }
226 return best;
227 }
228
229 /**
230 * pci_set_power_state - Set the power state of a PCI device
231 * @dev: PCI device to be suspended
232 * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering
233 *
234 * Transition a device to a new power state, using the Power Management
235 * Capabilities in the device's config space.
236 *
237 * RETURN VALUE:
238 * -EINVAL if trying to enter a lower state than we're already in.
239 * 0 if we're already in the requested state.
240 * -EIO if device does not support PCI PM.
241 * 0 if we can successfully change the power state.
242 */
243
244 int
245 pci_set_power_state(struct pci_dev *dev, pci_power_t state)
246 {
247 int pm;
248 u16 pmcsr, pmc;
249
250 /* bound the state we're entering */
251 if (state > PCI_D3hot)
252 state = PCI_D3hot;
253
254 /* Validate current state:
255 * Can enter D0 from any state, but if we can only go deeper
256 * to sleep if we're already in a low power state
257 */
258 if (state != PCI_D0 && dev->current_state > state)
259 return -EINVAL;
260 else if (dev->current_state == state)
261 return 0; /* we're already there */
262
263 /* find PCI PM capability in list */
264 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
265
266 /* abort if the device doesn't support PM capabilities */
267 if (!pm)
268 return -EIO;
269
270 pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc);
271 if ((pmc & PCI_PM_CAP_VER_MASK) > 2) {
272 printk(KERN_DEBUG
273 "PCI: %s has unsupported PM cap regs version (%u)\n",
274 dev->slot_name, pmc & PCI_PM_CAP_VER_MASK);
275 return -EIO;
276 }
277
278 /* check if this device supports the desired state */
279 if (state == PCI_D1 || state == PCI_D2) {
280 if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1))
281 return -EIO;
282 else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2))
283 return -EIO;
284 }
285
286 /* If we're in D3, force entire word to 0.
287 * This doesn't affect PME_Status, disables PME_En, and
288 * sets PowerState to 0.
289 */
290 if (dev->current_state >= PCI_D3hot)
291 pmcsr = 0;
292 else {
293 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
294 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
295 pmcsr |= state;
296 }
297
298 /* enter specified state */
299 pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr);
300
301 /* Mandatory power management transition delays */
302 /* see PCI PM 1.1 5.6.1 table 18 */
303 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
304 msleep(10);
305 else if (state == PCI_D2 || dev->current_state == PCI_D2)
306 udelay(200);
307 dev->current_state = state;
308
309 return 0;
310 }
311
312 /**
313 * pci_choose_state - Choose the power state of a PCI device
314 * @dev: PCI device to be suspended
315 * @state: target sleep state for the whole system
316 *
317 * Returns PCI power state suitable for given device and given system
318 * message.
319 */
320
321 pci_power_t pci_choose_state(struct pci_dev *dev, u32 state)
322 {
323 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
324 return PCI_D0;
325
326 switch (state) {
327 case 0: return PCI_D0;
328 case 2: return PCI_D2;
329 case 3: return PCI_D3hot;
330 default: BUG();
331 }
332 return PCI_D0;
333 }
334
335 EXPORT_SYMBOL(pci_choose_state);
336
337 /**
338 * pci_save_state - save the PCI configuration space of a device before suspending
339 * @dev: - PCI device that we're dealing with
340 * @buffer: - buffer to hold config space context
341 *
342 * @buffer must be large enough to hold the entire PCI 2.2 config space
343 * (>= 64 bytes).
344 */
345 int
346 pci_save_state(struct pci_dev *dev)
347 {
348 int i;
349 /* XXX: 100% dword access ok here? */
350 for (i = 0; i < 16; i++)
351 pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]);
352 return 0;
353 }
354
355 /**
356 * pci_restore_state - Restore the saved state of a PCI device
357 * @dev: - PCI device that we're dealing with
358 * @buffer: - saved PCI config space
359 *
360 */
361 int
362 pci_restore_state(struct pci_dev *dev)
363 {
364 int i;
365
366 for (i = 0; i < 16; i++)
367 pci_write_config_dword(dev,i * 4, dev->saved_config_space[i]);
368 return 0;
369 }
370
371 /**
372 * pci_enable_device_bars - Initialize some of a device for use
373 * @dev: PCI device to be initialized
374 * @bars: bitmask of BAR's that must be configured
375 *
376 * Initialize device before it's used by a driver. Ask low-level code
377 * to enable selected I/O and memory resources. Wake up the device if it
378 * was suspended. Beware, this function can fail.
379 */
380
381 int
382 pci_enable_device_bars(struct pci_dev *dev, int bars)
383 {
384 int err;
385
386 pci_set_power_state(dev, PCI_D0);
387 if ((err = pcibios_enable_device(dev, bars)) < 0)
388 return err;
389 return 0;
390 }
391
392 /**
393 * pci_enable_device - Initialize device before it's used by a driver.
394 * @dev: PCI device to be initialized
395 *
396 * Initialize device before it's used by a driver. Ask low-level code
397 * to enable I/O and memory. Wake up the device if it was suspended.
398 * Beware, this function can fail.
399 */
400 int
401 pci_enable_device(struct pci_dev *dev)
402 {
403 int err;
404
405 dev->is_enabled = 1;
406 if ((err = pci_enable_device_bars(dev, (1 << PCI_NUM_RESOURCES) - 1)))
407 return err;
408 pci_fixup_device(pci_fixup_enable, dev);
409 return 0;
410 }
411
412 /**
413 * pcibios_disable_device - disable arch specific PCI resources for device dev
414 * @dev: the PCI device to disable
415 *
416 * Disables architecture specific PCI resources for the device. This
417 * is the default implementation. Architecture implementations can
418 * override this.
419 */
420 void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
421
422 /**
423 * pci_disable_device - Disable PCI device after use
424 * @dev: PCI device to be disabled
425 *
426 * Signal to the system that the PCI device is not in use by the system
427 * anymore. This only involves disabling PCI bus-mastering, if active.
428 */
429 void
430 pci_disable_device(struct pci_dev *dev)
431 {
432 u16 pci_command;
433
434 dev->is_enabled = 0;
435 dev->is_busmaster = 0;
436
437 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
438 if (pci_command & PCI_COMMAND_MASTER) {
439 pci_command &= ~PCI_COMMAND_MASTER;
440 pci_write_config_word(dev, PCI_COMMAND, pci_command);
441 }
442
443 pcibios_disable_device(dev);
444 }
445
446 /**
447 * pci_enable_wake - enable device to generate PME# when suspended
448 * @dev: - PCI device to operate on
449 * @state: - Current state of device.
450 * @enable: - Flag to enable or disable generation
451 *
452 * Set the bits in the device's PM Capabilities to generate PME# when
453 * the system is suspended.
454 *
455 * -EIO is returned if device doesn't have PM Capabilities.
456 * -EINVAL is returned if device supports it, but can't generate wake events.
457 * 0 if operation is successful.
458 *
459 */
460 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable)
461 {
462 int pm;
463 u16 value;
464
465 /* find PCI PM capability in list */
466 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
467
468 /* If device doesn't support PM Capabilities, but request is to disable
469 * wake events, it's a nop; otherwise fail */
470 if (!pm)
471 return enable ? -EIO : 0;
472
473 /* Check device's ability to generate PME# */
474 pci_read_config_word(dev,pm+PCI_PM_PMC,&value);
475
476 value &= PCI_PM_CAP_PME_MASK;
477 value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */
478
479 /* Check if it can generate PME# from requested state. */
480 if (!value || !(value & (1 << state)))
481 return enable ? -EINVAL : 0;
482
483 pci_read_config_word(dev, pm + PCI_PM_CTRL, &value);
484
485 /* Clear PME_Status by writing 1 to it and enable PME# */
486 value |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
487
488 if (!enable)
489 value &= ~PCI_PM_CTRL_PME_ENABLE;
490
491 pci_write_config_word(dev, pm + PCI_PM_CTRL, value);
492
493 return 0;
494 }
495
496 int
497 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
498 {
499 u8 pin;
500
501 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
502 if (!pin)
503 return -1;
504 pin--;
505 while (dev->bus->self) {
506 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
507 dev = dev->bus->self;
508 }
509 *bridge = dev;
510 return pin;
511 }
512
513 /**
514 * pci_release_region - Release a PCI bar
515 * @pdev: PCI device whose resources were previously reserved by pci_request_region
516 * @bar: BAR to release
517 *
518 * Releases the PCI I/O and memory resources previously reserved by a
519 * successful call to pci_request_region. Call this function only
520 * after all use of the PCI regions has ceased.
521 */
522 void pci_release_region(struct pci_dev *pdev, int bar)
523 {
524 if (pci_resource_len(pdev, bar) == 0)
525 return;
526 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
527 release_region(pci_resource_start(pdev, bar),
528 pci_resource_len(pdev, bar));
529 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
530 release_mem_region(pci_resource_start(pdev, bar),
531 pci_resource_len(pdev, bar));
532 }
533
534 /**
535 * pci_request_region - Reserved PCI I/O and memory resource
536 * @pdev: PCI device whose resources are to be reserved
537 * @bar: BAR to be reserved
538 * @res_name: Name to be associated with resource.
539 *
540 * Mark the PCI region associated with PCI device @pdev BR @bar as
541 * being reserved by owner @res_name. Do not access any
542 * address inside the PCI regions unless this call returns
543 * successfully.
544 *
545 * Returns 0 on success, or %EBUSY on error. A warning
546 * message is also printed on failure.
547 */
548 int pci_request_region(struct pci_dev *pdev, int bar, char *res_name)
549 {
550 if (pci_resource_len(pdev, bar) == 0)
551 return 0;
552
553 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
554 if (!request_region(pci_resource_start(pdev, bar),
555 pci_resource_len(pdev, bar), res_name))
556 goto err_out;
557 }
558 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
559 if (!request_mem_region(pci_resource_start(pdev, bar),
560 pci_resource_len(pdev, bar), res_name))
561 goto err_out;
562 }
563
564 return 0;
565
566 err_out:
567 printk (KERN_WARNING "PCI: Unable to reserve %s region #%d:%lx@%lx for device %s\n",
568 pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem",
569 bar + 1, /* PCI BAR # */
570 pci_resource_len(pdev, bar), pci_resource_start(pdev, bar),
571 pci_name(pdev));
572 return -EBUSY;
573 }
574
575
576 /**
577 * pci_release_regions - Release reserved PCI I/O and memory resources
578 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
579 *
580 * Releases all PCI I/O and memory resources previously reserved by a
581 * successful call to pci_request_regions. Call this function only
582 * after all use of the PCI regions has ceased.
583 */
584
585 void pci_release_regions(struct pci_dev *pdev)
586 {
587 int i;
588
589 for (i = 0; i < 6; i++)
590 pci_release_region(pdev, i);
591 }
592
593 /**
594 * pci_request_regions - Reserved PCI I/O and memory resources
595 * @pdev: PCI device whose resources are to be reserved
596 * @res_name: Name to be associated with resource.
597 *
598 * Mark all PCI regions associated with PCI device @pdev as
599 * being reserved by owner @res_name. Do not access any
600 * address inside the PCI regions unless this call returns
601 * successfully.
602 *
603 * Returns 0 on success, or %EBUSY on error. A warning
604 * message is also printed on failure.
605 */
606 int pci_request_regions(struct pci_dev *pdev, char *res_name)
607 {
608 int i;
609
610 for (i = 0; i < 6; i++)
611 if(pci_request_region(pdev, i, res_name))
612 goto err_out;
613 return 0;
614
615 err_out:
616 while(--i >= 0)
617 pci_release_region(pdev, i);
618
619 return -EBUSY;
620 }
621
622 /**
623 * pci_set_master - enables bus-mastering for device dev
624 * @dev: the PCI device to enable
625 *
626 * Enables bus-mastering on the device and calls pcibios_set_master()
627 * to do the needed arch specific settings.
628 */
629 void
630 pci_set_master(struct pci_dev *dev)
631 {
632 u16 cmd;
633
634 pci_read_config_word(dev, PCI_COMMAND, &cmd);
635 if (! (cmd & PCI_COMMAND_MASTER)) {
636 DBG("PCI: Enabling bus mastering for device %s\n", pci_name(dev));
637 cmd |= PCI_COMMAND_MASTER;
638 pci_write_config_word(dev, PCI_COMMAND, cmd);
639 }
640 dev->is_busmaster = 1;
641 pcibios_set_master(dev);
642 }
643
644 #ifndef HAVE_ARCH_PCI_MWI
645 /* This can be overridden by arch code. */
646 u8 pci_cache_line_size = L1_CACHE_BYTES >> 2;
647
648 /**
649 * pci_generic_prep_mwi - helper function for pci_set_mwi
650 * @dev: the PCI device for which MWI is enabled
651 *
652 * Helper function for generic implementation of pcibios_prep_mwi
653 * function. Originally copied from drivers/net/acenic.c.
654 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
655 *
656 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
657 */
658 static int
659 pci_generic_prep_mwi(struct pci_dev *dev)
660 {
661 u8 cacheline_size;
662
663 if (!pci_cache_line_size)
664 return -EINVAL; /* The system doesn't support MWI. */
665
666 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
667 equal to or multiple of the right value. */
668 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
669 if (cacheline_size >= pci_cache_line_size &&
670 (cacheline_size % pci_cache_line_size) == 0)
671 return 0;
672
673 /* Write the correct value. */
674 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
675 /* Read it back. */
676 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
677 if (cacheline_size == pci_cache_line_size)
678 return 0;
679
680 printk(KERN_DEBUG "PCI: cache line size of %d is not supported "
681 "by device %s\n", pci_cache_line_size << 2, pci_name(dev));
682
683 return -EINVAL;
684 }
685 #endif /* !HAVE_ARCH_PCI_MWI */
686
687 /**
688 * pci_set_mwi - enables memory-write-invalidate PCI transaction
689 * @dev: the PCI device for which MWI is enabled
690 *
691 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND,
692 * and then calls @pcibios_set_mwi to do the needed arch specific
693 * operations or a generic mwi-prep function.
694 *
695 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
696 */
697 int
698 pci_set_mwi(struct pci_dev *dev)
699 {
700 int rc;
701 u16 cmd;
702
703 #ifdef HAVE_ARCH_PCI_MWI
704 rc = pcibios_prep_mwi(dev);
705 #else
706 rc = pci_generic_prep_mwi(dev);
707 #endif
708
709 if (rc)
710 return rc;
711
712 pci_read_config_word(dev, PCI_COMMAND, &cmd);
713 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
714 DBG("PCI: Enabling Mem-Wr-Inval for device %s\n", pci_name(dev));
715 cmd |= PCI_COMMAND_INVALIDATE;
716 pci_write_config_word(dev, PCI_COMMAND, cmd);
717 }
718
719 return 0;
720 }
721
722 /**
723 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
724 * @dev: the PCI device to disable
725 *
726 * Disables PCI Memory-Write-Invalidate transaction on the device
727 */
728 void
729 pci_clear_mwi(struct pci_dev *dev)
730 {
731 u16 cmd;
732
733 pci_read_config_word(dev, PCI_COMMAND, &cmd);
734 if (cmd & PCI_COMMAND_INVALIDATE) {
735 cmd &= ~PCI_COMMAND_INVALIDATE;
736 pci_write_config_word(dev, PCI_COMMAND, cmd);
737 }
738 }
739
740 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
741 /*
742 * These can be overridden by arch-specific implementations
743 */
744 int
745 pci_set_dma_mask(struct pci_dev *dev, u64 mask)
746 {
747 if (!pci_dma_supported(dev, mask))
748 return -EIO;
749
750 dev->dma_mask = mask;
751
752 return 0;
753 }
754
755 int
756 pci_dac_set_dma_mask(struct pci_dev *dev, u64 mask)
757 {
758 if (!pci_dac_dma_supported(dev, mask))
759 return -EIO;
760
761 dev->dma_mask = mask;
762
763 return 0;
764 }
765
766 int
767 pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
768 {
769 if (!pci_dma_supported(dev, mask))
770 return -EIO;
771
772 dev->dev.coherent_dma_mask = mask;
773
774 return 0;
775 }
776 #endif
777
778 static int __devinit pci_init(void)
779 {
780 struct pci_dev *dev = NULL;
781
782 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
783 pci_fixup_device(pci_fixup_final, dev);
784 }
785 return 0;
786 }
787
788 static int __devinit pci_setup(char *str)
789 {
790 while (str) {
791 char *k = strchr(str, ',');
792 if (k)
793 *k++ = 0;
794 if (*str && (str = pcibios_setup(str)) && *str) {
795 /* PCI layer options should be handled here */
796 printk(KERN_ERR "PCI: Unknown option `%s'\n", str);
797 }
798 str = k;
799 }
800 return 1;
801 }
802
803 device_initcall(pci_init);
804
805 __setup("pci=", pci_setup);
806
807 #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
808 /* FIXME: Some boxes have multiple ISA bridges! */
809 struct pci_dev *isa_bridge;
810 EXPORT_SYMBOL(isa_bridge);
811 #endif
812
813 EXPORT_SYMBOL(pci_enable_device_bars);
814 EXPORT_SYMBOL(pci_enable_device);
815 EXPORT_SYMBOL(pci_disable_device);
816 EXPORT_SYMBOL(pci_max_busnr);
817 EXPORT_SYMBOL(pci_bus_max_busnr);
818 EXPORT_SYMBOL(pci_find_capability);
819 EXPORT_SYMBOL(pci_bus_find_capability);
820 EXPORT_SYMBOL(pci_release_regions);
821 EXPORT_SYMBOL(pci_request_regions);
822 EXPORT_SYMBOL(pci_release_region);
823 EXPORT_SYMBOL(pci_request_region);
824 EXPORT_SYMBOL(pci_set_master);
825 EXPORT_SYMBOL(pci_set_mwi);
826 EXPORT_SYMBOL(pci_clear_mwi);
827 EXPORT_SYMBOL(pci_set_dma_mask);
828 EXPORT_SYMBOL(pci_dac_set_dma_mask);
829 EXPORT_SYMBOL(pci_set_consistent_dma_mask);
830 EXPORT_SYMBOL(pci_assign_resource);
831 EXPORT_SYMBOL(pci_find_parent_resource);
832
833 EXPORT_SYMBOL(pci_set_power_state);
834 EXPORT_SYMBOL(pci_save_state);
835 EXPORT_SYMBOL(pci_restore_state);
836 EXPORT_SYMBOL(pci_enable_wake);
837
838 /* Quirk info */
839
840 EXPORT_SYMBOL(isa_dma_bridge_buggy);
841 EXPORT_SYMBOL(pci_pci_problems);
842
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