1 /*
2 * Copyright (C) 2003-2004 Intel
3 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
4 */
5
6 #ifndef MSI_H
7 #define MSI_H
8
9 #define PCI_MSIX_ENTRY_SIZE 16
10 #define PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET 0
11 #define PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET 4
12 #define PCI_MSIX_ENTRY_DATA_OFFSET 8
13 #define PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET 12
14
15 #define msi_control_reg(base) (base + PCI_MSI_FLAGS)
16 #define msi_lower_address_reg(base) (base + PCI_MSI_ADDRESS_LO)
17 #define msi_upper_address_reg(base) (base + PCI_MSI_ADDRESS_HI)
18 #define msi_data_reg(base, is64bit) \
19 ( (is64bit == 1) ? base+PCI_MSI_DATA_64 : base+PCI_MSI_DATA_32 )
20 #define msi_mask_bits_reg(base, is64bit) \
21 ( (is64bit == 1) ? base+PCI_MSI_MASK_BIT : base+PCI_MSI_MASK_BIT-4)
22 #define msi_disable(control) control &= ~PCI_MSI_FLAGS_ENABLE
23 #define multi_msi_capable(control) \
24 (1 << ((control & PCI_MSI_FLAGS_QMASK) >> 1))
25 #define multi_msi_enable(control, num) \
26 control |= (((num >> 1) << 4) & PCI_MSI_FLAGS_QSIZE);
27 #define is_64bit_address(control) (!!(control & PCI_MSI_FLAGS_64BIT))
28 #define is_mask_bit_support(control) (!!(control & PCI_MSI_FLAGS_MASKBIT))
29 #define msi_enable(control, num) multi_msi_enable(control, num); \
30 control |= PCI_MSI_FLAGS_ENABLE
31
32 #define msix_table_offset_reg(base) (base + 0x04)
33 #define msix_pba_offset_reg(base) (base + 0x08)
34 #define msix_enable(control) control |= PCI_MSIX_FLAGS_ENABLE
35 #define msix_disable(control) control &= ~PCI_MSIX_FLAGS_ENABLE
36 #define msix_table_size(control) ((control & PCI_MSIX_FLAGS_QSIZE)+1)
37 #define multi_msix_capable msix_table_size
38 #define msix_unmask(address) (address & ~PCI_MSIX_FLAGS_BITMASK)
39 #define msix_mask(address) (address | PCI_MSIX_FLAGS_BITMASK)
40 #define msix_is_pending(address) (address & PCI_MSIX_FLAGS_PENDMASK)
41
42 #endif /* MSI_H */
43
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