1 /*
2 * File: msi.c
3 * Purpose: PCI Message Signaled Interrupt (MSI)
4 *
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
7 */
8
9 #include <linux/mm.h>
10 #include <linux/irq.h>
11 #include <linux/interrupt.h>
12 #include <linux/init.h>
13 #include <linux/config.h>
14 #include <linux/ioport.h>
15 #include <linux/smp_lock.h>
16 #include <linux/pci.h>
17 #include <linux/proc_fs.h>
18
19 #include <asm/errno.h>
20 #include <asm/io.h>
21 #include <asm/smp.h>
22
23 #include "msi.h"
24
25 static DEFINE_SPINLOCK(msi_lock);
26 static struct msi_desc* msi_desc[NR_IRQS] = { [0 ... NR_IRQS-1] = NULL };
27 static kmem_cache_t* msi_cachep;
28
29 static int pci_msi_enable = 1;
30 static int last_alloc_vector = 0;
31 static int nr_released_vectors = 0;
32 static int nr_reserved_vectors = NR_HP_RESERVED_VECTORS;
33 static int nr_msix_devices = 0;
34
35 #ifndef CONFIG_X86_IO_APIC
36 int vector_irq[NR_VECTORS] = { [0 ... NR_VECTORS - 1] = -1};
37 u8 irq_vector[NR_IRQ_VECTORS] = { FIRST_DEVICE_VECTOR , 0 };
38 #endif
39
40 static void msi_cache_ctor(void *p, kmem_cache_t *cache, unsigned long flags)
41 {
42 memset(p, 0, NR_IRQS * sizeof(struct msi_desc));
43 }
44
45 static int msi_cache_init(void)
46 {
47 msi_cachep = kmem_cache_create("msi_cache",
48 NR_IRQS * sizeof(struct msi_desc),
49 0, SLAB_HWCACHE_ALIGN, msi_cache_ctor, NULL);
50 if (!msi_cachep)
51 return -ENOMEM;
52
53 return 0;
54 }
55
56 static void msi_set_mask_bit(unsigned int vector, int flag)
57 {
58 struct msi_desc *entry;
59
60 entry = (struct msi_desc *)msi_desc[vector];
61 if (!entry || !entry->dev || !entry->mask_base)
62 return;
63 switch (entry->msi_attrib.type) {
64 case PCI_CAP_ID_MSI:
65 {
66 int pos;
67 u32 mask_bits;
68
69 pos = (int)entry->mask_base;
70 pci_read_config_dword(entry->dev, pos, &mask_bits);
71 mask_bits &= ~(1);
72 mask_bits |= flag;
73 pci_write_config_dword(entry->dev, pos, mask_bits);
74 break;
75 }
76 case PCI_CAP_ID_MSIX:
77 {
78 int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
79 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET;
80 writel(flag, entry->mask_base + offset);
81 break;
82 }
83 default:
84 break;
85 }
86 }
87
88 #ifdef CONFIG_SMP
89 static void set_msi_affinity(unsigned int vector, cpumask_t cpu_mask)
90 {
91 struct msi_desc *entry;
92 struct msg_address address;
93
94 entry = (struct msi_desc *)msi_desc[vector];
95 if (!entry || !entry->dev)
96 return;
97
98 switch (entry->msi_attrib.type) {
99 case PCI_CAP_ID_MSI:
100 {
101 int pos;
102
103 if (!(pos = pci_find_capability(entry->dev, PCI_CAP_ID_MSI)))
104 return;
105
106 pci_read_config_dword(entry->dev, msi_lower_address_reg(pos),
107 &address.lo_address.value);
108 address.lo_address.value &= MSI_ADDRESS_DEST_ID_MASK;
109 address.lo_address.value |= (cpu_mask_to_apicid(cpu_mask) <<
110 MSI_TARGET_CPU_SHIFT);
111 entry->msi_attrib.current_cpu = cpu_mask_to_apicid(cpu_mask);
112 pci_write_config_dword(entry->dev, msi_lower_address_reg(pos),
113 address.lo_address.value);
114 break;
115 }
116 case PCI_CAP_ID_MSIX:
117 {
118 int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
119 PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET;
120
121 address.lo_address.value = readl(entry->mask_base + offset);
122 address.lo_address.value &= MSI_ADDRESS_DEST_ID_MASK;
123 address.lo_address.value |= (cpu_mask_to_apicid(cpu_mask) <<
124 MSI_TARGET_CPU_SHIFT);
125 entry->msi_attrib.current_cpu = cpu_mask_to_apicid(cpu_mask);
126 writel(address.lo_address.value, entry->mask_base + offset);
127 break;
128 }
129 default:
130 break;
131 }
132 }
133
134 #ifdef CONFIG_IRQBALANCE
135 static inline void move_msi(int vector)
136 {
137 if (!cpus_empty(pending_irq_balance_cpumask[vector])) {
138 set_msi_affinity(vector, pending_irq_balance_cpumask[vector]);
139 cpus_clear(pending_irq_balance_cpumask[vector]);
140 }
141 }
142 #endif /* CONFIG_IRQBALANCE */
143 #endif /* CONFIG_SMP */
144
145 static void mask_MSI_irq(unsigned int vector)
146 {
147 msi_set_mask_bit(vector, 1);
148 }
149
150 static void unmask_MSI_irq(unsigned int vector)
151 {
152 msi_set_mask_bit(vector, 0);
153 }
154
155 static unsigned int startup_msi_irq_wo_maskbit(unsigned int vector)
156 {
157 struct msi_desc *entry;
158 unsigned long flags;
159
160 spin_lock_irqsave(&msi_lock, flags);
161 entry = msi_desc[vector];
162 if (!entry || !entry->dev) {
163 spin_unlock_irqrestore(&msi_lock, flags);
164 return 0;
165 }
166 entry->msi_attrib.state = 1; /* Mark it active */
167 spin_unlock_irqrestore(&msi_lock, flags);
168
169 return 0; /* never anything pending */
170 }
171
172 static void release_msi(unsigned int vector);
173 static void shutdown_msi_irq(unsigned int vector)
174 {
175 release_msi(vector);
176 }
177
178 #define shutdown_msi_irq_wo_maskbit shutdown_msi_irq
179 static void enable_msi_irq_wo_maskbit(unsigned int vector) {}
180 static void disable_msi_irq_wo_maskbit(unsigned int vector) {}
181 static void ack_msi_irq_wo_maskbit(unsigned int vector) {}
182 static void end_msi_irq_wo_maskbit(unsigned int vector)
183 {
184 move_msi(vector);
185 ack_APIC_irq();
186 }
187
188 static unsigned int startup_msi_irq_w_maskbit(unsigned int vector)
189 {
190 struct msi_desc *entry;
191 unsigned long flags;
192
193 spin_lock_irqsave(&msi_lock, flags);
194 entry = msi_desc[vector];
195 if (!entry || !entry->dev) {
196 spin_unlock_irqrestore(&msi_lock, flags);
197 return 0;
198 }
199 entry->msi_attrib.state = 1; /* Mark it active */
200 spin_unlock_irqrestore(&msi_lock, flags);
201
202 unmask_MSI_irq(vector);
203 return 0; /* never anything pending */
204 }
205
206 #define shutdown_msi_irq_w_maskbit shutdown_msi_irq
207 #define enable_msi_irq_w_maskbit unmask_MSI_irq
208 #define disable_msi_irq_w_maskbit mask_MSI_irq
209 #define ack_msi_irq_w_maskbit mask_MSI_irq
210
211 static void end_msi_irq_w_maskbit(unsigned int vector)
212 {
213 move_msi(vector);
214 unmask_MSI_irq(vector);
215 ack_APIC_irq();
216 }
217
218 /*
219 * Interrupt Type for MSI-X PCI/PCI-X/PCI-Express Devices,
220 * which implement the MSI-X Capability Structure.
221 */
222 static struct hw_interrupt_type msix_irq_type = {
223 .typename = "PCI-MSI-X",
224 .startup = startup_msi_irq_w_maskbit,
225 .shutdown = shutdown_msi_irq_w_maskbit,
226 .enable = enable_msi_irq_w_maskbit,
227 .disable = disable_msi_irq_w_maskbit,
228 .ack = ack_msi_irq_w_maskbit,
229 .end = end_msi_irq_w_maskbit,
230 .set_affinity = set_msi_irq_affinity
231 };
232
233 /*
234 * Interrupt Type for MSI PCI/PCI-X/PCI-Express Devices,
235 * which implement the MSI Capability Structure with
236 * Mask-and-Pending Bits.
237 */
238 static struct hw_interrupt_type msi_irq_w_maskbit_type = {
239 .typename = "PCI-MSI",
240 .startup = startup_msi_irq_w_maskbit,
241 .shutdown = shutdown_msi_irq_w_maskbit,
242 .enable = enable_msi_irq_w_maskbit,
243 .disable = disable_msi_irq_w_maskbit,
244 .ack = ack_msi_irq_w_maskbit,
245 .end = end_msi_irq_w_maskbit,
246 .set_affinity = set_msi_irq_affinity
247 };
248
249 /*
250 * Interrupt Type for MSI PCI/PCI-X/PCI-Express Devices,
251 * which implement the MSI Capability Structure without
252 * Mask-and-Pending Bits.
253 */
254 static struct hw_interrupt_type msi_irq_wo_maskbit_type = {
255 .typename = "PCI-MSI",
256 .startup = startup_msi_irq_wo_maskbit,
257 .shutdown = shutdown_msi_irq_wo_maskbit,
258 .enable = enable_msi_irq_wo_maskbit,
259 .disable = disable_msi_irq_wo_maskbit,
260 .ack = ack_msi_irq_wo_maskbit,
261 .end = end_msi_irq_wo_maskbit,
262 .set_affinity = set_msi_irq_affinity
263 };
264
265 static void msi_data_init(struct msg_data *msi_data,
266 unsigned int vector)
267 {
268 memset(msi_data, 0, sizeof(struct msg_data));
269 msi_data->vector = (u8)vector;
270 msi_data->delivery_mode = MSI_DELIVERY_MODE;
271 msi_data->level = MSI_LEVEL_MODE;
272 msi_data->trigger = MSI_TRIGGER_MODE;
273 }
274
275 static void msi_address_init(struct msg_address *msi_address)
276 {
277 unsigned int dest_id;
278
279 memset(msi_address, 0, sizeof(struct msg_address));
280 msi_address->hi_address = (u32)0;
281 dest_id = (MSI_ADDRESS_HEADER << MSI_ADDRESS_HEADER_SHIFT);
282 msi_address->lo_address.u.dest_mode = MSI_DEST_MODE;
283 msi_address->lo_address.u.redirection_hint = MSI_REDIRECTION_HINT_MODE;
284 msi_address->lo_address.u.dest_id = dest_id;
285 msi_address->lo_address.value |= (MSI_TARGET_CPU << MSI_TARGET_CPU_SHIFT);
286 }
287
288 static int msi_free_vector(struct pci_dev* dev, int vector, int reassign);
289 static int assign_msi_vector(void)
290 {
291 static int new_vector_avail = 1;
292 int vector;
293 unsigned long flags;
294
295 /*
296 * msi_lock is provided to ensure that successful allocation of MSI
297 * vector is assigned unique among drivers.
298 */
299 spin_lock_irqsave(&msi_lock, flags);
300
301 if (!new_vector_avail) {
302 int free_vector = 0;
303
304 /*
305 * vector_irq[] = -1 indicates that this specific vector is:
306 * - assigned for MSI (since MSI have no associated IRQ) or
307 * - assigned for legacy if less than 16, or
308 * - having no corresponding 1:1 vector-to-IOxAPIC IRQ mapping
309 * vector_irq[] = 0 indicates that this vector, previously
310 * assigned for MSI, is freed by hotplug removed operations.
311 * This vector will be reused for any subsequent hotplug added
312 * operations.
313 * vector_irq[] > 0 indicates that this vector is assigned for
314 * IOxAPIC IRQs. This vector and its value provides a 1-to-1
315 * vector-to-IOxAPIC IRQ mapping.
316 */
317 for (vector = FIRST_DEVICE_VECTOR; vector < NR_IRQS; vector++) {
318 if (vector_irq[vector] != 0)
319 continue;
320 free_vector = vector;
321 if (!msi_desc[vector])
322 break;
323 else
324 continue;
325 }
326 if (!free_vector) {
327 spin_unlock_irqrestore(&msi_lock, flags);
328 return -EBUSY;
329 }
330 vector_irq[free_vector] = -1;
331 nr_released_vectors--;
332 spin_unlock_irqrestore(&msi_lock, flags);
333 if (msi_desc[free_vector] != NULL) {
334 struct pci_dev *dev;
335 int tail;
336
337 /* free all linked vectors before re-assign */
338 do {
339 spin_lock_irqsave(&msi_lock, flags);
340 dev = msi_desc[free_vector]->dev;
341 tail = msi_desc[free_vector]->link.tail;
342 spin_unlock_irqrestore(&msi_lock, flags);
343 msi_free_vector(dev, tail, 1);
344 } while (free_vector != tail);
345 }
346
347 return free_vector;
348 }
349 vector = assign_irq_vector(AUTO_ASSIGN);
350 last_alloc_vector = vector;
351 if (vector == LAST_DEVICE_VECTOR)
352 new_vector_avail = 0;
353
354 spin_unlock_irqrestore(&msi_lock, flags);
355 return vector;
356 }
357
358 static int get_new_vector(void)
359 {
360 int vector;
361
362 if ((vector = assign_msi_vector()) > 0)
363 set_intr_gate(vector, interrupt[vector]);
364
365 return vector;
366 }
367
368 static int msi_init(void)
369 {
370 static int status = -ENOMEM;
371
372 if (!status)
373 return status;
374
375 if ((status = msi_cache_init()) < 0) {
376 pci_msi_enable = 0;
377 printk(KERN_WARNING "PCI: MSI cache init failed\n");
378 return status;
379 }
380 last_alloc_vector = assign_irq_vector(AUTO_ASSIGN);
381 if (last_alloc_vector < 0) {
382 pci_msi_enable = 0;
383 printk(KERN_WARNING "PCI: No interrupt vectors available for MSI\n");
384 status = -EBUSY;
385 return status;
386 }
387 vector_irq[last_alloc_vector] = 0;
388 nr_released_vectors++;
389
390 return status;
391 }
392
393 static int get_msi_vector(struct pci_dev *dev)
394 {
395 return get_new_vector();
396 }
397
398 static struct msi_desc* alloc_msi_entry(void)
399 {
400 struct msi_desc *entry;
401
402 entry = (struct msi_desc*) kmem_cache_alloc(msi_cachep, SLAB_KERNEL);
403 if (!entry)
404 return NULL;
405
406 memset(entry, 0, sizeof(struct msi_desc));
407 entry->link.tail = entry->link.head = 0; /* single message */
408 entry->dev = NULL;
409
410 return entry;
411 }
412
413 static void attach_msi_entry(struct msi_desc *entry, int vector)
414 {
415 unsigned long flags;
416
417 spin_lock_irqsave(&msi_lock, flags);
418 msi_desc[vector] = entry;
419 spin_unlock_irqrestore(&msi_lock, flags);
420 }
421
422 static void irq_handler_init(int cap_id, int pos, int mask)
423 {
424 spin_lock(&irq_desc[pos].lock);
425 if (cap_id == PCI_CAP_ID_MSIX)
426 irq_desc[pos].handler = &msix_irq_type;
427 else {
428 if (!mask)
429 irq_desc[pos].handler = &msi_irq_wo_maskbit_type;
430 else
431 irq_desc[pos].handler = &msi_irq_w_maskbit_type;
432 }
433 spin_unlock(&irq_desc[pos].lock);
434 }
435
436 static void enable_msi_mode(struct pci_dev *dev, int pos, int type)
437 {
438 u16 control;
439
440 pci_read_config_word(dev, msi_control_reg(pos), &control);
441 if (type == PCI_CAP_ID_MSI) {
442 /* Set enabled bits to single MSI & enable MSI_enable bit */
443 msi_enable(control, 1);
444 pci_write_config_word(dev, msi_control_reg(pos), control);
445 } else {
446 msix_enable(control);
447 pci_write_config_word(dev, msi_control_reg(pos), control);
448 }
449 if (pci_find_capability(dev, PCI_CAP_ID_EXP)) {
450 /* PCI Express Endpoint device detected */
451 u16 cmd;
452 pci_read_config_word(dev, PCI_COMMAND, &cmd);
453 cmd |= PCI_COMMAND_INTX_DISABLE;
454 pci_write_config_word(dev, PCI_COMMAND, cmd);
455 }
456 }
457
458 static void disable_msi_mode(struct pci_dev *dev, int pos, int type)
459 {
460 u16 control;
461
462 pci_read_config_word(dev, msi_control_reg(pos), &control);
463 if (type == PCI_CAP_ID_MSI) {
464 /* Set enabled bits to single MSI & enable MSI_enable bit */
465 msi_disable(control);
466 pci_write_config_word(dev, msi_control_reg(pos), control);
467 } else {
468 msix_disable(control);
469 pci_write_config_word(dev, msi_control_reg(pos), control);
470 }
471 if (pci_find_capability(dev, PCI_CAP_ID_EXP)) {
472 /* PCI Express Endpoint device detected */
473 u16 cmd;
474 pci_read_config_word(dev, PCI_COMMAND, &cmd);
475 cmd &= ~PCI_COMMAND_INTX_DISABLE;
476 pci_write_config_word(dev, PCI_COMMAND, cmd);
477 }
478 }
479
480 static int msi_lookup_vector(struct pci_dev *dev, int type)
481 {
482 int vector;
483 unsigned long flags;
484
485 spin_lock_irqsave(&msi_lock, flags);
486 for (vector = FIRST_DEVICE_VECTOR; vector < NR_IRQS; vector++) {
487 if (!msi_desc[vector] || msi_desc[vector]->dev != dev ||
488 msi_desc[vector]->msi_attrib.type != type ||
489 msi_desc[vector]->msi_attrib.default_vector != dev->irq)
490 continue;
491 spin_unlock_irqrestore(&msi_lock, flags);
492 /* This pre-assigned MSI vector for this device
493 already exits. Override dev->irq with this vector */
494 dev->irq = vector;
495 return 0;
496 }
497 spin_unlock_irqrestore(&msi_lock, flags);
498
499 return -EACCES;
500 }
501
502 void pci_scan_msi_device(struct pci_dev *dev)
503 {
504 if (!dev)
505 return;
506
507 if (pci_find_capability(dev, PCI_CAP_ID_MSIX) > 0)
508 nr_msix_devices++;
509 else if (pci_find_capability(dev, PCI_CAP_ID_MSI) > 0)
510 nr_reserved_vectors++;
511 }
512
513 /**
514 * msi_capability_init - configure device's MSI capability structure
515 * @dev: pointer to the pci_dev data structure of MSI device function
516 *
517 * Setup the MSI capability structure of device funtion with a single
518 * MSI vector, regardless of device function is capable of handling
519 * multiple messages. A return of zero indicates the successful setup
520 * of an entry zero with the new MSI vector or non-zero for otherwise.
521 **/
522 static int msi_capability_init(struct pci_dev *dev)
523 {
524 struct msi_desc *entry;
525 struct msg_address address;
526 struct msg_data data;
527 int pos, vector;
528 u16 control;
529
530 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
531 pci_read_config_word(dev, msi_control_reg(pos), &control);
532 /* MSI Entry Initialization */
533 if (!(entry = alloc_msi_entry()))
534 return -ENOMEM;
535
536 if ((vector = get_msi_vector(dev)) < 0) {
537 kmem_cache_free(msi_cachep, entry);
538 return -EBUSY;
539 }
540 entry->link.head = vector;
541 entry->link.tail = vector;
542 entry->msi_attrib.type = PCI_CAP_ID_MSI;
543 entry->msi_attrib.state = 0; /* Mark it not active */
544 entry->msi_attrib.entry_nr = 0;
545 entry->msi_attrib.maskbit = is_mask_bit_support(control);
546 entry->msi_attrib.default_vector = dev->irq; /* Save IOAPIC IRQ */
547 dev->irq = vector;
548 entry->dev = dev;
549 if (is_mask_bit_support(control)) {
550 entry->mask_base = (void __iomem *)msi_mask_bits_reg(pos,
551 is_64bit_address(control));
552 }
553 /* Replace with MSI handler */
554 irq_handler_init(PCI_CAP_ID_MSI, vector, entry->msi_attrib.maskbit);
555 /* Configure MSI capability structure */
556 msi_address_init(&address);
557 msi_data_init(&data, vector);
558 entry->msi_attrib.current_cpu = ((address.lo_address.u.dest_id >>
559 MSI_TARGET_CPU_SHIFT) & MSI_TARGET_CPU_MASK);
560 pci_write_config_dword(dev, msi_lower_address_reg(pos),
561 address.lo_address.value);
562 if (is_64bit_address(control)) {
563 pci_write_config_dword(dev,
564 msi_upper_address_reg(pos), address.hi_address);
565 pci_write_config_word(dev,
566 msi_data_reg(pos, 1), *((u32*)&data));
567 } else
568 pci_write_config_word(dev,
569 msi_data_reg(pos, 0), *((u32*)&data));
570 if (entry->msi_attrib.maskbit) {
571 unsigned int maskbits, temp;
572 /* All MSIs are unmasked by default, Mask them all */
573 pci_read_config_dword(dev,
574 msi_mask_bits_reg(pos, is_64bit_address(control)),
575 &maskbits);
576 temp = (1 << multi_msi_capable(control));
577 temp = ((temp - 1) & ~temp);
578 maskbits |= temp;
579 pci_write_config_dword(dev,
580 msi_mask_bits_reg(pos, is_64bit_address(control)),
581 maskbits);
582 }
583 attach_msi_entry(entry, vector);
584 /* Set MSI enabled bits */
585 enable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
586
587 return 0;
588 }
589
590 /**
591 * msix_capability_init - configure device's MSI-X capability
592 * @dev: pointer to the pci_dev data structure of MSI-X device function
593 *
594 * Setup the MSI-X capability structure of device funtion with a
595 * single MSI-X vector. A return of zero indicates the successful setup of
596 * requested MSI-X entries with allocated vectors or non-zero for otherwise.
597 **/
598 static int msix_capability_init(struct pci_dev *dev,
599 struct msix_entry *entries, int nvec)
600 {
601 struct msi_desc *head = NULL, *tail = NULL, *entry = NULL;
602 struct msg_address address;
603 struct msg_data data;
604 int vector, pos, i, j, nr_entries, temp = 0;
605 u32 phys_addr, table_offset;
606 u16 control;
607 u8 bir;
608 void __iomem *base;
609
610 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
611 /* Request & Map MSI-X table region */
612 pci_read_config_word(dev, msi_control_reg(pos), &control);
613 nr_entries = multi_msix_capable(control);
614 pci_read_config_dword(dev, msix_table_offset_reg(pos),
615 &table_offset);
616 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
617 phys_addr = pci_resource_start (dev, bir);
618 phys_addr += (u32)(table_offset & ~PCI_MSIX_FLAGS_BIRMASK);
619 if (!request_mem_region(phys_addr,
620 nr_entries * PCI_MSIX_ENTRY_SIZE,
621 "MSI-X vector table"))
622 return -ENOMEM;
623 base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
624 if (base == NULL) {
625 release_mem_region(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
626 return -ENOMEM;
627 }
628 /* MSI-X Table Initialization */
629 for (i = 0; i < nvec; i++) {
630 entry = alloc_msi_entry();
631 if (!entry)
632 break;
633 if ((vector = get_msi_vector(dev)) < 0)
634 break;
635
636 j = entries[i].entry;
637 entries[i].vector = vector;
638 entry->msi_attrib.type = PCI_CAP_ID_MSIX;
639 entry->msi_attrib.state = 0; /* Mark it not active */
640 entry->msi_attrib.entry_nr = j;
641 entry->msi_attrib.maskbit = 1;
642 entry->msi_attrib.default_vector = dev->irq;
643 entry->dev = dev;
644 entry->mask_base = base;
645 if (!head) {
646 entry->link.head = vector;
647 entry->link.tail = vector;
648 head = entry;
649 } else {
650 entry->link.head = temp;
651 entry->link.tail = tail->link.tail;
652 tail->link.tail = vector;
653 head->link.head = vector;
654 }
655 temp = vector;
656 tail = entry;
657 /* Replace with MSI-X handler */
658 irq_handler_init(PCI_CAP_ID_MSIX, vector, 1);
659 /* Configure MSI-X capability structure */
660 msi_address_init(&address);
661 msi_data_init(&data, vector);
662 entry->msi_attrib.current_cpu =
663 ((address.lo_address.u.dest_id >>
664 MSI_TARGET_CPU_SHIFT) & MSI_TARGET_CPU_MASK);
665 writel(address.lo_address.value,
666 base + j * PCI_MSIX_ENTRY_SIZE +
667 PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
668 writel(address.hi_address,
669 base + j * PCI_MSIX_ENTRY_SIZE +
670 PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
671 writel(*(u32*)&data,
672 base + j * PCI_MSIX_ENTRY_SIZE +
673 PCI_MSIX_ENTRY_DATA_OFFSET);
674 attach_msi_entry(entry, vector);
675 }
676 if (i != nvec) {
677 i--;
678 for (; i >= 0; i--) {
679 vector = (entries + i)->vector;
680 msi_free_vector(dev, vector, 0);
681 (entries + i)->vector = 0;
682 }
683 return -EBUSY;
684 }
685 /* Set MSI-X enabled bits */
686 enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
687
688 return 0;
689 }
690
691 /**
692 * pci_enable_msi - configure device's MSI capability structure
693 * @dev: pointer to the pci_dev data structure of MSI device function
694 *
695 * Setup the MSI capability structure of device function with
696 * a single MSI vector upon its software driver call to request for
697 * MSI mode enabled on its hardware device function. A return of zero
698 * indicates the successful setup of an entry zero with the new MSI
699 * vector or non-zero for otherwise.
700 **/
701 int pci_enable_msi(struct pci_dev* dev)
702 {
703 int pos, temp = dev->irq, status = -EINVAL;
704 u16 control;
705
706 if (!pci_msi_enable || !dev)
707 return status;
708
709 if ((status = msi_init()) < 0)
710 return status;
711
712 if (!(pos = pci_find_capability(dev, PCI_CAP_ID_MSI)))
713 return -EINVAL;
714
715 pci_read_config_word(dev, msi_control_reg(pos), &control);
716 if (control & PCI_MSI_FLAGS_ENABLE)
717 return 0; /* Already in MSI mode */
718
719 if (!msi_lookup_vector(dev, PCI_CAP_ID_MSI)) {
720 /* Lookup Sucess */
721 unsigned long flags;
722
723 spin_lock_irqsave(&msi_lock, flags);
724 if (!vector_irq[dev->irq]) {
725 msi_desc[dev->irq]->msi_attrib.state = 0;
726 vector_irq[dev->irq] = -1;
727 nr_released_vectors--;
728 spin_unlock_irqrestore(&msi_lock, flags);
729 enable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
730 return 0;
731 }
732 spin_unlock_irqrestore(&msi_lock, flags);
733 dev->irq = temp;
734 }
735 /* Check whether driver already requested for MSI-X vectors */
736 if ((pos = pci_find_capability(dev, PCI_CAP_ID_MSIX)) > 0 &&
737 !msi_lookup_vector(dev, PCI_CAP_ID_MSIX)) {
738 printk(KERN_INFO "PCI: %s: Can't enable MSI. "
739 "Device already has MSI-X vectors assigned\n",
740 pci_name(dev));
741 dev->irq = temp;
742 return -EINVAL;
743 }
744 status = msi_capability_init(dev);
745 if (!status) {
746 if (!pos)
747 nr_reserved_vectors--; /* Only MSI capable */
748 else if (nr_msix_devices > 0)
749 nr_msix_devices--; /* Both MSI and MSI-X capable,
750 but choose enabling MSI */
751 }
752
753 return status;
754 }
755
756 void pci_disable_msi(struct pci_dev* dev)
757 {
758 struct msi_desc *entry;
759 int pos, default_vector;
760 u16 control;
761 unsigned long flags;
762
763 if (!dev || !(pos = pci_find_capability(dev, PCI_CAP_ID_MSI)))
764 return;
765
766 pci_read_config_word(dev, msi_control_reg(pos), &control);
767 if (!(control & PCI_MSI_FLAGS_ENABLE))
768 return;
769
770 spin_lock_irqsave(&msi_lock, flags);
771 entry = msi_desc[dev->irq];
772 if (!entry || !entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI) {
773 spin_unlock_irqrestore(&msi_lock, flags);
774 return;
775 }
776 if (entry->msi_attrib.state) {
777 spin_unlock_irqrestore(&msi_lock, flags);
778 printk(KERN_WARNING "PCI: %s: pci_disable_msi() called without "
779 "free_irq() on MSI vector %d\n",
780 pci_name(dev), dev->irq);
781 BUG_ON(entry->msi_attrib.state > 0);
782 } else {
783 vector_irq[dev->irq] = 0; /* free it */
784 nr_released_vectors++;
785 default_vector = entry->msi_attrib.default_vector;
786 spin_unlock_irqrestore(&msi_lock, flags);
787 /* Restore dev->irq to its default pin-assertion vector */
788 dev->irq = default_vector;
789 disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI),
790 PCI_CAP_ID_MSI);
791 }
792 }
793
794 static void release_msi(unsigned int vector)
795 {
796 struct msi_desc *entry;
797 unsigned long flags;
798
799 spin_lock_irqsave(&msi_lock, flags);
800 entry = msi_desc[vector];
801 if (entry && entry->dev)
802 entry->msi_attrib.state = 0; /* Mark it not active */
803 spin_unlock_irqrestore(&msi_lock, flags);
804 }
805
806 static int msi_free_vector(struct pci_dev* dev, int vector, int reassign)
807 {
808 struct msi_desc *entry;
809 int head, entry_nr, type;
810 void __iomem *base;
811 unsigned long flags;
812
813 spin_lock_irqsave(&msi_lock, flags);
814 entry = msi_desc[vector];
815 if (!entry || entry->dev != dev) {
816 spin_unlock_irqrestore(&msi_lock, flags);
817 return -EINVAL;
818 }
819 type = entry->msi_attrib.type;
820 entry_nr = entry->msi_attrib.entry_nr;
821 head = entry->link.head;
822 base = entry->mask_base;
823 msi_desc[entry->link.head]->link.tail = entry->link.tail;
824 msi_desc[entry->link.tail]->link.head = entry->link.head;
825 entry->dev = NULL;
826 if (!reassign) {
827 vector_irq[vector] = 0;
828 nr_released_vectors++;
829 }
830 msi_desc[vector] = NULL;
831 spin_unlock_irqrestore(&msi_lock, flags);
832
833 kmem_cache_free(msi_cachep, entry);
834
835 if (type == PCI_CAP_ID_MSIX) {
836 if (!reassign)
837 writel(1, base +
838 entry_nr * PCI_MSIX_ENTRY_SIZE +
839 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET);
840
841 if (head == vector) {
842 /*
843 * Detect last MSI-X vector to be released.
844 * Release the MSI-X memory-mapped table.
845 */
846 int pos, nr_entries;
847 u32 phys_addr, table_offset;
848 u16 control;
849 u8 bir;
850
851 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
852 pci_read_config_word(dev, msi_control_reg(pos),
853 &control);
854 nr_entries = multi_msix_capable(control);
855 pci_read_config_dword(dev, msix_table_offset_reg(pos),
856 &table_offset);
857 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
858 phys_addr = pci_resource_start (dev, bir);
859 phys_addr += (u32)(table_offset &
860 ~PCI_MSIX_FLAGS_BIRMASK);
861 iounmap(base);
862 release_mem_region(phys_addr,
863 nr_entries * PCI_MSIX_ENTRY_SIZE);
864 }
865 }
866
867 return 0;
868 }
869
870 static int reroute_msix_table(int head, struct msix_entry *entries, int *nvec)
871 {
872 int vector = head, tail = 0;
873 int i, j = 0, nr_entries = 0;
874 void __iomem *base;
875 unsigned long flags;
876
877 spin_lock_irqsave(&msi_lock, flags);
878 while (head != tail) {
879 nr_entries++;
880 tail = msi_desc[vector]->link.tail;
881 if (entries[0].entry == msi_desc[vector]->msi_attrib.entry_nr)
882 j = vector;
883 vector = tail;
884 }
885 if (*nvec > nr_entries) {
886 spin_unlock_irqrestore(&msi_lock, flags);
887 *nvec = nr_entries;
888 return -EINVAL;
889 }
890 vector = ((j > 0) ? j : head);
891 for (i = 0; i < *nvec; i++) {
892 j = msi_desc[vector]->msi_attrib.entry_nr;
893 msi_desc[vector]->msi_attrib.state = 0; /* Mark it not active */
894 vector_irq[vector] = -1; /* Mark it busy */
895 nr_released_vectors--;
896 entries[i].vector = vector;
897 if (j != (entries + i)->entry) {
898 base = msi_desc[vector]->mask_base;
899 msi_desc[vector]->msi_attrib.entry_nr =
900 (entries + i)->entry;
901 writel( readl(base + j * PCI_MSIX_ENTRY_SIZE +
902 PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET), base +
903 (entries + i)->entry * PCI_MSIX_ENTRY_SIZE +
904 PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
905 writel( readl(base + j * PCI_MSIX_ENTRY_SIZE +
906 PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET), base +
907 (entries + i)->entry * PCI_MSIX_ENTRY_SIZE +
908 PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
909 writel( (readl(base + j * PCI_MSIX_ENTRY_SIZE +
910 PCI_MSIX_ENTRY_DATA_OFFSET) & 0xff00) | vector,
911 base + (entries+i)->entry*PCI_MSIX_ENTRY_SIZE +
912 PCI_MSIX_ENTRY_DATA_OFFSET);
913 }
914 vector = msi_desc[vector]->link.tail;
915 }
916 spin_unlock_irqrestore(&msi_lock, flags);
917
918 return 0;
919 }
920
921 /**
922 * pci_enable_msix - configure device's MSI-X capability structure
923 * @dev: pointer to the pci_dev data structure of MSI-X device function
924 * @data: pointer to an array of MSI-X entries
925 * @nvec: number of MSI-X vectors requested for allocation by device driver
926 *
927 * Setup the MSI-X capability structure of device function with the number
928 * of requested vectors upon its software driver call to request for
929 * MSI-X mode enabled on its hardware device function. A return of zero
930 * indicates the successful configuration of MSI-X capability structure
931 * with new allocated MSI-X vectors. A return of < 0 indicates a failure.
932 * Or a return of > 0 indicates that driver request is exceeding the number
933 * of vectors available. Driver should use the returned value to re-send
934 * its request.
935 **/
936 int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec)
937 {
938 int status, pos, nr_entries, free_vectors;
939 int i, j, temp;
940 u16 control;
941 unsigned long flags;
942
943 if (!pci_msi_enable || !dev || !entries)
944 return -EINVAL;
945
946 if ((status = msi_init()) < 0)
947 return status;
948
949 if (!(pos = pci_find_capability(dev, PCI_CAP_ID_MSIX)))
950 return -EINVAL;
951
952 pci_read_config_word(dev, msi_control_reg(pos), &control);
953 if (control & PCI_MSIX_FLAGS_ENABLE)
954 return -EINVAL; /* Already in MSI-X mode */
955
956 nr_entries = multi_msix_capable(control);
957 if (nvec > nr_entries)
958 return -EINVAL;
959
960 /* Check for any invalid entries */
961 for (i = 0; i < nvec; i++) {
962 if (entries[i].entry >= nr_entries)
963 return -EINVAL; /* invalid entry */
964 for (j = i + 1; j < nvec; j++) {
965 if (entries[i].entry == entries[j].entry)
966 return -EINVAL; /* duplicate entry */
967 }
968 }
969 temp = dev->irq;
970 if (!msi_lookup_vector(dev, PCI_CAP_ID_MSIX)) {
971 /* Lookup Sucess */
972 nr_entries = nvec;
973 /* Reroute MSI-X table */
974 if (reroute_msix_table(dev->irq, entries, &nr_entries)) {
975 /* #requested > #previous-assigned */
976 dev->irq = temp;
977 return nr_entries;
978 }
979 dev->irq = temp;
980 enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
981 return 0;
982 }
983 /* Check whether driver already requested for MSI vector */
984 if (pci_find_capability(dev, PCI_CAP_ID_MSI) > 0 &&
985 !msi_lookup_vector(dev, PCI_CAP_ID_MSI)) {
986 printk(KERN_INFO "PCI: %s: Can't enable MSI-X. "
987 "Device already has an MSI vector assigned\n",
988 pci_name(dev));
989 dev->irq = temp;
990 return -EINVAL;
991 }
992
993 spin_lock_irqsave(&msi_lock, flags);
994 /*
995 * msi_lock is provided to ensure that enough vectors resources are
996 * available before granting.
997 */
998 free_vectors = pci_vector_resources(last_alloc_vector,
999 nr_released_vectors);
1000 /* Ensure that each MSI/MSI-X device has one vector reserved by
1001 default to avoid any MSI-X driver to take all available
1002 resources */
1003 free_vectors -= nr_reserved_vectors;
1004 /* Find the average of free vectors among MSI-X devices */
1005 if (nr_msix_devices > 0)
1006 free_vectors /= nr_msix_devices;
1007 spin_unlock_irqrestore(&msi_lock, flags);
1008
1009 if (nvec > free_vectors) {
1010 if (free_vectors > 0)
1011 return free_vectors;
1012 else
1013 return -EBUSY;
1014 }
1015
1016 status = msix_capability_init(dev, entries, nvec);
1017 if (!status && nr_msix_devices > 0)
1018 nr_msix_devices--;
1019
1020 return status;
1021 }
1022
1023 void pci_disable_msix(struct pci_dev* dev)
1024 {
1025 int pos, temp;
1026 u16 control;
1027
1028 if (!dev || !(pos = pci_find_capability(dev, PCI_CAP_ID_MSIX)))
1029 return;
1030
1031 pci_read_config_word(dev, msi_control_reg(pos), &control);
1032 if (!(control & PCI_MSIX_FLAGS_ENABLE))
1033 return;
1034
1035 temp = dev->irq;
1036 if (!msi_lookup_vector(dev, PCI_CAP_ID_MSIX)) {
1037 int state, vector, head, tail = 0, warning = 0;
1038 unsigned long flags;
1039
1040 vector = head = dev->irq;
1041 spin_lock_irqsave(&msi_lock, flags);
1042 while (head != tail) {
1043 state = msi_desc[vector]->msi_attrib.state;
1044 if (state)
1045 warning = 1;
1046 else {
1047 vector_irq[vector] = 0; /* free it */
1048 nr_released_vectors++;
1049 }
1050 tail = msi_desc[vector]->link.tail;
1051 vector = tail;
1052 }
1053 spin_unlock_irqrestore(&msi_lock, flags);
1054 if (warning) {
1055 dev->irq = temp;
1056 printk(KERN_WARNING "PCI: %s: pci_disable_msix() called without "
1057 "free_irq() on all MSI-X vectors\n",
1058 pci_name(dev));
1059 BUG_ON(warning > 0);
1060 } else {
1061 dev->irq = temp;
1062 disable_msi_mode(dev,
1063 pci_find_capability(dev, PCI_CAP_ID_MSIX),
1064 PCI_CAP_ID_MSIX);
1065
1066 }
1067 }
1068 }
1069
1070 /**
1071 * msi_remove_pci_irq_vectors - reclaim MSI(X) vectors to unused state
1072 * @dev: pointer to the pci_dev data structure of MSI(X) device function
1073 *
1074 * Being called during hotplug remove, from which the device funciton
1075 * is hot-removed. All previous assigned MSI/MSI-X vectors, if
1076 * allocated for this device function, are reclaimed to unused state,
1077 * which may be used later on.
1078 **/
1079 void msi_remove_pci_irq_vectors(struct pci_dev* dev)
1080 {
1081 int state, pos, temp;
1082 unsigned long flags;
1083
1084 if (!pci_msi_enable || !dev)
1085 return;
1086
1087 temp = dev->irq; /* Save IOAPIC IRQ */
1088 if ((pos = pci_find_capability(dev, PCI_CAP_ID_MSI)) > 0 &&
1089 !msi_lookup_vector(dev, PCI_CAP_ID_MSI)) {
1090 spin_lock_irqsave(&msi_lock, flags);
1091 state = msi_desc[dev->irq]->msi_attrib.state;
1092 spin_unlock_irqrestore(&msi_lock, flags);
1093 if (state) {
1094 printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() "
1095 "called without free_irq() on MSI vector %d\n",
1096 pci_name(dev), dev->irq);
1097 BUG_ON(state > 0);
1098 } else /* Release MSI vector assigned to this device */
1099 msi_free_vector(dev, dev->irq, 0);
1100 dev->irq = temp; /* Restore IOAPIC IRQ */
1101 }
1102 if ((pos = pci_find_capability(dev, PCI_CAP_ID_MSIX)) > 0 &&
1103 !msi_lookup_vector(dev, PCI_CAP_ID_MSIX)) {
1104 int vector, head, tail = 0, warning = 0;
1105 void __iomem *base = NULL;
1106
1107 vector = head = dev->irq;
1108 while (head != tail) {
1109 spin_lock_irqsave(&msi_lock, flags);
1110 state = msi_desc[vector]->msi_attrib.state;
1111 tail = msi_desc[vector]->link.tail;
1112 base = msi_desc[vector]->mask_base;
1113 spin_unlock_irqrestore(&msi_lock, flags);
1114 if (state)
1115 warning = 1;
1116 else if (vector != head) /* Release MSI-X vector */
1117 msi_free_vector(dev, vector, 0);
1118 vector = tail;
1119 }
1120 msi_free_vector(dev, vector, 0);
1121 if (warning) {
1122 /* Force to release the MSI-X memory-mapped table */
1123 u32 phys_addr, table_offset;
1124 u16 control;
1125 u8 bir;
1126
1127 pci_read_config_word(dev, msi_control_reg(pos),
1128 &control);
1129 pci_read_config_dword(dev, msix_table_offset_reg(pos),
1130 &table_offset);
1131 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
1132 phys_addr = pci_resource_start (dev, bir);
1133 phys_addr += (u32)(table_offset &
1134 ~PCI_MSIX_FLAGS_BIRMASK);
1135 iounmap(base);
1136 release_mem_region(phys_addr, PCI_MSIX_ENTRY_SIZE *
1137 multi_msix_capable(control));
1138 printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() "
1139 "called without free_irq() on all MSI-X vectors\n",
1140 pci_name(dev));
1141 BUG_ON(warning > 0);
1142 }
1143 dev->irq = temp; /* Restore IOAPIC IRQ */
1144 }
1145 }
1146
1147 EXPORT_SYMBOL(pci_enable_msi);
1148 EXPORT_SYMBOL(pci_disable_msi);
1149 EXPORT_SYMBOL(pci_enable_msix);
1150 EXPORT_SYMBOL(pci_disable_msix);
1151
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