1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2009 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
23 *
24 *****************************************************************************/
25
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/pci.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/skbuff.h>
33 #include <linux/netdevice.h>
34 #include <linux/wireless.h>
35 #include <net/mac80211.h>
36 #include <linux/etherdevice.h>
37 #include <asm/unaligned.h>
38
39 #include "iwl-eeprom.h"
40 #include "iwl-dev.h"
41 #include "iwl-core.h"
42 #include "iwl-io.h"
43 #include "iwl-sta.h"
44 #include "iwl-helpers.h"
45 #include "iwl-5000-hw.h"
46 #include "iwl-6000-hw.h"
47
48 /* Highest firmware API version supported */
49 #define IWL5000_UCODE_API_MAX 2
50 #define IWL5150_UCODE_API_MAX 2
51
52 /* Lowest firmware API version supported */
53 #define IWL5000_UCODE_API_MIN 1
54 #define IWL5150_UCODE_API_MIN 1
55
56 #define IWL5000_FW_PRE "iwlwifi-5000-"
57 #define _IWL5000_MODULE_FIRMWARE(api) IWL5000_FW_PRE #api ".ucode"
58 #define IWL5000_MODULE_FIRMWARE(api) _IWL5000_MODULE_FIRMWARE(api)
59
60 #define IWL5150_FW_PRE "iwlwifi-5150-"
61 #define _IWL5150_MODULE_FIRMWARE(api) IWL5150_FW_PRE #api ".ucode"
62 #define IWL5150_MODULE_FIRMWARE(api) _IWL5150_MODULE_FIRMWARE(api)
63
64 static const u16 iwl5000_default_queue_to_tx_fifo[] = {
65 IWL_TX_FIFO_AC3,
66 IWL_TX_FIFO_AC2,
67 IWL_TX_FIFO_AC1,
68 IWL_TX_FIFO_AC0,
69 IWL50_CMD_FIFO_NUM,
70 IWL_TX_FIFO_HCCA_1,
71 IWL_TX_FIFO_HCCA_2
72 };
73
74 /* FIXME: same implementation as 4965 */
75 static int iwl5000_apm_stop_master(struct iwl_priv *priv)
76 {
77 unsigned long flags;
78
79 spin_lock_irqsave(&priv->lock, flags);
80
81 /* set stop master bit */
82 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
83
84 iwl_poll_direct_bit(priv, CSR_RESET,
85 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
86
87 spin_unlock_irqrestore(&priv->lock, flags);
88 IWL_DEBUG_INFO(priv, "stop master\n");
89
90 return 0;
91 }
92
93
94 static int iwl5000_apm_init(struct iwl_priv *priv)
95 {
96 int ret = 0;
97
98 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
99 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
100
101 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
102 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
103 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
104
105 /* Set FH wait threshold to maximum (HW error during stress W/A) */
106 iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
107
108 /* enable HAP INTA to move device L1a -> L0s */
109 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
110 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
111
112 if (priv->cfg->need_pll_cfg)
113 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
114
115 /* set "initialization complete" bit to move adapter
116 * D0U* --> D0A* state */
117 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
118
119 /* wait for clock stabilization */
120 ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
121 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
122 if (ret < 0) {
123 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
124 return ret;
125 }
126
127 /* enable DMA */
128 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
129
130 udelay(20);
131
132 /* disable L1-Active */
133 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
134 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
135
136 return ret;
137 }
138
139 /* FIXME: this is identical to 4965 */
140 static void iwl5000_apm_stop(struct iwl_priv *priv)
141 {
142 unsigned long flags;
143
144 iwl5000_apm_stop_master(priv);
145
146 spin_lock_irqsave(&priv->lock, flags);
147
148 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
149
150 udelay(10);
151
152 /* clear "init complete" move adapter D0A* --> D0U state */
153 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
154
155 spin_unlock_irqrestore(&priv->lock, flags);
156 }
157
158
159 static int iwl5000_apm_reset(struct iwl_priv *priv)
160 {
161 int ret = 0;
162
163 iwl5000_apm_stop_master(priv);
164
165 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
166
167 udelay(10);
168
169
170 /* FIXME: put here L1A -L0S w/a */
171
172 if (priv->cfg->need_pll_cfg)
173 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
174
175 /* set "initialization complete" bit to move adapter
176 * D0U* --> D0A* state */
177 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
178
179 /* wait for clock stabilization */
180 ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
181 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
182 if (ret < 0) {
183 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
184 goto out;
185 }
186
187 /* enable DMA */
188 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
189
190 udelay(20);
191
192 /* disable L1-Active */
193 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
194 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
195 out:
196
197 return ret;
198 }
199
200
201 static void iwl5000_nic_config(struct iwl_priv *priv)
202 {
203 unsigned long flags;
204 u16 radio_cfg;
205 u16 lctl;
206
207 spin_lock_irqsave(&priv->lock, flags);
208
209 lctl = iwl_pcie_link_ctl(priv);
210
211 /* HW bug W/A */
212 /* L1-ASPM is enabled by BIOS */
213 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN)
214 /* L1-APSM enabled: disable L0S */
215 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
216 else
217 /* L1-ASPM disabled: enable L0S */
218 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
219
220 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
221
222 /* write radio config values to register */
223 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_5000_RF_CFG_TYPE_MAX)
224 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
225 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
226 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
227 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
228
229 /* set CSR_HW_CONFIG_REG for uCode use */
230 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
231 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
232 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
233
234 /* W/A : NIC is stuck in a reset state after Early PCIe power off
235 * (PCIe power is lost before PERST# is asserted),
236 * causing ME FW to lose ownership and not being able to obtain it back.
237 */
238 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
239 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
240 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
241
242 if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) == CSR_HW_REV_TYPE_1000) {
243 /* Setting digital SVR for 1000 card to 1.32V */
244 iwl_set_bits_mask_prph(priv, APMG_DIGITAL_SVR_REG,
245 APMG_SVR_DIGITAL_VOLTAGE_1_32,
246 ~APMG_SVR_VOLTAGE_CONFIG_BIT_MSK);
247 }
248
249 spin_unlock_irqrestore(&priv->lock, flags);
250 }
251
252
253
254 /*
255 * EEPROM
256 */
257 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
258 {
259 u16 offset = 0;
260
261 if ((address & INDIRECT_ADDRESS) == 0)
262 return address;
263
264 switch (address & INDIRECT_TYPE_MSK) {
265 case INDIRECT_HOST:
266 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
267 break;
268 case INDIRECT_GENERAL:
269 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
270 break;
271 case INDIRECT_REGULATORY:
272 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
273 break;
274 case INDIRECT_CALIBRATION:
275 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
276 break;
277 case INDIRECT_PROCESS_ADJST:
278 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
279 break;
280 case INDIRECT_OTHERS:
281 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
282 break;
283 default:
284 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
285 address & INDIRECT_TYPE_MSK);
286 break;
287 }
288
289 /* translate the offset from words to byte */
290 return (address & ADDRESS_MSK) + (offset << 1);
291 }
292
293 static u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv)
294 {
295 struct iwl_eeprom_calib_hdr {
296 u8 version;
297 u8 pa_type;
298 u16 voltage;
299 } *hdr;
300
301 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
302 EEPROM_5000_CALIB_ALL);
303 return hdr->version;
304
305 }
306
307 static void iwl5000_gain_computation(struct iwl_priv *priv,
308 u32 average_noise[NUM_RX_CHAINS],
309 u16 min_average_noise_antenna_i,
310 u32 min_average_noise)
311 {
312 int i;
313 s32 delta_g;
314 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
315
316 /* Find Gain Code for the antennas B and C */
317 for (i = 1; i < NUM_RX_CHAINS; i++) {
318 if ((data->disconn_array[i])) {
319 data->delta_gain_code[i] = 0;
320 continue;
321 }
322 delta_g = (1000 * ((s32)average_noise[0] -
323 (s32)average_noise[i])) / 1500;
324 /* bound gain by 2 bits value max, 3rd bit is sign */
325 data->delta_gain_code[i] =
326 min(abs(delta_g), CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
327
328 if (delta_g < 0)
329 /* set negative sign */
330 data->delta_gain_code[i] |= (1 << 2);
331 }
332
333 IWL_DEBUG_CALIB(priv, "Delta gains: ANT_B = %d ANT_C = %d\n",
334 data->delta_gain_code[1], data->delta_gain_code[2]);
335
336 if (!data->radio_write) {
337 struct iwl_calib_chain_noise_gain_cmd cmd;
338
339 memset(&cmd, 0, sizeof(cmd));
340
341 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
342 cmd.hdr.first_group = 0;
343 cmd.hdr.groups_num = 1;
344 cmd.hdr.data_valid = 1;
345 cmd.delta_gain_1 = data->delta_gain_code[1];
346 cmd.delta_gain_2 = data->delta_gain_code[2];
347 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
348 sizeof(cmd), &cmd, NULL);
349
350 data->radio_write = 1;
351 data->state = IWL_CHAIN_NOISE_CALIBRATED;
352 }
353
354 data->chain_noise_a = 0;
355 data->chain_noise_b = 0;
356 data->chain_noise_c = 0;
357 data->chain_signal_a = 0;
358 data->chain_signal_b = 0;
359 data->chain_signal_c = 0;
360 data->beacon_count = 0;
361 }
362
363 static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
364 {
365 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
366 int ret;
367
368 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
369 struct iwl_calib_chain_noise_reset_cmd cmd;
370 memset(&cmd, 0, sizeof(cmd));
371
372 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
373 cmd.hdr.first_group = 0;
374 cmd.hdr.groups_num = 1;
375 cmd.hdr.data_valid = 1;
376 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
377 sizeof(cmd), &cmd);
378 if (ret)
379 IWL_ERR(priv,
380 "Could not send REPLY_PHY_CALIBRATION_CMD\n");
381 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
382 IWL_DEBUG_CALIB(priv, "Run chain_noise_calibrate\n");
383 }
384 }
385
386 void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
387 __le32 *tx_flags)
388 {
389 if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) ||
390 (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT))
391 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK;
392 else
393 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK;
394 }
395
396 static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
397 .min_nrg_cck = 95,
398 .max_nrg_cck = 0,
399 .auto_corr_min_ofdm = 90,
400 .auto_corr_min_ofdm_mrc = 170,
401 .auto_corr_min_ofdm_x1 = 120,
402 .auto_corr_min_ofdm_mrc_x1 = 240,
403
404 .auto_corr_max_ofdm = 120,
405 .auto_corr_max_ofdm_mrc = 210,
406 .auto_corr_max_ofdm_x1 = 155,
407 .auto_corr_max_ofdm_mrc_x1 = 290,
408
409 .auto_corr_min_cck = 125,
410 .auto_corr_max_cck = 200,
411 .auto_corr_min_cck_mrc = 170,
412 .auto_corr_max_cck_mrc = 400,
413 .nrg_th_cck = 95,
414 .nrg_th_ofdm = 95,
415 };
416
417 static const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
418 size_t offset)
419 {
420 u32 address = eeprom_indirect_address(priv, offset);
421 BUG_ON(address >= priv->cfg->eeprom_size);
422 return &priv->eeprom[address];
423 }
424
425 static void iwl5150_set_ct_threshold(struct iwl_priv *priv)
426 {
427 const s32 volt2temp_coef = IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF;
428 s32 threshold = (s32)CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD) -
429 iwl_temp_calib_to_offset(priv);
430
431 priv->hw_params.ct_kill_threshold = threshold * volt2temp_coef;
432 }
433
434 static void iwl5000_set_ct_threshold(struct iwl_priv *priv)
435 {
436 /* want Celsius */
437 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD;
438 }
439
440 /*
441 * Calibration
442 */
443 static int iwl5000_set_Xtal_calib(struct iwl_priv *priv)
444 {
445 struct iwl_calib_xtal_freq_cmd cmd;
446 u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
447
448 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
449 cmd.hdr.first_group = 0;
450 cmd.hdr.groups_num = 1;
451 cmd.hdr.data_valid = 1;
452 cmd.cap_pin1 = (u8)xtal_calib[0];
453 cmd.cap_pin2 = (u8)xtal_calib[1];
454 return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
455 (u8 *)&cmd, sizeof(cmd));
456 }
457
458 static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
459 {
460 struct iwl_calib_cfg_cmd calib_cfg_cmd;
461 struct iwl_host_cmd cmd = {
462 .id = CALIBRATION_CFG_CMD,
463 .len = sizeof(struct iwl_calib_cfg_cmd),
464 .data = &calib_cfg_cmd,
465 };
466
467 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
468 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
469 calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
470 calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
471 calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
472
473 return iwl_send_cmd(priv, &cmd);
474 }
475
476 static void iwl5000_rx_calib_result(struct iwl_priv *priv,
477 struct iwl_rx_mem_buffer *rxb)
478 {
479 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
480 struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
481 int len = le32_to_cpu(pkt->len) & FH_RSCSR_FRAME_SIZE_MSK;
482 int index;
483
484 /* reduce the size of the length field itself */
485 len -= 4;
486
487 /* Define the order in which the results will be sent to the runtime
488 * uCode. iwl_send_calib_results sends them in a row according to their
489 * index. We sort them here */
490 switch (hdr->op_code) {
491 case IWL_PHY_CALIBRATE_DC_CMD:
492 index = IWL_CALIB_DC;
493 break;
494 case IWL_PHY_CALIBRATE_LO_CMD:
495 index = IWL_CALIB_LO;
496 break;
497 case IWL_PHY_CALIBRATE_TX_IQ_CMD:
498 index = IWL_CALIB_TX_IQ;
499 break;
500 case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
501 index = IWL_CALIB_TX_IQ_PERD;
502 break;
503 case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
504 index = IWL_CALIB_BASE_BAND;
505 break;
506 default:
507 IWL_ERR(priv, "Unknown calibration notification %d\n",
508 hdr->op_code);
509 return;
510 }
511 iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
512 }
513
514 static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
515 struct iwl_rx_mem_buffer *rxb)
516 {
517 IWL_DEBUG_INFO(priv, "Init. calibration is completed, restarting fw.\n");
518 queue_work(priv->workqueue, &priv->restart);
519 }
520
521 /*
522 * ucode
523 */
524 static int iwl5000_load_section(struct iwl_priv *priv,
525 struct fw_desc *image,
526 u32 dst_addr)
527 {
528 dma_addr_t phy_addr = image->p_addr;
529 u32 byte_cnt = image->len;
530
531 iwl_write_direct32(priv,
532 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
533 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
534
535 iwl_write_direct32(priv,
536 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
537
538 iwl_write_direct32(priv,
539 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
540 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
541
542 iwl_write_direct32(priv,
543 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
544 (iwl_get_dma_hi_addr(phy_addr)
545 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
546
547 iwl_write_direct32(priv,
548 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
549 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
550 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
551 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
552
553 iwl_write_direct32(priv,
554 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
555 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
556 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
557 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
558
559 return 0;
560 }
561
562 static int iwl5000_load_given_ucode(struct iwl_priv *priv,
563 struct fw_desc *inst_image,
564 struct fw_desc *data_image)
565 {
566 int ret = 0;
567
568 ret = iwl5000_load_section(priv, inst_image,
569 IWL50_RTC_INST_LOWER_BOUND);
570 if (ret)
571 return ret;
572
573 IWL_DEBUG_INFO(priv, "INST uCode section being loaded...\n");
574 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
575 priv->ucode_write_complete, 5 * HZ);
576 if (ret == -ERESTARTSYS) {
577 IWL_ERR(priv, "Could not load the INST uCode section due "
578 "to interrupt\n");
579 return ret;
580 }
581 if (!ret) {
582 IWL_ERR(priv, "Could not load the INST uCode section\n");
583 return -ETIMEDOUT;
584 }
585
586 priv->ucode_write_complete = 0;
587
588 ret = iwl5000_load_section(
589 priv, data_image, IWL50_RTC_DATA_LOWER_BOUND);
590 if (ret)
591 return ret;
592
593 IWL_DEBUG_INFO(priv, "DATA uCode section being loaded...\n");
594
595 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
596 priv->ucode_write_complete, 5 * HZ);
597 if (ret == -ERESTARTSYS) {
598 IWL_ERR(priv, "Could not load the INST uCode section due "
599 "to interrupt\n");
600 return ret;
601 } else if (!ret) {
602 IWL_ERR(priv, "Could not load the DATA uCode section\n");
603 return -ETIMEDOUT;
604 } else
605 ret = 0;
606
607 priv->ucode_write_complete = 0;
608
609 return ret;
610 }
611
612 static int iwl5000_load_ucode(struct iwl_priv *priv)
613 {
614 int ret = 0;
615
616 /* check whether init ucode should be loaded, or rather runtime ucode */
617 if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
618 IWL_DEBUG_INFO(priv, "Init ucode found. Loading init ucode...\n");
619 ret = iwl5000_load_given_ucode(priv,
620 &priv->ucode_init, &priv->ucode_init_data);
621 if (!ret) {
622 IWL_DEBUG_INFO(priv, "Init ucode load complete.\n");
623 priv->ucode_type = UCODE_INIT;
624 }
625 } else {
626 IWL_DEBUG_INFO(priv, "Init ucode not found, or already loaded. "
627 "Loading runtime ucode...\n");
628 ret = iwl5000_load_given_ucode(priv,
629 &priv->ucode_code, &priv->ucode_data);
630 if (!ret) {
631 IWL_DEBUG_INFO(priv, "Runtime ucode load complete.\n");
632 priv->ucode_type = UCODE_RT;
633 }
634 }
635
636 return ret;
637 }
638
639 static void iwl5000_init_alive_start(struct iwl_priv *priv)
640 {
641 int ret = 0;
642
643 /* Check alive response for "valid" sign from uCode */
644 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
645 /* We had an error bringing up the hardware, so take it
646 * all the way back down so we can try again */
647 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
648 goto restart;
649 }
650
651 /* initialize uCode was loaded... verify inst image.
652 * This is a paranoid check, because we would not have gotten the
653 * "initialize" alive if code weren't properly loaded. */
654 if (iwl_verify_ucode(priv)) {
655 /* Runtime instruction load was bad;
656 * take it all the way back down so we can try again */
657 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
658 goto restart;
659 }
660
661 iwl_clear_stations_table(priv);
662 ret = priv->cfg->ops->lib->alive_notify(priv);
663 if (ret) {
664 IWL_WARN(priv,
665 "Could not complete ALIVE transition: %d\n", ret);
666 goto restart;
667 }
668
669 iwl5000_send_calib_cfg(priv);
670 return;
671
672 restart:
673 /* real restart (first load init_ucode) */
674 queue_work(priv->workqueue, &priv->restart);
675 }
676
677 static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
678 int txq_id, u32 index)
679 {
680 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
681 (index & 0xff) | (txq_id << 8));
682 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
683 }
684
685 static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
686 struct iwl_tx_queue *txq,
687 int tx_fifo_id, int scd_retry)
688 {
689 int txq_id = txq->q.id;
690 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
691
692 iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
693 (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
694 (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
695 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
696 IWL50_SCD_QUEUE_STTS_REG_MSK);
697
698 txq->sched_retry = scd_retry;
699
700 IWL_DEBUG_INFO(priv, "%s %s Queue %d on AC %d\n",
701 active ? "Activate" : "Deactivate",
702 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
703 }
704
705 static int iwl5000_send_wimax_coex(struct iwl_priv *priv)
706 {
707 struct iwl_wimax_coex_cmd coex_cmd;
708
709 memset(&coex_cmd, 0, sizeof(coex_cmd));
710
711 return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
712 sizeof(coex_cmd), &coex_cmd);
713 }
714
715 static int iwl5000_alive_notify(struct iwl_priv *priv)
716 {
717 u32 a;
718 unsigned long flags;
719 int i, chan;
720 u32 reg_val;
721
722 spin_lock_irqsave(&priv->lock, flags);
723
724 priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
725 a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
726 for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
727 a += 4)
728 iwl_write_targ_mem(priv, a, 0);
729 for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
730 a += 4)
731 iwl_write_targ_mem(priv, a, 0);
732 for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
733 iwl_write_targ_mem(priv, a, 0);
734
735 iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
736 priv->scd_bc_tbls.dma >> 10);
737
738 /* Enable DMA channel */
739 for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
740 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
741 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
742 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
743
744 /* Update FH chicken bits */
745 reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
746 iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
747 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
748
749 iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
750 IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num));
751 iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
752
753 /* initiate the queues */
754 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
755 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
756 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
757 iwl_write_targ_mem(priv, priv->scd_base_addr +
758 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
759 iwl_write_targ_mem(priv, priv->scd_base_addr +
760 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
761 sizeof(u32),
762 ((SCD_WIN_SIZE <<
763 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
764 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
765 ((SCD_FRAME_LIMIT <<
766 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
767 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
768 }
769
770 iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
771 IWL_MASK(0, priv->hw_params.max_txq_num));
772
773 /* Activate all Tx DMA/FIFO channels */
774 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
775
776 iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
777
778 /* map qos queues to fifos one-to-one */
779 for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
780 int ac = iwl5000_default_queue_to_tx_fifo[i];
781 iwl_txq_ctx_activate(priv, i);
782 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
783 }
784 /* TODO - need to initialize those FIFOs inside the loop above,
785 * not only mark them as active */
786 iwl_txq_ctx_activate(priv, 4);
787 iwl_txq_ctx_activate(priv, 7);
788 iwl_txq_ctx_activate(priv, 8);
789 iwl_txq_ctx_activate(priv, 9);
790
791 spin_unlock_irqrestore(&priv->lock, flags);
792
793
794 iwl5000_send_wimax_coex(priv);
795
796 iwl5000_set_Xtal_calib(priv);
797 iwl_send_calib_results(priv);
798
799 return 0;
800 }
801
802 static int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
803 {
804 if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) ||
805 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
806 IWL_ERR(priv,
807 "invalid queues_num, should be between %d and %d\n",
808 IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES);
809 return -EINVAL;
810 }
811
812 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
813 priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
814 priv->hw_params.scd_bc_tbls_size =
815 IWL50_NUM_QUEUES * sizeof(struct iwl5000_scd_bc_tbl);
816 priv->hw_params.tfd_size = sizeof(struct iwl_tfd);
817 priv->hw_params.max_stations = IWL5000_STATION_COUNT;
818 priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
819
820 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
821 case CSR_HW_REV_TYPE_6x00:
822 case CSR_HW_REV_TYPE_6x50:
823 priv->hw_params.max_data_size = IWL60_RTC_DATA_SIZE;
824 priv->hw_params.max_inst_size = IWL60_RTC_INST_SIZE;
825 break;
826 default:
827 priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
828 priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
829 }
830
831 priv->hw_params.max_bsm_size = 0;
832 priv->hw_params.fat_channel = BIT(IEEE80211_BAND_2GHZ) |
833 BIT(IEEE80211_BAND_5GHZ);
834 priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
835
836 priv->hw_params.sens = &iwl5000_sensitivity;
837
838 priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant);
839 priv->hw_params.rx_chains_num = num_of_ant(priv->cfg->valid_rx_ant);
840 priv->hw_params.valid_tx_ant = priv->cfg->valid_tx_ant;
841 priv->hw_params.valid_rx_ant = priv->cfg->valid_rx_ant;
842
843 if (priv->cfg->ops->lib->temp_ops.set_ct_kill)
844 priv->cfg->ops->lib->temp_ops.set_ct_kill(priv);
845
846 /* Set initial calibration set */
847 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
848 case CSR_HW_REV_TYPE_5150:
849 priv->hw_params.calib_init_cfg =
850 BIT(IWL_CALIB_DC) |
851 BIT(IWL_CALIB_LO) |
852 BIT(IWL_CALIB_TX_IQ) |
853 BIT(IWL_CALIB_BASE_BAND);
854
855 break;
856 default:
857 priv->hw_params.calib_init_cfg =
858 BIT(IWL_CALIB_XTAL) |
859 BIT(IWL_CALIB_LO) |
860 BIT(IWL_CALIB_TX_IQ) |
861 BIT(IWL_CALIB_TX_IQ_PERD) |
862 BIT(IWL_CALIB_BASE_BAND);
863 break;
864 }
865
866 return 0;
867 }
868
869 /**
870 * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
871 */
872 static void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
873 struct iwl_tx_queue *txq,
874 u16 byte_cnt)
875 {
876 struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
877 int write_ptr = txq->q.write_ptr;
878 int txq_id = txq->q.id;
879 u8 sec_ctl = 0;
880 u8 sta_id = 0;
881 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
882 __le16 bc_ent;
883
884 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
885
886 if (txq_id != IWL_CMD_QUEUE_NUM) {
887 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
888 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
889
890 switch (sec_ctl & TX_CMD_SEC_MSK) {
891 case TX_CMD_SEC_CCM:
892 len += CCMP_MIC_LEN;
893 break;
894 case TX_CMD_SEC_TKIP:
895 len += TKIP_ICV_LEN;
896 break;
897 case TX_CMD_SEC_WEP:
898 len += WEP_IV_LEN + WEP_ICV_LEN;
899 break;
900 }
901 }
902
903 bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
904
905 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
906
907 if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
908 scd_bc_tbl[txq_id].
909 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
910 }
911
912 static void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
913 struct iwl_tx_queue *txq)
914 {
915 struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
916 int txq_id = txq->q.id;
917 int read_ptr = txq->q.read_ptr;
918 u8 sta_id = 0;
919 __le16 bc_ent;
920
921 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
922
923 if (txq_id != IWL_CMD_QUEUE_NUM)
924 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
925
926 bc_ent = cpu_to_le16(1 | (sta_id << 12));
927 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
928
929 if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
930 scd_bc_tbl[txq_id].
931 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
932 }
933
934 static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
935 u16 txq_id)
936 {
937 u32 tbl_dw_addr;
938 u32 tbl_dw;
939 u16 scd_q2ratid;
940
941 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
942
943 tbl_dw_addr = priv->scd_base_addr +
944 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
945
946 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
947
948 if (txq_id & 0x1)
949 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
950 else
951 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
952
953 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
954
955 return 0;
956 }
957 static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
958 {
959 /* Simply stop the queue, but don't change any configuration;
960 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
961 iwl_write_prph(priv,
962 IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
963 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
964 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
965 }
966
967 static int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
968 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
969 {
970 unsigned long flags;
971 u16 ra_tid;
972
973 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
974 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
975 IWL_WARN(priv,
976 "queue number out of range: %d, must be %d to %d\n",
977 txq_id, IWL50_FIRST_AMPDU_QUEUE,
978 IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
979 return -EINVAL;
980 }
981
982 ra_tid = BUILD_RAxTID(sta_id, tid);
983
984 /* Modify device's station table to Tx this TID */
985 iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
986
987 spin_lock_irqsave(&priv->lock, flags);
988
989 /* Stop this Tx queue before configuring it */
990 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
991
992 /* Map receiver-address / traffic-ID to this queue */
993 iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
994
995 /* Set this queue as a chain-building queue */
996 iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
997
998 /* enable aggregations for the queue */
999 iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
1000
1001 /* Place first TFD at index corresponding to start sequence number.
1002 * Assumes that ssn_idx is valid (!= 0xFFF) */
1003 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1004 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1005 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1006
1007 /* Set up Tx window size and frame limit for this queue */
1008 iwl_write_targ_mem(priv, priv->scd_base_addr +
1009 IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
1010 sizeof(u32),
1011 ((SCD_WIN_SIZE <<
1012 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1013 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1014 ((SCD_FRAME_LIMIT <<
1015 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1016 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1017
1018 iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1019
1020 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1021 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
1022
1023 spin_unlock_irqrestore(&priv->lock, flags);
1024
1025 return 0;
1026 }
1027
1028 static int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1029 u16 ssn_idx, u8 tx_fifo)
1030 {
1031 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
1032 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
1033 IWL_ERR(priv,
1034 "queue number out of range: %d, must be %d to %d\n",
1035 txq_id, IWL50_FIRST_AMPDU_QUEUE,
1036 IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
1037 return -EINVAL;
1038 }
1039
1040 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1041
1042 iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
1043
1044 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1045 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1046 /* supposes that ssn_idx is valid (!= 0xFFF) */
1047 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1048
1049 iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1050 iwl_txq_ctx_deactivate(priv, txq_id);
1051 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1052
1053 return 0;
1054 }
1055
1056 u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
1057 {
1058 u16 size = (u16)sizeof(struct iwl_addsta_cmd);
1059 struct iwl_addsta_cmd *addsta = (struct iwl_addsta_cmd *)data;
1060 memcpy(addsta, cmd, size);
1061 /* resrved in 5000 */
1062 addsta->rate_n_flags = cpu_to_le16(0);
1063 return size;
1064 }
1065
1066
1067 /*
1068 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1069 * must be called under priv->lock and mac access
1070 */
1071 static void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
1072 {
1073 iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
1074 }
1075
1076
1077 static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
1078 {
1079 return le32_to_cpup((__le32 *)&tx_resp->status +
1080 tx_resp->frame_count) & MAX_SN;
1081 }
1082
1083 static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv,
1084 struct iwl_ht_agg *agg,
1085 struct iwl5000_tx_resp *tx_resp,
1086 int txq_id, u16 start_idx)
1087 {
1088 u16 status;
1089 struct agg_tx_status *frame_status = &tx_resp->status;
1090 struct ieee80211_tx_info *info = NULL;
1091 struct ieee80211_hdr *hdr = NULL;
1092 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
1093 int i, sh, idx;
1094 u16 seq;
1095
1096 if (agg->wait_for_ba)
1097 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
1098
1099 agg->frame_count = tx_resp->frame_count;
1100 agg->start_idx = start_idx;
1101 agg->rate_n_flags = rate_n_flags;
1102 agg->bitmap = 0;
1103
1104 /* # frames attempted by Tx command */
1105 if (agg->frame_count == 1) {
1106 /* Only one frame was attempted; no block-ack will arrive */
1107 status = le16_to_cpu(frame_status[0].status);
1108 idx = start_idx;
1109
1110 /* FIXME: code repetition */
1111 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
1112 agg->frame_count, agg->start_idx, idx);
1113
1114 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
1115 info->status.rates[0].count = tx_resp->failure_frame + 1;
1116 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
1117 info->flags |= iwl_is_tx_success(status) ?
1118 IEEE80211_TX_STAT_ACK : 0;
1119 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
1120
1121 /* FIXME: code repetition end */
1122
1123 IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n",
1124 status & 0xff, tx_resp->failure_frame);
1125 IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags);
1126
1127 agg->wait_for_ba = 0;
1128 } else {
1129 /* Two or more frames were attempted; expect block-ack */
1130 u64 bitmap = 0;
1131 int start = agg->start_idx;
1132
1133 /* Construct bit-map of pending frames within Tx window */
1134 for (i = 0; i < agg->frame_count; i++) {
1135 u16 sc;
1136 status = le16_to_cpu(frame_status[i].status);
1137 seq = le16_to_cpu(frame_status[i].sequence);
1138 idx = SEQ_TO_INDEX(seq);
1139 txq_id = SEQ_TO_QUEUE(seq);
1140
1141 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1142 AGG_TX_STATE_ABORT_MSK))
1143 continue;
1144
1145 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
1146 agg->frame_count, txq_id, idx);
1147
1148 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1149
1150 sc = le16_to_cpu(hdr->seq_ctrl);
1151 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
1152 IWL_ERR(priv,
1153 "BUG_ON idx doesn't match seq control"
1154 " idx=%d, seq_idx=%d, seq=%d\n",
1155 idx, SEQ_TO_SN(sc),
1156 hdr->seq_ctrl);
1157 return -1;
1158 }
1159
1160 IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
1161 i, idx, SEQ_TO_SN(sc));
1162
1163 sh = idx - start;
1164 if (sh > 64) {
1165 sh = (start - idx) + 0xff;
1166 bitmap = bitmap << sh;
1167 sh = 0;
1168 start = idx;
1169 } else if (sh < -64)
1170 sh = 0xff - (start - idx);
1171 else if (sh < 0) {
1172 sh = start - idx;
1173 start = idx;
1174 bitmap = bitmap << sh;
1175 sh = 0;
1176 }
1177 bitmap |= 1ULL << sh;
1178 IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
1179 start, (unsigned long long)bitmap);
1180 }
1181
1182 agg->bitmap = bitmap;
1183 agg->start_idx = start;
1184 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
1185 agg->frame_count, agg->start_idx,
1186 (unsigned long long)agg->bitmap);
1187
1188 if (bitmap)
1189 agg->wait_for_ba = 1;
1190 }
1191 return 0;
1192 }
1193
1194 static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
1195 struct iwl_rx_mem_buffer *rxb)
1196 {
1197 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1198 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1199 int txq_id = SEQ_TO_QUEUE(sequence);
1200 int index = SEQ_TO_INDEX(sequence);
1201 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1202 struct ieee80211_tx_info *info;
1203 struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
1204 u32 status = le16_to_cpu(tx_resp->status.status);
1205 int tid;
1206 int sta_id;
1207 int freed;
1208
1209 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
1210 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
1211 "is out of range [0-%d] %d %d\n", txq_id,
1212 index, txq->q.n_bd, txq->q.write_ptr,
1213 txq->q.read_ptr);
1214 return;
1215 }
1216
1217 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
1218 memset(&info->status, 0, sizeof(info->status));
1219
1220 tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS;
1221 sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS;
1222
1223 if (txq->sched_retry) {
1224 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp);
1225 struct iwl_ht_agg *agg = NULL;
1226
1227 agg = &priv->stations[sta_id].tid[tid].agg;
1228
1229 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
1230
1231 /* check if BAR is needed */
1232 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
1233 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1234
1235 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
1236 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
1237 IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
1238 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1239 scd_ssn , index, txq_id, txq->swq_id);
1240
1241 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1242 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1243
1244 if (priv->mac80211_registered &&
1245 (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1246 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
1247 if (agg->state == IWL_AGG_OFF)
1248 iwl_wake_queue(priv, txq_id);
1249 else
1250 iwl_wake_queue(priv, txq->swq_id);
1251 }
1252 }
1253 } else {
1254 BUG_ON(txq_id != txq->swq_id);
1255
1256 info->status.rates[0].count = tx_resp->failure_frame + 1;
1257 info->flags |= iwl_is_tx_success(status) ?
1258 IEEE80211_TX_STAT_ACK : 0;
1259 iwl_hwrate_to_tx_control(priv,
1260 le32_to_cpu(tx_resp->rate_n_flags),
1261 info);
1262
1263 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
1264 "0x%x retries %d\n",
1265 txq_id,
1266 iwl_get_tx_fail_reason(status), status,
1267 le32_to_cpu(tx_resp->rate_n_flags),
1268 tx_resp->failure_frame);
1269
1270 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1271 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1272 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1273
1274 if (priv->mac80211_registered &&
1275 (iwl_queue_space(&txq->q) > txq->q.low_mark))
1276 iwl_wake_queue(priv, txq_id);
1277 }
1278
1279 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1280 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
1281
1282 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
1283 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
1284 }
1285
1286 /* Currently 5000 is the superset of everything */
1287 u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
1288 {
1289 return len;
1290 }
1291
1292 static void iwl5000_setup_deferred_work(struct iwl_priv *priv)
1293 {
1294 /* in 5000 the tx power calibration is done in uCode */
1295 priv->disable_tx_power_cal = 1;
1296 }
1297
1298 static void iwl5000_rx_handler_setup(struct iwl_priv *priv)
1299 {
1300 /* init calibration handlers */
1301 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
1302 iwl5000_rx_calib_result;
1303 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
1304 iwl5000_rx_calib_complete;
1305 priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
1306 }
1307
1308
1309 static int iwl5000_hw_valid_rtc_data_addr(u32 addr)
1310 {
1311 return (addr >= IWL50_RTC_DATA_LOWER_BOUND) &&
1312 (addr < IWL50_RTC_DATA_UPPER_BOUND);
1313 }
1314
1315 static int iwl5000_send_rxon_assoc(struct iwl_priv *priv)
1316 {
1317 int ret = 0;
1318 struct iwl5000_rxon_assoc_cmd rxon_assoc;
1319 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1320 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1321
1322 if ((rxon1->flags == rxon2->flags) &&
1323 (rxon1->filter_flags == rxon2->filter_flags) &&
1324 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1325 (rxon1->ofdm_ht_single_stream_basic_rates ==
1326 rxon2->ofdm_ht_single_stream_basic_rates) &&
1327 (rxon1->ofdm_ht_dual_stream_basic_rates ==
1328 rxon2->ofdm_ht_dual_stream_basic_rates) &&
1329 (rxon1->ofdm_ht_triple_stream_basic_rates ==
1330 rxon2->ofdm_ht_triple_stream_basic_rates) &&
1331 (rxon1->acquisition_data == rxon2->acquisition_data) &&
1332 (rxon1->rx_chain == rxon2->rx_chain) &&
1333 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1334 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
1335 return 0;
1336 }
1337
1338 rxon_assoc.flags = priv->staging_rxon.flags;
1339 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1340 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1341 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1342 rxon_assoc.reserved1 = 0;
1343 rxon_assoc.reserved2 = 0;
1344 rxon_assoc.reserved3 = 0;
1345 rxon_assoc.ofdm_ht_single_stream_basic_rates =
1346 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1347 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1348 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1349 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1350 rxon_assoc.ofdm_ht_triple_stream_basic_rates =
1351 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates;
1352 rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data;
1353
1354 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1355 sizeof(rxon_assoc), &rxon_assoc, NULL);
1356 if (ret)
1357 return ret;
1358
1359 return ret;
1360 }
1361 static int iwl5000_send_tx_power(struct iwl_priv *priv)
1362 {
1363 struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
1364 u8 tx_ant_cfg_cmd;
1365
1366 /* half dBm need to multiply */
1367 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
1368 tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
1369 tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
1370
1371 if (IWL_UCODE_API(priv->ucode_ver) == 1)
1372 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
1373 else
1374 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
1375
1376 return iwl_send_cmd_pdu_async(priv, tx_ant_cfg_cmd,
1377 sizeof(tx_power_cmd), &tx_power_cmd,
1378 NULL);
1379 }
1380
1381 static void iwl5000_temperature(struct iwl_priv *priv)
1382 {
1383 /* store temperature from statistics (in Celsius) */
1384 priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
1385 }
1386
1387 static void iwl5150_temperature(struct iwl_priv *priv)
1388 {
1389 u32 vt = 0;
1390 s32 offset = iwl_temp_calib_to_offset(priv);
1391
1392 vt = le32_to_cpu(priv->statistics.general.temperature);
1393 vt = vt / IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF + offset;
1394 /* now vt hold the temperature in Kelvin */
1395 priv->temperature = KELVIN_TO_CELSIUS(vt);
1396 }
1397
1398 /* Calc max signal level (dBm) among 3 possible receivers */
1399 int iwl5000_calc_rssi(struct iwl_priv *priv,
1400 struct iwl_rx_phy_res *rx_resp)
1401 {
1402 /* data from PHY/DSP regarding signal strength, etc.,
1403 * contents are always there, not configurable by host
1404 */
1405 struct iwl5000_non_cfg_phy *ncphy =
1406 (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
1407 u32 val, rssi_a, rssi_b, rssi_c, max_rssi;
1408 u8 agc;
1409
1410 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]);
1411 agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS;
1412
1413 /* Find max rssi among 3 possible receivers.
1414 * These values are measured by the digital signal processor (DSP).
1415 * They should stay fairly constant even as the signal strength varies,
1416 * if the radio's automatic gain control (AGC) is working right.
1417 * AGC value (see below) will provide the "interesting" info.
1418 */
1419 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]);
1420 rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS;
1421 rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS;
1422 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]);
1423 rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS;
1424
1425 max_rssi = max_t(u32, rssi_a, rssi_b);
1426 max_rssi = max_t(u32, max_rssi, rssi_c);
1427
1428 IWL_DEBUG_STATS(priv, "Rssi In A %d B %d C %d Max %d AGC dB %d\n",
1429 rssi_a, rssi_b, rssi_c, max_rssi, agc);
1430
1431 /* dBm = max_rssi dB - agc dB - constant.
1432 * Higher AGC (higher radio gain) means lower signal. */
1433 return max_rssi - agc - IWL49_RSSI_OFFSET;
1434 }
1435
1436 #define IWL5000_UCODE_GET(item) \
1437 static u32 iwl5000_ucode_get_##item(const struct iwl_ucode_header *ucode,\
1438 u32 api_ver) \
1439 { \
1440 if (api_ver <= 2) \
1441 return le32_to_cpu(ucode->u.v1.item); \
1442 return le32_to_cpu(ucode->u.v2.item); \
1443 }
1444
1445 static u32 iwl5000_ucode_get_header_size(u32 api_ver)
1446 {
1447 if (api_ver <= 2)
1448 return UCODE_HEADER_SIZE(1);
1449 return UCODE_HEADER_SIZE(2);
1450 }
1451
1452 static u32 iwl5000_ucode_get_build(const struct iwl_ucode_header *ucode,
1453 u32 api_ver)
1454 {
1455 if (api_ver <= 2)
1456 return 0;
1457 return le32_to_cpu(ucode->u.v2.build);
1458 }
1459
1460 static u8 *iwl5000_ucode_get_data(const struct iwl_ucode_header *ucode,
1461 u32 api_ver)
1462 {
1463 if (api_ver <= 2)
1464 return (u8 *) ucode->u.v1.data;
1465 return (u8 *) ucode->u.v2.data;
1466 }
1467
1468 IWL5000_UCODE_GET(inst_size);
1469 IWL5000_UCODE_GET(data_size);
1470 IWL5000_UCODE_GET(init_size);
1471 IWL5000_UCODE_GET(init_data_size);
1472 IWL5000_UCODE_GET(boot_size);
1473
1474 struct iwl_hcmd_ops iwl5000_hcmd = {
1475 .rxon_assoc = iwl5000_send_rxon_assoc,
1476 .commit_rxon = iwl_commit_rxon,
1477 .set_rxon_chain = iwl_set_rxon_chain,
1478 };
1479
1480 struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
1481 .get_hcmd_size = iwl5000_get_hcmd_size,
1482 .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
1483 .gain_computation = iwl5000_gain_computation,
1484 .chain_noise_reset = iwl5000_chain_noise_reset,
1485 .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag,
1486 .calc_rssi = iwl5000_calc_rssi,
1487 };
1488
1489 struct iwl_ucode_ops iwl5000_ucode = {
1490 .get_header_size = iwl5000_ucode_get_header_size,
1491 .get_build = iwl5000_ucode_get_build,
1492 .get_inst_size = iwl5000_ucode_get_inst_size,
1493 .get_data_size = iwl5000_ucode_get_data_size,
1494 .get_init_size = iwl5000_ucode_get_init_size,
1495 .get_init_data_size = iwl5000_ucode_get_init_data_size,
1496 .get_boot_size = iwl5000_ucode_get_boot_size,
1497 .get_data = iwl5000_ucode_get_data,
1498 };
1499
1500 struct iwl_lib_ops iwl5000_lib = {
1501 .set_hw_params = iwl5000_hw_set_hw_params,
1502 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1503 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1504 .txq_set_sched = iwl5000_txq_set_sched,
1505 .txq_agg_enable = iwl5000_txq_agg_enable,
1506 .txq_agg_disable = iwl5000_txq_agg_disable,
1507 .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1508 .txq_free_tfd = iwl_hw_txq_free_tfd,
1509 .txq_init = iwl_hw_tx_queue_init,
1510 .rx_handler_setup = iwl5000_rx_handler_setup,
1511 .setup_deferred_work = iwl5000_setup_deferred_work,
1512 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1513 .load_ucode = iwl5000_load_ucode,
1514 .init_alive_start = iwl5000_init_alive_start,
1515 .alive_notify = iwl5000_alive_notify,
1516 .send_tx_power = iwl5000_send_tx_power,
1517 .update_chain_flags = iwl_update_chain_flags,
1518 .apm_ops = {
1519 .init = iwl5000_apm_init,
1520 .reset = iwl5000_apm_reset,
1521 .stop = iwl5000_apm_stop,
1522 .config = iwl5000_nic_config,
1523 .set_pwr_src = iwl_set_pwr_src,
1524 },
1525 .eeprom_ops = {
1526 .regulatory_bands = {
1527 EEPROM_5000_REG_BAND_1_CHANNELS,
1528 EEPROM_5000_REG_BAND_2_CHANNELS,
1529 EEPROM_5000_REG_BAND_3_CHANNELS,
1530 EEPROM_5000_REG_BAND_4_CHANNELS,
1531 EEPROM_5000_REG_BAND_5_CHANNELS,
1532 EEPROM_5000_REG_BAND_24_FAT_CHANNELS,
1533 EEPROM_5000_REG_BAND_52_FAT_CHANNELS
1534 },
1535 .verify_signature = iwlcore_eeprom_verify_signature,
1536 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1537 .release_semaphore = iwlcore_eeprom_release_semaphore,
1538 .calib_version = iwl5000_eeprom_calib_version,
1539 .query_addr = iwl5000_eeprom_query_addr,
1540 },
1541 .post_associate = iwl_post_associate,
1542 .isr = iwl_isr_ict,
1543 .config_ap = iwl_config_ap,
1544 .temp_ops = {
1545 .temperature = iwl5000_temperature,
1546 .set_ct_kill = iwl5000_set_ct_threshold,
1547 },
1548 };
1549
1550 static struct iwl_lib_ops iwl5150_lib = {
1551 .set_hw_params = iwl5000_hw_set_hw_params,
1552 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1553 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1554 .txq_set_sched = iwl5000_txq_set_sched,
1555 .txq_agg_enable = iwl5000_txq_agg_enable,
1556 .txq_agg_disable = iwl5000_txq_agg_disable,
1557 .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1558 .txq_free_tfd = iwl_hw_txq_free_tfd,
1559 .txq_init = iwl_hw_tx_queue_init,
1560 .rx_handler_setup = iwl5000_rx_handler_setup,
1561 .setup_deferred_work = iwl5000_setup_deferred_work,
1562 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1563 .load_ucode = iwl5000_load_ucode,
1564 .init_alive_start = iwl5000_init_alive_start,
1565 .alive_notify = iwl5000_alive_notify,
1566 .send_tx_power = iwl5000_send_tx_power,
1567 .update_chain_flags = iwl_update_chain_flags,
1568 .apm_ops = {
1569 .init = iwl5000_apm_init,
1570 .reset = iwl5000_apm_reset,
1571 .stop = iwl5000_apm_stop,
1572 .config = iwl5000_nic_config,
1573 .set_pwr_src = iwl_set_pwr_src,
1574 },
1575 .eeprom_ops = {
1576 .regulatory_bands = {
1577 EEPROM_5000_REG_BAND_1_CHANNELS,
1578 EEPROM_5000_REG_BAND_2_CHANNELS,
1579 EEPROM_5000_REG_BAND_3_CHANNELS,
1580 EEPROM_5000_REG_BAND_4_CHANNELS,
1581 EEPROM_5000_REG_BAND_5_CHANNELS,
1582 EEPROM_5000_REG_BAND_24_FAT_CHANNELS,
1583 EEPROM_5000_REG_BAND_52_FAT_CHANNELS
1584 },
1585 .verify_signature = iwlcore_eeprom_verify_signature,
1586 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1587 .release_semaphore = iwlcore_eeprom_release_semaphore,
1588 .calib_version = iwl5000_eeprom_calib_version,
1589 .query_addr = iwl5000_eeprom_query_addr,
1590 },
1591 .post_associate = iwl_post_associate,
1592 .isr = iwl_isr_ict,
1593 .config_ap = iwl_config_ap,
1594 .temp_ops = {
1595 .temperature = iwl5150_temperature,
1596 .set_ct_kill = iwl5150_set_ct_threshold,
1597 },
1598 };
1599
1600 struct iwl_ops iwl5000_ops = {
1601 .ucode = &iwl5000_ucode,
1602 .lib = &iwl5000_lib,
1603 .hcmd = &iwl5000_hcmd,
1604 .utils = &iwl5000_hcmd_utils,
1605 };
1606
1607 static struct iwl_ops iwl5150_ops = {
1608 .ucode = &iwl5000_ucode,
1609 .lib = &iwl5150_lib,
1610 .hcmd = &iwl5000_hcmd,
1611 .utils = &iwl5000_hcmd_utils,
1612 };
1613
1614 struct iwl_mod_params iwl50_mod_params = {
1615 .num_of_queues = IWL50_NUM_QUEUES,
1616 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1617 .amsdu_size_8K = 1,
1618 .restart_fw = 1,
1619 /* the rest are 0 by default */
1620 };
1621
1622
1623 struct iwl_cfg iwl5300_agn_cfg = {
1624 .name = "5300AGN",
1625 .fw_name_pre = IWL5000_FW_PRE,
1626 .ucode_api_max = IWL5000_UCODE_API_MAX,
1627 .ucode_api_min = IWL5000_UCODE_API_MIN,
1628 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1629 .ops = &iwl5000_ops,
1630 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1631 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1632 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1633 .mod_params = &iwl50_mod_params,
1634 .valid_tx_ant = ANT_ABC,
1635 .valid_rx_ant = ANT_ABC,
1636 .need_pll_cfg = true,
1637 };
1638
1639 struct iwl_cfg iwl5100_bg_cfg = {
1640 .name = "5100BG",
1641 .fw_name_pre = IWL5000_FW_PRE,
1642 .ucode_api_max = IWL5000_UCODE_API_MAX,
1643 .ucode_api_min = IWL5000_UCODE_API_MIN,
1644 .sku = IWL_SKU_G,
1645 .ops = &iwl5000_ops,
1646 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1647 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1648 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1649 .mod_params = &iwl50_mod_params,
1650 .valid_tx_ant = ANT_B,
1651 .valid_rx_ant = ANT_AB,
1652 .need_pll_cfg = true,
1653 };
1654
1655 struct iwl_cfg iwl5100_abg_cfg = {
1656 .name = "5100ABG",
1657 .fw_name_pre = IWL5000_FW_PRE,
1658 .ucode_api_max = IWL5000_UCODE_API_MAX,
1659 .ucode_api_min = IWL5000_UCODE_API_MIN,
1660 .sku = IWL_SKU_A|IWL_SKU_G,
1661 .ops = &iwl5000_ops,
1662 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1663 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1664 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1665 .mod_params = &iwl50_mod_params,
1666 .valid_tx_ant = ANT_B,
1667 .valid_rx_ant = ANT_AB,
1668 .need_pll_cfg = true,
1669 };
1670
1671 struct iwl_cfg iwl5100_agn_cfg = {
1672 .name = "5100AGN",
1673 .fw_name_pre = IWL5000_FW_PRE,
1674 .ucode_api_max = IWL5000_UCODE_API_MAX,
1675 .ucode_api_min = IWL5000_UCODE_API_MIN,
1676 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1677 .ops = &iwl5000_ops,
1678 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1679 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1680 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1681 .mod_params = &iwl50_mod_params,
1682 .valid_tx_ant = ANT_B,
1683 .valid_rx_ant = ANT_AB,
1684 .need_pll_cfg = true,
1685 };
1686
1687 struct iwl_cfg iwl5350_agn_cfg = {
1688 .name = "5350AGN",
1689 .fw_name_pre = IWL5000_FW_PRE,
1690 .ucode_api_max = IWL5000_UCODE_API_MAX,
1691 .ucode_api_min = IWL5000_UCODE_API_MIN,
1692 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1693 .ops = &iwl5000_ops,
1694 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1695 .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1696 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1697 .mod_params = &iwl50_mod_params,
1698 .valid_tx_ant = ANT_ABC,
1699 .valid_rx_ant = ANT_ABC,
1700 .need_pll_cfg = true,
1701 };
1702
1703 struct iwl_cfg iwl5150_agn_cfg = {
1704 .name = "5150AGN",
1705 .fw_name_pre = IWL5150_FW_PRE,
1706 .ucode_api_max = IWL5150_UCODE_API_MAX,
1707 .ucode_api_min = IWL5150_UCODE_API_MIN,
1708 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1709 .ops = &iwl5150_ops,
1710 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1711 .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1712 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1713 .mod_params = &iwl50_mod_params,
1714 .valid_tx_ant = ANT_A,
1715 .valid_rx_ant = ANT_AB,
1716 .need_pll_cfg = true,
1717 };
1718
1719 MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE(IWL5000_UCODE_API_MAX));
1720 MODULE_FIRMWARE(IWL5150_MODULE_FIRMWARE(IWL5150_UCODE_API_MAX));
1721
1722 module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444);
1723 MODULE_PARM_DESC(swcrypto50,
1724 "using software crypto engine (default 0 [hardware])\n");
1725 module_param_named(debug50, iwl50_mod_params.debug, uint, 0444);
1726 MODULE_PARM_DESC(debug50, "50XX debug output mask");
1727 module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444);
1728 MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
1729 module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, 0444);
1730 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality");
1731 module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444);
1732 MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
1733 module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, 0444);
1734 MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");
1735
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