1 #ifndef BCM43xx_DMA_H_
2 #define BCM43xx_DMA_H_
3
4 #include <linux/list.h>
5 #include <linux/spinlock.h>
6 #include <linux/workqueue.h>
7 #include <linux/dma-mapping.h>
8 #include <linux/linkage.h>
9 #include <asm/atomic.h>
10
11
12 /* DMA-Interrupt reasons. */
13 #define BCM43xx_DMAIRQ_FATALMASK ((1 << 10) | (1 << 11) | (1 << 12) \
14 | (1 << 14) | (1 << 15))
15 #define BCM43xx_DMAIRQ_NONFATALMASK (1 << 13)
16 #define BCM43xx_DMAIRQ_RX_DONE (1 << 16)
17
18
19 /*** 32-bit DMA Engine. ***/
20
21 /* 32-bit DMA controller registers. */
22 #define BCM43xx_DMA32_TXCTL 0x00
23 #define BCM43xx_DMA32_TXENABLE 0x00000001
24 #define BCM43xx_DMA32_TXSUSPEND 0x00000002
25 #define BCM43xx_DMA32_TXLOOPBACK 0x00000004
26 #define BCM43xx_DMA32_TXFLUSH 0x00000010
27 #define BCM43xx_DMA32_TXADDREXT_MASK 0x00030000
28 #define BCM43xx_DMA32_TXADDREXT_SHIFT 16
29 #define BCM43xx_DMA32_TXRING 0x04
30 #define BCM43xx_DMA32_TXINDEX 0x08
31 #define BCM43xx_DMA32_TXSTATUS 0x0C
32 #define BCM43xx_DMA32_TXDPTR 0x00000FFF
33 #define BCM43xx_DMA32_TXSTATE 0x0000F000
34 #define BCM43xx_DMA32_TXSTAT_DISABLED 0x00000000
35 #define BCM43xx_DMA32_TXSTAT_ACTIVE 0x00001000
36 #define BCM43xx_DMA32_TXSTAT_IDLEWAIT 0x00002000
37 #define BCM43xx_DMA32_TXSTAT_STOPPED 0x00003000
38 #define BCM43xx_DMA32_TXSTAT_SUSP 0x00004000
39 #define BCM43xx_DMA32_TXERROR 0x000F0000
40 #define BCM43xx_DMA32_TXERR_NOERR 0x00000000
41 #define BCM43xx_DMA32_TXERR_PROT 0x00010000
42 #define BCM43xx_DMA32_TXERR_UNDERRUN 0x00020000
43 #define BCM43xx_DMA32_TXERR_BUFREAD 0x00030000
44 #define BCM43xx_DMA32_TXERR_DESCREAD 0x00040000
45 #define BCM43xx_DMA32_TXACTIVE 0xFFF00000
46 #define BCM43xx_DMA32_RXCTL 0x10
47 #define BCM43xx_DMA32_RXENABLE 0x00000001
48 #define BCM43xx_DMA32_RXFROFF_MASK 0x000000FE
49 #define BCM43xx_DMA32_RXFROFF_SHIFT 1
50 #define BCM43xx_DMA32_RXDIRECTFIFO 0x00000100
51 #define BCM43xx_DMA32_RXADDREXT_MASK 0x00030000
52 #define BCM43xx_DMA32_RXADDREXT_SHIFT 16
53 #define BCM43xx_DMA32_RXRING 0x14
54 #define BCM43xx_DMA32_RXINDEX 0x18
55 #define BCM43xx_DMA32_RXSTATUS 0x1C
56 #define BCM43xx_DMA32_RXDPTR 0x00000FFF
57 #define BCM43xx_DMA32_RXSTATE 0x0000F000
58 #define BCM43xx_DMA32_RXSTAT_DISABLED 0x00000000
59 #define BCM43xx_DMA32_RXSTAT_ACTIVE 0x00001000
60 #define BCM43xx_DMA32_RXSTAT_IDLEWAIT 0x00002000
61 #define BCM43xx_DMA32_RXSTAT_STOPPED 0x00003000
62 #define BCM43xx_DMA32_RXERROR 0x000F0000
63 #define BCM43xx_DMA32_RXERR_NOERR 0x00000000
64 #define BCM43xx_DMA32_RXERR_PROT 0x00010000
65 #define BCM43xx_DMA32_RXERR_OVERFLOW 0x00020000
66 #define BCM43xx_DMA32_RXERR_BUFWRITE 0x00030000
67 #define BCM43xx_DMA32_RXERR_DESCREAD 0x00040000
68 #define BCM43xx_DMA32_RXACTIVE 0xFFF00000
69
70 /* 32-bit DMA descriptor. */
71 struct bcm43xx_dmadesc32 {
72 __le32 control;
73 __le32 address;
74 } __attribute__((__packed__));
75 #define BCM43xx_DMA32_DCTL_BYTECNT 0x00001FFF
76 #define BCM43xx_DMA32_DCTL_ADDREXT_MASK 0x00030000
77 #define BCM43xx_DMA32_DCTL_ADDREXT_SHIFT 16
78 #define BCM43xx_DMA32_DCTL_DTABLEEND 0x10000000
79 #define BCM43xx_DMA32_DCTL_IRQ 0x20000000
80 #define BCM43xx_DMA32_DCTL_FRAMEEND 0x40000000
81 #define BCM43xx_DMA32_DCTL_FRAMESTART 0x80000000
82
83 /* Address field Routing value. */
84 #define BCM43xx_DMA32_ROUTING 0xC0000000
85 #define BCM43xx_DMA32_ROUTING_SHIFT 30
86 #define BCM43xx_DMA32_NOTRANS 0x00000000
87 #define BCM43xx_DMA32_CLIENTTRANS 0x40000000
88
89
90
91 /*** 64-bit DMA Engine. ***/
92
93 /* 64-bit DMA controller registers. */
94 #define BCM43xx_DMA64_TXCTL 0x00
95 #define BCM43xx_DMA64_TXENABLE 0x00000001
96 #define BCM43xx_DMA64_TXSUSPEND 0x00000002
97 #define BCM43xx_DMA64_TXLOOPBACK 0x00000004
98 #define BCM43xx_DMA64_TXFLUSH 0x00000010
99 #define BCM43xx_DMA64_TXADDREXT_MASK 0x00030000
100 #define BCM43xx_DMA64_TXADDREXT_SHIFT 16
101 #define BCM43xx_DMA64_TXINDEX 0x04
102 #define BCM43xx_DMA64_TXRINGLO 0x08
103 #define BCM43xx_DMA64_TXRINGHI 0x0C
104 #define BCM43xx_DMA64_TXSTATUS 0x10
105 #define BCM43xx_DMA64_TXSTATDPTR 0x00001FFF
106 #define BCM43xx_DMA64_TXSTAT 0xF0000000
107 #define BCM43xx_DMA64_TXSTAT_DISABLED 0x00000000
108 #define BCM43xx_DMA64_TXSTAT_ACTIVE 0x10000000
109 #define BCM43xx_DMA64_TXSTAT_IDLEWAIT 0x20000000
110 #define BCM43xx_DMA64_TXSTAT_STOPPED 0x30000000
111 #define BCM43xx_DMA64_TXSTAT_SUSP 0x40000000
112 #define BCM43xx_DMA64_TXERROR 0x14
113 #define BCM43xx_DMA64_TXERRDPTR 0x0001FFFF
114 #define BCM43xx_DMA64_TXERR 0xF0000000
115 #define BCM43xx_DMA64_TXERR_NOERR 0x00000000
116 #define BCM43xx_DMA64_TXERR_PROT 0x10000000
117 #define BCM43xx_DMA64_TXERR_UNDERRUN 0x20000000
118 #define BCM43xx_DMA64_TXERR_TRANSFER 0x30000000
119 #define BCM43xx_DMA64_TXERR_DESCREAD 0x40000000
120 #define BCM43xx_DMA64_TXERR_CORE 0x50000000
121 #define BCM43xx_DMA64_RXCTL 0x20
122 #define BCM43xx_DMA64_RXENABLE 0x00000001
123 #define BCM43xx_DMA64_RXFROFF_MASK 0x000000FE
124 #define BCM43xx_DMA64_RXFROFF_SHIFT 1
125 #define BCM43xx_DMA64_RXDIRECTFIFO 0x00000100
126 #define BCM43xx_DMA64_RXADDREXT_MASK 0x00030000
127 #define BCM43xx_DMA64_RXADDREXT_SHIFT 16
128 #define BCM43xx_DMA64_RXINDEX 0x24
129 #define BCM43xx_DMA64_RXRINGLO 0x28
130 #define BCM43xx_DMA64_RXRINGHI 0x2C
131 #define BCM43xx_DMA64_RXSTATUS 0x30
132 #define BCM43xx_DMA64_RXSTATDPTR 0x00001FFF
133 #define BCM43xx_DMA64_RXSTAT 0xF0000000
134 #define BCM43xx_DMA64_RXSTAT_DISABLED 0x00000000
135 #define BCM43xx_DMA64_RXSTAT_ACTIVE 0x10000000
136 #define BCM43xx_DMA64_RXSTAT_IDLEWAIT 0x20000000
137 #define BCM43xx_DMA64_RXSTAT_STOPPED 0x30000000
138 #define BCM43xx_DMA64_RXSTAT_SUSP 0x40000000
139 #define BCM43xx_DMA64_RXERROR 0x34
140 #define BCM43xx_DMA64_RXERRDPTR 0x0001FFFF
141 #define BCM43xx_DMA64_RXERR 0xF0000000
142 #define BCM43xx_DMA64_RXERR_NOERR 0x00000000
143 #define BCM43xx_DMA64_RXERR_PROT 0x10000000
144 #define BCM43xx_DMA64_RXERR_UNDERRUN 0x20000000
145 #define BCM43xx_DMA64_RXERR_TRANSFER 0x30000000
146 #define BCM43xx_DMA64_RXERR_DESCREAD 0x40000000
147 #define BCM43xx_DMA64_RXERR_CORE 0x50000000
148
149 /* 64-bit DMA descriptor. */
150 struct bcm43xx_dmadesc64 {
151 __le32 control0;
152 __le32 control1;
153 __le32 address_low;
154 __le32 address_high;
155 } __attribute__((__packed__));
156 #define BCM43xx_DMA64_DCTL0_DTABLEEND 0x10000000
157 #define BCM43xx_DMA64_DCTL0_IRQ 0x20000000
158 #define BCM43xx_DMA64_DCTL0_FRAMEEND 0x40000000
159 #define BCM43xx_DMA64_DCTL0_FRAMESTART 0x80000000
160 #define BCM43xx_DMA64_DCTL1_BYTECNT 0x00001FFF
161 #define BCM43xx_DMA64_DCTL1_ADDREXT_MASK 0x00030000
162 #define BCM43xx_DMA64_DCTL1_ADDREXT_SHIFT 16
163
164 /* Address field Routing value. */
165 #define BCM43xx_DMA64_ROUTING 0xC0000000
166 #define BCM43xx_DMA64_ROUTING_SHIFT 30
167 #define BCM43xx_DMA64_NOTRANS 0x00000000
168 #define BCM43xx_DMA64_CLIENTTRANS 0x80000000
169
170
171
172 struct bcm43xx_dmadesc_generic {
173 union {
174 struct bcm43xx_dmadesc32 dma32;
175 struct bcm43xx_dmadesc64 dma64;
176 } __attribute__((__packed__));
177 } __attribute__((__packed__));
178
179
180 /* Misc DMA constants */
181 #define BCM43xx_DMA_RINGMEMSIZE PAGE_SIZE
182 #define BCM43xx_DMA0_RX_FRAMEOFFSET 30
183 #define BCM43xx_DMA3_RX_FRAMEOFFSET 0
184
185
186 /* DMA engine tuning knobs */
187 #define BCM43xx_TXRING_SLOTS 512
188 #define BCM43xx_RXRING_SLOTS 64
189 #define BCM43xx_DMA0_RX_BUFFERSIZE (2304 + 100)
190 #define BCM43xx_DMA3_RX_BUFFERSIZE 16
191 /* Suspend the tx queue, if less than this percent slots are free. */
192 #define BCM43xx_TXSUSPEND_PERCENT 20
193 /* Resume the tx queue, if more than this percent slots are free. */
194 #define BCM43xx_TXRESUME_PERCENT 50
195
196
197
198 #ifdef CONFIG_BCM43XX_DMA
199
200
201 struct sk_buff;
202 struct bcm43xx_private;
203 struct bcm43xx_xmitstatus;
204
205
206 struct bcm43xx_dmadesc_meta {
207 /* The kernel DMA-able buffer. */
208 struct sk_buff *skb;
209 /* DMA base bus-address of the descriptor buffer. */
210 dma_addr_t dmaaddr;
211 };
212
213 struct bcm43xx_dmaring {
214 /* Kernel virtual base address of the ring memory. */
215 void *descbase;
216 /* Meta data about all descriptors. */
217 struct bcm43xx_dmadesc_meta *meta;
218 /* DMA Routing value. */
219 u32 routing;
220 /* (Unadjusted) DMA base bus-address of the ring memory. */
221 dma_addr_t dmabase;
222 /* Number of descriptor slots in the ring. */
223 int nr_slots;
224 /* Number of used descriptor slots. */
225 int used_slots;
226 /* Currently used slot in the ring. */
227 int current_slot;
228 /* Marks to suspend/resume the queue. */
229 int suspend_mark;
230 int resume_mark;
231 /* Frameoffset in octets. */
232 u32 frameoffset;
233 /* Descriptor buffer size. */
234 u16 rx_buffersize;
235 /* The MMIO base register of the DMA controller. */
236 u16 mmio_base;
237 /* DMA controller index number (0-5). */
238 int index;
239 /* Boolean. Is this a TX ring? */
240 u8 tx;
241 /* Boolean. 64bit DMA if true, 32bit DMA otherwise. */
242 u8 dma64;
243 /* Boolean. Are transfers suspended on this ring? */
244 u8 suspended;
245 struct bcm43xx_private *bcm;
246 #ifdef CONFIG_BCM43XX_DEBUG
247 /* Maximum number of used slots. */
248 int max_used_slots;
249 #endif /* CONFIG_BCM43XX_DEBUG*/
250 };
251
252
253 static inline
254 int bcm43xx_dma_desc2idx(struct bcm43xx_dmaring *ring,
255 struct bcm43xx_dmadesc_generic *desc)
256 {
257 if (ring->dma64) {
258 struct bcm43xx_dmadesc64 *dd64 = ring->descbase;
259 return (int)(&(desc->dma64) - dd64);
260 } else {
261 struct bcm43xx_dmadesc32 *dd32 = ring->descbase;
262 return (int)(&(desc->dma32) - dd32);
263 }
264 }
265
266 static inline
267 struct bcm43xx_dmadesc_generic * bcm43xx_dma_idx2desc(struct bcm43xx_dmaring *ring,
268 int slot,
269 struct bcm43xx_dmadesc_meta **meta)
270 {
271 *meta = &(ring->meta[slot]);
272 if (ring->dma64) {
273 struct bcm43xx_dmadesc64 *dd64 = ring->descbase;
274 return (struct bcm43xx_dmadesc_generic *)(&(dd64[slot]));
275 } else {
276 struct bcm43xx_dmadesc32 *dd32 = ring->descbase;
277 return (struct bcm43xx_dmadesc_generic *)(&(dd32[slot]));
278 }
279 }
280
281 static inline
282 u32 bcm43xx_dma_read(struct bcm43xx_dmaring *ring,
283 u16 offset)
284 {
285 return bcm43xx_read32(ring->bcm, ring->mmio_base + offset);
286 }
287
288 static inline
289 void bcm43xx_dma_write(struct bcm43xx_dmaring *ring,
290 u16 offset, u32 value)
291 {
292 bcm43xx_write32(ring->bcm, ring->mmio_base + offset, value);
293 }
294
295
296 int bcm43xx_dma_init(struct bcm43xx_private *bcm);
297 void bcm43xx_dma_free(struct bcm43xx_private *bcm);
298
299 int bcm43xx_dmacontroller_rx_reset(struct bcm43xx_private *bcm,
300 u16 dmacontroller_mmio_base,
301 int dma64);
302 int bcm43xx_dmacontroller_tx_reset(struct bcm43xx_private *bcm,
303 u16 dmacontroller_mmio_base,
304 int dma64);
305
306 u16 bcm43xx_dmacontroller_base(int dma64bit, int dmacontroller_idx);
307
308 void bcm43xx_dma_tx_suspend(struct bcm43xx_dmaring *ring);
309 void bcm43xx_dma_tx_resume(struct bcm43xx_dmaring *ring);
310
311 void bcm43xx_dma_handle_xmitstatus(struct bcm43xx_private *bcm,
312 struct bcm43xx_xmitstatus *status);
313
314 int bcm43xx_dma_tx(struct bcm43xx_private *bcm,
315 struct ieee80211_txb *txb);
316 void bcm43xx_dma_rx(struct bcm43xx_dmaring *ring);
317
318 /* Helper function that returns the dma mask for this device. */
319 static inline
320 u64 bcm43xx_get_supported_dma_mask(struct bcm43xx_private *bcm)
321 {
322 int dma64 = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH) &
323 BCM43xx_SBTMSTATEHIGH_DMA64BIT;
324 u16 mmio_base = bcm43xx_dmacontroller_base(dma64, 0);
325 u32 mask = BCM43xx_DMA32_TXADDREXT_MASK;
326
327 if (dma64)
328 return DMA_64BIT_MASK;
329 bcm43xx_write32(bcm, mmio_base + BCM43xx_DMA32_TXCTL, mask);
330 if (bcm43xx_read32(bcm, mmio_base + BCM43xx_DMA32_TXCTL) & mask)
331 return DMA_32BIT_MASK;
332 return DMA_30BIT_MASK;
333 }
334
335 #else /* CONFIG_BCM43XX_DMA */
336
337
338 static inline
339 int bcm43xx_dma_init(struct bcm43xx_private *bcm)
340 {
341 return 0;
342 }
343 static inline
344 void bcm43xx_dma_free(struct bcm43xx_private *bcm)
345 {
346 }
347 static inline
348 int bcm43xx_dmacontroller_rx_reset(struct bcm43xx_private *bcm,
349 u16 dmacontroller_mmio_base,
350 int dma64)
351 {
352 return 0;
353 }
354 static inline
355 int bcm43xx_dmacontroller_tx_reset(struct bcm43xx_private *bcm,
356 u16 dmacontroller_mmio_base,
357 int dma64)
358 {
359 return 0;
360 }
361 static inline
362 int bcm43xx_dma_tx(struct bcm43xx_private *bcm,
363 struct ieee80211_txb *txb)
364 {
365 return 0;
366 }
367 static inline
368 void bcm43xx_dma_handle_xmitstatus(struct bcm43xx_private *bcm,
369 struct bcm43xx_xmitstatus *status)
370 {
371 }
372 static inline
373 void bcm43xx_dma_rx(struct bcm43xx_dmaring *ring)
374 {
375 }
376 static inline
377 void bcm43xx_dma_tx_suspend(struct bcm43xx_dmaring *ring)
378 {
379 }
380 static inline
381 void bcm43xx_dma_tx_resume(struct bcm43xx_dmaring *ring)
382 {
383 }
384
385 #endif /* CONFIG_BCM43XX_DMA */
386 #endif /* BCM43xx_DMA_H_ */
387
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