1 #ifndef B43legacy_H_
2 #define B43legacy_H_
3
4 #include <linux/hw_random.h>
5 #include <linux/kernel.h>
6 #include <linux/spinlock.h>
7 #include <linux/interrupt.h>
8 #include <linux/stringify.h>
9 #include <linux/netdevice.h>
10 #include <linux/pci.h>
11 #include <asm/atomic.h>
12 #include <linux/io.h>
13
14 #include <linux/ssb/ssb.h>
15 #include <linux/ssb/ssb_driver_chipcommon.h>
16
17 #include <linux/wireless.h>
18 #include <net/mac80211.h>
19
20 #include "debugfs.h"
21 #include "leds.h"
22 #include "rfkill.h"
23 #include "phy.h"
24
25
26 /* The unique identifier of the firmware that's officially supported by this
27 * driver version. */
28 #define B43legacy_SUPPORTED_FIRMWARE_ID "FW10"
29
30 #define B43legacy_IRQWAIT_MAX_RETRIES 20
31
32 #define B43legacy_RX_MAX_SSI 60 /* best guess at max ssi */
33
34 /* MMIO offsets */
35 #define B43legacy_MMIO_DMA0_REASON 0x20
36 #define B43legacy_MMIO_DMA0_IRQ_MASK 0x24
37 #define B43legacy_MMIO_DMA1_REASON 0x28
38 #define B43legacy_MMIO_DMA1_IRQ_MASK 0x2C
39 #define B43legacy_MMIO_DMA2_REASON 0x30
40 #define B43legacy_MMIO_DMA2_IRQ_MASK 0x34
41 #define B43legacy_MMIO_DMA3_REASON 0x38
42 #define B43legacy_MMIO_DMA3_IRQ_MASK 0x3C
43 #define B43legacy_MMIO_DMA4_REASON 0x40
44 #define B43legacy_MMIO_DMA4_IRQ_MASK 0x44
45 #define B43legacy_MMIO_DMA5_REASON 0x48
46 #define B43legacy_MMIO_DMA5_IRQ_MASK 0x4C
47 #define B43legacy_MMIO_MACCTL 0x120 /* MAC control */
48 #define B43legacy_MMIO_MACCMD 0x124 /* MAC command */
49 #define B43legacy_MMIO_GEN_IRQ_REASON 0x128
50 #define B43legacy_MMIO_GEN_IRQ_MASK 0x12C
51 #define B43legacy_MMIO_RAM_CONTROL 0x130
52 #define B43legacy_MMIO_RAM_DATA 0x134
53 #define B43legacy_MMIO_PS_STATUS 0x140
54 #define B43legacy_MMIO_RADIO_HWENABLED_HI 0x158
55 #define B43legacy_MMIO_SHM_CONTROL 0x160
56 #define B43legacy_MMIO_SHM_DATA 0x164
57 #define B43legacy_MMIO_SHM_DATA_UNALIGNED 0x166
58 #define B43legacy_MMIO_XMITSTAT_0 0x170
59 #define B43legacy_MMIO_XMITSTAT_1 0x174
60 #define B43legacy_MMIO_REV3PLUS_TSF_LOW 0x180 /* core rev >= 3 only */
61 #define B43legacy_MMIO_REV3PLUS_TSF_HIGH 0x184 /* core rev >= 3 only */
62 #define B43legacy_MMIO_TSF_CFP_REP 0x188
63 #define B43legacy_MMIO_TSF_CFP_START 0x18C
64 /* 32-bit DMA */
65 #define B43legacy_MMIO_DMA32_BASE0 0x200
66 #define B43legacy_MMIO_DMA32_BASE1 0x220
67 #define B43legacy_MMIO_DMA32_BASE2 0x240
68 #define B43legacy_MMIO_DMA32_BASE3 0x260
69 #define B43legacy_MMIO_DMA32_BASE4 0x280
70 #define B43legacy_MMIO_DMA32_BASE5 0x2A0
71 /* 64-bit DMA */
72 #define B43legacy_MMIO_DMA64_BASE0 0x200
73 #define B43legacy_MMIO_DMA64_BASE1 0x240
74 #define B43legacy_MMIO_DMA64_BASE2 0x280
75 #define B43legacy_MMIO_DMA64_BASE3 0x2C0
76 #define B43legacy_MMIO_DMA64_BASE4 0x300
77 #define B43legacy_MMIO_DMA64_BASE5 0x340
78 /* PIO */
79 #define B43legacy_MMIO_PIO1_BASE 0x300
80 #define B43legacy_MMIO_PIO2_BASE 0x310
81 #define B43legacy_MMIO_PIO3_BASE 0x320
82 #define B43legacy_MMIO_PIO4_BASE 0x330
83
84 #define B43legacy_MMIO_PHY_VER 0x3E0
85 #define B43legacy_MMIO_PHY_RADIO 0x3E2
86 #define B43legacy_MMIO_PHY0 0x3E6
87 #define B43legacy_MMIO_ANTENNA 0x3E8
88 #define B43legacy_MMIO_CHANNEL 0x3F0
89 #define B43legacy_MMIO_CHANNEL_EXT 0x3F4
90 #define B43legacy_MMIO_RADIO_CONTROL 0x3F6
91 #define B43legacy_MMIO_RADIO_DATA_HIGH 0x3F8
92 #define B43legacy_MMIO_RADIO_DATA_LOW 0x3FA
93 #define B43legacy_MMIO_PHY_CONTROL 0x3FC
94 #define B43legacy_MMIO_PHY_DATA 0x3FE
95 #define B43legacy_MMIO_MACFILTER_CONTROL 0x420
96 #define B43legacy_MMIO_MACFILTER_DATA 0x422
97 #define B43legacy_MMIO_RCMTA_COUNT 0x43C /* Receive Match Transmitter Addr */
98 #define B43legacy_MMIO_RADIO_HWENABLED_LO 0x49A
99 #define B43legacy_MMIO_GPIO_CONTROL 0x49C
100 #define B43legacy_MMIO_GPIO_MASK 0x49E
101 #define B43legacy_MMIO_TSF_CFP_PRETBTT 0x612
102 #define B43legacy_MMIO_TSF_0 0x632 /* core rev < 3 only */
103 #define B43legacy_MMIO_TSF_1 0x634 /* core rev < 3 only */
104 #define B43legacy_MMIO_TSF_2 0x636 /* core rev < 3 only */
105 #define B43legacy_MMIO_TSF_3 0x638 /* core rev < 3 only */
106 #define B43legacy_MMIO_RNG 0x65A
107 #define B43legacy_MMIO_POWERUP_DELAY 0x6A8
108
109 /* SPROM boardflags_lo values */
110 #define B43legacy_BFL_PACTRL 0x0002
111 #define B43legacy_BFL_RSSI 0x0008
112 #define B43legacy_BFL_EXTLNA 0x1000
113
114 /* GPIO register offset, in both ChipCommon and PCI core. */
115 #define B43legacy_GPIO_CONTROL 0x6c
116
117 /* SHM Routing */
118 #define B43legacy_SHM_SHARED 0x0001
119 #define B43legacy_SHM_WIRELESS 0x0002
120 #define B43legacy_SHM_HW 0x0004
121 #define B43legacy_SHM_UCODE 0x0300
122
123 /* SHM Routing modifiers */
124 #define B43legacy_SHM_AUTOINC_R 0x0200 /* Read Auto-increment */
125 #define B43legacy_SHM_AUTOINC_W 0x0100 /* Write Auto-increment */
126 #define B43legacy_SHM_AUTOINC_RW (B43legacy_SHM_AUTOINC_R | \
127 B43legacy_SHM_AUTOINC_W)
128
129 /* Misc SHM_SHARED offsets */
130 #define B43legacy_SHM_SH_WLCOREREV 0x0016 /* 802.11 core revision */
131 #define B43legacy_SHM_SH_HOSTFLO 0x005E /* Hostflags ucode opts (low) */
132 #define B43legacy_SHM_SH_HOSTFHI 0x0060 /* Hostflags ucode opts (high) */
133 /* SHM_SHARED crypto engine */
134 #define B43legacy_SHM_SH_KEYIDXBLOCK 0x05D4 /* Key index/algorithm block */
135 /* SHM_SHARED beacon/AP variables */
136 #define B43legacy_SHM_SH_DTIMP 0x0012 /* DTIM period */
137 #define B43legacy_SHM_SH_BTL0 0x0018 /* Beacon template length 0 */
138 #define B43legacy_SHM_SH_BTL1 0x001A /* Beacon template length 1 */
139 #define B43legacy_SHM_SH_BTSFOFF 0x001C /* Beacon TSF offset */
140 #define B43legacy_SHM_SH_TIMPOS 0x001E /* TIM position in beacon */
141 #define B43legacy_SHM_SH_BEACPHYCTL 0x0054 /* Beacon PHY TX control word */
142 /* SHM_SHARED ACK/CTS control */
143 #define B43legacy_SHM_SH_ACKCTSPHYCTL 0x0022 /* ACK/CTS PHY control word */
144 /* SHM_SHARED probe response variables */
145 #define B43legacy_SHM_SH_PRTLEN 0x004A /* Probe Response template length */
146 #define B43legacy_SHM_SH_PRMAXTIME 0x0074 /* Probe Response max time */
147 #define B43legacy_SHM_SH_PRPHYCTL 0x0188 /* Probe Resp PHY TX control */
148 /* SHM_SHARED rate tables */
149 #define B43legacy_SHM_SH_OFDMDIRECT 0x0480 /* Pointer to OFDM direct map */
150 #define B43legacy_SHM_SH_OFDMBASIC 0x04A0 /* Pointer to OFDM basic rate map */
151 #define B43legacy_SHM_SH_CCKDIRECT 0x04C0 /* Pointer to CCK direct map */
152 #define B43legacy_SHM_SH_CCKBASIC 0x04E0 /* Pointer to CCK basic rate map */
153 /* SHM_SHARED microcode soft registers */
154 #define B43legacy_SHM_SH_UCODEREV 0x0000 /* Microcode revision */
155 #define B43legacy_SHM_SH_UCODEPATCH 0x0002 /* Microcode patchlevel */
156 #define B43legacy_SHM_SH_UCODEDATE 0x0004 /* Microcode date */
157 #define B43legacy_SHM_SH_UCODETIME 0x0006 /* Microcode time */
158 #define B43legacy_SHM_SH_SPUWKUP 0x0094 /* pre-wakeup for synth PU in us */
159 #define B43legacy_SHM_SH_PRETBTT 0x0096 /* pre-TBTT in us */
160
161 #define B43legacy_UCODEFLAGS_OFFSET 0x005E
162
163 /* Hardware Radio Enable masks */
164 #define B43legacy_MMIO_RADIO_HWENABLED_HI_MASK (1 << 16)
165 #define B43legacy_MMIO_RADIO_HWENABLED_LO_MASK (1 << 4)
166
167 /* HostFlags. See b43legacy_hf_read/write() */
168 #define B43legacy_HF_SYMW 0x00000002 /* G-PHY SYM workaround */
169 #define B43legacy_HF_GDCW 0x00000020 /* G-PHY DV cancel filter */
170 #define B43legacy_HF_OFDMPABOOST 0x00000040 /* Enable PA boost OFDM */
171 #define B43legacy_HF_EDCF 0x00000100 /* on if WME/MAC suspended */
172
173 /* MacFilter offsets. */
174 #define B43legacy_MACFILTER_SELF 0x0000
175 #define B43legacy_MACFILTER_BSSID 0x0003
176 #define B43legacy_MACFILTER_MAC 0x0010
177
178 /* PHYVersioning */
179 #define B43legacy_PHYTYPE_B 0x01
180 #define B43legacy_PHYTYPE_G 0x02
181
182 /* PHYRegisters */
183 #define B43legacy_PHY_G_LO_CONTROL 0x0810
184 #define B43legacy_PHY_ILT_G_CTRL 0x0472
185 #define B43legacy_PHY_ILT_G_DATA1 0x0473
186 #define B43legacy_PHY_ILT_G_DATA2 0x0474
187 #define B43legacy_PHY_G_PCTL 0x0029
188 #define B43legacy_PHY_RADIO_BITFIELD 0x0401
189 #define B43legacy_PHY_G_CRS 0x0429
190 #define B43legacy_PHY_NRSSILT_CTRL 0x0803
191 #define B43legacy_PHY_NRSSILT_DATA 0x0804
192
193 /* RadioRegisters */
194 #define B43legacy_RADIOCTL_ID 0x01
195
196 /* MAC Control bitfield */
197 #define B43legacy_MACCTL_ENABLED 0x00000001 /* MAC Enabled */
198 #define B43legacy_MACCTL_PSM_RUN 0x00000002 /* Run Microcode */
199 #define B43legacy_MACCTL_PSM_JMP0 0x00000004 /* Microcode jump to 0 */
200 #define B43legacy_MACCTL_SHM_ENABLED 0x00000100 /* SHM Enabled */
201 #define B43legacy_MACCTL_IHR_ENABLED 0x00000400 /* IHR Region Enabled */
202 #define B43legacy_MACCTL_BE 0x00010000 /* Big Endian mode */
203 #define B43legacy_MACCTL_INFRA 0x00020000 /* Infrastructure mode */
204 #define B43legacy_MACCTL_AP 0x00040000 /* AccessPoint mode */
205 #define B43legacy_MACCTL_RADIOLOCK 0x00080000 /* Radio lock */
206 #define B43legacy_MACCTL_BEACPROMISC 0x00100000 /* Beacon Promiscuous */
207 #define B43legacy_MACCTL_KEEP_BADPLCP 0x00200000 /* Keep bad PLCP frames */
208 #define B43legacy_MACCTL_KEEP_CTL 0x00400000 /* Keep control frames */
209 #define B43legacy_MACCTL_KEEP_BAD 0x00800000 /* Keep bad frames (FCS) */
210 #define B43legacy_MACCTL_PROMISC 0x01000000 /* Promiscuous mode */
211 #define B43legacy_MACCTL_HWPS 0x02000000 /* Hardware Power Saving */
212 #define B43legacy_MACCTL_AWAKE 0x04000000 /* Device is awake */
213 #define B43legacy_MACCTL_TBTTHOLD 0x10000000 /* TBTT Hold */
214 #define B43legacy_MACCTL_GMODE 0x80000000 /* G Mode */
215
216 /* MAC Command bitfield */
217 #define B43legacy_MACCMD_BEACON0_VALID 0x00000001 /* Beacon 0 in template RAM is busy/valid */
218 #define B43legacy_MACCMD_BEACON1_VALID 0x00000002 /* Beacon 1 in template RAM is busy/valid */
219 #define B43legacy_MACCMD_DFQ_VALID 0x00000004 /* Directed frame queue valid (IBSS PS mode, ATIM) */
220 #define B43legacy_MACCMD_CCA 0x00000008 /* Clear channel assessment */
221 #define B43legacy_MACCMD_BGNOISE 0x00000010 /* Background noise */
222
223 /* 802.11 core specific TM State Low flags */
224 #define B43legacy_TMSLOW_GMODE 0x20000000 /* G Mode Enable */
225 #define B43legacy_TMSLOW_PLLREFSEL 0x00200000 /* PLL Freq Ref Select */
226 #define B43legacy_TMSLOW_MACPHYCLKEN 0x00100000 /* MAC PHY Clock Ctrl Enbl */
227 #define B43legacy_TMSLOW_PHYRESET 0x00080000 /* PHY Reset */
228 #define B43legacy_TMSLOW_PHYCLKEN 0x00040000 /* PHY Clock Enable */
229
230 /* 802.11 core specific TM State High flags */
231 #define B43legacy_TMSHIGH_FCLOCK 0x00040000 /* Fast Clock Available */
232 #define B43legacy_TMSHIGH_GPHY 0x00010000 /* G-PHY avail (rev >= 5) */
233
234 #define B43legacy_UCODEFLAG_AUTODIV 0x0001
235
236 /* Generic-Interrupt reasons. */
237 #define B43legacy_IRQ_MAC_SUSPENDED 0x00000001
238 #define B43legacy_IRQ_BEACON 0x00000002
239 #define B43legacy_IRQ_TBTT_INDI 0x00000004 /* Target Beacon Transmit Time */
240 #define B43legacy_IRQ_BEACON_TX_OK 0x00000008
241 #define B43legacy_IRQ_BEACON_CANCEL 0x00000010
242 #define B43legacy_IRQ_ATIM_END 0x00000020
243 #define B43legacy_IRQ_PMQ 0x00000040
244 #define B43legacy_IRQ_PIO_WORKAROUND 0x00000100
245 #define B43legacy_IRQ_MAC_TXERR 0x00000200
246 #define B43legacy_IRQ_PHY_TXERR 0x00000800
247 #define B43legacy_IRQ_PMEVENT 0x00001000
248 #define B43legacy_IRQ_TIMER0 0x00002000
249 #define B43legacy_IRQ_TIMER1 0x00004000
250 #define B43legacy_IRQ_DMA 0x00008000
251 #define B43legacy_IRQ_TXFIFO_FLUSH_OK 0x00010000
252 #define B43legacy_IRQ_CCA_MEASURE_OK 0x00020000
253 #define B43legacy_IRQ_NOISESAMPLE_OK 0x00040000
254 #define B43legacy_IRQ_UCODE_DEBUG 0x08000000
255 #define B43legacy_IRQ_RFKILL 0x10000000
256 #define B43legacy_IRQ_TX_OK 0x20000000
257 #define B43legacy_IRQ_PHY_G_CHANGED 0x40000000
258 #define B43legacy_IRQ_TIMEOUT 0x80000000
259
260 #define B43legacy_IRQ_ALL 0xFFFFFFFF
261 #define B43legacy_IRQ_MASKTEMPLATE (B43legacy_IRQ_MAC_SUSPENDED | \
262 B43legacy_IRQ_TBTT_INDI | \
263 B43legacy_IRQ_ATIM_END | \
264 B43legacy_IRQ_PMQ | \
265 B43legacy_IRQ_MAC_TXERR | \
266 B43legacy_IRQ_PHY_TXERR | \
267 B43legacy_IRQ_DMA | \
268 B43legacy_IRQ_TXFIFO_FLUSH_OK | \
269 B43legacy_IRQ_NOISESAMPLE_OK | \
270 B43legacy_IRQ_UCODE_DEBUG | \
271 B43legacy_IRQ_RFKILL | \
272 B43legacy_IRQ_TX_OK)
273
274 /* Device specific rate values.
275 * The actual values defined here are (rate_in_mbps * 2).
276 * Some code depends on this. Don't change it. */
277 #define B43legacy_CCK_RATE_1MB 2
278 #define B43legacy_CCK_RATE_2MB 4
279 #define B43legacy_CCK_RATE_5MB 11
280 #define B43legacy_CCK_RATE_11MB 22
281 #define B43legacy_OFDM_RATE_6MB 12
282 #define B43legacy_OFDM_RATE_9MB 18
283 #define B43legacy_OFDM_RATE_12MB 24
284 #define B43legacy_OFDM_RATE_18MB 36
285 #define B43legacy_OFDM_RATE_24MB 48
286 #define B43legacy_OFDM_RATE_36MB 72
287 #define B43legacy_OFDM_RATE_48MB 96
288 #define B43legacy_OFDM_RATE_54MB 108
289 /* Convert a b43legacy rate value to a rate in 100kbps */
290 #define B43legacy_RATE_TO_100KBPS(rate) (((rate) * 10) / 2)
291
292
293 #define B43legacy_DEFAULT_SHORT_RETRY_LIMIT 7
294 #define B43legacy_DEFAULT_LONG_RETRY_LIMIT 4
295
296 #define B43legacy_PHY_TX_BADNESS_LIMIT 1000
297
298 /* Max size of a security key */
299 #define B43legacy_SEC_KEYSIZE 16
300 /* Security algorithms. */
301 enum {
302 B43legacy_SEC_ALGO_NONE = 0, /* unencrypted, as of TX header. */
303 B43legacy_SEC_ALGO_WEP40,
304 B43legacy_SEC_ALGO_TKIP,
305 B43legacy_SEC_ALGO_AES,
306 B43legacy_SEC_ALGO_WEP104,
307 B43legacy_SEC_ALGO_AES_LEGACY,
308 };
309
310 /* Core Information Registers */
311 #define B43legacy_CIR_BASE 0xf00
312 #define B43legacy_CIR_SBTPSFLAG (B43legacy_CIR_BASE + 0x18)
313 #define B43legacy_CIR_SBIMSTATE (B43legacy_CIR_BASE + 0x90)
314 #define B43legacy_CIR_SBINTVEC (B43legacy_CIR_BASE + 0x94)
315 #define B43legacy_CIR_SBTMSTATELOW (B43legacy_CIR_BASE + 0x98)
316 #define B43legacy_CIR_SBTMSTATEHIGH (B43legacy_CIR_BASE + 0x9c)
317 #define B43legacy_CIR_SBIMCONFIGLOW (B43legacy_CIR_BASE + 0xa8)
318 #define B43legacy_CIR_SB_ID_HI (B43legacy_CIR_BASE + 0xfc)
319
320 /* sbtmstatehigh state flags */
321 #define B43legacy_SBTMSTATEHIGH_SERROR 0x00000001
322 #define B43legacy_SBTMSTATEHIGH_BUSY 0x00000004
323 #define B43legacy_SBTMSTATEHIGH_TIMEOUT 0x00000020
324 #define B43legacy_SBTMSTATEHIGH_G_PHY_AVAIL 0x00010000
325 #define B43legacy_SBTMSTATEHIGH_COREFLAGS 0x1FFF0000
326 #define B43legacy_SBTMSTATEHIGH_DMA64BIT 0x10000000
327 #define B43legacy_SBTMSTATEHIGH_GATEDCLK 0x20000000
328 #define B43legacy_SBTMSTATEHIGH_BISTFAILED 0x40000000
329 #define B43legacy_SBTMSTATEHIGH_BISTCOMPLETE 0x80000000
330
331 /* sbimstate flags */
332 #define B43legacy_SBIMSTATE_IB_ERROR 0x20000
333 #define B43legacy_SBIMSTATE_TIMEOUT 0x40000
334
335 #define PFX KBUILD_MODNAME ": "
336 #ifdef assert
337 # undef assert
338 #endif
339 #ifdef CONFIG_B43LEGACY_DEBUG
340 # define B43legacy_WARN_ON(x) WARN_ON(x)
341 # define B43legacy_BUG_ON(expr) \
342 do { \
343 if (unlikely((expr))) { \
344 printk(KERN_INFO PFX "Test (%s) failed\n", \
345 #expr); \
346 BUG_ON(expr); \
347 } \
348 } while (0)
349 # define B43legacy_DEBUG 1
350 #else
351 /* This will evaluate the argument even if debugging is disabled. */
352 static inline bool __b43legacy_warn_on_dummy(bool x) { return x; }
353 # define B43legacy_WARN_ON(x) __b43legacy_warn_on_dummy(unlikely(!!(x)))
354 # define B43legacy_BUG_ON(x) do { /* nothing */ } while (0)
355 # define B43legacy_DEBUG 0
356 #endif
357
358
359 struct net_device;
360 struct pci_dev;
361 struct b43legacy_dmaring;
362 struct b43legacy_pioqueue;
363
364 /* The firmware file header */
365 #define B43legacy_FW_TYPE_UCODE 'u'
366 #define B43legacy_FW_TYPE_PCM 'p'
367 #define B43legacy_FW_TYPE_IV 'i'
368 struct b43legacy_fw_header {
369 /* File type */
370 u8 type;
371 /* File format version */
372 u8 ver;
373 u8 __padding[2];
374 /* Size of the data. For ucode and PCM this is in bytes.
375 * For IV this is number-of-ivs. */
376 __be32 size;
377 } __attribute__((__packed__));
378
379 /* Initial Value file format */
380 #define B43legacy_IV_OFFSET_MASK 0x7FFF
381 #define B43legacy_IV_32BIT 0x8000
382 struct b43legacy_iv {
383 __be16 offset_size;
384 union {
385 __be16 d16;
386 __be32 d32;
387 } data __attribute__((__packed__));
388 } __attribute__((__packed__));
389
390 #define B43legacy_PHYMODE(phytype) (1 << (phytype))
391 #define B43legacy_PHYMODE_B B43legacy_PHYMODE \
392 ((B43legacy_PHYTYPE_B))
393 #define B43legacy_PHYMODE_G B43legacy_PHYMODE \
394 ((B43legacy_PHYTYPE_G))
395
396 /* Value pair to measure the LocalOscillator. */
397 struct b43legacy_lopair {
398 s8 low;
399 s8 high;
400 u8 used:1;
401 };
402 #define B43legacy_LO_COUNT (14*4)
403
404 struct b43legacy_phy {
405 /* Possible PHYMODEs on this PHY */
406 u8 possible_phymodes;
407 /* GMODE bit enabled in MACCTL? */
408 bool gmode;
409
410 /* Analog Type */
411 u8 analog;
412 /* B43legacy_PHYTYPE_ */
413 u8 type;
414 /* PHY revision number. */
415 u8 rev;
416
417 u16 antenna_diversity;
418 u16 savedpctlreg;
419 /* Radio versioning */
420 u16 radio_manuf; /* Radio manufacturer */
421 u16 radio_ver; /* Radio version */
422 u8 calibrated:1;
423 u8 radio_rev; /* Radio revision */
424
425 bool dyn_tssi_tbl; /* tssi2dbm is kmalloc()ed. */
426
427 /* ACI (adjacent channel interference) flags. */
428 bool aci_enable;
429 bool aci_wlan_automatic;
430 bool aci_hw_rssi;
431
432 /* Radio switched on/off */
433 bool radio_on;
434 struct {
435 /* Values saved when turning the radio off.
436 * They are needed when turning it on again. */
437 bool valid;
438 u16 rfover;
439 u16 rfoverval;
440 } radio_off_context;
441
442 u16 minlowsig[2];
443 u16 minlowsigpos[2];
444
445 /* LO Measurement Data.
446 * Use b43legacy_get_lopair() to get a value.
447 */
448 struct b43legacy_lopair *_lo_pairs;
449 /* TSSI to dBm table in use */
450 const s8 *tssi2dbm;
451 /* idle TSSI value */
452 s8 idle_tssi;
453 /* Target idle TSSI */
454 int tgt_idle_tssi;
455 /* Current idle TSSI */
456 int cur_idle_tssi;
457
458 /* LocalOscillator control values. */
459 struct b43legacy_txpower_lo_control *lo_control;
460 /* Values from b43legacy_calc_loopback_gain() */
461 s16 max_lb_gain; /* Maximum Loopback gain in hdB */
462 s16 trsw_rx_gain; /* TRSW RX gain in hdB */
463 s16 lna_lod_gain; /* LNA lod */
464 s16 lna_gain; /* LNA */
465 s16 pga_gain; /* PGA */
466
467 /* Desired TX power level (in dBm). This is set by the user and
468 * adjusted in b43legacy_phy_xmitpower(). */
469 u8 power_level;
470
471 /* Values from b43legacy_calc_loopback_gain() */
472 u16 loopback_gain[2];
473
474 /* TX Power control values. */
475 /* B/G PHY */
476 struct {
477 /* Current Radio Attenuation for TXpower recalculation. */
478 u16 rfatt;
479 /* Current Baseband Attenuation for TXpower recalculation. */
480 u16 bbatt;
481 /* Current TXpower control value for TXpower recalculation. */
482 u16 txctl1;
483 u16 txctl2;
484 };
485 /* A PHY */
486 struct {
487 u16 txpwr_offset;
488 };
489
490 /* Current Interference Mitigation mode */
491 int interfmode;
492 /* Stack of saved values from the Interference Mitigation code.
493 * Each value in the stack is layed out as follows:
494 * bit 0-11: offset
495 * bit 12-15: register ID
496 * bit 16-32: value
497 * register ID is: 0x1 PHY, 0x2 Radio, 0x3 ILT
498 */
499 #define B43legacy_INTERFSTACK_SIZE 26
500 u32 interfstack[B43legacy_INTERFSTACK_SIZE];
501
502 /* Saved values from the NRSSI Slope calculation */
503 s16 nrssi[2];
504 s32 nrssislope;
505 /* In memory nrssi lookup table. */
506 s8 nrssi_lt[64];
507
508 /* current channel */
509 u8 channel;
510
511 u16 lofcal;
512
513 u16 initval;
514
515 /* PHY TX errors counter. */
516 atomic_t txerr_cnt;
517
518 #if B43legacy_DEBUG
519 /* Manual TX-power control enabled? */
520 bool manual_txpower_control;
521 /* PHY registers locked by b43legacy_phy_lock()? */
522 bool phy_locked;
523 #endif /* B43legacy_DEBUG */
524 };
525
526 /* Data structures for DMA transmission, per 80211 core. */
527 struct b43legacy_dma {
528 struct b43legacy_dmaring *tx_ring0;
529 struct b43legacy_dmaring *tx_ring1;
530 struct b43legacy_dmaring *tx_ring2;
531 struct b43legacy_dmaring *tx_ring3;
532 struct b43legacy_dmaring *tx_ring4;
533 struct b43legacy_dmaring *tx_ring5;
534
535 struct b43legacy_dmaring *rx_ring0;
536 struct b43legacy_dmaring *rx_ring3; /* only on core.rev < 5 */
537 };
538
539 /* Data structures for PIO transmission, per 80211 core. */
540 struct b43legacy_pio {
541 struct b43legacy_pioqueue *queue0;
542 struct b43legacy_pioqueue *queue1;
543 struct b43legacy_pioqueue *queue2;
544 struct b43legacy_pioqueue *queue3;
545 };
546
547 /* Context information for a noise calculation (Link Quality). */
548 struct b43legacy_noise_calculation {
549 u8 channel_at_start;
550 bool calculation_running;
551 u8 nr_samples;
552 s8 samples[8][4];
553 };
554
555 struct b43legacy_stats {
556 u8 link_noise;
557 /* Store the last TX/RX times here for updating the leds. */
558 unsigned long last_tx;
559 unsigned long last_rx;
560 };
561
562 struct b43legacy_key {
563 void *keyconf;
564 bool enabled;
565 u8 algorithm;
566 };
567
568 struct b43legacy_wldev;
569
570 /* Data structure for the WLAN parts (802.11 cores) of the b43legacy chip. */
571 struct b43legacy_wl {
572 /* Pointer to the active wireless device on this chip */
573 struct b43legacy_wldev *current_dev;
574 /* Pointer to the ieee80211 hardware data structure */
575 struct ieee80211_hw *hw;
576
577 spinlock_t irq_lock; /* locks IRQ */
578 struct mutex mutex; /* locks wireless core state */
579 spinlock_t leds_lock; /* lock for leds */
580
581 /* We can only have one operating interface (802.11 core)
582 * at a time. General information about this interface follows.
583 */
584
585 struct ieee80211_vif *vif;
586 /* MAC address (can be NULL). */
587 u8 mac_addr[ETH_ALEN];
588 /* Current BSSID (can be NULL). */
589 u8 bssid[ETH_ALEN];
590 /* Interface type. (IEEE80211_IF_TYPE_XXX) */
591 int if_type;
592 /* Is the card operating in AP, STA or IBSS mode? */
593 bool operating;
594 /* filter flags */
595 unsigned int filter_flags;
596 /* Stats about the wireless interface */
597 struct ieee80211_low_level_stats ieee_stats;
598
599 #ifdef CONFIG_B43LEGACY_HWRNG
600 struct hwrng rng;
601 u8 rng_initialized;
602 char rng_name[30 + 1];
603 #endif
604
605 /* List of all wireless devices on this chip */
606 struct list_head devlist;
607 u8 nr_devs;
608
609 bool radiotap_enabled;
610 bool radio_enabled;
611
612 /* The beacon we are currently using (AP or IBSS mode).
613 * This beacon stuff is protected by the irq_lock. */
614 struct sk_buff *current_beacon;
615 bool beacon0_uploaded;
616 bool beacon1_uploaded;
617 bool beacon_templates_virgin; /* Never wrote the templates? */
618 struct work_struct beacon_update_trigger;
619 };
620
621 /* Pointers to the firmware data and meta information about it. */
622 struct b43legacy_firmware {
623 /* Microcode */
624 const struct firmware *ucode;
625 /* PCM code */
626 const struct firmware *pcm;
627 /* Initial MMIO values for the firmware */
628 const struct firmware *initvals;
629 /* Initial MMIO values for the firmware, band-specific */
630 const struct firmware *initvals_band;
631 /* Firmware revision */
632 u16 rev;
633 /* Firmware patchlevel */
634 u16 patch;
635 };
636
637 /* Device (802.11 core) initialization status. */
638 enum {
639 B43legacy_STAT_UNINIT = 0, /* Uninitialized. */
640 B43legacy_STAT_INITIALIZED = 1, /* Initialized, not yet started. */
641 B43legacy_STAT_STARTED = 2, /* Up and running. */
642 };
643 #define b43legacy_status(wldev) atomic_read(&(wldev)->__init_status)
644 #define b43legacy_set_status(wldev, stat) do { \
645 atomic_set(&(wldev)->__init_status, (stat)); \
646 smp_wmb(); \
647 } while (0)
648
649 /* *** --- HOW LOCKING WORKS IN B43legacy --- ***
650 *
651 * You should always acquire both, wl->mutex and wl->irq_lock unless:
652 * - You don't need to acquire wl->irq_lock, if the interface is stopped.
653 * - You don't need to acquire wl->mutex in the IRQ handler, IRQ tasklet
654 * and packet TX path (and _ONLY_ there.)
655 */
656
657 /* Data structure for one wireless device (802.11 core) */
658 struct b43legacy_wldev {
659 struct ssb_device *dev;
660 struct b43legacy_wl *wl;
661
662 /* The device initialization status.
663 * Use b43legacy_status() to query. */
664 atomic_t __init_status;
665 /* Saved init status for handling suspend. */
666 int suspend_init_status;
667
668 bool __using_pio; /* Using pio rather than dma. */
669 bool bad_frames_preempt;/* Use "Bad Frames Preemption". */
670 bool dfq_valid; /* Directed frame queue valid (IBSS PS mode, ATIM). */
671 bool short_preamble; /* TRUE if using short preamble. */
672 bool radio_hw_enable; /* State of radio hardware enable bit. */
673
674 /* PHY/Radio device. */
675 struct b43legacy_phy phy;
676 union {
677 /* DMA engines. */
678 struct b43legacy_dma dma;
679 /* PIO engines. */
680 struct b43legacy_pio pio;
681 };
682
683 /* Various statistics about the physical device. */
684 struct b43legacy_stats stats;
685
686 /* The device LEDs. */
687 struct b43legacy_led led_tx;
688 struct b43legacy_led led_rx;
689 struct b43legacy_led led_assoc;
690 struct b43legacy_led led_radio;
691
692 /* Reason code of the last interrupt. */
693 u32 irq_reason;
694 u32 dma_reason[6];
695 /* The currently active generic-interrupt mask. */
696 u32 irq_mask;
697 /* Link Quality calculation context. */
698 struct b43legacy_noise_calculation noisecalc;
699 /* if > 0 MAC is suspended. if == 0 MAC is enabled. */
700 int mac_suspended;
701
702 /* Interrupt Service Routine tasklet (bottom-half) */
703 struct tasklet_struct isr_tasklet;
704
705 /* Periodic tasks */
706 struct delayed_work periodic_work;
707 unsigned int periodic_state;
708
709 struct work_struct restart_work;
710
711 /* encryption/decryption */
712 u16 ktp; /* Key table pointer */
713 u8 max_nr_keys;
714 struct b43legacy_key key[58];
715
716 /* Firmware data */
717 struct b43legacy_firmware fw;
718
719 /* Devicelist in struct b43legacy_wl (all 802.11 cores) */
720 struct list_head list;
721
722 /* Debugging stuff follows. */
723 #ifdef CONFIG_B43LEGACY_DEBUG
724 struct b43legacy_dfsentry *dfsentry;
725 #endif
726 };
727
728
729 static inline
730 struct b43legacy_wl *hw_to_b43legacy_wl(struct ieee80211_hw *hw)
731 {
732 return hw->priv;
733 }
734
735 /* Helper function, which returns a boolean.
736 * TRUE, if PIO is used; FALSE, if DMA is used.
737 */
738 #if defined(CONFIG_B43LEGACY_DMA) && defined(CONFIG_B43LEGACY_PIO)
739 static inline
740 int b43legacy_using_pio(struct b43legacy_wldev *dev)
741 {
742 return dev->__using_pio;
743 }
744 #elif defined(CONFIG_B43LEGACY_DMA)
745 static inline
746 int b43legacy_using_pio(struct b43legacy_wldev *dev)
747 {
748 return 0;
749 }
750 #elif defined(CONFIG_B43LEGACY_PIO)
751 static inline
752 int b43legacy_using_pio(struct b43legacy_wldev *dev)
753 {
754 return 1;
755 }
756 #else
757 # error "Using neither DMA nor PIO? Confused..."
758 #endif
759
760
761 static inline
762 struct b43legacy_wldev *dev_to_b43legacy_wldev(struct device *dev)
763 {
764 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
765 return ssb_get_drvdata(ssb_dev);
766 }
767
768 /* Is the device operating in a specified mode (IEEE80211_IF_TYPE_XXX). */
769 static inline
770 int b43legacy_is_mode(struct b43legacy_wl *wl, int type)
771 {
772 return (wl->operating &&
773 wl->if_type == type);
774 }
775
776 static inline
777 bool is_bcm_board_vendor(struct b43legacy_wldev *dev)
778 {
779 return (dev->dev->bus->boardinfo.vendor == PCI_VENDOR_ID_BROADCOM);
780 }
781
782 static inline
783 u16 b43legacy_read16(struct b43legacy_wldev *dev, u16 offset)
784 {
785 return ssb_read16(dev->dev, offset);
786 }
787
788 static inline
789 void b43legacy_write16(struct b43legacy_wldev *dev, u16 offset, u16 value)
790 {
791 ssb_write16(dev->dev, offset, value);
792 }
793
794 static inline
795 u32 b43legacy_read32(struct b43legacy_wldev *dev, u16 offset)
796 {
797 return ssb_read32(dev->dev, offset);
798 }
799
800 static inline
801 void b43legacy_write32(struct b43legacy_wldev *dev, u16 offset, u32 value)
802 {
803 ssb_write32(dev->dev, offset, value);
804 }
805
806 static inline
807 struct b43legacy_lopair *b43legacy_get_lopair(struct b43legacy_phy *phy,
808 u16 radio_attenuation,
809 u16 baseband_attenuation)
810 {
811 return phy->_lo_pairs + (radio_attenuation
812 + 14 * (baseband_attenuation / 2));
813 }
814
815
816
817 /* Message printing */
818 void b43legacyinfo(struct b43legacy_wl *wl, const char *fmt, ...)
819 __attribute__((format(printf, 2, 3)));
820 void b43legacyerr(struct b43legacy_wl *wl, const char *fmt, ...)
821 __attribute__((format(printf, 2, 3)));
822 void b43legacywarn(struct b43legacy_wl *wl, const char *fmt, ...)
823 __attribute__((format(printf, 2, 3)));
824 #if B43legacy_DEBUG
825 void b43legacydbg(struct b43legacy_wl *wl, const char *fmt, ...)
826 __attribute__((format(printf, 2, 3)));
827 #else /* DEBUG */
828 # define b43legacydbg(wl, fmt...) do { /* nothing */ } while (0)
829 #endif /* DEBUG */
830
831 /* Macros for printing a value in Q5.2 format */
832 #define Q52_FMT "%u.%u"
833 #define Q52_ARG(q52) ((q52) / 4), (((q52) & 3) * 100 / 4)
834
835 #endif /* B43legacy_H_ */
836
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