1 /*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
13
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
18
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
23
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
28
29 */
30
31 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/moduleparam.h>
34 #include <linux/if_arp.h>
35 #include <linux/etherdevice.h>
36 #include <linux/version.h>
37 #include <linux/firmware.h>
38 #include <linux/wireless.h>
39 #include <linux/workqueue.h>
40 #include <linux/skbuff.h>
41 #include <linux/io.h>
42 #include <linux/dma-mapping.h>
43 #include <asm/unaligned.h>
44
45 #include "b43.h"
46 #include "main.h"
47 #include "debugfs.h"
48 #include "phy.h"
49 #include "dma.h"
50 #include "sysfs.h"
51 #include "xmit.h"
52 #include "lo.h"
53 #include "pcmcia.h"
54
55 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
56 MODULE_AUTHOR("Martin Langer");
57 MODULE_AUTHOR("Stefano Brivio");
58 MODULE_AUTHOR("Michael Buesch");
59 MODULE_LICENSE("GPL");
60
61 MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID);
62
63
64 static int modparam_bad_frames_preempt;
65 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
66 MODULE_PARM_DESC(bad_frames_preempt,
67 "enable(1) / disable(0) Bad Frames Preemption");
68
69 static char modparam_fwpostfix[16];
70 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
71 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
72
73 static int modparam_hwpctl;
74 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
75 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
76
77 static int modparam_nohwcrypt;
78 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
79 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
80
81 static int modparam_btcoex = 1;
82 module_param_named(btcoex, modparam_btcoex, int, 0444);
83 MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistance (default on)");
84
85
86 static const struct ssb_device_id b43_ssb_tbl[] = {
87 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
88 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
89 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
90 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
91 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
92 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
93 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
94 SSB_DEVTABLE_END
95 };
96
97 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
98
99 /* Channel and ratetables are shared for all devices.
100 * They can't be const, because ieee80211 puts some precalculated
101 * data in there. This data is the same for all devices, so we don't
102 * get concurrency issues */
103 #define RATETAB_ENT(_rateid, _flags) \
104 { \
105 .rate = B43_RATE_TO_BASE100KBPS(_rateid), \
106 .val = (_rateid), \
107 .val2 = (_rateid), \
108 .flags = (_flags), \
109 }
110 static struct ieee80211_rate __b43_ratetable[] = {
111 RATETAB_ENT(B43_CCK_RATE_1MB, IEEE80211_RATE_CCK),
112 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_CCK_2),
113 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_CCK_2),
114 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_CCK_2),
115 RATETAB_ENT(B43_OFDM_RATE_6MB, IEEE80211_RATE_OFDM),
116 RATETAB_ENT(B43_OFDM_RATE_9MB, IEEE80211_RATE_OFDM),
117 RATETAB_ENT(B43_OFDM_RATE_12MB, IEEE80211_RATE_OFDM),
118 RATETAB_ENT(B43_OFDM_RATE_18MB, IEEE80211_RATE_OFDM),
119 RATETAB_ENT(B43_OFDM_RATE_24MB, IEEE80211_RATE_OFDM),
120 RATETAB_ENT(B43_OFDM_RATE_36MB, IEEE80211_RATE_OFDM),
121 RATETAB_ENT(B43_OFDM_RATE_48MB, IEEE80211_RATE_OFDM),
122 RATETAB_ENT(B43_OFDM_RATE_54MB, IEEE80211_RATE_OFDM),
123 };
124
125 #define b43_a_ratetable (__b43_ratetable + 4)
126 #define b43_a_ratetable_size 8
127 #define b43_b_ratetable (__b43_ratetable + 0)
128 #define b43_b_ratetable_size 4
129 #define b43_g_ratetable (__b43_ratetable + 0)
130 #define b43_g_ratetable_size 12
131
132 #define CHANTAB_ENT(_chanid, _freq) \
133 { \
134 .chan = (_chanid), \
135 .freq = (_freq), \
136 .val = (_chanid), \
137 .flag = IEEE80211_CHAN_W_SCAN | \
138 IEEE80211_CHAN_W_ACTIVE_SCAN | \
139 IEEE80211_CHAN_W_IBSS, \
140 .power_level = 0xFF, \
141 .antenna_max = 0xFF, \
142 }
143 static struct ieee80211_channel b43_2ghz_chantable[] = {
144 CHANTAB_ENT(1, 2412),
145 CHANTAB_ENT(2, 2417),
146 CHANTAB_ENT(3, 2422),
147 CHANTAB_ENT(4, 2427),
148 CHANTAB_ENT(5, 2432),
149 CHANTAB_ENT(6, 2437),
150 CHANTAB_ENT(7, 2442),
151 CHANTAB_ENT(8, 2447),
152 CHANTAB_ENT(9, 2452),
153 CHANTAB_ENT(10, 2457),
154 CHANTAB_ENT(11, 2462),
155 CHANTAB_ENT(12, 2467),
156 CHANTAB_ENT(13, 2472),
157 CHANTAB_ENT(14, 2484),
158 };
159 #define b43_2ghz_chantable_size ARRAY_SIZE(b43_2ghz_chantable)
160
161 #if 0
162 static struct ieee80211_channel b43_5ghz_chantable[] = {
163 CHANTAB_ENT(36, 5180),
164 CHANTAB_ENT(40, 5200),
165 CHANTAB_ENT(44, 5220),
166 CHANTAB_ENT(48, 5240),
167 CHANTAB_ENT(52, 5260),
168 CHANTAB_ENT(56, 5280),
169 CHANTAB_ENT(60, 5300),
170 CHANTAB_ENT(64, 5320),
171 CHANTAB_ENT(149, 5745),
172 CHANTAB_ENT(153, 5765),
173 CHANTAB_ENT(157, 5785),
174 CHANTAB_ENT(161, 5805),
175 CHANTAB_ENT(165, 5825),
176 };
177 #define b43_5ghz_chantable_size ARRAY_SIZE(b43_5ghz_chantable)
178 #endif
179
180 static void b43_wireless_core_exit(struct b43_wldev *dev);
181 static int b43_wireless_core_init(struct b43_wldev *dev);
182 static void b43_wireless_core_stop(struct b43_wldev *dev);
183 static int b43_wireless_core_start(struct b43_wldev *dev);
184
185 static int b43_ratelimit(struct b43_wl *wl)
186 {
187 if (!wl || !wl->current_dev)
188 return 1;
189 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
190 return 1;
191 /* We are up and running.
192 * Ratelimit the messages to avoid DoS over the net. */
193 return net_ratelimit();
194 }
195
196 void b43info(struct b43_wl *wl, const char *fmt, ...)
197 {
198 va_list args;
199
200 if (!b43_ratelimit(wl))
201 return;
202 va_start(args, fmt);
203 printk(KERN_INFO "b43-%s: ",
204 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
205 vprintk(fmt, args);
206 va_end(args);
207 }
208
209 void b43err(struct b43_wl *wl, const char *fmt, ...)
210 {
211 va_list args;
212
213 if (!b43_ratelimit(wl))
214 return;
215 va_start(args, fmt);
216 printk(KERN_ERR "b43-%s ERROR: ",
217 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
218 vprintk(fmt, args);
219 va_end(args);
220 }
221
222 void b43warn(struct b43_wl *wl, const char *fmt, ...)
223 {
224 va_list args;
225
226 if (!b43_ratelimit(wl))
227 return;
228 va_start(args, fmt);
229 printk(KERN_WARNING "b43-%s warning: ",
230 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
231 vprintk(fmt, args);
232 va_end(args);
233 }
234
235 #if B43_DEBUG
236 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
237 {
238 va_list args;
239
240 va_start(args, fmt);
241 printk(KERN_DEBUG "b43-%s debug: ",
242 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
243 vprintk(fmt, args);
244 va_end(args);
245 }
246 #endif /* DEBUG */
247
248 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
249 {
250 u32 macctl;
251
252 B43_WARN_ON(offset % 4 != 0);
253
254 macctl = b43_read32(dev, B43_MMIO_MACCTL);
255 if (macctl & B43_MACCTL_BE)
256 val = swab32(val);
257
258 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
259 mmiowb();
260 b43_write32(dev, B43_MMIO_RAM_DATA, val);
261 }
262
263 static inline void b43_shm_control_word(struct b43_wldev *dev,
264 u16 routing, u16 offset)
265 {
266 u32 control;
267
268 /* "offset" is the WORD offset. */
269 control = routing;
270 control <<= 16;
271 control |= offset;
272 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
273 }
274
275 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
276 {
277 struct b43_wl *wl = dev->wl;
278 unsigned long flags;
279 u32 ret;
280
281 spin_lock_irqsave(&wl->shm_lock, flags);
282 if (routing == B43_SHM_SHARED) {
283 B43_WARN_ON(offset & 0x0001);
284 if (offset & 0x0003) {
285 /* Unaligned access */
286 b43_shm_control_word(dev, routing, offset >> 2);
287 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
288 ret <<= 16;
289 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
290 ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
291
292 goto out;
293 }
294 offset >>= 2;
295 }
296 b43_shm_control_word(dev, routing, offset);
297 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
298 out:
299 spin_unlock_irqrestore(&wl->shm_lock, flags);
300
301 return ret;
302 }
303
304 u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset)
305 {
306 struct b43_wl *wl = dev->wl;
307 unsigned long flags;
308 u16 ret;
309
310 spin_lock_irqsave(&wl->shm_lock, flags);
311 if (routing == B43_SHM_SHARED) {
312 B43_WARN_ON(offset & 0x0001);
313 if (offset & 0x0003) {
314 /* Unaligned access */
315 b43_shm_control_word(dev, routing, offset >> 2);
316 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
317
318 goto out;
319 }
320 offset >>= 2;
321 }
322 b43_shm_control_word(dev, routing, offset);
323 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
324 out:
325 spin_unlock_irqrestore(&wl->shm_lock, flags);
326
327 return ret;
328 }
329
330 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
331 {
332 struct b43_wl *wl = dev->wl;
333 unsigned long flags;
334
335 spin_lock_irqsave(&wl->shm_lock, flags);
336 if (routing == B43_SHM_SHARED) {
337 B43_WARN_ON(offset & 0x0001);
338 if (offset & 0x0003) {
339 /* Unaligned access */
340 b43_shm_control_word(dev, routing, offset >> 2);
341 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
342 (value >> 16) & 0xffff);
343 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
344 b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
345 goto out;
346 }
347 offset >>= 2;
348 }
349 b43_shm_control_word(dev, routing, offset);
350 b43_write32(dev, B43_MMIO_SHM_DATA, value);
351 out:
352 spin_unlock_irqrestore(&wl->shm_lock, flags);
353 }
354
355 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
356 {
357 struct b43_wl *wl = dev->wl;
358 unsigned long flags;
359
360 spin_lock_irqsave(&wl->shm_lock, flags);
361 if (routing == B43_SHM_SHARED) {
362 B43_WARN_ON(offset & 0x0001);
363 if (offset & 0x0003) {
364 /* Unaligned access */
365 b43_shm_control_word(dev, routing, offset >> 2);
366 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
367 goto out;
368 }
369 offset >>= 2;
370 }
371 b43_shm_control_word(dev, routing, offset);
372 b43_write16(dev, B43_MMIO_SHM_DATA, value);
373 out:
374 spin_unlock_irqrestore(&wl->shm_lock, flags);
375 }
376
377 /* Read HostFlags */
378 u32 b43_hf_read(struct b43_wldev * dev)
379 {
380 u32 ret;
381
382 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
383 ret <<= 16;
384 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
385
386 return ret;
387 }
388
389 /* Write HostFlags */
390 void b43_hf_write(struct b43_wldev *dev, u32 value)
391 {
392 b43_shm_write16(dev, B43_SHM_SHARED,
393 B43_SHM_SH_HOSTFLO, (value & 0x0000FFFF));
394 b43_shm_write16(dev, B43_SHM_SHARED,
395 B43_SHM_SH_HOSTFHI, ((value & 0xFFFF0000) >> 16));
396 }
397
398 void b43_tsf_read(struct b43_wldev *dev, u64 * tsf)
399 {
400 /* We need to be careful. As we read the TSF from multiple
401 * registers, we should take care of register overflows.
402 * In theory, the whole tsf read process should be atomic.
403 * We try to be atomic here, by restaring the read process,
404 * if any of the high registers changed (overflew).
405 */
406 if (dev->dev->id.revision >= 3) {
407 u32 low, high, high2;
408
409 do {
410 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
411 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
412 high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
413 } while (unlikely(high != high2));
414
415 *tsf = high;
416 *tsf <<= 32;
417 *tsf |= low;
418 } else {
419 u64 tmp;
420 u16 v0, v1, v2, v3;
421 u16 test1, test2, test3;
422
423 do {
424 v3 = b43_read16(dev, B43_MMIO_TSF_3);
425 v2 = b43_read16(dev, B43_MMIO_TSF_2);
426 v1 = b43_read16(dev, B43_MMIO_TSF_1);
427 v0 = b43_read16(dev, B43_MMIO_TSF_0);
428
429 test3 = b43_read16(dev, B43_MMIO_TSF_3);
430 test2 = b43_read16(dev, B43_MMIO_TSF_2);
431 test1 = b43_read16(dev, B43_MMIO_TSF_1);
432 } while (v3 != test3 || v2 != test2 || v1 != test1);
433
434 *tsf = v3;
435 *tsf <<= 48;
436 tmp = v2;
437 tmp <<= 32;
438 *tsf |= tmp;
439 tmp = v1;
440 tmp <<= 16;
441 *tsf |= tmp;
442 *tsf |= v0;
443 }
444 }
445
446 static void b43_time_lock(struct b43_wldev *dev)
447 {
448 u32 macctl;
449
450 macctl = b43_read32(dev, B43_MMIO_MACCTL);
451 macctl |= B43_MACCTL_TBTTHOLD;
452 b43_write32(dev, B43_MMIO_MACCTL, macctl);
453 /* Commit the write */
454 b43_read32(dev, B43_MMIO_MACCTL);
455 }
456
457 static void b43_time_unlock(struct b43_wldev *dev)
458 {
459 u32 macctl;
460
461 macctl = b43_read32(dev, B43_MMIO_MACCTL);
462 macctl &= ~B43_MACCTL_TBTTHOLD;
463 b43_write32(dev, B43_MMIO_MACCTL, macctl);
464 /* Commit the write */
465 b43_read32(dev, B43_MMIO_MACCTL);
466 }
467
468 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
469 {
470 /* Be careful with the in-progress timer.
471 * First zero out the low register, so we have a full
472 * register-overflow duration to complete the operation.
473 */
474 if (dev->dev->id.revision >= 3) {
475 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
476 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
477
478 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0);
479 mmiowb();
480 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi);
481 mmiowb();
482 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo);
483 } else {
484 u16 v0 = (tsf & 0x000000000000FFFFULL);
485 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
486 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
487 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
488
489 b43_write16(dev, B43_MMIO_TSF_0, 0);
490 mmiowb();
491 b43_write16(dev, B43_MMIO_TSF_3, v3);
492 mmiowb();
493 b43_write16(dev, B43_MMIO_TSF_2, v2);
494 mmiowb();
495 b43_write16(dev, B43_MMIO_TSF_1, v1);
496 mmiowb();
497 b43_write16(dev, B43_MMIO_TSF_0, v0);
498 }
499 }
500
501 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
502 {
503 b43_time_lock(dev);
504 b43_tsf_write_locked(dev, tsf);
505 b43_time_unlock(dev);
506 }
507
508 static
509 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
510 {
511 static const u8 zero_addr[ETH_ALEN] = { 0 };
512 u16 data;
513
514 if (!mac)
515 mac = zero_addr;
516
517 offset |= 0x0020;
518 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
519
520 data = mac[0];
521 data |= mac[1] << 8;
522 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
523 data = mac[2];
524 data |= mac[3] << 8;
525 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
526 data = mac[4];
527 data |= mac[5] << 8;
528 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
529 }
530
531 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
532 {
533 const u8 *mac;
534 const u8 *bssid;
535 u8 mac_bssid[ETH_ALEN * 2];
536 int i;
537 u32 tmp;
538
539 bssid = dev->wl->bssid;
540 mac = dev->wl->mac_addr;
541
542 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
543
544 memcpy(mac_bssid, mac, ETH_ALEN);
545 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
546
547 /* Write our MAC address and BSSID to template ram */
548 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
549 tmp = (u32) (mac_bssid[i + 0]);
550 tmp |= (u32) (mac_bssid[i + 1]) << 8;
551 tmp |= (u32) (mac_bssid[i + 2]) << 16;
552 tmp |= (u32) (mac_bssid[i + 3]) << 24;
553 b43_ram_write(dev, 0x20 + i, tmp);
554 }
555 }
556
557 static void b43_upload_card_macaddress(struct b43_wldev *dev)
558 {
559 b43_write_mac_bssid_templates(dev);
560 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
561 }
562
563 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
564 {
565 /* slot_time is in usec. */
566 if (dev->phy.type != B43_PHYTYPE_G)
567 return;
568 b43_write16(dev, 0x684, 510 + slot_time);
569 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
570 }
571
572 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
573 {
574 b43_set_slot_time(dev, 9);
575 dev->short_slot = 1;
576 }
577
578 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
579 {
580 b43_set_slot_time(dev, 20);
581 dev->short_slot = 0;
582 }
583
584 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
585 * Returns the _previously_ enabled IRQ mask.
586 */
587 static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
588 {
589 u32 old_mask;
590
591 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
592 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
593
594 return old_mask;
595 }
596
597 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
598 * Returns the _previously_ enabled IRQ mask.
599 */
600 static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
601 {
602 u32 old_mask;
603
604 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
605 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
606
607 return old_mask;
608 }
609
610 /* Synchronize IRQ top- and bottom-half.
611 * IRQs must be masked before calling this.
612 * This must not be called with the irq_lock held.
613 */
614 static void b43_synchronize_irq(struct b43_wldev *dev)
615 {
616 synchronize_irq(dev->dev->irq);
617 tasklet_kill(&dev->isr_tasklet);
618 }
619
620 /* DummyTransmission function, as documented on
621 * http://bcm-specs.sipsolutions.net/DummyTransmission
622 */
623 void b43_dummy_transmission(struct b43_wldev *dev)
624 {
625 struct b43_wl *wl = dev->wl;
626 struct b43_phy *phy = &dev->phy;
627 unsigned int i, max_loop;
628 u16 value;
629 u32 buffer[5] = {
630 0x00000000,
631 0x00D40000,
632 0x00000000,
633 0x01000000,
634 0x00000000,
635 };
636
637 switch (phy->type) {
638 case B43_PHYTYPE_A:
639 max_loop = 0x1E;
640 buffer[0] = 0x000201CC;
641 break;
642 case B43_PHYTYPE_B:
643 case B43_PHYTYPE_G:
644 max_loop = 0xFA;
645 buffer[0] = 0x000B846E;
646 break;
647 default:
648 B43_WARN_ON(1);
649 return;
650 }
651
652 spin_lock_irq(&wl->irq_lock);
653 write_lock(&wl->tx_lock);
654
655 for (i = 0; i < 5; i++)
656 b43_ram_write(dev, i * 4, buffer[i]);
657
658 /* Commit writes */
659 b43_read32(dev, B43_MMIO_MACCTL);
660
661 b43_write16(dev, 0x0568, 0x0000);
662 b43_write16(dev, 0x07C0, 0x0000);
663 value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
664 b43_write16(dev, 0x050C, value);
665 b43_write16(dev, 0x0508, 0x0000);
666 b43_write16(dev, 0x050A, 0x0000);
667 b43_write16(dev, 0x054C, 0x0000);
668 b43_write16(dev, 0x056A, 0x0014);
669 b43_write16(dev, 0x0568, 0x0826);
670 b43_write16(dev, 0x0500, 0x0000);
671 b43_write16(dev, 0x0502, 0x0030);
672
673 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
674 b43_radio_write16(dev, 0x0051, 0x0017);
675 for (i = 0x00; i < max_loop; i++) {
676 value = b43_read16(dev, 0x050E);
677 if (value & 0x0080)
678 break;
679 udelay(10);
680 }
681 for (i = 0x00; i < 0x0A; i++) {
682 value = b43_read16(dev, 0x050E);
683 if (value & 0x0400)
684 break;
685 udelay(10);
686 }
687 for (i = 0x00; i < 0x0A; i++) {
688 value = b43_read16(dev, 0x0690);
689 if (!(value & 0x0100))
690 break;
691 udelay(10);
692 }
693 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
694 b43_radio_write16(dev, 0x0051, 0x0037);
695
696 write_unlock(&wl->tx_lock);
697 spin_unlock_irq(&wl->irq_lock);
698 }
699
700 static void key_write(struct b43_wldev *dev,
701 u8 index, u8 algorithm, const u8 * key)
702 {
703 unsigned int i;
704 u32 offset;
705 u16 value;
706 u16 kidx;
707
708 /* Key index/algo block */
709 kidx = b43_kidx_to_fw(dev, index);
710 value = ((kidx << 4) | algorithm);
711 b43_shm_write16(dev, B43_SHM_SHARED,
712 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
713
714 /* Write the key to the Key Table Pointer offset */
715 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
716 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
717 value = key[i];
718 value |= (u16) (key[i + 1]) << 8;
719 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
720 }
721 }
722
723 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
724 {
725 u32 addrtmp[2] = { 0, 0, };
726 u8 per_sta_keys_start = 8;
727
728 if (b43_new_kidx_api(dev))
729 per_sta_keys_start = 4;
730
731 B43_WARN_ON(index < per_sta_keys_start);
732 /* We have two default TX keys and possibly two default RX keys.
733 * Physical mac 0 is mapped to physical key 4 or 8, depending
734 * on the firmware version.
735 * So we must adjust the index here.
736 */
737 index -= per_sta_keys_start;
738
739 if (addr) {
740 addrtmp[0] = addr[0];
741 addrtmp[0] |= ((u32) (addr[1]) << 8);
742 addrtmp[0] |= ((u32) (addr[2]) << 16);
743 addrtmp[0] |= ((u32) (addr[3]) << 24);
744 addrtmp[1] = addr[4];
745 addrtmp[1] |= ((u32) (addr[5]) << 8);
746 }
747
748 if (dev->dev->id.revision >= 5) {
749 /* Receive match transmitter address mechanism */
750 b43_shm_write32(dev, B43_SHM_RCMTA,
751 (index * 2) + 0, addrtmp[0]);
752 b43_shm_write16(dev, B43_SHM_RCMTA,
753 (index * 2) + 1, addrtmp[1]);
754 } else {
755 /* RXE (Receive Engine) and
756 * PSM (Programmable State Machine) mechanism
757 */
758 if (index < 8) {
759 /* TODO write to RCM 16, 19, 22 and 25 */
760 } else {
761 b43_shm_write32(dev, B43_SHM_SHARED,
762 B43_SHM_SH_PSM + (index * 6) + 0,
763 addrtmp[0]);
764 b43_shm_write16(dev, B43_SHM_SHARED,
765 B43_SHM_SH_PSM + (index * 6) + 4,
766 addrtmp[1]);
767 }
768 }
769 }
770
771 static void do_key_write(struct b43_wldev *dev,
772 u8 index, u8 algorithm,
773 const u8 * key, size_t key_len, const u8 * mac_addr)
774 {
775 u8 buf[B43_SEC_KEYSIZE] = { 0, };
776 u8 per_sta_keys_start = 8;
777
778 if (b43_new_kidx_api(dev))
779 per_sta_keys_start = 4;
780
781 B43_WARN_ON(index >= dev->max_nr_keys);
782 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
783
784 if (index >= per_sta_keys_start)
785 keymac_write(dev, index, NULL); /* First zero out mac. */
786 if (key)
787 memcpy(buf, key, key_len);
788 key_write(dev, index, algorithm, buf);
789 if (index >= per_sta_keys_start)
790 keymac_write(dev, index, mac_addr);
791
792 dev->key[index].algorithm = algorithm;
793 }
794
795 static int b43_key_write(struct b43_wldev *dev,
796 int index, u8 algorithm,
797 const u8 * key, size_t key_len,
798 const u8 * mac_addr,
799 struct ieee80211_key_conf *keyconf)
800 {
801 int i;
802 int sta_keys_start;
803
804 if (key_len > B43_SEC_KEYSIZE)
805 return -EINVAL;
806 for (i = 0; i < dev->max_nr_keys; i++) {
807 /* Check that we don't already have this key. */
808 B43_WARN_ON(dev->key[i].keyconf == keyconf);
809 }
810 if (index < 0) {
811 /* Either pairwise key or address is 00:00:00:00:00:00
812 * for transmit-only keys. Search the index. */
813 if (b43_new_kidx_api(dev))
814 sta_keys_start = 4;
815 else
816 sta_keys_start = 8;
817 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
818 if (!dev->key[i].keyconf) {
819 /* found empty */
820 index = i;
821 break;
822 }
823 }
824 if (index < 0) {
825 b43err(dev->wl, "Out of hardware key memory\n");
826 return -ENOSPC;
827 }
828 } else
829 B43_WARN_ON(index > 3);
830
831 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
832 if ((index <= 3) && !b43_new_kidx_api(dev)) {
833 /* Default RX key */
834 B43_WARN_ON(mac_addr);
835 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
836 }
837 keyconf->hw_key_idx = index;
838 dev->key[index].keyconf = keyconf;
839
840 return 0;
841 }
842
843 static int b43_key_clear(struct b43_wldev *dev, int index)
844 {
845 if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
846 return -EINVAL;
847 do_key_write(dev, index, B43_SEC_ALGO_NONE,
848 NULL, B43_SEC_KEYSIZE, NULL);
849 if ((index <= 3) && !b43_new_kidx_api(dev)) {
850 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
851 NULL, B43_SEC_KEYSIZE, NULL);
852 }
853 dev->key[index].keyconf = NULL;
854
855 return 0;
856 }
857
858 static void b43_clear_keys(struct b43_wldev *dev)
859 {
860 int i;
861
862 for (i = 0; i < dev->max_nr_keys; i++)
863 b43_key_clear(dev, i);
864 }
865
866 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
867 {
868 u32 macctl;
869 u16 ucstat;
870 bool hwps;
871 bool awake;
872 int i;
873
874 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
875 (ps_flags & B43_PS_DISABLED));
876 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
877
878 if (ps_flags & B43_PS_ENABLED) {
879 hwps = 1;
880 } else if (ps_flags & B43_PS_DISABLED) {
881 hwps = 0;
882 } else {
883 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
884 // and thus is not an AP and we are associated, set bit 25
885 }
886 if (ps_flags & B43_PS_AWAKE) {
887 awake = 1;
888 } else if (ps_flags & B43_PS_ASLEEP) {
889 awake = 0;
890 } else {
891 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
892 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
893 // successful, set bit26
894 }
895
896 /* FIXME: For now we force awake-on and hwps-off */
897 hwps = 0;
898 awake = 1;
899
900 macctl = b43_read32(dev, B43_MMIO_MACCTL);
901 if (hwps)
902 macctl |= B43_MACCTL_HWPS;
903 else
904 macctl &= ~B43_MACCTL_HWPS;
905 if (awake)
906 macctl |= B43_MACCTL_AWAKE;
907 else
908 macctl &= ~B43_MACCTL_AWAKE;
909 b43_write32(dev, B43_MMIO_MACCTL, macctl);
910 /* Commit write */
911 b43_read32(dev, B43_MMIO_MACCTL);
912 if (awake && dev->dev->id.revision >= 5) {
913 /* Wait for the microcode to wake up. */
914 for (i = 0; i < 100; i++) {
915 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
916 B43_SHM_SH_UCODESTAT);
917 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
918 break;
919 udelay(10);
920 }
921 }
922 }
923
924 /* Turn the Analog ON/OFF */
925 static void b43_switch_analog(struct b43_wldev *dev, int on)
926 {
927 b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
928 }
929
930 void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
931 {
932 u32 tmslow;
933 u32 macctl;
934
935 flags |= B43_TMSLOW_PHYCLKEN;
936 flags |= B43_TMSLOW_PHYRESET;
937 ssb_device_enable(dev->dev, flags);
938 msleep(2); /* Wait for the PLL to turn on. */
939
940 /* Now take the PHY out of Reset again */
941 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
942 tmslow |= SSB_TMSLOW_FGC;
943 tmslow &= ~B43_TMSLOW_PHYRESET;
944 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
945 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
946 msleep(1);
947 tmslow &= ~SSB_TMSLOW_FGC;
948 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
949 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
950 msleep(1);
951
952 /* Turn Analog ON */
953 b43_switch_analog(dev, 1);
954
955 macctl = b43_read32(dev, B43_MMIO_MACCTL);
956 macctl &= ~B43_MACCTL_GMODE;
957 if (flags & B43_TMSLOW_GMODE)
958 macctl |= B43_MACCTL_GMODE;
959 macctl |= B43_MACCTL_IHR_ENABLED;
960 b43_write32(dev, B43_MMIO_MACCTL, macctl);
961 }
962
963 static void handle_irq_transmit_status(struct b43_wldev *dev)
964 {
965 u32 v0, v1;
966 u16 tmp;
967 struct b43_txstatus stat;
968
969 while (1) {
970 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
971 if (!(v0 & 0x00000001))
972 break;
973 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
974
975 stat.cookie = (v0 >> 16);
976 stat.seq = (v1 & 0x0000FFFF);
977 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
978 tmp = (v0 & 0x0000FFFF);
979 stat.frame_count = ((tmp & 0xF000) >> 12);
980 stat.rts_count = ((tmp & 0x0F00) >> 8);
981 stat.supp_reason = ((tmp & 0x001C) >> 2);
982 stat.pm_indicated = !!(tmp & 0x0080);
983 stat.intermediate = !!(tmp & 0x0040);
984 stat.for_ampdu = !!(tmp & 0x0020);
985 stat.acked = !!(tmp & 0x0002);
986
987 b43_handle_txstatus(dev, &stat);
988 }
989 }
990
991 static void drain_txstatus_queue(struct b43_wldev *dev)
992 {
993 u32 dummy;
994
995 if (dev->dev->id.revision < 5)
996 return;
997 /* Read all entries from the microcode TXstatus FIFO
998 * and throw them away.
999 */
1000 while (1) {
1001 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1002 if (!(dummy & 0x00000001))
1003 break;
1004 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1005 }
1006 }
1007
1008 static u32 b43_jssi_read(struct b43_wldev *dev)
1009 {
1010 u32 val = 0;
1011
1012 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1013 val <<= 16;
1014 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1015
1016 return val;
1017 }
1018
1019 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1020 {
1021 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1022 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1023 }
1024
1025 static void b43_generate_noise_sample(struct b43_wldev *dev)
1026 {
1027 b43_jssi_write(dev, 0x7F7F7F7F);
1028 b43_write32(dev, B43_MMIO_MACCMD,
1029 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1030 }
1031
1032 static void b43_calculate_link_quality(struct b43_wldev *dev)
1033 {
1034 /* Top half of Link Quality calculation. */
1035
1036 if (dev->noisecalc.calculation_running)
1037 return;
1038 dev->noisecalc.calculation_running = 1;
1039 dev->noisecalc.nr_samples = 0;
1040
1041 b43_generate_noise_sample(dev);
1042 }
1043
1044 static void handle_irq_noise(struct b43_wldev *dev)
1045 {
1046 struct b43_phy *phy = &dev->phy;
1047 u16 tmp;
1048 u8 noise[4];
1049 u8 i, j;
1050 s32 average;
1051
1052 /* Bottom half of Link Quality calculation. */
1053
1054 /* Possible race condition: It might be possible that the user
1055 * changed to a different channel in the meantime since we
1056 * started the calculation. We ignore that fact, since it's
1057 * not really that much of a problem. The background noise is
1058 * an estimation only anyway. Slightly wrong results will get damped
1059 * by the averaging of the 8 sample rounds. Additionally the
1060 * value is shortlived. So it will be replaced by the next noise
1061 * calculation round soon. */
1062
1063 B43_WARN_ON(!dev->noisecalc.calculation_running);
1064 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1065 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1066 noise[2] == 0x7F || noise[3] == 0x7F)
1067 goto generate_new;
1068
1069 /* Get the noise samples. */
1070 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1071 i = dev->noisecalc.nr_samples;
1072 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1073 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1074 noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1075 noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1076 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1077 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1078 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1079 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1080 dev->noisecalc.nr_samples++;
1081 if (dev->noisecalc.nr_samples == 8) {
1082 /* Calculate the Link Quality by the noise samples. */
1083 average = 0;
1084 for (i = 0; i < 8; i++) {
1085 for (j = 0; j < 4; j++)
1086 average += dev->noisecalc.samples[i][j];
1087 }
1088 average /= (8 * 4);
1089 average *= 125;
1090 average += 64;
1091 average /= 128;
1092 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1093 tmp = (tmp / 128) & 0x1F;
1094 if (tmp >= 8)
1095 average += 2;
1096 else
1097 average -= 25;
1098 if (tmp == 8)
1099 average -= 72;
1100 else
1101 average -= 48;
1102
1103 dev->stats.link_noise = average;
1104 dev->noisecalc.calculation_running = 0;
1105 return;
1106 }
1107 generate_new:
1108 b43_generate_noise_sample(dev);
1109 }
1110
1111 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1112 {
1113 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
1114 ///TODO: PS TBTT
1115 } else {
1116 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1117 b43_power_saving_ctl_bits(dev, 0);
1118 }
1119 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
1120 dev->dfq_valid = 1;
1121 }
1122
1123 static void handle_irq_atim_end(struct b43_wldev *dev)
1124 {
1125 if (dev->dfq_valid) {
1126 b43_write32(dev, B43_MMIO_MACCMD,
1127 b43_read32(dev, B43_MMIO_MACCMD)
1128 | B43_MACCMD_DFQ_VALID);
1129 dev->dfq_valid = 0;
1130 }
1131 }
1132
1133 static void handle_irq_pmq(struct b43_wldev *dev)
1134 {
1135 u32 tmp;
1136
1137 //TODO: AP mode.
1138
1139 while (1) {
1140 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1141 if (!(tmp & 0x00000008))
1142 break;
1143 }
1144 /* 16bit write is odd, but correct. */
1145 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1146 }
1147
1148 static void b43_write_template_common(struct b43_wldev *dev,
1149 const u8 * data, u16 size,
1150 u16 ram_offset,
1151 u16 shm_size_offset, u8 rate)
1152 {
1153 u32 i, tmp;
1154 struct b43_plcp_hdr4 plcp;
1155
1156 plcp.data = 0;
1157 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1158 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1159 ram_offset += sizeof(u32);
1160 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1161 * So leave the first two bytes of the next write blank.
1162 */
1163 tmp = (u32) (data[0]) << 16;
1164 tmp |= (u32) (data[1]) << 24;
1165 b43_ram_write(dev, ram_offset, tmp);
1166 ram_offset += sizeof(u32);
1167 for (i = 2; i < size; i += sizeof(u32)) {
1168 tmp = (u32) (data[i + 0]);
1169 if (i + 1 < size)
1170 tmp |= (u32) (data[i + 1]) << 8;
1171 if (i + 2 < size)
1172 tmp |= (u32) (data[i + 2]) << 16;
1173 if (i + 3 < size)
1174 tmp |= (u32) (data[i + 3]) << 24;
1175 b43_ram_write(dev, ram_offset + i - 2, tmp);
1176 }
1177 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1178 size + sizeof(struct b43_plcp_hdr6));
1179 }
1180
1181 static void b43_write_beacon_template(struct b43_wldev *dev,
1182 u16 ram_offset,
1183 u16 shm_size_offset, u8 rate)
1184 {
1185 unsigned int i, len, variable_len;
1186 const struct ieee80211_mgmt *bcn;
1187 const u8 *ie;
1188 bool tim_found = 0;
1189
1190 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1191 len = min((size_t) dev->wl->current_beacon->len,
1192 0x200 - sizeof(struct b43_plcp_hdr6));
1193
1194 b43_write_template_common(dev, (const u8 *)bcn,
1195 len, ram_offset, shm_size_offset, rate);
1196
1197 /* Find the position of the TIM and the DTIM_period value
1198 * and write them to SHM. */
1199 ie = bcn->u.beacon.variable;
1200 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1201 for (i = 0; i < variable_len - 2; ) {
1202 uint8_t ie_id, ie_len;
1203
1204 ie_id = ie[i];
1205 ie_len = ie[i + 1];
1206 if (ie_id == 5) {
1207 u16 tim_position;
1208 u16 dtim_period;
1209 /* This is the TIM Information Element */
1210
1211 /* Check whether the ie_len is in the beacon data range. */
1212 if (variable_len < ie_len + 2 + i)
1213 break;
1214 /* A valid TIM is at least 4 bytes long. */
1215 if (ie_len < 4)
1216 break;
1217 tim_found = 1;
1218
1219 tim_position = sizeof(struct b43_plcp_hdr6);
1220 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1221 tim_position += i;
1222
1223 dtim_period = ie[i + 3];
1224
1225 b43_shm_write16(dev, B43_SHM_SHARED,
1226 B43_SHM_SH_TIMBPOS, tim_position);
1227 b43_shm_write16(dev, B43_SHM_SHARED,
1228 B43_SHM_SH_DTIMPER, dtim_period);
1229 break;
1230 }
1231 i += ie_len + 2;
1232 }
1233 if (!tim_found) {
1234 b43warn(dev->wl, "Did not find a valid TIM IE in "
1235 "the beacon template packet. AP or IBSS operation "
1236 "may be broken.\n");
1237 }
1238 }
1239
1240 static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
1241 u16 shm_offset, u16 size, u8 rate)
1242 {
1243 struct b43_plcp_hdr4 plcp;
1244 u32 tmp;
1245 __le16 dur;
1246
1247 plcp.data = 0;
1248 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1249 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1250 dev->wl->vif, size,
1251 B43_RATE_TO_BASE100KBPS(rate));
1252 /* Write PLCP in two parts and timing for packet transfer */
1253 tmp = le32_to_cpu(plcp.data);
1254 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1255 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1256 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1257 }
1258
1259 /* Instead of using custom probe response template, this function
1260 * just patches custom beacon template by:
1261 * 1) Changing packet type
1262 * 2) Patching duration field
1263 * 3) Stripping TIM
1264 */
1265 static const u8 * b43_generate_probe_resp(struct b43_wldev *dev,
1266 u16 *dest_size, u8 rate)
1267 {
1268 const u8 *src_data;
1269 u8 *dest_data;
1270 u16 src_size, elem_size, src_pos, dest_pos;
1271 __le16 dur;
1272 struct ieee80211_hdr *hdr;
1273 size_t ie_start;
1274
1275 src_size = dev->wl->current_beacon->len;
1276 src_data = (const u8 *)dev->wl->current_beacon->data;
1277
1278 /* Get the start offset of the variable IEs in the packet. */
1279 ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1280 B43_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt, u.beacon.variable));
1281
1282 if (B43_WARN_ON(src_size < ie_start))
1283 return NULL;
1284
1285 dest_data = kmalloc(src_size, GFP_ATOMIC);
1286 if (unlikely(!dest_data))
1287 return NULL;
1288
1289 /* Copy the static data and all Information Elements, except the TIM. */
1290 memcpy(dest_data, src_data, ie_start);
1291 src_pos = ie_start;
1292 dest_pos = ie_start;
1293 for ( ; src_pos < src_size - 2; src_pos += elem_size) {
1294 elem_size = src_data[src_pos + 1] + 2;
1295 if (src_data[src_pos] == 5) {
1296 /* This is the TIM. */
1297 continue;
1298 }
1299 memcpy(dest_data + dest_pos, src_data + src_pos,
1300 elem_size);
1301 dest_pos += elem_size;
1302 }
1303 *dest_size = dest_pos;
1304 hdr = (struct ieee80211_hdr *)dest_data;
1305
1306 /* Set the frame control. */
1307 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1308 IEEE80211_STYPE_PROBE_RESP);
1309 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1310 dev->wl->vif, *dest_size,
1311 B43_RATE_TO_BASE100KBPS(rate));
1312 hdr->duration_id = dur;
1313
1314 return dest_data;
1315 }
1316
1317 static void b43_write_probe_resp_template(struct b43_wldev *dev,
1318 u16 ram_offset,
1319 u16 shm_size_offset, u8 rate)
1320 {
1321 const u8 *probe_resp_data;
1322 u16 size;
1323
1324 size = dev->wl->current_beacon->len;
1325 probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1326 if (unlikely(!probe_resp_data))
1327 return;
1328
1329 /* Looks like PLCP headers plus packet timings are stored for
1330 * all possible basic rates
1331 */
1332 b43_write_probe_resp_plcp(dev, 0x31A, size, B43_CCK_RATE_1MB);
1333 b43_write_probe_resp_plcp(dev, 0x32C, size, B43_CCK_RATE_2MB);
1334 b43_write_probe_resp_plcp(dev, 0x33E, size, B43_CCK_RATE_5MB);
1335 b43_write_probe_resp_plcp(dev, 0x350, size, B43_CCK_RATE_11MB);
1336
1337 size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1338 b43_write_template_common(dev, probe_resp_data,
1339 size, ram_offset, shm_size_offset, rate);
1340 kfree(probe_resp_data);
1341 }
1342
1343 /* Asynchronously update the packet templates in template RAM.
1344 * Locking: Requires wl->irq_lock to be locked. */
1345 static void b43_update_templates(struct b43_wl *wl, struct sk_buff *beacon)
1346 {
1347 /* This is the top half of the ansynchronous beacon update.
1348 * The bottom half is the beacon IRQ.
1349 * Beacon update must be asynchronous to avoid sending an
1350 * invalid beacon. This can happen for example, if the firmware
1351 * transmits a beacon while we are updating it. */
1352
1353 if (wl->current_beacon)
1354 dev_kfree_skb_any(wl->current_beacon);
1355 wl->current_beacon = beacon;
1356 wl->beacon0_uploaded = 0;
1357 wl->beacon1_uploaded = 0;
1358 }
1359
1360 static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len)
1361 {
1362 u32 tmp;
1363 u16 i, len;
1364
1365 len = min((u16) ssid_len, (u16) 0x100);
1366 for (i = 0; i < len; i += sizeof(u32)) {
1367 tmp = (u32) (ssid[i + 0]);
1368 if (i + 1 < len)
1369 tmp |= (u32) (ssid[i + 1]) << 8;
1370 if (i + 2 < len)
1371 tmp |= (u32) (ssid[i + 2]) << 16;
1372 if (i + 3 < len)
1373 tmp |= (u32) (ssid[i + 3]) << 24;
1374 b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp);
1375 }
1376 b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len);
1377 }
1378
1379 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1380 {
1381 b43_time_lock(dev);
1382 if (dev->dev->id.revision >= 3) {
1383 b43_write32(dev, 0x188, (beacon_int << 16));
1384 } else {
1385 b43_write16(dev, 0x606, (beacon_int >> 6));
1386 b43_write16(dev, 0x610, beacon_int);
1387 }
1388 b43_time_unlock(dev);
1389 }
1390
1391 static void handle_irq_beacon(struct b43_wldev *dev)
1392 {
1393 struct b43_wl *wl = dev->wl;
1394 u32 cmd;
1395
1396 if (!b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
1397 return;
1398
1399 /* This is the bottom half of the asynchronous beacon update. */
1400
1401 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1402 if (!(cmd & B43_MACCMD_BEACON0_VALID)) {
1403 if (!wl->beacon0_uploaded) {
1404 b43_write_beacon_template(dev, 0x68, 0x18,
1405 B43_CCK_RATE_1MB);
1406 b43_write_probe_resp_template(dev, 0x268, 0x4A,
1407 B43_CCK_RATE_11MB);
1408 wl->beacon0_uploaded = 1;
1409 }
1410 cmd |= B43_MACCMD_BEACON0_VALID;
1411 }
1412 if (!(cmd & B43_MACCMD_BEACON1_VALID)) {
1413 if (!wl->beacon1_uploaded) {
1414 b43_write_beacon_template(dev, 0x468, 0x1A,
1415 B43_CCK_RATE_1MB);
1416 wl->beacon1_uploaded = 1;
1417 }
1418 cmd |= B43_MACCMD_BEACON1_VALID;
1419 }
1420 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1421 }
1422
1423 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1424 {
1425 //TODO
1426 }
1427
1428 /* Interrupt handler bottom-half */
1429 static void b43_interrupt_tasklet(struct b43_wldev *dev)
1430 {
1431 u32 reason;
1432 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1433 u32 merged_dma_reason = 0;
1434 int i;
1435 unsigned long flags;
1436
1437 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1438
1439 B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1440
1441 reason = dev->irq_reason;
1442 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1443 dma_reason[i] = dev->dma_reason[i];
1444 merged_dma_reason |= dma_reason[i];
1445 }
1446
1447 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1448 b43err(dev->wl, "MAC transmission error\n");
1449
1450 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1451 b43err(dev->wl, "PHY transmission error\n");
1452 rmb();
1453 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1454 atomic_set(&dev->phy.txerr_cnt,
1455 B43_PHY_TX_BADNESS_LIMIT);
1456 b43err(dev->wl, "Too many PHY TX errors, "
1457 "restarting the controller\n");
1458 b43_controller_restart(dev, "PHY TX errors");
1459 }
1460 }
1461
1462 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1463 B43_DMAIRQ_NONFATALMASK))) {
1464 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1465 b43err(dev->wl, "Fatal DMA error: "
1466 "0x%08X, 0x%08X, 0x%08X, "
1467 "0x%08X, 0x%08X, 0x%08X\n",
1468 dma_reason[0], dma_reason[1],
1469 dma_reason[2], dma_reason[3],
1470 dma_reason[4], dma_reason[5]);
1471 b43_controller_restart(dev, "DMA error");
1472 mmiowb();
1473 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1474 return;
1475 }
1476 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1477 b43err(dev->wl, "DMA error: "
1478 "0x%08X, 0x%08X, 0x%08X, "
1479 "0x%08X, 0x%08X, 0x%08X\n",
1480 dma_reason[0], dma_reason[1],
1481 dma_reason[2], dma_reason[3],
1482 dma_reason[4], dma_reason[5]);
1483 }
1484 }
1485
1486 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1487 handle_irq_ucode_debug(dev);
1488 if (reason & B43_IRQ_TBTT_INDI)
1489 handle_irq_tbtt_indication(dev);
1490 if (reason & B43_IRQ_ATIM_END)
1491 handle_irq_atim_end(dev);
1492 if (reason & B43_IRQ_BEACON)
1493 handle_irq_beacon(dev);
1494 if (reason & B43_IRQ_PMQ)
1495 handle_irq_pmq(dev);
1496 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1497 ;/* TODO */
1498 if (reason & B43_IRQ_NOISESAMPLE_OK)
1499 handle_irq_noise(dev);
1500
1501 /* Check the DMA reason registers for received data. */
1502 if (dma_reason[0] & B43_DMAIRQ_RX_DONE)
1503 b43_dma_rx(dev->dma.rx_ring0);
1504 if (dma_reason[3] & B43_DMAIRQ_RX_DONE)
1505 b43_dma_rx(dev->dma.rx_ring3);
1506 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1507 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1508 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1509 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1510
1511 if (reason & B43_IRQ_TX_OK)
1512 handle_irq_transmit_status(dev);
1513
1514 b43_interrupt_enable(dev, dev->irq_savedstate);
1515 mmiowb();
1516 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1517 }
1518
1519 static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1520 {
1521 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1522
1523 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1524 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1525 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1526 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1527 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1528 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1529 }
1530
1531 /* Interrupt handler top-half */
1532 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1533 {
1534 irqreturn_t ret = IRQ_NONE;
1535 struct b43_wldev *dev = dev_id;
1536 u32 reason;
1537
1538 if (!dev)
1539 return IRQ_NONE;
1540
1541 spin_lock(&dev->wl->irq_lock);
1542
1543 if (b43_status(dev) < B43_STAT_STARTED)
1544 goto out;
1545 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1546 if (reason == 0xffffffff) /* shared IRQ */
1547 goto out;
1548 ret = IRQ_HANDLED;
1549 reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1550 if (!reason)
1551 goto out;
1552
1553 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1554 & 0x0001DC00;
1555 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1556 & 0x0000DC00;
1557 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1558 & 0x0000DC00;
1559 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1560 & 0x0001DC00;
1561 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1562 & 0x0000DC00;
1563 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1564 & 0x0000DC00;
1565
1566 b43_interrupt_ack(dev, reason);
1567 /* disable all IRQs. They are enabled again in the bottom half. */
1568 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
1569 /* save the reason code and call our bottom half. */
1570 dev->irq_reason = reason;
1571 tasklet_schedule(&dev->isr_tasklet);
1572 out:
1573 mmiowb();
1574 spin_unlock(&dev->wl->irq_lock);
1575
1576 return ret;
1577 }
1578
1579 static void do_release_fw(struct b43_firmware_file *fw)
1580 {
1581 release_firmware(fw->data);
1582 fw->data = NULL;
1583 fw->filename = NULL;
1584 }
1585
1586 static void b43_release_firmware(struct b43_wldev *dev)
1587 {
1588 do_release_fw(&dev->fw.ucode);
1589 do_release_fw(&dev->fw.pcm);
1590 do_release_fw(&dev->fw.initvals);
1591 do_release_fw(&dev->fw.initvals_band);
1592 }
1593
1594 static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
1595 {
1596 const char *text;
1597
1598 text = "You must go to "
1599 "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware "
1600 "and download the latest firmware (version 4).\n";
1601 if (error)
1602 b43err(wl, text);
1603 else
1604 b43warn(wl, text);
1605 }
1606
1607 static int do_request_fw(struct b43_wldev *dev,
1608 const char *name,
1609 struct b43_firmware_file *fw)
1610 {
1611 char path[sizeof(modparam_fwpostfix) + 32];
1612 const struct firmware *blob;
1613 struct b43_fw_header *hdr;
1614 u32 size;
1615 int err;
1616
1617 if (!name) {
1618 /* Don't fetch anything. Free possibly cached firmware. */
1619 do_release_fw(fw);
1620 return 0;
1621 }
1622 if (fw->filename) {
1623 if (strcmp(fw->filename, name) == 0)
1624 return 0; /* Already have this fw. */
1625 /* Free the cached firmware first. */
1626 do_release_fw(fw);
1627 }
1628
1629 snprintf(path, ARRAY_SIZE(path),
1630 "b43%s/%s.fw",
1631 modparam_fwpostfix, name);
1632 err = request_firmware(&blob, path, dev->dev->dev);
1633 if (err) {
1634 b43err(dev->wl, "Firmware file \"%s\" not found "
1635 "or load failed.\n", path);
1636 return err;
1637 }
1638 if (blob->size < sizeof(struct b43_fw_header))
1639 goto err_format;
1640 hdr = (struct b43_fw_header *)(blob->data);
1641 switch (hdr->type) {
1642 case B43_FW_TYPE_UCODE:
1643 case B43_FW_TYPE_PCM:
1644 size = be32_to_cpu(hdr->size);
1645 if (size != blob->size - sizeof(struct b43_fw_header))
1646 goto err_format;
1647 /* fallthrough */
1648 case B43_FW_TYPE_IV:
1649 if (hdr->ver != 1)
1650 goto err_format;
1651 break;
1652 default:
1653 goto err_format;
1654 }
1655
1656 fw->data = blob;
1657 fw->filename = name;
1658
1659 return 0;
1660
1661 err_format:
1662 b43err(dev->wl, "Firmware file \"%s\" format error.\n", path);
1663 release_firmware(blob);
1664
1665 return -EPROTO;
1666 }
1667
1668 static int b43_request_firmware(struct b43_wldev *dev)
1669 {
1670 struct b43_firmware *fw = &dev->fw;
1671 const u8 rev = dev->dev->id.revision;
1672 const char *filename;
1673 u32 tmshigh;
1674 int err;
1675
1676 /* Get microcode */
1677 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
1678 if ((rev >= 5) && (rev <= 10))
1679 filename = "ucode5";
1680 else if ((rev >= 11) && (rev <= 12))
1681 filename = "ucode11";
1682 else if (rev >= 13)
1683 filename = "ucode13";
1684 else
1685 goto err_no_ucode;
1686 err = do_request_fw(dev, filename, &fw->ucode);
1687 if (err)
1688 goto err_load;
1689
1690 /* Get PCM code */
1691 if ((rev >= 5) && (rev <= 10))
1692 filename = "pcm5";
1693 else if (rev >= 11)
1694 filename = NULL;
1695 else
1696 goto err_no_pcm;
1697 err = do_request_fw(dev, filename, &fw->pcm);
1698 if (err)
1699 goto err_load;
1700
1701 /* Get initvals */
1702 switch (dev->phy.type) {
1703 case B43_PHYTYPE_A:
1704 if ((rev >= 5) && (rev <= 10)) {
1705 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
1706 filename = "a0g1initvals5";
1707 else
1708 filename = "a0g0initvals5";
1709 } else
1710 goto err_no_initvals;
1711 break;
1712 case B43_PHYTYPE_G:
1713 if ((rev >= 5) && (rev <= 10))
1714 filename = "b0g0initvals5";
1715 else if (rev >= 13)
1716 filename = "lp0initvals13";
1717 else
1718 goto err_no_initvals;
1719 break;
1720 case B43_PHYTYPE_N:
1721 if ((rev >= 11) && (rev <= 12))
1722 filename = "n0initvals11";
1723 else
1724 goto err_no_initvals;
1725 break;
1726 default:
1727 goto err_no_initvals;
1728 }
1729 err = do_request_fw(dev, filename, &fw->initvals);
1730 if (err)
1731 goto err_load;
1732
1733 /* Get bandswitch initvals */
1734 switch (dev->phy.type) {
1735 case B43_PHYTYPE_A:
1736 if ((rev >= 5) && (rev <= 10)) {
1737 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
1738 filename = "a0g1bsinitvals5";
1739 else
1740 filename = "a0g0bsinitvals5";
1741 } else if (rev >= 11)
1742 filename = NULL;
1743 else
1744 goto err_no_initvals;
1745 break;
1746 case B43_PHYTYPE_G:
1747 if ((rev >= 5) && (rev <= 10))
1748 filename = "b0g0bsinitvals5";
1749 else if (rev >= 11)
1750 filename = NULL;
1751 else
1752 goto err_no_initvals;
1753 break;
1754 case B43_PHYTYPE_N:
1755 if ((rev >= 11) && (rev <= 12))
1756 filename = "n0bsinitvals11";
1757 else
1758 goto err_no_initvals;
1759 break;
1760 default:
1761 goto err_no_initvals;
1762 }
1763 err = do_request_fw(dev, filename, &fw->initvals_band);
1764 if (err)
1765 goto err_load;
1766
1767 return 0;
1768
1769 err_load:
1770 b43_print_fw_helptext(dev->wl, 1);
1771 goto error;
1772
1773 err_no_ucode:
1774 err = -ENODEV;
1775 b43err(dev->wl, "No microcode available for core rev %u\n", rev);
1776 goto error;
1777
1778 err_no_pcm:
1779 err = -ENODEV;
1780 b43err(dev->wl, "No PCM available for core rev %u\n", rev);
1781 goto error;
1782
1783 err_no_initvals:
1784 err = -ENODEV;
1785 b43err(dev->wl, "No Initial Values firmware file for PHY %u, "
1786 "core rev %u\n", dev->phy.type, rev);
1787 goto error;
1788
1789 error:
1790 b43_release_firmware(dev);
1791 return err;
1792 }
1793
1794 static int b43_upload_microcode(struct b43_wldev *dev)
1795 {
1796 const size_t hdr_len = sizeof(struct b43_fw_header);
1797 const __be32 *data;
1798 unsigned int i, len;
1799 u16 fwrev, fwpatch, fwdate, fwtime;
1800 u32 tmp, macctl;
1801 int err = 0;
1802
1803 /* Jump the microcode PSM to offset 0 */
1804 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1805 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
1806 macctl |= B43_MACCTL_PSM_JMP0;
1807 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1808 /* Zero out all microcode PSM registers and shared memory. */
1809 for (i = 0; i < 64; i++)
1810 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
1811 for (i = 0; i < 4096; i += 2)
1812 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
1813
1814 /* Upload Microcode. */
1815 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
1816 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
1817 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
1818 for (i = 0; i < len; i++) {
1819 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1820 udelay(10);
1821 }
1822
1823 if (dev->fw.pcm.data) {
1824 /* Upload PCM data. */
1825 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
1826 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
1827 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
1828 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
1829 /* No need for autoinc bit in SHM_HW */
1830 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
1831 for (i = 0; i < len; i++) {
1832 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1833 udelay(10);
1834 }
1835 }
1836
1837 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1838
1839 /* Start the microcode PSM */
1840 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1841 macctl &= ~B43_MACCTL_PSM_JMP0;
1842 macctl |= B43_MACCTL_PSM_RUN;
1843 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1844
1845 /* Wait for the microcode to load and respond */
1846 i = 0;
1847 while (1) {
1848 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1849 if (tmp == B43_IRQ_MAC_SUSPENDED)
1850 break;
1851 i++;
1852 if (i >= 20) {
1853 b43err(dev->wl, "Microcode not responding\n");
1854 b43_print_fw_helptext(dev->wl, 1);
1855 err = -ENODEV;
1856 goto error;
1857 }
1858 msleep_interruptible(50);
1859 if (signal_pending(current)) {
1860 err = -EINTR;
1861 goto error;
1862 }
1863 }
1864 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
1865
1866 /* Get and check the revisions. */
1867 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
1868 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
1869 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
1870 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
1871
1872 if (fwrev <= 0x128) {
1873 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
1874 "binary drivers older than version 4.x is unsupported. "
1875 "You must upgrade your firmware files.\n");
1876 b43_print_fw_helptext(dev->wl, 1);
1877 err = -EOPNOTSUPP;
1878 goto error;
1879 }
1880 b43info(dev->wl, "Loading firmware version %u.%u "
1881 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
1882 fwrev, fwpatch,
1883 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1884 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
1885
1886 dev->fw.rev = fwrev;
1887 dev->fw.patch = fwpatch;
1888
1889 if (b43_is_old_txhdr_format(dev)) {
1890 b43warn(dev->wl, "You are using an old firmware image. "
1891 "Support for old firmware will be removed in July 2008.\n");
1892 b43_print_fw_helptext(dev->wl, 0);
1893 }
1894
1895 return 0;
1896
1897 error:
1898 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1899 macctl &= ~B43_MACCTL_PSM_RUN;
1900 macctl |= B43_MACCTL_PSM_JMP0;
1901 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1902
1903 return err;
1904 }
1905
1906 static int b43_write_initvals(struct b43_wldev *dev,
1907 const struct b43_iv *ivals,
1908 size_t count,
1909 size_t array_size)
1910 {
1911 const struct b43_iv *iv;
1912 u16 offset;
1913 size_t i;
1914 bool bit32;
1915
1916 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
1917 iv = ivals;
1918 for (i = 0; i < count; i++) {
1919 if (array_size < sizeof(iv->offset_size))
1920 goto err_format;
1921 array_size -= sizeof(iv->offset_size);
1922 offset = be16_to_cpu(iv->offset_size);
1923 bit32 = !!(offset & B43_IV_32BIT);
1924 offset &= B43_IV_OFFSET_MASK;
1925 if (offset >= 0x1000)
1926 goto err_format;
1927 if (bit32) {
1928 u32 value;
1929
1930 if (array_size < sizeof(iv->data.d32))
1931 goto err_format;
1932 array_size -= sizeof(iv->data.d32);
1933
1934 value = be32_to_cpu(get_unaligned(&iv->data.d32));
1935 b43_write32(dev, offset, value);
1936
1937 iv = (const struct b43_iv *)((const uint8_t *)iv +
1938 sizeof(__be16) +
1939 sizeof(__be32));
1940 } else {
1941 u16 value;
1942
1943 if (array_size < sizeof(iv->data.d16))
1944 goto err_format;
1945 array_size -= sizeof(iv->data.d16);
1946
1947 value = be16_to_cpu(iv->data.d16);
1948 b43_write16(dev, offset, value);
1949
1950 iv = (const struct b43_iv *)((const uint8_t *)iv +
1951 sizeof(__be16) +
1952 sizeof(__be16));
1953 }
1954 }
1955 if (array_size)
1956 goto err_format;
1957
1958 return 0;
1959
1960 err_format:
1961 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
1962 b43_print_fw_helptext(dev->wl, 1);
1963
1964 return -EPROTO;
1965 }
1966
1967 static int b43_upload_initvals(struct b43_wldev *dev)
1968 {
1969 const size_t hdr_len = sizeof(struct b43_fw_header);
1970 const struct b43_fw_header *hdr;
1971 struct b43_firmware *fw = &dev->fw;
1972 const struct b43_iv *ivals;
1973 size_t count;
1974 int err;
1975
1976 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
1977 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
1978 count = be32_to_cpu(hdr->size);
1979 err = b43_write_initvals(dev, ivals, count,
1980 fw->initvals.data->size - hdr_len);
1981 if (err)
1982 goto out;
1983 if (fw->initvals_band.data) {
1984 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
1985 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
1986 count = be32_to_cpu(hdr->size);
1987 err = b43_write_initvals(dev, ivals, count,
1988 fw->initvals_band.data->size - hdr_len);
1989 if (err)
1990 goto out;
1991 }
1992 out:
1993
1994 return err;
1995 }
1996
1997 /* Initialize the GPIOs
1998 * http://bcm-specs.sipsolutions.net/GPIO
1999 */
2000 static int b43_gpio_init(struct b43_wldev *dev)
2001 {
2002 struct ssb_bus *bus = dev->dev->bus;
2003 struct ssb_device *gpiodev, *pcidev = NULL;
2004 u32 mask, set;
2005
2006 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2007 & ~B43_MACCTL_GPOUTSMSK);
2008
2009 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
2010 | 0x000F);
2011
2012 mask = 0x0000001F;
2013 set = 0x0000000F;
2014 if (dev->dev->bus->chip_id == 0x4301) {
2015 mask |= 0x0060;
2016 set |= 0x0060;
2017 }
2018 if (0 /* FIXME: conditional unknown */ ) {
2019 b43_write16(dev, B43_MMIO_GPIO_MASK,
2020 b43_read16(dev, B43_MMIO_GPIO_MASK)
2021 | 0x0100);
2022 mask |= 0x0180;
2023 set |= 0x0180;
2024 }
2025 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
2026 b43_write16(dev, B43_MMIO_GPIO_MASK,
2027 b43_read16(dev, B43_MMIO_GPIO_MASK)
2028 | 0x0200);
2029 mask |= 0x0200;
2030 set |= 0x0200;
2031 }
2032 if (dev->dev->id.revision >= 2)
2033 mask |= 0x0010; /* FIXME: This is redundant. */
2034
2035 #ifdef CONFIG_SSB_DRIVER_PCICORE
2036 pcidev = bus->pcicore.dev;
2037 #endif
2038 gpiodev = bus->chipco.dev ? : pcidev;
2039 if (!gpiodev)
2040 return 0;
2041 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2042 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2043 & mask) | set);
2044
2045 return 0;
2046 }
2047
2048 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2049 static void b43_gpio_cleanup(struct b43_wldev *dev)
2050 {
2051 struct ssb_bus *bus = dev->dev->bus;
2052 struct ssb_device *gpiodev, *pcidev = NULL;
2053
2054 #ifdef CONFIG_SSB_DRIVER_PCICORE
2055 pcidev = bus->pcicore.dev;
2056 #endif
2057 gpiodev = bus->chipco.dev ? : pcidev;
2058 if (!gpiodev)
2059 return;
2060 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2061 }
2062
2063 /* http://bcm-specs.sipsolutions.net/EnableMac */
2064 void b43_mac_enable(struct b43_wldev *dev)
2065 {
2066 dev->mac_suspended--;
2067 B43_WARN_ON(dev->mac_suspended < 0);
2068 if (dev->mac_suspended == 0) {
2069 b43_write32(dev, B43_MMIO_MACCTL,
2070 b43_read32(dev, B43_MMIO_MACCTL)
2071 | B43_MACCTL_ENABLED);
2072 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2073 B43_IRQ_MAC_SUSPENDED);
2074 /* Commit writes */
2075 b43_read32(dev, B43_MMIO_MACCTL);
2076 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2077 b43_power_saving_ctl_bits(dev, 0);
2078
2079 /* Re-enable IRQs. */
2080 spin_lock_irq(&dev->wl->irq_lock);
2081 b43_interrupt_enable(dev, dev->irq_savedstate);
2082 spin_unlock_irq(&dev->wl->irq_lock);
2083 }
2084 }
2085
2086 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2087 void b43_mac_suspend(struct b43_wldev *dev)
2088 {
2089 int i;
2090 u32 tmp;
2091
2092 might_sleep();
2093 B43_WARN_ON(dev->mac_suspended < 0);
2094
2095 if (dev->mac_suspended == 0) {
2096 /* Mask IRQs before suspending MAC. Otherwise
2097 * the MAC stays busy and won't suspend. */
2098 spin_lock_irq(&dev->wl->irq_lock);
2099 tmp = b43_interrupt_disable(dev, B43_IRQ_ALL);
2100 spin_unlock_irq(&dev->wl->irq_lock);
2101 b43_synchronize_irq(dev);
2102 dev->irq_savedstate = tmp;
2103
2104 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2105 b43_write32(dev, B43_MMIO_MACCTL,
2106 b43_read32(dev, B43_MMIO_MACCTL)
2107 & ~B43_MACCTL_ENABLED);
2108 /* force pci to flush the write */
2109 b43_read32(dev, B43_MMIO_MACCTL);
2110 for (i = 40; i; i--) {
2111 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2112 if (tmp & B43_IRQ_MAC_SUSPENDED)
2113 goto out;
2114 msleep(1);
2115 }
2116 b43err(dev->wl, "MAC suspend failed\n");
2117 }
2118 out:
2119 dev->mac_suspended++;
2120 }
2121
2122 static void b43_adjust_opmode(struct b43_wldev *dev)
2123 {
2124 struct b43_wl *wl = dev->wl;
2125 u32 ctl;
2126 u16 cfp_pretbtt;
2127
2128 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2129 /* Reset status to STA infrastructure mode. */
2130 ctl &= ~B43_MACCTL_AP;
2131 ctl &= ~B43_MACCTL_KEEP_CTL;
2132 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2133 ctl &= ~B43_MACCTL_KEEP_BAD;
2134 ctl &= ~B43_MACCTL_PROMISC;
2135 ctl &= ~B43_MACCTL_BEACPROMISC;
2136 ctl |= B43_MACCTL_INFRA;
2137
2138 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2139 ctl |= B43_MACCTL_AP;
2140 else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
2141 ctl &= ~B43_MACCTL_INFRA;
2142
2143 if (wl->filter_flags & FIF_CONTROL)
2144 ctl |= B43_MACCTL_KEEP_CTL;
2145 if (wl->filter_flags & FIF_FCSFAIL)
2146 ctl |= B43_MACCTL_KEEP_BAD;
2147 if (wl->filter_flags & FIF_PLCPFAIL)
2148 ctl |= B43_MACCTL_KEEP_BADPLCP;
2149 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2150 ctl |= B43_MACCTL_PROMISC;
2151 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2152 ctl |= B43_MACCTL_BEACPROMISC;
2153
2154 /* Workaround: On old hardware the HW-MAC-address-filter
2155 * doesn't work properly, so always run promisc in filter
2156 * it in software. */
2157 if (dev->dev->id.revision <= 4)
2158 ctl |= B43_MACCTL_PROMISC;
2159
2160 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2161
2162 cfp_pretbtt = 2;
2163 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2164 if (dev->dev->bus->chip_id == 0x4306 &&
2165 dev->dev->bus->chip_rev == 3)
2166 cfp_pretbtt = 100;
2167 else
2168 cfp_pretbtt = 50;
2169 }
2170 b43_write16(dev, 0x612, cfp_pretbtt);
2171 }
2172
2173 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2174 {
2175 u16 offset;
2176
2177 if (is_ofdm) {
2178 offset = 0x480;
2179 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2180 } else {
2181 offset = 0x4C0;
2182 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2183 }
2184 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2185 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2186 }
2187
2188 static void b43_rate_memory_init(struct b43_wldev *dev)
2189 {
2190 switch (dev->phy.type) {
2191 case B43_PHYTYPE_A:
2192 case B43_PHYTYPE_G:
2193 case B43_PHYTYPE_N:
2194 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2195 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2196 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2197 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2198 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2199 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2200 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2201 if (dev->phy.type == B43_PHYTYPE_A)
2202 break;
2203 /* fallthrough */
2204 case B43_PHYTYPE_B:
2205 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2206 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2207 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2208 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2209 break;
2210 default:
2211 B43_WARN_ON(1);
2212 }
2213 }
2214
2215 /* Set the TX-Antenna for management frames sent by firmware. */
2216 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2217 {
2218 u16 ant = 0;
2219 u16 tmp;
2220
2221 switch (antenna) {
2222 case B43_ANTENNA0:
2223 ant |= B43_TXH_PHY_ANT0;
2224 break;
2225 case B43_ANTENNA1:
2226 ant |= B43_TXH_PHY_ANT1;
2227 break;
2228 case B43_ANTENNA2:
2229 ant |= B43_TXH_PHY_ANT2;
2230 break;
2231 case B43_ANTENNA3:
2232 ant |= B43_TXH_PHY_ANT3;
2233 break;
2234 case B43_ANTENNA_AUTO:
2235 ant |= B43_TXH_PHY_ANT01AUTO;
2236 break;
2237 default:
2238 B43_WARN_ON(1);
2239 }
2240
2241 /* FIXME We also need to set the other flags of the PHY control field somewhere. */
2242
2243 /* For Beacons */
2244 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
2245 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2246 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, tmp);
2247 /* For ACK/CTS */
2248 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2249 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2250 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2251 /* For Probe Resposes */
2252 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2253 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2254 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2255 }
2256
2257 /* This is the opposite of b43_chip_init() */
2258 static void b43_chip_exit(struct b43_wldev *dev)
2259 {
2260 b43_radio_turn_off(dev, 1);
2261 b43_gpio_cleanup(dev);
2262 /* firmware is released later */
2263 }
2264
2265 /* Initialize the chip
2266 * http://bcm-specs.sipsolutions.net/ChipInit
2267 */
2268 static int b43_chip_init(struct b43_wldev *dev)
2269 {
2270 struct b43_phy *phy = &dev->phy;
2271 int err, tmp;
2272 u32 value32, macctl;
2273 u16 value16;
2274
2275 /* Initialize the MAC control */
2276 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
2277 if (dev->phy.gmode)
2278 macctl |= B43_MACCTL_GMODE;
2279 macctl |= B43_MACCTL_INFRA;
2280 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2281
2282 err = b43_request_firmware(dev);
2283 if (err)
2284 goto out;
2285 err = b43_upload_microcode(dev);
2286 if (err)
2287 goto out; /* firmware is released later */
2288
2289 err = b43_gpio_init(dev);
2290 if (err)
2291 goto out; /* firmware is released later */
2292
2293 err = b43_upload_initvals(dev);
2294 if (err)
2295 goto err_gpio_clean;
2296 b43_radio_turn_on(dev);
2297
2298 b43_write16(dev, 0x03E6, 0x0000);
2299 err = b43_phy_init(dev);
2300 if (err)
2301 goto err_radio_off;
2302
2303 /* Select initial Interference Mitigation. */
2304 tmp = phy->interfmode;
2305 phy->interfmode = B43_INTERFMODE_NONE;
2306 b43_radio_set_interference_mitigation(dev, tmp);
2307
2308 b43_set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2309 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2310
2311 if (phy->type == B43_PHYTYPE_B) {
2312 value16 = b43_read16(dev, 0x005E);
2313 value16 |= 0x0004;
2314 b43_write16(dev, 0x005E, value16);
2315 }
2316 b43_write32(dev, 0x0100, 0x01000000);
2317 if (dev->dev->id.revision < 5)
2318 b43_write32(dev, 0x010C, 0x01000000);
2319
2320 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2321 & ~B43_MACCTL_INFRA);
2322 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2323 | B43_MACCTL_INFRA);
2324
2325 /* Probe Response Timeout value */
2326 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2327 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2328
2329 /* Initially set the wireless operation mode. */
2330 b43_adjust_opmode(dev);
2331
2332 if (dev->dev->id.revision < 3) {
2333 b43_write16(dev, 0x060E, 0x0000);
2334 b43_write16(dev, 0x0610, 0x8000);
2335 b43_write16(dev, 0x0604, 0x0000);
2336 b43_write16(dev, 0x0606, 0x0200);
2337 } else {
2338 b43_write32(dev, 0x0188, 0x80000000);
2339 b43_write32(dev, 0x018C, 0x02000000);
2340 }
2341 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2342 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2343 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2344 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2345 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2346 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2347 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2348
2349 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2350 value32 |= 0x00100000;
2351 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2352
2353 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2354 dev->dev->bus->chipco.fast_pwrup_delay);
2355
2356 err = 0;
2357 b43dbg(dev->wl, "Chip initialized\n");
2358 out:
2359 return err;
2360
2361 err_radio_off:
2362 b43_radio_turn_off(dev, 1);
2363 err_gpio_clean:
2364 b43_gpio_cleanup(dev);
2365 return err;
2366 }
2367
2368 static void b43_periodic_every120sec(struct b43_wldev *dev)
2369 {
2370 struct b43_phy *phy = &dev->phy;
2371
2372 if (phy->type != B43_PHYTYPE_G || phy->rev < 2)
2373 return;
2374
2375 b43_mac_suspend(dev);
2376 b43_lo_g_measure(dev);
2377 b43_mac_enable(dev);
2378 if (b43_has_hardware_pctl(phy))
2379 b43_lo_g_ctl_mark_all_unused(dev);
2380 }
2381
2382 static void b43_periodic_every60sec(struct b43_wldev *dev)
2383 {
2384 struct b43_phy *phy = &dev->phy;
2385
2386 if (phy->type != B43_PHYTYPE_G)
2387 return;
2388 if (!b43_has_hardware_pctl(phy))
2389 b43_lo_g_ctl_mark_all_unused(dev);
2390 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI) {
2391 b43_mac_suspend(dev);
2392 b43_calc_nrssi_slope(dev);
2393 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) {
2394 u8 old_chan = phy->channel;
2395
2396 /* VCO Calibration */
2397 if (old_chan >= 8)
2398 b43_radio_selectchannel(dev, 1, 0);
2399 else
2400 b43_radio_selectchannel(dev, 13, 0);
2401 b43_radio_selectchannel(dev, old_chan, 0);
2402 }
2403 b43_mac_enable(dev);
2404 }
2405 }
2406
2407 static void b43_periodic_every30sec(struct b43_wldev *dev)
2408 {
2409 /* Update device statistics. */
2410 b43_calculate_link_quality(dev);
2411 }
2412
2413 static void b43_periodic_every15sec(struct b43_wldev *dev)
2414 {
2415 struct b43_phy *phy = &dev->phy;
2416
2417 if (phy->type == B43_PHYTYPE_G) {
2418 //TODO: update_aci_moving_average
2419 if (phy->aci_enable && phy->aci_wlan_automatic) {
2420 b43_mac_suspend(dev);
2421 if (!phy->aci_enable && 1 /*TODO: not scanning? */ ) {
2422 if (0 /*TODO: bunch of conditions */ ) {
2423 b43_radio_set_interference_mitigation
2424 (dev, B43_INTERFMODE_MANUALWLAN);
2425 }
2426 } else if (1 /*TODO*/) {
2427 /*
2428 if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) {
2429 b43_radio_set_interference_mitigation(dev,
2430 B43_INTERFMODE_NONE);
2431 }
2432 */
2433 }
2434 b43_mac_enable(dev);
2435 } else if (phy->interfmode == B43_INTERFMODE_NONWLAN &&
2436 phy->rev == 1) {
2437 //TODO: implement rev1 workaround
2438 }
2439 }
2440 b43_phy_xmitpower(dev); //FIXME: unless scanning?
2441 //TODO for APHY (temperature?)
2442
2443 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2444 wmb();
2445 }
2446
2447 static void do_periodic_work(struct b43_wldev *dev)
2448 {
2449 unsigned int state;
2450
2451 state = dev->periodic_state;
2452 if (state % 8 == 0)
2453 b43_periodic_every120sec(dev);
2454 if (state % 4 == 0)
2455 b43_periodic_every60sec(dev);
2456 if (state % 2 == 0)
2457 b43_periodic_every30sec(dev);
2458 b43_periodic_every15sec(dev);
2459 }
2460
2461 /* Periodic work locking policy:
2462 * The whole periodic work handler is protected by
2463 * wl->mutex. If another lock is needed somewhere in the
2464 * pwork callchain, it's aquired in-place, where it's needed.
2465 */
2466 static void b43_periodic_work_handler(struct work_struct *work)
2467 {
2468 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2469 periodic_work.work);
2470 struct b43_wl *wl = dev->wl;
2471 unsigned long delay;
2472
2473 mutex_lock(&wl->mutex);
2474
2475 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2476 goto out;
2477 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2478 goto out_requeue;
2479
2480 do_periodic_work(dev);
2481
2482 dev->periodic_state++;
2483 out_requeue:
2484 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2485 delay = msecs_to_jiffies(50);
2486 else
2487 delay = round_jiffies_relative(HZ * 15);
2488 queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
2489 out:
2490 mutex_unlock(&wl->mutex);
2491 }
2492
2493 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2494 {
2495 struct delayed_work *work = &dev->periodic_work;
2496
2497 dev->periodic_state = 0;
2498 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2499 queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2500 }
2501
2502 /* Check if communication with the device works correctly. */
2503 static int b43_validate_chipaccess(struct b43_wldev *dev)
2504 {
2505 u32 v, backup;
2506
2507 backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2508
2509 /* Check for read/write and endianness problems. */
2510 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2511 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2512 goto error;
2513 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2514 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
2515 goto error;
2516
2517 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup);
2518
2519 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
2520 /* The 32bit register shadows the two 16bit registers
2521 * with update sideeffects. Validate this. */
2522 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
2523 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
2524 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
2525 goto error;
2526 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
2527 goto error;
2528 }
2529 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
2530
2531 v = b43_read32(dev, B43_MMIO_MACCTL);
2532 v |= B43_MACCTL_GMODE;
2533 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
2534 goto error;
2535
2536 return 0;
2537 error:
2538 b43err(dev->wl, "Failed to validate the chipaccess\n");
2539 return -ENODEV;
2540 }
2541
2542 static void b43_security_init(struct b43_wldev *dev)
2543 {
2544 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2545 B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2546 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2547 /* KTP is a word address, but we address SHM bytewise.
2548 * So multiply by two.
2549 */
2550 dev->ktp *= 2;
2551 if (dev->dev->id.revision >= 5) {
2552 /* Number of RCMTA address slots */
2553 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2554 }
2555 b43_clear_keys(dev);
2556 }
2557
2558 static int b43_rng_read(struct hwrng *rng, u32 * data)
2559 {
2560 struct b43_wl *wl = (struct b43_wl *)rng->priv;
2561 unsigned long flags;
2562
2563 /* Don't take wl->mutex here, as it could deadlock with
2564 * hwrng internal locking. It's not needed to take
2565 * wl->mutex here, anyway. */
2566
2567 spin_lock_irqsave(&wl->irq_lock, flags);
2568 *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2569 spin_unlock_irqrestore(&wl->irq_lock, flags);
2570
2571 return (sizeof(u16));
2572 }
2573
2574 static void b43_rng_exit(struct b43_wl *wl, bool suspended)
2575 {
2576 if (wl->rng_initialized)
2577 __hwrng_unregister(&wl->rng, suspended);
2578 }
2579
2580 static int b43_rng_init(struct b43_wl *wl)
2581 {
2582 int err;
2583
2584 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2585 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2586 wl->rng.name = wl->rng_name;
2587 wl->rng.data_read = b43_rng_read;
2588 wl->rng.priv = (unsigned long)wl;
2589 wl->rng_initialized = 1;
2590 err = hwrng_register(&wl->rng);
2591 if (err) {
2592 wl->rng_initialized = 0;
2593 b43err(wl, "Failed to register the random "
2594 "number generator (%d)\n", err);
2595 }
2596
2597 return err;
2598 }
2599
2600 static int b43_op_tx(struct ieee80211_hw *hw,
2601 struct sk_buff *skb,
2602 struct ieee80211_tx_control *ctl)
2603 {
2604 struct b43_wl *wl = hw_to_b43_wl(hw);
2605 struct b43_wldev *dev = wl->current_dev;
2606 unsigned long flags;
2607 int err;
2608
2609 if (unlikely(!dev))
2610 return NETDEV_TX_BUSY;
2611
2612 /* Transmissions on seperate queues can run concurrently. */
2613 read_lock_irqsave(&wl->tx_lock, flags);
2614
2615 err = -ENODEV;
2616 if (likely(b43_status(dev) >= B43_STAT_STARTED))
2617 err = b43_dma_tx(dev, skb, ctl);
2618
2619 read_unlock_irqrestore(&wl->tx_lock, flags);
2620
2621 if (unlikely(err))
2622 return NETDEV_TX_BUSY;
2623 return NETDEV_TX_OK;
2624 }
2625
2626 static int b43_op_conf_tx(struct ieee80211_hw *hw,
2627 int queue,
2628 const struct ieee80211_tx_queue_params *params)
2629 {
2630 return 0;
2631 }
2632
2633 static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
2634 struct ieee80211_tx_queue_stats *stats)
2635 {
2636 struct b43_wl *wl = hw_to_b43_wl(hw);
2637 struct b43_wldev *dev = wl->current_dev;
2638 unsigned long flags;
2639 int err = -ENODEV;
2640
2641 if (!dev)
2642 goto out;
2643 spin_lock_irqsave(&wl->irq_lock, flags);
2644 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
2645 b43_dma_get_tx_stats(dev, stats);
2646 err = 0;
2647 }
2648 spin_unlock_irqrestore(&wl->irq_lock, flags);
2649 out:
2650 return err;
2651 }
2652
2653 static int b43_op_get_stats(struct ieee80211_hw *hw,
2654 struct ieee80211_low_level_stats *stats)
2655 {
2656 struct b43_wl *wl = hw_to_b43_wl(hw);
2657 unsigned long flags;
2658
2659 spin_lock_irqsave(&wl->irq_lock, flags);
2660 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2661 spin_unlock_irqrestore(&wl->irq_lock, flags);
2662
2663 return 0;
2664 }
2665
2666 static const char *phymode_to_string(unsigned int phymode)
2667 {
2668 switch (phymode) {
2669 case B43_PHYMODE_A:
2670 return "A";
2671 case B43_PHYMODE_B:
2672 return "B";
2673 case B43_PHYMODE_G:
2674 return "G";
2675 default:
2676 B43_WARN_ON(1);
2677 }
2678 return "";
2679 }
2680
2681 static int find_wldev_for_phymode(struct b43_wl *wl,
2682 unsigned int phymode,
2683 struct b43_wldev **dev, bool * gmode)
2684 {
2685 struct b43_wldev *d;
2686
2687 list_for_each_entry(d, &wl->devlist, list) {
2688 if (d->phy.possible_phymodes & phymode) {
2689 /* Ok, this device supports the PHY-mode.
2690 * Now figure out how the gmode bit has to be
2691 * set to support it. */
2692 if (phymode == B43_PHYMODE_A)
2693 *gmode = 0;
2694 else
2695 *gmode = 1;
2696 *dev = d;
2697
2698 return 0;
2699 }
2700 }
2701
2702 return -ESRCH;
2703 }
2704
2705 static void b43_put_phy_into_reset(struct b43_wldev *dev)
2706 {
2707 struct ssb_device *sdev = dev->dev;
2708 u32 tmslow;
2709
2710 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2711 tmslow &= ~B43_TMSLOW_GMODE;
2712 tmslow |= B43_TMSLOW_PHYRESET;
2713 tmslow |= SSB_TMSLOW_FGC;
2714 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2715 msleep(1);
2716
2717 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2718 tmslow &= ~SSB_TMSLOW_FGC;
2719 tmslow |= B43_TMSLOW_PHYRESET;
2720 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2721 msleep(1);
2722 }
2723
2724 /* Expects wl->mutex locked */
2725 static int b43_switch_phymode(struct b43_wl *wl, unsigned int new_mode)
2726 {
2727 struct b43_wldev *up_dev;
2728 struct b43_wldev *down_dev;
2729 int err;
2730 bool gmode = 0;
2731 int prev_status;
2732
2733 err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
2734 if (err) {
2735 b43err(wl, "Could not find a device for %s-PHY mode\n",
2736 phymode_to_string(new_mode));
2737 return err;
2738 }
2739 if ((up_dev == wl->current_dev) &&
2740 (!!wl->current_dev->phy.gmode == !!gmode)) {
2741 /* This device is already running. */
2742 return 0;
2743 }
2744 b43dbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
2745 phymode_to_string(new_mode));
2746 down_dev = wl->current_dev;
2747
2748 prev_status = b43_status(down_dev);
2749 /* Shutdown the currently running core. */
2750 if (prev_status >= B43_STAT_STARTED)
2751 b43_wireless_core_stop(down_dev);
2752 if (prev_status >= B43_STAT_INITIALIZED)
2753 b43_wireless_core_exit(down_dev);
2754
2755 if (down_dev != up_dev) {
2756 /* We switch to a different core, so we put PHY into
2757 * RESET on the old core. */
2758 b43_put_phy_into_reset(down_dev);
2759 }
2760
2761 /* Now start the new core. */
2762 up_dev->phy.gmode = gmode;
2763 if (prev_status >= B43_STAT_INITIALIZED) {
2764 err = b43_wireless_core_init(up_dev);
2765 if (err) {
2766 b43err(wl, "Fatal: Could not initialize device for "
2767 "newly selected %s-PHY mode\n",
2768 phymode_to_string(new_mode));
2769 goto init_failure;
2770 }
2771 }
2772 if (prev_status >= B43_STAT_STARTED) {
2773 err = b43_wireless_core_start(up_dev);
2774 if (err) {
2775 b43err(wl, "Fatal: Coult not start device for "
2776 "newly selected %s-PHY mode\n",
2777 phymode_to_string(new_mode));
2778 b43_wireless_core_exit(up_dev);
2779 goto init_failure;
2780 }
2781 }
2782 B43_WARN_ON(b43_status(up_dev) != prev_status);
2783
2784 wl->current_dev = up_dev;
2785
2786 return 0;
2787 init_failure:
2788 /* Whoops, failed to init the new core. No core is operating now. */
2789 wl->current_dev = NULL;
2790 return err;
2791 }
2792
2793 /* Check if the use of the antenna that ieee80211 told us to
2794 * use is possible. This will fall back to DEFAULT.
2795 * "antenna_nr" is the antenna identifier we got from ieee80211. */
2796 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
2797 u8 antenna_nr)
2798 {
2799 u8 antenna_mask;
2800
2801 if (antenna_nr == 0) {
2802 /* Zero means "use default antenna". That's always OK. */
2803 return 0;
2804 }
2805
2806 /* Get the mask of available antennas. */
2807 if (dev->phy.gmode)
2808 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
2809 else
2810 antenna_mask = dev->dev->bus->sprom.ant_available_a;
2811
2812 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
2813 /* This antenna is not available. Fall back to default. */
2814 return 0;
2815 }
2816
2817 return antenna_nr;
2818 }
2819
2820 static int b43_antenna_from_ieee80211(struct b43_wldev *dev, u8 antenna)
2821 {
2822 antenna = b43_ieee80211_antenna_sanitize(dev, antenna);
2823 switch (antenna) {
2824 case 0: /* default/diversity */
2825 return B43_ANTENNA_DEFAULT;
2826 case 1: /* Antenna 0 */
2827 return B43_ANTENNA0;
2828 case 2: /* Antenna 1 */
2829 return B43_ANTENNA1;
2830 case 3: /* Antenna 2 */
2831 return B43_ANTENNA2;
2832 case 4: /* Antenna 3 */
2833 return B43_ANTENNA3;
2834 default:
2835 return B43_ANTENNA_DEFAULT;
2836 }
2837 }
2838
2839 static int b43_op_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
2840 {
2841 struct b43_wl *wl = hw_to_b43_wl(hw);
2842 struct b43_wldev *dev;
2843 struct b43_phy *phy;
2844 unsigned long flags;
2845 unsigned int new_phymode = 0xFFFF;
2846 int antenna;
2847 int err = 0;
2848 u32 savedirqs;
2849
2850 mutex_lock(&wl->mutex);
2851
2852 /* Switch the PHY mode (if necessary). */
2853 switch (conf->phymode) {
2854 case MODE_IEEE80211A:
2855 new_phymode = B43_PHYMODE_A;
2856 break;
2857 case MODE_IEEE80211B:
2858 new_phymode = B43_PHYMODE_B;
2859 break;
2860 case MODE_IEEE80211G:
2861 new_phymode = B43_PHYMODE_G;
2862 break;
2863 default:
2864 B43_WARN_ON(1);
2865 }
2866 err = b43_switch_phymode(wl, new_phymode);
2867 if (err)
2868 goto out_unlock_mutex;
2869 dev = wl->current_dev;
2870 phy = &dev->phy;
2871
2872 /* Disable IRQs while reconfiguring the device.
2873 * This makes it possible to drop the spinlock throughout
2874 * the reconfiguration process. */
2875 spin_lock_irqsave(&wl->irq_lock, flags);
2876 if (b43_status(dev) < B43_STAT_STARTED) {
2877 spin_unlock_irqrestore(&wl->irq_lock, flags);
2878 goto out_unlock_mutex;
2879 }
2880 savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL);
2881 spin_unlock_irqrestore(&wl->irq_lock, flags);
2882 b43_synchronize_irq(dev);
2883
2884 /* Switch to the requested channel.
2885 * The firmware takes care of races with the TX handler. */
2886 if (conf->channel_val != phy->channel)
2887 b43_radio_selectchannel(dev, conf->channel_val, 0);
2888
2889 /* Enable/Disable ShortSlot timing. */
2890 if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) !=
2891 dev->short_slot) {
2892 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2893 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
2894 b43_short_slot_timing_enable(dev);
2895 else
2896 b43_short_slot_timing_disable(dev);
2897 }
2898
2899 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
2900
2901 /* Adjust the desired TX power level. */
2902 if (conf->power_level != 0) {
2903 if (conf->power_level != phy->power_level) {
2904 phy->power_level = conf->power_level;
2905 b43_phy_xmitpower(dev);
2906 }
2907 }
2908
2909 /* Antennas for RX and management frame TX. */
2910 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_tx);
2911 b43_mgmtframe_txantenna(dev, antenna);
2912 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_rx);
2913 b43_set_rx_antenna(dev, antenna);
2914
2915 /* Update templates for AP mode. */
2916 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2917 b43_set_beacon_int(dev, conf->beacon_int);
2918
2919 if (!!conf->radio_enabled != phy->radio_on) {
2920 if (conf->radio_enabled) {
2921 b43_radio_turn_on(dev);
2922 b43info(dev->wl, "Radio turned on by software\n");
2923 if (!dev->radio_hw_enable) {
2924 b43info(dev->wl, "The hardware RF-kill button "
2925 "still turns the radio physically off. "
2926 "Press the button to turn it on.\n");
2927 }
2928 } else {
2929 b43_radio_turn_off(dev, 0);
2930 b43info(dev->wl, "Radio turned off by software\n");
2931 }
2932 }
2933
2934 spin_lock_irqsave(&wl->irq_lock, flags);
2935 b43_interrupt_enable(dev, savedirqs);
2936 mmiowb();
2937 spin_unlock_irqrestore(&wl->irq_lock, flags);
2938 out_unlock_mutex:
2939 mutex_unlock(&wl->mutex);
2940
2941 return err;
2942 }
2943
2944 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2945 const u8 *local_addr, const u8 *addr,
2946 struct ieee80211_key_conf *key)
2947 {
2948 struct b43_wl *wl = hw_to_b43_wl(hw);
2949 struct b43_wldev *dev;
2950 unsigned long flags;
2951 u8 algorithm;
2952 u8 index;
2953 int err;
2954 DECLARE_MAC_BUF(mac);
2955
2956 if (modparam_nohwcrypt)
2957 return -ENOSPC; /* User disabled HW-crypto */
2958
2959 mutex_lock(&wl->mutex);
2960 spin_lock_irqsave(&wl->irq_lock, flags);
2961
2962 dev = wl->current_dev;
2963 err = -ENODEV;
2964 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
2965 goto out_unlock;
2966
2967 err = -EINVAL;
2968 switch (key->alg) {
2969 case ALG_WEP:
2970 if (key->keylen == 5)
2971 algorithm = B43_SEC_ALGO_WEP40;
2972 else
2973 algorithm = B43_SEC_ALGO_WEP104;
2974 break;
2975 case ALG_TKIP:
2976 algorithm = B43_SEC_ALGO_TKIP;
2977 break;
2978 case ALG_CCMP:
2979 algorithm = B43_SEC_ALGO_AES;
2980 break;
2981 default:
2982 B43_WARN_ON(1);
2983 goto out_unlock;
2984 }
2985 index = (u8) (key->keyidx);
2986 if (index > 3)
2987 goto out_unlock;
2988
2989 switch (cmd) {
2990 case SET_KEY:
2991 if (algorithm == B43_SEC_ALGO_TKIP) {
2992 /* FIXME: No TKIP hardware encryption for now. */
2993 err = -EOPNOTSUPP;
2994 goto out_unlock;
2995 }
2996
2997 if (is_broadcast_ether_addr(addr)) {
2998 /* addr is FF:FF:FF:FF:FF:FF for default keys */
2999 err = b43_key_write(dev, index, algorithm,
3000 key->key, key->keylen, NULL, key);
3001 } else {
3002 /*
3003 * either pairwise key or address is 00:00:00:00:00:00
3004 * for transmit-only keys
3005 */
3006 err = b43_key_write(dev, -1, algorithm,
3007 key->key, key->keylen, addr, key);
3008 }
3009 if (err)
3010 goto out_unlock;
3011
3012 if (algorithm == B43_SEC_ALGO_WEP40 ||
3013 algorithm == B43_SEC_ALGO_WEP104) {
3014 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
3015 } else {
3016 b43_hf_write(dev,
3017 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
3018 }
3019 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3020 break;
3021 case DISABLE_KEY: {
3022 err = b43_key_clear(dev, key->hw_key_idx);
3023 if (err)
3024 goto out_unlock;
3025 break;
3026 }
3027 default:
3028 B43_WARN_ON(1);
3029 }
3030 out_unlock:
3031 spin_unlock_irqrestore(&wl->irq_lock, flags);
3032 mutex_unlock(&wl->mutex);
3033 if (!err) {
3034 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
3035 "mac: %s\n",
3036 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
3037 print_mac(mac, addr));
3038 }
3039 return err;
3040 }
3041
3042 static void b43_op_configure_filter(struct ieee80211_hw *hw,
3043 unsigned int changed, unsigned int *fflags,
3044 int mc_count, struct dev_addr_list *mc_list)
3045 {
3046 struct b43_wl *wl = hw_to_b43_wl(hw);
3047 struct b43_wldev *dev = wl->current_dev;
3048 unsigned long flags;
3049
3050 if (!dev) {
3051 *fflags = 0;
3052 return;
3053 }
3054
3055 spin_lock_irqsave(&wl->irq_lock, flags);
3056 *fflags &= FIF_PROMISC_IN_BSS |
3057 FIF_ALLMULTI |
3058 FIF_FCSFAIL |
3059 FIF_PLCPFAIL |
3060 FIF_CONTROL |
3061 FIF_OTHER_BSS |
3062 FIF_BCN_PRBRESP_PROMISC;
3063
3064 changed &= FIF_PROMISC_IN_BSS |
3065 FIF_ALLMULTI |
3066 FIF_FCSFAIL |
3067 FIF_PLCPFAIL |
3068 FIF_CONTROL |
3069 FIF_OTHER_BSS |
3070 FIF_BCN_PRBRESP_PROMISC;
3071
3072 wl->filter_flags = *fflags;
3073
3074 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
3075 b43_adjust_opmode(dev);
3076 spin_unlock_irqrestore(&wl->irq_lock, flags);
3077 }
3078
3079 static int b43_op_config_interface(struct ieee80211_hw *hw,
3080 struct ieee80211_vif *vif,
3081 struct ieee80211_if_conf *conf)
3082 {
3083 struct b43_wl *wl = hw_to_b43_wl(hw);
3084 struct b43_wldev *dev = wl->current_dev;
3085 unsigned long flags;
3086
3087 if (!dev)
3088 return -ENODEV;
3089 mutex_lock(&wl->mutex);
3090 spin_lock_irqsave(&wl->irq_lock, flags);
3091 B43_WARN_ON(wl->vif != vif);
3092 if (conf->bssid)
3093 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3094 else
3095 memset(wl->bssid, 0, ETH_ALEN);
3096 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3097 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
3098 B43_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP);
3099 b43_set_ssid(dev, conf->ssid, conf->ssid_len);
3100 if (conf->beacon)
3101 b43_update_templates(wl, conf->beacon);
3102 }
3103 b43_write_mac_bssid_templates(dev);
3104 }
3105 spin_unlock_irqrestore(&wl->irq_lock, flags);
3106 mutex_unlock(&wl->mutex);
3107
3108 return 0;
3109 }
3110
3111 /* Locking: wl->mutex */
3112 static void b43_wireless_core_stop(struct b43_wldev *dev)
3113 {
3114 struct b43_wl *wl = dev->wl;
3115 unsigned long flags;
3116
3117 if (b43_status(dev) < B43_STAT_STARTED)
3118 return;
3119
3120 /* Disable and sync interrupts. We must do this before than
3121 * setting the status to INITIALIZED, as the interrupt handler
3122 * won't care about IRQs then. */
3123 spin_lock_irqsave(&wl->irq_lock, flags);
3124 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
3125 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
3126 spin_unlock_irqrestore(&wl->irq_lock, flags);
3127 b43_synchronize_irq(dev);
3128
3129 write_lock_irqsave(&wl->tx_lock, flags);
3130 b43_set_status(dev, B43_STAT_INITIALIZED);
3131 write_unlock_irqrestore(&wl->tx_lock, flags);
3132
3133 mutex_unlock(&wl->mutex);
3134 /* Must unlock as it would otherwise deadlock. No races here.
3135 * Cancel the possibly running self-rearming periodic work. */
3136 cancel_delayed_work_sync(&dev->periodic_work);
3137 mutex_lock(&wl->mutex);
3138
3139 b43_mac_suspend(dev);
3140 free_irq(dev->dev->irq, dev);
3141 b43dbg(wl, "Wireless interface stopped\n");
3142 }
3143
3144 /* Locking: wl->mutex */
3145 static int b43_wireless_core_start(struct b43_wldev *dev)
3146 {
3147 int err;
3148
3149 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3150
3151 drain_txstatus_queue(dev);
3152 err = request_irq(dev->dev->irq, b43_interrupt_handler,
3153 IRQF_SHARED, KBUILD_MODNAME, dev);
3154 if (err) {
3155 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3156 goto out;
3157 }
3158
3159 /* We are ready to run. */
3160 b43_set_status(dev, B43_STAT_STARTED);
3161
3162 /* Start data flow (TX/RX). */
3163 b43_mac_enable(dev);
3164 b43_interrupt_enable(dev, dev->irq_savedstate);
3165 ieee80211_start_queues(dev->wl->hw);
3166
3167 /* Start maintainance work */
3168 b43_periodic_tasks_setup(dev);
3169
3170 b43dbg(dev->wl, "Wireless interface started\n");
3171 out:
3172 return err;
3173 }
3174
3175 /* Get PHY and RADIO versioning numbers */
3176 static int b43_phy_versioning(struct b43_wldev *dev)
3177 {
3178 struct b43_phy *phy = &dev->phy;
3179 u32 tmp;
3180 u8 analog_type;
3181 u8 phy_type;
3182 u8 phy_rev;
3183 u16 radio_manuf;
3184 u16 radio_ver;
3185 u16 radio_rev;
3186 int unsupported = 0;
3187
3188 /* Get PHY versioning */
3189 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3190 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3191 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3192 phy_rev = (tmp & B43_PHYVER_VERSION);
3193 switch (phy_type) {
3194 case B43_PHYTYPE_A:
3195 if (phy_rev >= 4)
3196 unsupported = 1;
3197 break;
3198 case B43_PHYTYPE_B:
3199 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3200 && phy_rev != 7)
3201 unsupported = 1;
3202 break;
3203 case B43_PHYTYPE_G:
3204 if (phy_rev > 9)
3205 unsupported = 1;
3206 break;
3207 #ifdef CONFIG_B43_NPHY
3208 case B43_PHYTYPE_N:
3209 if (phy_rev > 1)
3210 unsupported = 1;
3211 break;
3212 #endif
3213 default:
3214 unsupported = 1;
3215 };
3216 if (unsupported) {
3217 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3218 "(Analog %u, Type %u, Revision %u)\n",
3219 analog_type, phy_type, phy_rev);
3220 return -EOPNOTSUPP;
3221 }
3222 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3223 analog_type, phy_type, phy_rev);
3224
3225 /* Get RADIO versioning */
3226 if (dev->dev->bus->chip_id == 0x4317) {
3227 if (dev->dev->bus->chip_rev == 0)
3228 tmp = 0x3205017F;
3229 else if (dev->dev->bus->chip_rev == 1)
3230 tmp = 0x4205017F;
3231 else
3232 tmp = 0x5205017F;
3233 } else {
3234 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3235 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3236 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3237 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
3238 }
3239 radio_manuf = (tmp & 0x00000FFF);
3240 radio_ver = (tmp & 0x0FFFF000) >> 12;
3241 radio_rev = (tmp & 0xF0000000) >> 28;
3242 if (radio_manuf != 0x17F /* Broadcom */)
3243 unsupported = 1;
3244 switch (phy_type) {
3245 case B43_PHYTYPE_A:
3246 if (radio_ver != 0x2060)
3247 unsupported = 1;
3248 if (radio_rev != 1)
3249 unsupported = 1;
3250 if (radio_manuf != 0x17F)
3251 unsupported = 1;
3252 break;
3253 case B43_PHYTYPE_B:
3254 if ((radio_ver & 0xFFF0) != 0x2050)
3255 unsupported = 1;
3256 break;
3257 case B43_PHYTYPE_G:
3258 if (radio_ver != 0x2050)
3259 unsupported = 1;
3260 break;
3261 case B43_PHYTYPE_N:
3262 if (radio_ver != 0x2055)
3263 unsupported = 1;
3264 break;
3265 default:
3266 B43_WARN_ON(1);
3267 }
3268 if (unsupported) {
3269 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3270 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3271 radio_manuf, radio_ver, radio_rev);
3272 return -EOPNOTSUPP;
3273 }
3274 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3275 radio_manuf, radio_ver, radio_rev);
3276
3277 phy->radio_manuf = radio_manuf;
3278 phy->radio_ver = radio_ver;
3279 phy->radio_rev = radio_rev;
3280
3281 phy->analog = analog_type;
3282 phy->type = phy_type;
3283 phy->rev = phy_rev;
3284
3285 return 0;
3286 }
3287
3288 static void setup_struct_phy_for_init(struct b43_wldev *dev,
3289 struct b43_phy *phy)
3290 {
3291 struct b43_txpower_lo_control *lo;
3292 int i;
3293
3294 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3295 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3296
3297 phy->aci_enable = 0;
3298 phy->aci_wlan_automatic = 0;
3299 phy->aci_hw_rssi = 0;
3300
3301 phy->radio_off_context.valid = 0;
3302
3303 lo = phy->lo_control;
3304 if (lo) {
3305 memset(lo, 0, sizeof(*(phy->lo_control)));
3306 lo->rebuild = 1;
3307 lo->tx_bias = 0xFF;
3308 }
3309 phy->max_lb_gain = 0;
3310 phy->trsw_rx_gain = 0;
3311 phy->txpwr_offset = 0;
3312
3313 /* NRSSI */
3314 phy->nrssislope = 0;
3315 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3316 phy->nrssi[i] = -1000;
3317 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3318 phy->nrssi_lt[i] = i;
3319
3320 phy->lofcal = 0xFFFF;
3321 phy->initval = 0xFFFF;
3322
3323 phy->interfmode = B43_INTERFMODE_NONE;
3324 phy->channel = 0xFF;
3325
3326 phy->hardware_power_control = !!modparam_hwpctl;
3327
3328 /* PHY TX errors counter. */
3329 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3330
3331 /* OFDM-table address caching. */
3332 phy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_UNKNOWN;
3333 }
3334
3335 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3336 {
3337 dev->dfq_valid = 0;
3338
3339 /* Assume the radio is enabled. If it's not enabled, the state will
3340 * immediately get fixed on the first periodic work run. */
3341 dev->radio_hw_enable = 1;
3342
3343 /* Stats */
3344 memset(&dev->stats, 0, sizeof(dev->stats));
3345
3346 setup_struct_phy_for_init(dev, &dev->phy);
3347
3348 /* IRQ related flags */
3349 dev->irq_reason = 0;
3350 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3351 dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
3352
3353 dev->mac_suspended = 1;
3354
3355 /* Noise calculation context */
3356 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3357 }
3358
3359 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
3360 {
3361 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3362 u32 hf;
3363
3364 if (!modparam_btcoex)
3365 return;
3366 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
3367 return;
3368 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
3369 return;
3370
3371 hf = b43_hf_read(dev);
3372 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
3373 hf |= B43_HF_BTCOEXALT;
3374 else
3375 hf |= B43_HF_BTCOEX;
3376 b43_hf_write(dev, hf);
3377 }
3378
3379 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
3380 {
3381 if (!modparam_btcoex)
3382 return;
3383 //TODO
3384 }
3385
3386 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
3387 {
3388 #ifdef CONFIG_SSB_DRIVER_PCICORE
3389 struct ssb_bus *bus = dev->dev->bus;
3390 u32 tmp;
3391
3392 if (bus->pcicore.dev &&
3393 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3394 bus->pcicore.dev->id.revision <= 5) {
3395 /* IMCFGLO timeouts workaround. */
3396 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3397 tmp &= ~SSB_IMCFGLO_REQTO;
3398 tmp &= ~SSB_IMCFGLO_SERTO;
3399 switch (bus->bustype) {
3400 case SSB_BUSTYPE_PCI:
3401 case SSB_BUSTYPE_PCMCIA:
3402 tmp |= 0x32;
3403 break;
3404 case SSB_BUSTYPE_SSB:
3405 tmp |= 0x53;
3406 break;
3407 }
3408 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3409 }
3410 #endif /* CONFIG_SSB_DRIVER_PCICORE */
3411 }
3412
3413 /* Write the short and long frame retry limit values. */
3414 static void b43_set_retry_limits(struct b43_wldev *dev,
3415 unsigned int short_retry,
3416 unsigned int long_retry)
3417 {
3418 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3419 * the chip-internal counter. */
3420 short_retry = min(short_retry, (unsigned int)0xF);
3421 long_retry = min(long_retry, (unsigned int)0xF);
3422
3423 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3424 short_retry);
3425 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3426 long_retry);
3427 }
3428
3429 /* Shutdown a wireless core */
3430 /* Locking: wl->mutex */
3431 static void b43_wireless_core_exit(struct b43_wldev *dev)
3432 {
3433 struct b43_phy *phy = &dev->phy;
3434 u32 macctl;
3435
3436 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
3437 if (b43_status(dev) != B43_STAT_INITIALIZED)
3438 return;
3439 b43_set_status(dev, B43_STAT_UNINIT);
3440
3441 /* Stop the microcode PSM. */
3442 macctl = b43_read32(dev, B43_MMIO_MACCTL);
3443 macctl &= ~B43_MACCTL_PSM_RUN;
3444 macctl |= B43_MACCTL_PSM_JMP0;
3445 b43_write32(dev, B43_MMIO_MACCTL, macctl);
3446
3447 if (!dev->suspend_in_progress) {
3448 b43_leds_exit(dev);
3449 b43_rng_exit(dev->wl, false);
3450 }
3451 b43_dma_free(dev);
3452 b43_chip_exit(dev);
3453 b43_radio_turn_off(dev, 1);
3454 b43_switch_analog(dev, 0);
3455 if (phy->dyn_tssi_tbl)
3456 kfree(phy->tssi2dbm);
3457 kfree(phy->lo_control);
3458 phy->lo_control = NULL;
3459 if (dev->wl->current_beacon) {
3460 dev_kfree_skb_any(dev->wl->current_beacon);
3461 dev->wl->current_beacon = NULL;
3462 }
3463
3464 ssb_device_disable(dev->dev, 0);
3465 ssb_bus_may_powerdown(dev->dev->bus);
3466 }
3467
3468 /* Initialize a wireless core */
3469 static int b43_wireless_core_init(struct b43_wldev *dev)
3470 {
3471 struct b43_wl *wl = dev->wl;
3472 struct ssb_bus *bus = dev->dev->bus;
3473 struct ssb_sprom *sprom = &bus->sprom;
3474 struct b43_phy *phy = &dev->phy;
3475 int err;
3476 u32 hf, tmp;
3477
3478 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3479
3480 err = ssb_bus_powerup(bus, 0);
3481 if (err)
3482 goto out;
3483 if (!ssb_device_is_enabled(dev->dev)) {
3484 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
3485 b43_wireless_core_reset(dev, tmp);
3486 }
3487
3488 if ((phy->type == B43_PHYTYPE_B) || (phy->type == B43_PHYTYPE_G)) {
3489 phy->lo_control =
3490 kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL);
3491 if (!phy->lo_control) {
3492 err = -ENOMEM;
3493 goto err_busdown;
3494 }
3495 }
3496 setup_struct_wldev_for_init(dev);
3497
3498 err = b43_phy_init_tssi2dbm_table(dev);
3499 if (err)
3500 goto err_kfree_lo_control;
3501
3502 /* Enable IRQ routing to this device. */
3503 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3504
3505 b43_imcfglo_timeouts_workaround(dev);
3506 b43_bluetooth_coext_disable(dev);
3507 b43_phy_early_init(dev);
3508 err = b43_chip_init(dev);
3509 if (err)
3510 goto err_kfree_tssitbl;
3511 b43_shm_write16(dev, B43_SHM_SHARED,
3512 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
3513 hf = b43_hf_read(dev);
3514 if (phy->type == B43_PHYTYPE_G) {
3515 hf |= B43_HF_SYMW;
3516 if (phy->rev == 1)
3517 hf |= B43_HF_GDCW;
3518 if (sprom->boardflags_lo & B43_BFL_PACTRL)
3519 hf |= B43_HF_OFDMPABOOST;
3520 } else if (phy->type == B43_PHYTYPE_B) {
3521 hf |= B43_HF_SYMW;
3522 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3523 hf &= ~B43_HF_GDCW;
3524 }
3525 b43_hf_write(dev, hf);
3526
3527 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
3528 B43_DEFAULT_LONG_RETRY_LIMIT);
3529 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
3530 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
3531
3532 /* Disable sending probe responses from firmware.
3533 * Setting the MaxTime to one usec will always trigger
3534 * a timeout, so we never send any probe resp.
3535 * A timeout of zero is infinite. */
3536 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
3537
3538 b43_rate_memory_init(dev);
3539
3540 /* Minimum Contention Window */
3541 if (phy->type == B43_PHYTYPE_B) {
3542 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
3543 } else {
3544 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
3545 }
3546 /* Maximum Contention Window */
3547 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
3548
3549 err = b43_dma_init(dev);
3550 if (err)
3551 goto err_chip_exit;
3552 b43_qos_init(dev);
3553
3554 //FIXME
3555 #if 1
3556 b43_write16(dev, 0x0612, 0x0050);
3557 b43_shm_write16(dev, B43_SHM_SHARED, 0x0416, 0x0050);
3558 b43_shm_write16(dev, B43_SHM_SHARED, 0x0414, 0x01F4);
3559 #endif
3560
3561 b43_bluetooth_coext_enable(dev);
3562
3563 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
3564 b43_upload_card_macaddress(dev);
3565 b43_security_init(dev);
3566 if (!dev->suspend_in_progress)
3567 b43_rng_init(wl);
3568
3569 b43_set_status(dev, B43_STAT_INITIALIZED);
3570
3571 if (!dev->suspend_in_progress)
3572 b43_leds_init(dev);
3573 out:
3574 return err;
3575
3576 err_chip_exit:
3577 b43_chip_exit(dev);
3578 err_kfree_tssitbl:
3579 if (phy->dyn_tssi_tbl)
3580 kfree(phy->tssi2dbm);
3581 err_kfree_lo_control:
3582 kfree(phy->lo_control);
3583 phy->lo_control = NULL;
3584 err_busdown:
3585 ssb_bus_may_powerdown(bus);
3586 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3587 return err;
3588 }
3589
3590 static int b43_op_add_interface(struct ieee80211_hw *hw,
3591 struct ieee80211_if_init_conf *conf)
3592 {
3593 struct b43_wl *wl = hw_to_b43_wl(hw);
3594 struct b43_wldev *dev;
3595 unsigned long flags;
3596 int err = -EOPNOTSUPP;
3597
3598 /* TODO: allow WDS/AP devices to coexist */
3599
3600 if (conf->type != IEEE80211_IF_TYPE_AP &&
3601 conf->type != IEEE80211_IF_TYPE_STA &&
3602 conf->type != IEEE80211_IF_TYPE_WDS &&
3603 conf->type != IEEE80211_IF_TYPE_IBSS)
3604 return -EOPNOTSUPP;
3605
3606 mutex_lock(&wl->mutex);
3607 if (wl->operating)
3608 goto out_mutex_unlock;
3609
3610 b43dbg(wl, "Adding Interface type %d\n", conf->type);
3611
3612 dev = wl->current_dev;
3613 wl->operating = 1;
3614 wl->vif = conf->vif;
3615 wl->if_type = conf->type;
3616 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
3617
3618 spin_lock_irqsave(&wl->irq_lock, flags);
3619 b43_adjust_opmode(dev);
3620 b43_upload_card_macaddress(dev);
3621 spin_unlock_irqrestore(&wl->irq_lock, flags);
3622
3623 err = 0;
3624 out_mutex_unlock:
3625 mutex_unlock(&wl->mutex);
3626
3627 return err;
3628 }
3629
3630 static void b43_op_remove_interface(struct ieee80211_hw *hw,
3631 struct ieee80211_if_init_conf *conf)
3632 {
3633 struct b43_wl *wl = hw_to_b43_wl(hw);
3634 struct b43_wldev *dev = wl->current_dev;
3635 unsigned long flags;
3636
3637 b43dbg(wl, "Removing Interface type %d\n", conf->type);
3638
3639 mutex_lock(&wl->mutex);
3640
3641 B43_WARN_ON(!wl->operating);
3642 B43_WARN_ON(wl->vif != conf->vif);
3643 wl->vif = NULL;
3644
3645 wl->operating = 0;
3646
3647 spin_lock_irqsave(&wl->irq_lock, flags);
3648 b43_adjust_opmode(dev);
3649 memset(wl->mac_addr, 0, ETH_ALEN);
3650 b43_upload_card_macaddress(dev);
3651 spin_unlock_irqrestore(&wl->irq_lock, flags);
3652
3653 mutex_unlock(&wl->mutex);
3654 }
3655
3656 static int b43_op_start(struct ieee80211_hw *hw)
3657 {
3658 struct b43_wl *wl = hw_to_b43_wl(hw);
3659 struct b43_wldev *dev = wl->current_dev;
3660 int did_init = 0;
3661 int err = 0;
3662 bool do_rfkill_exit = 0;
3663
3664 /* Kill all old instance specific information to make sure
3665 * the card won't use it in the short timeframe between start
3666 * and mac80211 reconfiguring it. */
3667 memset(wl->bssid, 0, ETH_ALEN);
3668 memset(wl->mac_addr, 0, ETH_ALEN);
3669 wl->filter_flags = 0;
3670 wl->radiotap_enabled = 0;
3671
3672 /* First register RFkill.
3673 * LEDs that are registered later depend on it. */
3674 b43_rfkill_init(dev);
3675
3676 mutex_lock(&wl->mutex);
3677
3678 if (b43_status(dev) < B43_STAT_INITIALIZED) {
3679 err = b43_wireless_core_init(dev);
3680 if (err) {
3681 do_rfkill_exit = 1;
3682 goto out_mutex_unlock;
3683 }
3684 did_init = 1;
3685 }
3686
3687 if (b43_status(dev) < B43_STAT_STARTED) {
3688 err = b43_wireless_core_start(dev);
3689 if (err) {
3690 if (did_init)
3691 b43_wireless_core_exit(dev);
3692 do_rfkill_exit = 1;
3693 goto out_mutex_unlock;
3694 }
3695 }
3696
3697 out_mutex_unlock:
3698 mutex_unlock(&wl->mutex);
3699
3700 if (do_rfkill_exit)
3701 b43_rfkill_exit(dev);
3702
3703 return err;
3704 }
3705
3706 static void b43_op_stop(struct ieee80211_hw *hw)
3707 {
3708 struct b43_wl *wl = hw_to_b43_wl(hw);
3709 struct b43_wldev *dev = wl->current_dev;
3710
3711 b43_rfkill_exit(dev);
3712
3713 mutex_lock(&wl->mutex);
3714 if (b43_status(dev) >= B43_STAT_STARTED)
3715 b43_wireless_core_stop(dev);
3716 b43_wireless_core_exit(dev);
3717 mutex_unlock(&wl->mutex);
3718 }
3719
3720 static int b43_op_set_retry_limit(struct ieee80211_hw *hw,
3721 u32 short_retry_limit, u32 long_retry_limit)
3722 {
3723 struct b43_wl *wl = hw_to_b43_wl(hw);
3724 struct b43_wldev *dev;
3725 int err = 0;
3726
3727 mutex_lock(&wl->mutex);
3728 dev = wl->current_dev;
3729 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) {
3730 err = -ENODEV;
3731 goto out_unlock;
3732 }
3733 b43_set_retry_limits(dev, short_retry_limit, long_retry_limit);
3734 out_unlock:
3735 mutex_unlock(&wl->mutex);
3736
3737 return err;
3738 }
3739
3740 static int b43_op_beacon_set_tim(struct ieee80211_hw *hw, int aid, int set)
3741 {
3742 struct b43_wl *wl = hw_to_b43_wl(hw);
3743 struct sk_buff *beacon;
3744 unsigned long flags;
3745
3746 /* We could modify the existing beacon and set the aid bit in
3747 * the TIM field, but that would probably require resizing and
3748 * moving of data within the beacon template.
3749 * Simply request a new beacon and let mac80211 do the hard work. */
3750 beacon = ieee80211_beacon_get(hw, wl->vif, NULL);
3751 if (unlikely(!beacon))
3752 return -ENOMEM;
3753 spin_lock_irqsave(&wl->irq_lock, flags);
3754 b43_update_templates(wl, beacon);
3755 spin_unlock_irqrestore(&wl->irq_lock, flags);
3756
3757 return 0;
3758 }
3759
3760 static int b43_op_ibss_beacon_update(struct ieee80211_hw *hw,
3761 struct sk_buff *beacon,
3762 struct ieee80211_tx_control *ctl)
3763 {
3764 struct b43_wl *wl = hw_to_b43_wl(hw);
3765 unsigned long flags;
3766
3767 spin_lock_irqsave(&wl->irq_lock, flags);
3768 b43_update_templates(wl, beacon);
3769 spin_unlock_irqrestore(&wl->irq_lock, flags);
3770
3771 return 0;
3772 }
3773
3774 static const struct ieee80211_ops b43_hw_ops = {
3775 .tx = b43_op_tx,
3776 .conf_tx = b43_op_conf_tx,
3777 .add_interface = b43_op_add_interface,
3778 .remove_interface = b43_op_remove_interface,
3779 .config = b43_op_config,
3780 .config_interface = b43_op_config_interface,
3781 .configure_filter = b43_op_configure_filter,
3782 .set_key = b43_op_set_key,
3783 .get_stats = b43_op_get_stats,
3784 .get_tx_stats = b43_op_get_tx_stats,
3785 .start = b43_op_start,
3786 .stop = b43_op_stop,
3787 .set_retry_limit = b43_op_set_retry_limit,
3788 .set_tim = b43_op_beacon_set_tim,
3789 .beacon_update = b43_op_ibss_beacon_update,
3790 };
3791
3792 /* Hard-reset the chip. Do not call this directly.
3793 * Use b43_controller_restart()
3794 */
3795 static void b43_chip_reset(struct work_struct *work)
3796 {
3797 struct b43_wldev *dev =
3798 container_of(work, struct b43_wldev, restart_work);
3799 struct b43_wl *wl = dev->wl;
3800 int err = 0;
3801 int prev_status;
3802
3803 mutex_lock(&wl->mutex);
3804
3805 prev_status = b43_status(dev);
3806 /* Bring the device down... */
3807 if (prev_status >= B43_STAT_STARTED)
3808 b43_wireless_core_stop(dev);
3809 if (prev_status >= B43_STAT_INITIALIZED)
3810 b43_wireless_core_exit(dev);
3811
3812 /* ...and up again. */
3813 if (prev_status >= B43_STAT_INITIALIZED) {
3814 err = b43_wireless_core_init(dev);
3815 if (err)
3816 goto out;
3817 }
3818 if (prev_status >= B43_STAT_STARTED) {
3819 err = b43_wireless_core_start(dev);
3820 if (err) {
3821 b43_wireless_core_exit(dev);
3822 goto out;
3823 }
3824 }
3825 out:
3826 if (err)
3827 wl->current_dev = NULL; /* Failed to init the dev. */
3828 mutex_unlock(&wl->mutex);
3829 if (err)
3830 b43err(wl, "Controller restart FAILED\n");
3831 else
3832 b43info(wl, "Controller restarted\n");
3833 }
3834
3835 static int b43_setup_modes(struct b43_wldev *dev,
3836 bool have_2ghz_phy, bool have_5ghz_phy)
3837 {
3838 struct ieee80211_hw *hw = dev->wl->hw;
3839 struct ieee80211_hw_mode *mode;
3840 struct b43_phy *phy = &dev->phy;
3841 int err;
3842
3843 /* XXX: This function will go away soon, when mac80211
3844 * band stuff is rewritten. So this is just a hack.
3845 * For now we always claim GPHY mode, as there is no
3846 * support for NPHY and APHY in the device, yet.
3847 * This assumption is OK, as any B, N or A PHY will already
3848 * have died a horrible sanity check death earlier. */
3849
3850 mode = &phy->hwmodes[0];
3851 mode->mode = MODE_IEEE80211G;
3852 mode->num_channels = b43_2ghz_chantable_size;
3853 mode->channels = b43_2ghz_chantable;
3854 mode->num_rates = b43_g_ratetable_size;
3855 mode->rates = b43_g_ratetable;
3856 err = ieee80211_register_hwmode(hw, mode);
3857 if (err)
3858 return err;
3859 phy->possible_phymodes |= B43_PHYMODE_G;
3860
3861 return 0;
3862 }
3863
3864 static void b43_wireless_core_detach(struct b43_wldev *dev)
3865 {
3866 /* We release firmware that late to not be required to re-request
3867 * is all the time when we reinit the core. */
3868 b43_release_firmware(dev);
3869 }
3870
3871 static int b43_wireless_core_attach(struct b43_wldev *dev)
3872 {
3873 struct b43_wl *wl = dev->wl;
3874 struct ssb_bus *bus = dev->dev->bus;
3875 struct pci_dev *pdev = bus->host_pci;
3876 int err;
3877 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
3878 u32 tmp;
3879
3880 /* Do NOT do any device initialization here.
3881 * Do it in wireless_core_init() instead.
3882 * This function is for gathering basic information about the HW, only.
3883 * Also some structs may be set up here. But most likely you want to have
3884 * that in core_init(), too.
3885 */
3886
3887 err = ssb_bus_powerup(bus, 0);
3888 if (err) {
3889 b43err(wl, "Bus powerup failed\n");
3890 goto out;
3891 }
3892 /* Get the PHY type. */
3893 if (dev->dev->id.revision >= 5) {
3894 u32 tmshigh;
3895
3896 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
3897 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
3898 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
3899 } else
3900 B43_WARN_ON(1);
3901
3902 dev->phy.gmode = have_2ghz_phy;
3903 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3904 b43_wireless_core_reset(dev, tmp);
3905
3906 err = b43_phy_versioning(dev);
3907 if (err)
3908 goto err_powerdown;
3909 /* Check if this device supports multiband. */
3910 if (!pdev ||
3911 (pdev->device != 0x4312 &&
3912 pdev->device != 0x4319 && pdev->device != 0x4324)) {
3913 /* No multiband support. */
3914 have_2ghz_phy = 0;
3915 have_5ghz_phy = 0;
3916 switch (dev->phy.type) {
3917 case B43_PHYTYPE_A:
3918 have_5ghz_phy = 1;
3919 break;
3920 case B43_PHYTYPE_G:
3921 case B43_PHYTYPE_N:
3922 have_2ghz_phy = 1;
3923 break;
3924 default:
3925 B43_WARN_ON(1);
3926 }
3927 }
3928 if (dev->phy.type == B43_PHYTYPE_A) {
3929 /* FIXME */
3930 b43err(wl, "IEEE 802.11a devices are unsupported\n");
3931 err = -EOPNOTSUPP;
3932 goto err_powerdown;
3933 }
3934 if (1 /* disable A-PHY */) {
3935 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
3936 if (dev->phy.type != B43_PHYTYPE_N) {
3937 have_2ghz_phy = 1;
3938 have_5ghz_phy = 0;
3939 }
3940 }
3941
3942 dev->phy.gmode = have_2ghz_phy;
3943 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3944 b43_wireless_core_reset(dev, tmp);
3945
3946 err = b43_validate_chipaccess(dev);
3947 if (err)
3948 goto err_powerdown;
3949 err = b43_setup_modes(dev, have_2ghz_phy, have_5ghz_phy);
3950 if (err)
3951 goto err_powerdown;
3952
3953 /* Now set some default "current_dev" */
3954 if (!wl->current_dev)
3955 wl->current_dev = dev;
3956 INIT_WORK(&dev->restart_work, b43_chip_reset);
3957
3958 b43_radio_turn_off(dev, 1);
3959 b43_switch_analog(dev, 0);
3960 ssb_device_disable(dev->dev, 0);
3961 ssb_bus_may_powerdown(bus);
3962
3963 out:
3964 return err;
3965
3966 err_powerdown:
3967 ssb_bus_may_powerdown(bus);
3968 return err;
3969 }
3970
3971 static void b43_one_core_detach(struct ssb_device *dev)
3972 {
3973 struct b43_wldev *wldev;
3974 struct b43_wl *wl;
3975
3976 /* Do not cancel ieee80211-workqueue based work here.
3977 * See comment in b43_remove(). */
3978
3979 wldev = ssb_get_drvdata(dev);
3980 wl = wldev->wl;
3981 b43_debugfs_remove_device(wldev);
3982 b43_wireless_core_detach(wldev);
3983 list_del(&wldev->list);
3984 wl->nr_devs--;
3985 ssb_set_drvdata(dev, NULL);
3986 kfree(wldev);
3987 }
3988
3989 static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
3990 {
3991 struct b43_wldev *wldev;
3992 struct pci_dev *pdev;
3993 int err = -ENOMEM;
3994
3995 if (!list_empty(&wl->devlist)) {
3996 /* We are not the first core on this chip. */
3997 pdev = dev->bus->host_pci;
3998 /* Only special chips support more than one wireless
3999 * core, although some of the other chips have more than
4000 * one wireless core as well. Check for this and
4001 * bail out early.
4002 */
4003 if (!pdev ||
4004 ((pdev->device != 0x4321) &&
4005 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
4006 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
4007 return -ENODEV;
4008 }
4009 }
4010
4011 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
4012 if (!wldev)
4013 goto out;
4014
4015 wldev->dev = dev;
4016 wldev->wl = wl;
4017 b43_set_status(wldev, B43_STAT_UNINIT);
4018 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
4019 tasklet_init(&wldev->isr_tasklet,
4020 (void (*)(unsigned long))b43_interrupt_tasklet,
4021 (unsigned long)wldev);
4022 INIT_LIST_HEAD(&wldev->list);
4023
4024 err = b43_wireless_core_attach(wldev);
4025 if (err)
4026 goto err_kfree_wldev;
4027
4028 list_add(&wldev->list, &wl->devlist);
4029 wl->nr_devs++;
4030 ssb_set_drvdata(dev, wldev);
4031 b43_debugfs_add_device(wldev);
4032
4033 out:
4034 return err;
4035
4036 err_kfree_wldev:
4037 kfree(wldev);
4038 return err;
4039 }
4040
4041 #define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
4042 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
4043 (pdev->device == _device) && \
4044 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
4045 (pdev->subsystem_device == _subdevice) )
4046
4047 static void b43_sprom_fixup(struct ssb_bus *bus)
4048 {
4049 struct pci_dev *pdev;
4050
4051 /* boardflags workarounds */
4052 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
4053 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
4054 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
4055 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
4056 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
4057 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
4058 if (bus->bustype == SSB_BUSTYPE_PCI) {
4059 pdev = bus->host_pci;
4060 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
4061 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
4062 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013))
4063 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
4064 }
4065 }
4066
4067 static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
4068 {
4069 struct ieee80211_hw *hw = wl->hw;
4070
4071 ssb_set_devtypedata(dev, NULL);
4072 ieee80211_free_hw(hw);
4073 }
4074
4075 static int b43_wireless_init(struct ssb_device *dev)
4076 {
4077 struct ssb_sprom *sprom = &dev->bus->sprom;
4078 struct ieee80211_hw *hw;
4079 struct b43_wl *wl;
4080 int err = -ENOMEM;
4081
4082 b43_sprom_fixup(dev->bus);
4083
4084 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
4085 if (!hw) {
4086 b43err(NULL, "Could not allocate ieee80211 device\n");
4087 goto out;
4088 }
4089
4090 /* fill hw info */
4091 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
4092 IEEE80211_HW_RX_INCLUDES_FCS;
4093 hw->max_signal = 100;
4094 hw->max_rssi = -110;
4095 hw->max_noise = -110;
4096 hw->queues = 1; /* FIXME: hardware has more queues */
4097 SET_IEEE80211_DEV(hw, dev->dev);
4098 if (is_valid_ether_addr(sprom->et1mac))
4099 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
4100 else
4101 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
4102
4103 /* Get and initialize struct b43_wl */
4104 wl = hw_to_b43_wl(hw);
4105 memset(wl, 0, sizeof(*wl));
4106 wl->hw = hw;
4107 spin_lock_init(&wl->irq_lock);
4108 rwlock_init(&wl->tx_lock);
4109 spin_lock_init(&wl->leds_lock);
4110 spin_lock_init(&wl->shm_lock);
4111 mutex_init(&wl->mutex);
4112 INIT_LIST_HEAD(&wl->devlist);
4113
4114 ssb_set_devtypedata(dev, wl);
4115 b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
4116 err = 0;
4117 out:
4118 return err;
4119 }
4120
4121 static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
4122 {
4123 struct b43_wl *wl;
4124 int err;
4125 int first = 0;
4126
4127 wl = ssb_get_devtypedata(dev);
4128 if (!wl) {
4129 /* Probing the first core. Must setup common struct b43_wl */
4130 first = 1;
4131 err = b43_wireless_init(dev);
4132 if (err)
4133 goto out;
4134 wl = ssb_get_devtypedata(dev);
4135 B43_WARN_ON(!wl);
4136 }
4137 err = b43_one_core_attach(dev, wl);
4138 if (err)
4139 goto err_wireless_exit;
4140
4141 if (first) {
4142 err = ieee80211_register_hw(wl->hw);
4143 if (err)
4144 goto err_one_core_detach;
4145 }
4146
4147 out:
4148 return err;
4149
4150 err_one_core_detach:
4151 b43_one_core_detach(dev);
4152 err_wireless_exit:
4153 if (first)
4154 b43_wireless_exit(dev, wl);
4155 return err;
4156 }
4157
4158 static void b43_remove(struct ssb_device *dev)
4159 {
4160 struct b43_wl *wl = ssb_get_devtypedata(dev);
4161 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4162
4163 /* We must cancel any work here before unregistering from ieee80211,
4164 * as the ieee80211 unreg will destroy the workqueue. */
4165 cancel_work_sync(&wldev->restart_work);
4166
4167 B43_WARN_ON(!wl);
4168 if (wl->current_dev == wldev)
4169 ieee80211_unregister_hw(wl->hw);
4170
4171 b43_one_core_detach(dev);
4172
4173 if (list_empty(&wl->devlist)) {
4174 /* Last core on the chip unregistered.
4175 * We can destroy common struct b43_wl.
4176 */
4177 b43_wireless_exit(dev, wl);
4178 }
4179 }
4180
4181 /* Perform a hardware reset. This can be called from any context. */
4182 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
4183 {
4184 /* Must avoid requeueing, if we are in shutdown. */
4185 if (b43_status(dev) < B43_STAT_INITIALIZED)
4186 return;
4187 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
4188 queue_work(dev->wl->hw->workqueue, &dev->restart_work);
4189 }
4190
4191 #ifdef CONFIG_PM
4192
4193 static int b43_suspend(struct ssb_device *dev, pm_message_t state)
4194 {
4195 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4196 struct b43_wl *wl = wldev->wl;
4197
4198 b43dbg(wl, "Suspending...\n");
4199
4200 mutex_lock(&wl->mutex);
4201 wldev->suspend_in_progress = true;
4202 wldev->suspend_init_status = b43_status(wldev);
4203 if (wldev->suspend_init_status >= B43_STAT_STARTED)
4204 b43_wireless_core_stop(wldev);
4205 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
4206 b43_wireless_core_exit(wldev);
4207 mutex_unlock(&wl->mutex);
4208
4209 b43dbg(wl, "Device suspended.\n");
4210
4211 return 0;
4212 }
4213
4214 static int b43_resume(struct ssb_device *dev)
4215 {
4216 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4217 struct b43_wl *wl = wldev->wl;
4218 int err = 0;
4219
4220 b43dbg(wl, "Resuming...\n");
4221
4222 mutex_lock(&wl->mutex);
4223 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4224 err = b43_wireless_core_init(wldev);
4225 if (err) {
4226 b43err(wl, "Resume failed at core init\n");
4227 goto out;
4228 }
4229 }
4230 if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4231 err = b43_wireless_core_start(wldev);
4232 if (err) {
4233 b43_leds_exit(wldev);
4234 b43_rng_exit(wldev->wl, true);
4235 b43_wireless_core_exit(wldev);
4236 b43err(wl, "Resume failed at core start\n");
4237 goto out;
4238 }
4239 }
4240 b43dbg(wl, "Device resumed.\n");
4241 out:
4242 wldev->suspend_in_progress = false;
4243 mutex_unlock(&wl->mutex);
4244 return err;
4245 }
4246
4247 #else /* CONFIG_PM */
4248 # define b43_suspend NULL
4249 # define b43_resume NULL
4250 #endif /* CONFIG_PM */
4251
4252 static struct ssb_driver b43_ssb_driver = {
4253 .name = KBUILD_MODNAME,
4254 .id_table = b43_ssb_tbl,
4255 .probe = b43_probe,
4256 .remove = b43_remove,
4257 .suspend = b43_suspend,
4258 .resume = b43_resume,
4259 };
4260
4261 static void b43_print_driverinfo(void)
4262 {
4263 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
4264 *feat_leds = "", *feat_rfkill = "";
4265
4266 #ifdef CONFIG_B43_PCI_AUTOSELECT
4267 feat_pci = "P";
4268 #endif
4269 #ifdef CONFIG_B43_PCMCIA
4270 feat_pcmcia = "M";
4271 #endif
4272 #ifdef CONFIG_B43_NPHY
4273 feat_nphy = "N";
4274 #endif
4275 #ifdef CONFIG_B43_LEDS
4276 feat_leds = "L";
4277 #endif
4278 #ifdef CONFIG_B43_RFKILL
4279 feat_rfkill = "R";
4280 #endif
4281 printk(KERN_INFO "Broadcom 43xx driver loaded "
4282 "[ Features: %s%s%s%s%s, Firmware-ID: "
4283 B43_SUPPORTED_FIRMWARE_ID " ]\n",
4284 feat_pci, feat_pcmcia, feat_nphy,
4285 feat_leds, feat_rfkill);
4286 }
4287
4288 static int __init b43_init(void)
4289 {
4290 int err;
4291
4292 b43_debugfs_init();
4293 err = b43_pcmcia_init();
4294 if (err)
4295 goto err_dfs_exit;
4296 err = ssb_driver_register(&b43_ssb_driver);
4297 if (err)
4298 goto err_pcmcia_exit;
4299 b43_print_driverinfo();
4300
4301 return err;
4302
4303 err_pcmcia_exit:
4304 b43_pcmcia_exit();
4305 err_dfs_exit:
4306 b43_debugfs_exit();
4307 return err;
4308 }
4309
4310 static void __exit b43_exit(void)
4311 {
4312 ssb_driver_unregister(&b43_ssb_driver);
4313 b43_pcmcia_exit();
4314 b43_debugfs_exit();
4315 }
4316
4317 module_init(b43_init)
4318 module_exit(b43_exit)
4319
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