1 /*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005-2009 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
13
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
18
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
23
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
28
29 */
30
31 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/moduleparam.h>
34 #include <linux/if_arp.h>
35 #include <linux/etherdevice.h>
36 #include <linux/firmware.h>
37 #include <linux/wireless.h>
38 #include <linux/workqueue.h>
39 #include <linux/skbuff.h>
40 #include <linux/io.h>
41 #include <linux/dma-mapping.h>
42 #include <asm/unaligned.h>
43
44 #include "b43.h"
45 #include "main.h"
46 #include "debugfs.h"
47 #include "phy_common.h"
48 #include "phy_g.h"
49 #include "phy_n.h"
50 #include "dma.h"
51 #include "pio.h"
52 #include "sysfs.h"
53 #include "xmit.h"
54 #include "lo.h"
55 #include "pcmcia.h"
56
57 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
58 MODULE_AUTHOR("Martin Langer");
59 MODULE_AUTHOR("Stefano Brivio");
60 MODULE_AUTHOR("Michael Buesch");
61 MODULE_LICENSE("GPL");
62
63 MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID);
64
65
66 static int modparam_bad_frames_preempt;
67 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
68 MODULE_PARM_DESC(bad_frames_preempt,
69 "enable(1) / disable(0) Bad Frames Preemption");
70
71 static char modparam_fwpostfix[16];
72 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
73 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
74
75 static int modparam_hwpctl;
76 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
77 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
78
79 static int modparam_nohwcrypt;
80 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
81 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
82
83 static int modparam_qos = 1;
84 module_param_named(qos, modparam_qos, int, 0444);
85 MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
86
87 static int modparam_btcoex = 1;
88 module_param_named(btcoex, modparam_btcoex, int, 0444);
89 MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistance (default on)");
90
91 int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
92 module_param_named(verbose, b43_modparam_verbose, int, 0644);
93 MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
94
95
96 static const struct ssb_device_id b43_ssb_tbl[] = {
97 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
98 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
99 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
100 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
101 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
102 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
103 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
104 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
105 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
106 SSB_DEVTABLE_END
107 };
108
109 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
110
111 /* Channel and ratetables are shared for all devices.
112 * They can't be const, because ieee80211 puts some precalculated
113 * data in there. This data is the same for all devices, so we don't
114 * get concurrency issues */
115 #define RATETAB_ENT(_rateid, _flags) \
116 { \
117 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
118 .hw_value = (_rateid), \
119 .flags = (_flags), \
120 }
121
122 /*
123 * NOTE: When changing this, sync with xmit.c's
124 * b43_plcp_get_bitrate_idx_* functions!
125 */
126 static struct ieee80211_rate __b43_ratetable[] = {
127 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
128 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
129 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
130 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
131 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
132 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
133 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
134 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
135 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
136 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
137 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
138 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
139 };
140
141 #define b43_a_ratetable (__b43_ratetable + 4)
142 #define b43_a_ratetable_size 8
143 #define b43_b_ratetable (__b43_ratetable + 0)
144 #define b43_b_ratetable_size 4
145 #define b43_g_ratetable (__b43_ratetable + 0)
146 #define b43_g_ratetable_size 12
147
148 #define CHAN4G(_channel, _freq, _flags) { \
149 .band = IEEE80211_BAND_2GHZ, \
150 .center_freq = (_freq), \
151 .hw_value = (_channel), \
152 .flags = (_flags), \
153 .max_antenna_gain = 0, \
154 .max_power = 30, \
155 }
156 static struct ieee80211_channel b43_2ghz_chantable[] = {
157 CHAN4G(1, 2412, 0),
158 CHAN4G(2, 2417, 0),
159 CHAN4G(3, 2422, 0),
160 CHAN4G(4, 2427, 0),
161 CHAN4G(5, 2432, 0),
162 CHAN4G(6, 2437, 0),
163 CHAN4G(7, 2442, 0),
164 CHAN4G(8, 2447, 0),
165 CHAN4G(9, 2452, 0),
166 CHAN4G(10, 2457, 0),
167 CHAN4G(11, 2462, 0),
168 CHAN4G(12, 2467, 0),
169 CHAN4G(13, 2472, 0),
170 CHAN4G(14, 2484, 0),
171 };
172 #undef CHAN4G
173
174 #define CHAN5G(_channel, _flags) { \
175 .band = IEEE80211_BAND_5GHZ, \
176 .center_freq = 5000 + (5 * (_channel)), \
177 .hw_value = (_channel), \
178 .flags = (_flags), \
179 .max_antenna_gain = 0, \
180 .max_power = 30, \
181 }
182 static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
183 CHAN5G(32, 0), CHAN5G(34, 0),
184 CHAN5G(36, 0), CHAN5G(38, 0),
185 CHAN5G(40, 0), CHAN5G(42, 0),
186 CHAN5G(44, 0), CHAN5G(46, 0),
187 CHAN5G(48, 0), CHAN5G(50, 0),
188 CHAN5G(52, 0), CHAN5G(54, 0),
189 CHAN5G(56, 0), CHAN5G(58, 0),
190 CHAN5G(60, 0), CHAN5G(62, 0),
191 CHAN5G(64, 0), CHAN5G(66, 0),
192 CHAN5G(68, 0), CHAN5G(70, 0),
193 CHAN5G(72, 0), CHAN5G(74, 0),
194 CHAN5G(76, 0), CHAN5G(78, 0),
195 CHAN5G(80, 0), CHAN5G(82, 0),
196 CHAN5G(84, 0), CHAN5G(86, 0),
197 CHAN5G(88, 0), CHAN5G(90, 0),
198 CHAN5G(92, 0), CHAN5G(94, 0),
199 CHAN5G(96, 0), CHAN5G(98, 0),
200 CHAN5G(100, 0), CHAN5G(102, 0),
201 CHAN5G(104, 0), CHAN5G(106, 0),
202 CHAN5G(108, 0), CHAN5G(110, 0),
203 CHAN5G(112, 0), CHAN5G(114, 0),
204 CHAN5G(116, 0), CHAN5G(118, 0),
205 CHAN5G(120, 0), CHAN5G(122, 0),
206 CHAN5G(124, 0), CHAN5G(126, 0),
207 CHAN5G(128, 0), CHAN5G(130, 0),
208 CHAN5G(132, 0), CHAN5G(134, 0),
209 CHAN5G(136, 0), CHAN5G(138, 0),
210 CHAN5G(140, 0), CHAN5G(142, 0),
211 CHAN5G(144, 0), CHAN5G(145, 0),
212 CHAN5G(146, 0), CHAN5G(147, 0),
213 CHAN5G(148, 0), CHAN5G(149, 0),
214 CHAN5G(150, 0), CHAN5G(151, 0),
215 CHAN5G(152, 0), CHAN5G(153, 0),
216 CHAN5G(154, 0), CHAN5G(155, 0),
217 CHAN5G(156, 0), CHAN5G(157, 0),
218 CHAN5G(158, 0), CHAN5G(159, 0),
219 CHAN5G(160, 0), CHAN5G(161, 0),
220 CHAN5G(162, 0), CHAN5G(163, 0),
221 CHAN5G(164, 0), CHAN5G(165, 0),
222 CHAN5G(166, 0), CHAN5G(168, 0),
223 CHAN5G(170, 0), CHAN5G(172, 0),
224 CHAN5G(174, 0), CHAN5G(176, 0),
225 CHAN5G(178, 0), CHAN5G(180, 0),
226 CHAN5G(182, 0), CHAN5G(184, 0),
227 CHAN5G(186, 0), CHAN5G(188, 0),
228 CHAN5G(190, 0), CHAN5G(192, 0),
229 CHAN5G(194, 0), CHAN5G(196, 0),
230 CHAN5G(198, 0), CHAN5G(200, 0),
231 CHAN5G(202, 0), CHAN5G(204, 0),
232 CHAN5G(206, 0), CHAN5G(208, 0),
233 CHAN5G(210, 0), CHAN5G(212, 0),
234 CHAN5G(214, 0), CHAN5G(216, 0),
235 CHAN5G(218, 0), CHAN5G(220, 0),
236 CHAN5G(222, 0), CHAN5G(224, 0),
237 CHAN5G(226, 0), CHAN5G(228, 0),
238 };
239
240 static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
241 CHAN5G(34, 0), CHAN5G(36, 0),
242 CHAN5G(38, 0), CHAN5G(40, 0),
243 CHAN5G(42, 0), CHAN5G(44, 0),
244 CHAN5G(46, 0), CHAN5G(48, 0),
245 CHAN5G(52, 0), CHAN5G(56, 0),
246 CHAN5G(60, 0), CHAN5G(64, 0),
247 CHAN5G(100, 0), CHAN5G(104, 0),
248 CHAN5G(108, 0), CHAN5G(112, 0),
249 CHAN5G(116, 0), CHAN5G(120, 0),
250 CHAN5G(124, 0), CHAN5G(128, 0),
251 CHAN5G(132, 0), CHAN5G(136, 0),
252 CHAN5G(140, 0), CHAN5G(149, 0),
253 CHAN5G(153, 0), CHAN5G(157, 0),
254 CHAN5G(161, 0), CHAN5G(165, 0),
255 CHAN5G(184, 0), CHAN5G(188, 0),
256 CHAN5G(192, 0), CHAN5G(196, 0),
257 CHAN5G(200, 0), CHAN5G(204, 0),
258 CHAN5G(208, 0), CHAN5G(212, 0),
259 CHAN5G(216, 0),
260 };
261 #undef CHAN5G
262
263 static struct ieee80211_supported_band b43_band_5GHz_nphy = {
264 .band = IEEE80211_BAND_5GHZ,
265 .channels = b43_5ghz_nphy_chantable,
266 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
267 .bitrates = b43_a_ratetable,
268 .n_bitrates = b43_a_ratetable_size,
269 };
270
271 static struct ieee80211_supported_band b43_band_5GHz_aphy = {
272 .band = IEEE80211_BAND_5GHZ,
273 .channels = b43_5ghz_aphy_chantable,
274 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
275 .bitrates = b43_a_ratetable,
276 .n_bitrates = b43_a_ratetable_size,
277 };
278
279 static struct ieee80211_supported_band b43_band_2GHz = {
280 .band = IEEE80211_BAND_2GHZ,
281 .channels = b43_2ghz_chantable,
282 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
283 .bitrates = b43_g_ratetable,
284 .n_bitrates = b43_g_ratetable_size,
285 };
286
287 static void b43_wireless_core_exit(struct b43_wldev *dev);
288 static int b43_wireless_core_init(struct b43_wldev *dev);
289 static void b43_wireless_core_stop(struct b43_wldev *dev);
290 static int b43_wireless_core_start(struct b43_wldev *dev);
291
292 static int b43_ratelimit(struct b43_wl *wl)
293 {
294 if (!wl || !wl->current_dev)
295 return 1;
296 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
297 return 1;
298 /* We are up and running.
299 * Ratelimit the messages to avoid DoS over the net. */
300 return net_ratelimit();
301 }
302
303 void b43info(struct b43_wl *wl, const char *fmt, ...)
304 {
305 va_list args;
306
307 if (b43_modparam_verbose < B43_VERBOSITY_INFO)
308 return;
309 if (!b43_ratelimit(wl))
310 return;
311 va_start(args, fmt);
312 printk(KERN_INFO "b43-%s: ",
313 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
314 vprintk(fmt, args);
315 va_end(args);
316 }
317
318 void b43err(struct b43_wl *wl, const char *fmt, ...)
319 {
320 va_list args;
321
322 if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
323 return;
324 if (!b43_ratelimit(wl))
325 return;
326 va_start(args, fmt);
327 printk(KERN_ERR "b43-%s ERROR: ",
328 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
329 vprintk(fmt, args);
330 va_end(args);
331 }
332
333 void b43warn(struct b43_wl *wl, const char *fmt, ...)
334 {
335 va_list args;
336
337 if (b43_modparam_verbose < B43_VERBOSITY_WARN)
338 return;
339 if (!b43_ratelimit(wl))
340 return;
341 va_start(args, fmt);
342 printk(KERN_WARNING "b43-%s warning: ",
343 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
344 vprintk(fmt, args);
345 va_end(args);
346 }
347
348 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
349 {
350 va_list args;
351
352 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
353 return;
354 va_start(args, fmt);
355 printk(KERN_DEBUG "b43-%s debug: ",
356 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
357 vprintk(fmt, args);
358 va_end(args);
359 }
360
361 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
362 {
363 u32 macctl;
364
365 B43_WARN_ON(offset % 4 != 0);
366
367 macctl = b43_read32(dev, B43_MMIO_MACCTL);
368 if (macctl & B43_MACCTL_BE)
369 val = swab32(val);
370
371 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
372 mmiowb();
373 b43_write32(dev, B43_MMIO_RAM_DATA, val);
374 }
375
376 static inline void b43_shm_control_word(struct b43_wldev *dev,
377 u16 routing, u16 offset)
378 {
379 u32 control;
380
381 /* "offset" is the WORD offset. */
382 control = routing;
383 control <<= 16;
384 control |= offset;
385 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
386 }
387
388 u32 __b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
389 {
390 u32 ret;
391
392 if (routing == B43_SHM_SHARED) {
393 B43_WARN_ON(offset & 0x0001);
394 if (offset & 0x0003) {
395 /* Unaligned access */
396 b43_shm_control_word(dev, routing, offset >> 2);
397 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
398 ret <<= 16;
399 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
400 ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
401
402 goto out;
403 }
404 offset >>= 2;
405 }
406 b43_shm_control_word(dev, routing, offset);
407 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
408 out:
409 return ret;
410 }
411
412 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
413 {
414 struct b43_wl *wl = dev->wl;
415 unsigned long flags;
416 u32 ret;
417
418 spin_lock_irqsave(&wl->shm_lock, flags);
419 ret = __b43_shm_read32(dev, routing, offset);
420 spin_unlock_irqrestore(&wl->shm_lock, flags);
421
422 return ret;
423 }
424
425 u16 __b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
426 {
427 u16 ret;
428
429 if (routing == B43_SHM_SHARED) {
430 B43_WARN_ON(offset & 0x0001);
431 if (offset & 0x0003) {
432 /* Unaligned access */
433 b43_shm_control_word(dev, routing, offset >> 2);
434 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
435
436 goto out;
437 }
438 offset >>= 2;
439 }
440 b43_shm_control_word(dev, routing, offset);
441 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
442 out:
443 return ret;
444 }
445
446 u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
447 {
448 struct b43_wl *wl = dev->wl;
449 unsigned long flags;
450 u16 ret;
451
452 spin_lock_irqsave(&wl->shm_lock, flags);
453 ret = __b43_shm_read16(dev, routing, offset);
454 spin_unlock_irqrestore(&wl->shm_lock, flags);
455
456 return ret;
457 }
458
459 void __b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
460 {
461 if (routing == B43_SHM_SHARED) {
462 B43_WARN_ON(offset & 0x0001);
463 if (offset & 0x0003) {
464 /* Unaligned access */
465 b43_shm_control_word(dev, routing, offset >> 2);
466 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
467 (value >> 16) & 0xffff);
468 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
469 b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
470 return;
471 }
472 offset >>= 2;
473 }
474 b43_shm_control_word(dev, routing, offset);
475 b43_write32(dev, B43_MMIO_SHM_DATA, value);
476 }
477
478 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
479 {
480 struct b43_wl *wl = dev->wl;
481 unsigned long flags;
482
483 spin_lock_irqsave(&wl->shm_lock, flags);
484 __b43_shm_write32(dev, routing, offset, value);
485 spin_unlock_irqrestore(&wl->shm_lock, flags);
486 }
487
488 void __b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
489 {
490 if (routing == B43_SHM_SHARED) {
491 B43_WARN_ON(offset & 0x0001);
492 if (offset & 0x0003) {
493 /* Unaligned access */
494 b43_shm_control_word(dev, routing, offset >> 2);
495 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
496 return;
497 }
498 offset >>= 2;
499 }
500 b43_shm_control_word(dev, routing, offset);
501 b43_write16(dev, B43_MMIO_SHM_DATA, value);
502 }
503
504 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
505 {
506 struct b43_wl *wl = dev->wl;
507 unsigned long flags;
508
509 spin_lock_irqsave(&wl->shm_lock, flags);
510 __b43_shm_write16(dev, routing, offset, value);
511 spin_unlock_irqrestore(&wl->shm_lock, flags);
512 }
513
514 /* Read HostFlags */
515 u64 b43_hf_read(struct b43_wldev *dev)
516 {
517 u64 ret;
518
519 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
520 ret <<= 16;
521 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
522 ret <<= 16;
523 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
524
525 return ret;
526 }
527
528 /* Write HostFlags */
529 void b43_hf_write(struct b43_wldev *dev, u64 value)
530 {
531 u16 lo, mi, hi;
532
533 lo = (value & 0x00000000FFFFULL);
534 mi = (value & 0x0000FFFF0000ULL) >> 16;
535 hi = (value & 0xFFFF00000000ULL) >> 32;
536 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
537 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
538 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
539 }
540
541 /* Read the firmware capabilities bitmask (Opensource firmware only) */
542 static u16 b43_fwcapa_read(struct b43_wldev *dev)
543 {
544 B43_WARN_ON(!dev->fw.opensource);
545 return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
546 }
547
548 void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
549 {
550 u32 low, high;
551
552 B43_WARN_ON(dev->dev->id.revision < 3);
553
554 /* The hardware guarantees us an atomic read, if we
555 * read the low register first. */
556 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
557 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
558
559 *tsf = high;
560 *tsf <<= 32;
561 *tsf |= low;
562 }
563
564 static void b43_time_lock(struct b43_wldev *dev)
565 {
566 u32 macctl;
567
568 macctl = b43_read32(dev, B43_MMIO_MACCTL);
569 macctl |= B43_MACCTL_TBTTHOLD;
570 b43_write32(dev, B43_MMIO_MACCTL, macctl);
571 /* Commit the write */
572 b43_read32(dev, B43_MMIO_MACCTL);
573 }
574
575 static void b43_time_unlock(struct b43_wldev *dev)
576 {
577 u32 macctl;
578
579 macctl = b43_read32(dev, B43_MMIO_MACCTL);
580 macctl &= ~B43_MACCTL_TBTTHOLD;
581 b43_write32(dev, B43_MMIO_MACCTL, macctl);
582 /* Commit the write */
583 b43_read32(dev, B43_MMIO_MACCTL);
584 }
585
586 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
587 {
588 u32 low, high;
589
590 B43_WARN_ON(dev->dev->id.revision < 3);
591
592 low = tsf;
593 high = (tsf >> 32);
594 /* The hardware guarantees us an atomic write, if we
595 * write the low register first. */
596 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
597 mmiowb();
598 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
599 mmiowb();
600 }
601
602 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
603 {
604 b43_time_lock(dev);
605 b43_tsf_write_locked(dev, tsf);
606 b43_time_unlock(dev);
607 }
608
609 static
610 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
611 {
612 static const u8 zero_addr[ETH_ALEN] = { 0 };
613 u16 data;
614
615 if (!mac)
616 mac = zero_addr;
617
618 offset |= 0x0020;
619 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
620
621 data = mac[0];
622 data |= mac[1] << 8;
623 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
624 data = mac[2];
625 data |= mac[3] << 8;
626 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
627 data = mac[4];
628 data |= mac[5] << 8;
629 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
630 }
631
632 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
633 {
634 const u8 *mac;
635 const u8 *bssid;
636 u8 mac_bssid[ETH_ALEN * 2];
637 int i;
638 u32 tmp;
639
640 bssid = dev->wl->bssid;
641 mac = dev->wl->mac_addr;
642
643 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
644
645 memcpy(mac_bssid, mac, ETH_ALEN);
646 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
647
648 /* Write our MAC address and BSSID to template ram */
649 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
650 tmp = (u32) (mac_bssid[i + 0]);
651 tmp |= (u32) (mac_bssid[i + 1]) << 8;
652 tmp |= (u32) (mac_bssid[i + 2]) << 16;
653 tmp |= (u32) (mac_bssid[i + 3]) << 24;
654 b43_ram_write(dev, 0x20 + i, tmp);
655 }
656 }
657
658 static void b43_upload_card_macaddress(struct b43_wldev *dev)
659 {
660 b43_write_mac_bssid_templates(dev);
661 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
662 }
663
664 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
665 {
666 /* slot_time is in usec. */
667 /* This test used to exit for all but a G PHY. */
668 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
669 return;
670 b43_write16(dev, B43_MMIO_IFSSLOT, 510 + slot_time);
671 /* Shared memory location 0x0010 is the slot time and should be
672 * set to slot_time; however, this register is initially 0 and changing
673 * the value adversely affects the transmit rate for BCM4311
674 * devices. Until this behavior is unterstood, delete this step
675 *
676 * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
677 */
678 }
679
680 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
681 {
682 b43_set_slot_time(dev, 9);
683 }
684
685 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
686 {
687 b43_set_slot_time(dev, 20);
688 }
689
690 /* Synchronize IRQ top- and bottom-half.
691 * IRQs must be masked before calling this.
692 * This must not be called with the irq_lock held.
693 */
694 static void b43_synchronize_irq(struct b43_wldev *dev)
695 {
696 synchronize_irq(dev->dev->irq);
697 tasklet_kill(&dev->isr_tasklet);
698 }
699
700 /* DummyTransmission function, as documented on
701 * http://bcm-specs.sipsolutions.net/DummyTransmission
702 */
703 void b43_dummy_transmission(struct b43_wldev *dev)
704 {
705 struct b43_wl *wl = dev->wl;
706 struct b43_phy *phy = &dev->phy;
707 unsigned int i, max_loop;
708 u16 value;
709 u32 buffer[5] = {
710 0x00000000,
711 0x00D40000,
712 0x00000000,
713 0x01000000,
714 0x00000000,
715 };
716
717 switch (phy->type) {
718 case B43_PHYTYPE_A:
719 max_loop = 0x1E;
720 buffer[0] = 0x000201CC;
721 break;
722 case B43_PHYTYPE_B:
723 case B43_PHYTYPE_G:
724 max_loop = 0xFA;
725 buffer[0] = 0x000B846E;
726 break;
727 default:
728 B43_WARN_ON(1);
729 return;
730 }
731
732 spin_lock_irq(&wl->irq_lock);
733 write_lock(&wl->tx_lock);
734
735 for (i = 0; i < 5; i++)
736 b43_ram_write(dev, i * 4, buffer[i]);
737
738 /* Commit writes */
739 b43_read32(dev, B43_MMIO_MACCTL);
740
741 b43_write16(dev, 0x0568, 0x0000);
742 b43_write16(dev, 0x07C0, 0x0000);
743 value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
744 b43_write16(dev, 0x050C, value);
745 b43_write16(dev, 0x0508, 0x0000);
746 b43_write16(dev, 0x050A, 0x0000);
747 b43_write16(dev, 0x054C, 0x0000);
748 b43_write16(dev, 0x056A, 0x0014);
749 b43_write16(dev, 0x0568, 0x0826);
750 b43_write16(dev, 0x0500, 0x0000);
751 b43_write16(dev, 0x0502, 0x0030);
752
753 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
754 b43_radio_write16(dev, 0x0051, 0x0017);
755 for (i = 0x00; i < max_loop; i++) {
756 value = b43_read16(dev, 0x050E);
757 if (value & 0x0080)
758 break;
759 udelay(10);
760 }
761 for (i = 0x00; i < 0x0A; i++) {
762 value = b43_read16(dev, 0x050E);
763 if (value & 0x0400)
764 break;
765 udelay(10);
766 }
767 for (i = 0x00; i < 0x19; i++) {
768 value = b43_read16(dev, 0x0690);
769 if (!(value & 0x0100))
770 break;
771 udelay(10);
772 }
773 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
774 b43_radio_write16(dev, 0x0051, 0x0037);
775
776 write_unlock(&wl->tx_lock);
777 spin_unlock_irq(&wl->irq_lock);
778 }
779
780 static void key_write(struct b43_wldev *dev,
781 u8 index, u8 algorithm, const u8 *key)
782 {
783 unsigned int i;
784 u32 offset;
785 u16 value;
786 u16 kidx;
787
788 /* Key index/algo block */
789 kidx = b43_kidx_to_fw(dev, index);
790 value = ((kidx << 4) | algorithm);
791 b43_shm_write16(dev, B43_SHM_SHARED,
792 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
793
794 /* Write the key to the Key Table Pointer offset */
795 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
796 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
797 value = key[i];
798 value |= (u16) (key[i + 1]) << 8;
799 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
800 }
801 }
802
803 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
804 {
805 u32 addrtmp[2] = { 0, 0, };
806 u8 per_sta_keys_start = 8;
807
808 if (b43_new_kidx_api(dev))
809 per_sta_keys_start = 4;
810
811 B43_WARN_ON(index < per_sta_keys_start);
812 /* We have two default TX keys and possibly two default RX keys.
813 * Physical mac 0 is mapped to physical key 4 or 8, depending
814 * on the firmware version.
815 * So we must adjust the index here.
816 */
817 index -= per_sta_keys_start;
818
819 if (addr) {
820 addrtmp[0] = addr[0];
821 addrtmp[0] |= ((u32) (addr[1]) << 8);
822 addrtmp[0] |= ((u32) (addr[2]) << 16);
823 addrtmp[0] |= ((u32) (addr[3]) << 24);
824 addrtmp[1] = addr[4];
825 addrtmp[1] |= ((u32) (addr[5]) << 8);
826 }
827
828 if (dev->dev->id.revision >= 5) {
829 /* Receive match transmitter address mechanism */
830 b43_shm_write32(dev, B43_SHM_RCMTA,
831 (index * 2) + 0, addrtmp[0]);
832 b43_shm_write16(dev, B43_SHM_RCMTA,
833 (index * 2) + 1, addrtmp[1]);
834 } else {
835 /* RXE (Receive Engine) and
836 * PSM (Programmable State Machine) mechanism
837 */
838 if (index < 8) {
839 /* TODO write to RCM 16, 19, 22 and 25 */
840 } else {
841 b43_shm_write32(dev, B43_SHM_SHARED,
842 B43_SHM_SH_PSM + (index * 6) + 0,
843 addrtmp[0]);
844 b43_shm_write16(dev, B43_SHM_SHARED,
845 B43_SHM_SH_PSM + (index * 6) + 4,
846 addrtmp[1]);
847 }
848 }
849 }
850
851 static void do_key_write(struct b43_wldev *dev,
852 u8 index, u8 algorithm,
853 const u8 *key, size_t key_len, const u8 *mac_addr)
854 {
855 u8 buf[B43_SEC_KEYSIZE] = { 0, };
856 u8 per_sta_keys_start = 8;
857
858 if (b43_new_kidx_api(dev))
859 per_sta_keys_start = 4;
860
861 B43_WARN_ON(index >= dev->max_nr_keys);
862 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
863
864 if (index >= per_sta_keys_start)
865 keymac_write(dev, index, NULL); /* First zero out mac. */
866 if (key)
867 memcpy(buf, key, key_len);
868 key_write(dev, index, algorithm, buf);
869 if (index >= per_sta_keys_start)
870 keymac_write(dev, index, mac_addr);
871
872 dev->key[index].algorithm = algorithm;
873 }
874
875 static int b43_key_write(struct b43_wldev *dev,
876 int index, u8 algorithm,
877 const u8 *key, size_t key_len,
878 const u8 *mac_addr,
879 struct ieee80211_key_conf *keyconf)
880 {
881 int i;
882 int sta_keys_start;
883
884 if (key_len > B43_SEC_KEYSIZE)
885 return -EINVAL;
886 for (i = 0; i < dev->max_nr_keys; i++) {
887 /* Check that we don't already have this key. */
888 B43_WARN_ON(dev->key[i].keyconf == keyconf);
889 }
890 if (index < 0) {
891 /* Pairwise key. Get an empty slot for the key. */
892 if (b43_new_kidx_api(dev))
893 sta_keys_start = 4;
894 else
895 sta_keys_start = 8;
896 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
897 if (!dev->key[i].keyconf) {
898 /* found empty */
899 index = i;
900 break;
901 }
902 }
903 if (index < 0) {
904 b43warn(dev->wl, "Out of hardware key memory\n");
905 return -ENOSPC;
906 }
907 } else
908 B43_WARN_ON(index > 3);
909
910 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
911 if ((index <= 3) && !b43_new_kidx_api(dev)) {
912 /* Default RX key */
913 B43_WARN_ON(mac_addr);
914 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
915 }
916 keyconf->hw_key_idx = index;
917 dev->key[index].keyconf = keyconf;
918
919 return 0;
920 }
921
922 static int b43_key_clear(struct b43_wldev *dev, int index)
923 {
924 if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
925 return -EINVAL;
926 do_key_write(dev, index, B43_SEC_ALGO_NONE,
927 NULL, B43_SEC_KEYSIZE, NULL);
928 if ((index <= 3) && !b43_new_kidx_api(dev)) {
929 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
930 NULL, B43_SEC_KEYSIZE, NULL);
931 }
932 dev->key[index].keyconf = NULL;
933
934 return 0;
935 }
936
937 static void b43_clear_keys(struct b43_wldev *dev)
938 {
939 int i;
940
941 for (i = 0; i < dev->max_nr_keys; i++)
942 b43_key_clear(dev, i);
943 }
944
945 static void b43_dump_keymemory(struct b43_wldev *dev)
946 {
947 unsigned int i, index, offset;
948 DECLARE_MAC_BUF(macbuf);
949 u8 mac[ETH_ALEN];
950 u16 algo;
951 u32 rcmta0;
952 u16 rcmta1;
953 u64 hf;
954 struct b43_key *key;
955
956 if (!b43_debug(dev, B43_DBG_KEYS))
957 return;
958
959 hf = b43_hf_read(dev);
960 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n",
961 !!(hf & B43_HF_USEDEFKEYS));
962 for (index = 0; index < dev->max_nr_keys; index++) {
963 key = &(dev->key[index]);
964 printk(KERN_DEBUG "Key slot %02u: %s",
965 index, (key->keyconf == NULL) ? " " : "*");
966 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
967 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
968 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
969 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
970 }
971
972 algo = b43_shm_read16(dev, B43_SHM_SHARED,
973 B43_SHM_SH_KEYIDXBLOCK + (index * 2));
974 printk(" Algo: %04X/%02X", algo, key->algorithm);
975
976 if (index >= 4) {
977 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
978 ((index - 4) * 2) + 0);
979 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
980 ((index - 4) * 2) + 1);
981 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
982 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
983 printk(" MAC: %s",
984 print_mac(macbuf, mac));
985 } else
986 printk(" DEFAULT KEY");
987 printk("\n");
988 }
989 }
990
991 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
992 {
993 u32 macctl;
994 u16 ucstat;
995 bool hwps;
996 bool awake;
997 int i;
998
999 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1000 (ps_flags & B43_PS_DISABLED));
1001 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1002
1003 if (ps_flags & B43_PS_ENABLED) {
1004 hwps = 1;
1005 } else if (ps_flags & B43_PS_DISABLED) {
1006 hwps = 0;
1007 } else {
1008 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1009 // and thus is not an AP and we are associated, set bit 25
1010 }
1011 if (ps_flags & B43_PS_AWAKE) {
1012 awake = 1;
1013 } else if (ps_flags & B43_PS_ASLEEP) {
1014 awake = 0;
1015 } else {
1016 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1017 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1018 // successful, set bit26
1019 }
1020
1021 /* FIXME: For now we force awake-on and hwps-off */
1022 hwps = 0;
1023 awake = 1;
1024
1025 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1026 if (hwps)
1027 macctl |= B43_MACCTL_HWPS;
1028 else
1029 macctl &= ~B43_MACCTL_HWPS;
1030 if (awake)
1031 macctl |= B43_MACCTL_AWAKE;
1032 else
1033 macctl &= ~B43_MACCTL_AWAKE;
1034 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1035 /* Commit write */
1036 b43_read32(dev, B43_MMIO_MACCTL);
1037 if (awake && dev->dev->id.revision >= 5) {
1038 /* Wait for the microcode to wake up. */
1039 for (i = 0; i < 100; i++) {
1040 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1041 B43_SHM_SH_UCODESTAT);
1042 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1043 break;
1044 udelay(10);
1045 }
1046 }
1047 }
1048
1049 void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
1050 {
1051 u32 tmslow;
1052 u32 macctl;
1053
1054 flags |= B43_TMSLOW_PHYCLKEN;
1055 flags |= B43_TMSLOW_PHYRESET;
1056 ssb_device_enable(dev->dev, flags);
1057 msleep(2); /* Wait for the PLL to turn on. */
1058
1059 /* Now take the PHY out of Reset again */
1060 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
1061 tmslow |= SSB_TMSLOW_FGC;
1062 tmslow &= ~B43_TMSLOW_PHYRESET;
1063 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1064 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1065 msleep(1);
1066 tmslow &= ~SSB_TMSLOW_FGC;
1067 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1068 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1069 msleep(1);
1070
1071 /* Turn Analog ON, but only if we already know the PHY-type.
1072 * This protects against very early setup where we don't know the
1073 * PHY-type, yet. wireless_core_reset will be called once again later,
1074 * when we know the PHY-type. */
1075 if (dev->phy.ops)
1076 dev->phy.ops->switch_analog(dev, 1);
1077
1078 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1079 macctl &= ~B43_MACCTL_GMODE;
1080 if (flags & B43_TMSLOW_GMODE)
1081 macctl |= B43_MACCTL_GMODE;
1082 macctl |= B43_MACCTL_IHR_ENABLED;
1083 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1084 }
1085
1086 static void handle_irq_transmit_status(struct b43_wldev *dev)
1087 {
1088 u32 v0, v1;
1089 u16 tmp;
1090 struct b43_txstatus stat;
1091
1092 while (1) {
1093 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1094 if (!(v0 & 0x00000001))
1095 break;
1096 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1097
1098 stat.cookie = (v0 >> 16);
1099 stat.seq = (v1 & 0x0000FFFF);
1100 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1101 tmp = (v0 & 0x0000FFFF);
1102 stat.frame_count = ((tmp & 0xF000) >> 12);
1103 stat.rts_count = ((tmp & 0x0F00) >> 8);
1104 stat.supp_reason = ((tmp & 0x001C) >> 2);
1105 stat.pm_indicated = !!(tmp & 0x0080);
1106 stat.intermediate = !!(tmp & 0x0040);
1107 stat.for_ampdu = !!(tmp & 0x0020);
1108 stat.acked = !!(tmp & 0x0002);
1109
1110 b43_handle_txstatus(dev, &stat);
1111 }
1112 }
1113
1114 static void drain_txstatus_queue(struct b43_wldev *dev)
1115 {
1116 u32 dummy;
1117
1118 if (dev->dev->id.revision < 5)
1119 return;
1120 /* Read all entries from the microcode TXstatus FIFO
1121 * and throw them away.
1122 */
1123 while (1) {
1124 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1125 if (!(dummy & 0x00000001))
1126 break;
1127 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1128 }
1129 }
1130
1131 static u32 b43_jssi_read(struct b43_wldev *dev)
1132 {
1133 u32 val = 0;
1134
1135 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1136 val <<= 16;
1137 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1138
1139 return val;
1140 }
1141
1142 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1143 {
1144 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1145 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1146 }
1147
1148 static void b43_generate_noise_sample(struct b43_wldev *dev)
1149 {
1150 b43_jssi_write(dev, 0x7F7F7F7F);
1151 b43_write32(dev, B43_MMIO_MACCMD,
1152 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1153 }
1154
1155 static void b43_calculate_link_quality(struct b43_wldev *dev)
1156 {
1157 /* Top half of Link Quality calculation. */
1158
1159 if (dev->phy.type != B43_PHYTYPE_G)
1160 return;
1161 if (dev->noisecalc.calculation_running)
1162 return;
1163 dev->noisecalc.calculation_running = 1;
1164 dev->noisecalc.nr_samples = 0;
1165
1166 b43_generate_noise_sample(dev);
1167 }
1168
1169 static void handle_irq_noise(struct b43_wldev *dev)
1170 {
1171 struct b43_phy_g *phy = dev->phy.g;
1172 u16 tmp;
1173 u8 noise[4];
1174 u8 i, j;
1175 s32 average;
1176
1177 /* Bottom half of Link Quality calculation. */
1178
1179 if (dev->phy.type != B43_PHYTYPE_G)
1180 return;
1181
1182 /* Possible race condition: It might be possible that the user
1183 * changed to a different channel in the meantime since we
1184 * started the calculation. We ignore that fact, since it's
1185 * not really that much of a problem. The background noise is
1186 * an estimation only anyway. Slightly wrong results will get damped
1187 * by the averaging of the 8 sample rounds. Additionally the
1188 * value is shortlived. So it will be replaced by the next noise
1189 * calculation round soon. */
1190
1191 B43_WARN_ON(!dev->noisecalc.calculation_running);
1192 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1193 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1194 noise[2] == 0x7F || noise[3] == 0x7F)
1195 goto generate_new;
1196
1197 /* Get the noise samples. */
1198 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1199 i = dev->noisecalc.nr_samples;
1200 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1201 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1202 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1203 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1204 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1205 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1206 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1207 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1208 dev->noisecalc.nr_samples++;
1209 if (dev->noisecalc.nr_samples == 8) {
1210 /* Calculate the Link Quality by the noise samples. */
1211 average = 0;
1212 for (i = 0; i < 8; i++) {
1213 for (j = 0; j < 4; j++)
1214 average += dev->noisecalc.samples[i][j];
1215 }
1216 average /= (8 * 4);
1217 average *= 125;
1218 average += 64;
1219 average /= 128;
1220 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1221 tmp = (tmp / 128) & 0x1F;
1222 if (tmp >= 8)
1223 average += 2;
1224 else
1225 average -= 25;
1226 if (tmp == 8)
1227 average -= 72;
1228 else
1229 average -= 48;
1230
1231 dev->stats.link_noise = average;
1232 dev->noisecalc.calculation_running = 0;
1233 return;
1234 }
1235 generate_new:
1236 b43_generate_noise_sample(dev);
1237 }
1238
1239 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1240 {
1241 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
1242 ///TODO: PS TBTT
1243 } else {
1244 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1245 b43_power_saving_ctl_bits(dev, 0);
1246 }
1247 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
1248 dev->dfq_valid = 1;
1249 }
1250
1251 static void handle_irq_atim_end(struct b43_wldev *dev)
1252 {
1253 if (dev->dfq_valid) {
1254 b43_write32(dev, B43_MMIO_MACCMD,
1255 b43_read32(dev, B43_MMIO_MACCMD)
1256 | B43_MACCMD_DFQ_VALID);
1257 dev->dfq_valid = 0;
1258 }
1259 }
1260
1261 static void handle_irq_pmq(struct b43_wldev *dev)
1262 {
1263 u32 tmp;
1264
1265 //TODO: AP mode.
1266
1267 while (1) {
1268 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1269 if (!(tmp & 0x00000008))
1270 break;
1271 }
1272 /* 16bit write is odd, but correct. */
1273 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1274 }
1275
1276 static void b43_write_template_common(struct b43_wldev *dev,
1277 const u8 *data, u16 size,
1278 u16 ram_offset,
1279 u16 shm_size_offset, u8 rate)
1280 {
1281 u32 i, tmp;
1282 struct b43_plcp_hdr4 plcp;
1283
1284 plcp.data = 0;
1285 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1286 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1287 ram_offset += sizeof(u32);
1288 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1289 * So leave the first two bytes of the next write blank.
1290 */
1291 tmp = (u32) (data[0]) << 16;
1292 tmp |= (u32) (data[1]) << 24;
1293 b43_ram_write(dev, ram_offset, tmp);
1294 ram_offset += sizeof(u32);
1295 for (i = 2; i < size; i += sizeof(u32)) {
1296 tmp = (u32) (data[i + 0]);
1297 if (i + 1 < size)
1298 tmp |= (u32) (data[i + 1]) << 8;
1299 if (i + 2 < size)
1300 tmp |= (u32) (data[i + 2]) << 16;
1301 if (i + 3 < size)
1302 tmp |= (u32) (data[i + 3]) << 24;
1303 b43_ram_write(dev, ram_offset + i - 2, tmp);
1304 }
1305 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1306 size + sizeof(struct b43_plcp_hdr6));
1307 }
1308
1309 /* Check if the use of the antenna that ieee80211 told us to
1310 * use is possible. This will fall back to DEFAULT.
1311 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1312 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1313 u8 antenna_nr)
1314 {
1315 u8 antenna_mask;
1316
1317 if (antenna_nr == 0) {
1318 /* Zero means "use default antenna". That's always OK. */
1319 return 0;
1320 }
1321
1322 /* Get the mask of available antennas. */
1323 if (dev->phy.gmode)
1324 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
1325 else
1326 antenna_mask = dev->dev->bus->sprom.ant_available_a;
1327
1328 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1329 /* This antenna is not available. Fall back to default. */
1330 return 0;
1331 }
1332
1333 return antenna_nr;
1334 }
1335
1336 /* Convert a b43 antenna number value to the PHY TX control value. */
1337 static u16 b43_antenna_to_phyctl(int antenna)
1338 {
1339 switch (antenna) {
1340 case B43_ANTENNA0:
1341 return B43_TXH_PHY_ANT0;
1342 case B43_ANTENNA1:
1343 return B43_TXH_PHY_ANT1;
1344 case B43_ANTENNA2:
1345 return B43_TXH_PHY_ANT2;
1346 case B43_ANTENNA3:
1347 return B43_TXH_PHY_ANT3;
1348 case B43_ANTENNA_AUTO:
1349 return B43_TXH_PHY_ANT01AUTO;
1350 }
1351 B43_WARN_ON(1);
1352 return 0;
1353 }
1354
1355 static void b43_write_beacon_template(struct b43_wldev *dev,
1356 u16 ram_offset,
1357 u16 shm_size_offset)
1358 {
1359 unsigned int i, len, variable_len;
1360 const struct ieee80211_mgmt *bcn;
1361 const u8 *ie;
1362 bool tim_found = 0;
1363 unsigned int rate;
1364 u16 ctl;
1365 int antenna;
1366 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
1367
1368 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1369 len = min((size_t) dev->wl->current_beacon->len,
1370 0x200 - sizeof(struct b43_plcp_hdr6));
1371 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
1372
1373 b43_write_template_common(dev, (const u8 *)bcn,
1374 len, ram_offset, shm_size_offset, rate);
1375
1376 /* Write the PHY TX control parameters. */
1377 antenna = B43_ANTENNA_DEFAULT;
1378 antenna = b43_antenna_to_phyctl(antenna);
1379 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1380 /* We can't send beacons with short preamble. Would get PHY errors. */
1381 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1382 ctl &= ~B43_TXH_PHY_ANT;
1383 ctl &= ~B43_TXH_PHY_ENC;
1384 ctl |= antenna;
1385 if (b43_is_cck_rate(rate))
1386 ctl |= B43_TXH_PHY_ENC_CCK;
1387 else
1388 ctl |= B43_TXH_PHY_ENC_OFDM;
1389 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1390
1391 /* Find the position of the TIM and the DTIM_period value
1392 * and write them to SHM. */
1393 ie = bcn->u.beacon.variable;
1394 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1395 for (i = 0; i < variable_len - 2; ) {
1396 uint8_t ie_id, ie_len;
1397
1398 ie_id = ie[i];
1399 ie_len = ie[i + 1];
1400 if (ie_id == 5) {
1401 u16 tim_position;
1402 u16 dtim_period;
1403 /* This is the TIM Information Element */
1404
1405 /* Check whether the ie_len is in the beacon data range. */
1406 if (variable_len < ie_len + 2 + i)
1407 break;
1408 /* A valid TIM is at least 4 bytes long. */
1409 if (ie_len < 4)
1410 break;
1411 tim_found = 1;
1412
1413 tim_position = sizeof(struct b43_plcp_hdr6);
1414 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1415 tim_position += i;
1416
1417 dtim_period = ie[i + 3];
1418
1419 b43_shm_write16(dev, B43_SHM_SHARED,
1420 B43_SHM_SH_TIMBPOS, tim_position);
1421 b43_shm_write16(dev, B43_SHM_SHARED,
1422 B43_SHM_SH_DTIMPER, dtim_period);
1423 break;
1424 }
1425 i += ie_len + 2;
1426 }
1427 if (!tim_found) {
1428 /*
1429 * If ucode wants to modify TIM do it behind the beacon, this
1430 * will happen, for example, when doing mesh networking.
1431 */
1432 b43_shm_write16(dev, B43_SHM_SHARED,
1433 B43_SHM_SH_TIMBPOS,
1434 len + sizeof(struct b43_plcp_hdr6));
1435 b43_shm_write16(dev, B43_SHM_SHARED,
1436 B43_SHM_SH_DTIMPER, 0);
1437 }
1438 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
1439 }
1440
1441 static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
1442 u16 shm_offset, u16 size,
1443 struct ieee80211_rate *rate)
1444 {
1445 struct b43_plcp_hdr4 plcp;
1446 u32 tmp;
1447 __le16 dur;
1448
1449 plcp.data = 0;
1450 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate->hw_value);
1451 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1452 dev->wl->vif, size,
1453 rate);
1454 /* Write PLCP in two parts and timing for packet transfer */
1455 tmp = le32_to_cpu(plcp.data);
1456 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1457 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1458 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1459 }
1460
1461 /* Instead of using custom probe response template, this function
1462 * just patches custom beacon template by:
1463 * 1) Changing packet type
1464 * 2) Patching duration field
1465 * 3) Stripping TIM
1466 */
1467 static const u8 *b43_generate_probe_resp(struct b43_wldev *dev,
1468 u16 *dest_size,
1469 struct ieee80211_rate *rate)
1470 {
1471 const u8 *src_data;
1472 u8 *dest_data;
1473 u16 src_size, elem_size, src_pos, dest_pos;
1474 __le16 dur;
1475 struct ieee80211_hdr *hdr;
1476 size_t ie_start;
1477
1478 src_size = dev->wl->current_beacon->len;
1479 src_data = (const u8 *)dev->wl->current_beacon->data;
1480
1481 /* Get the start offset of the variable IEs in the packet. */
1482 ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1483 B43_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt, u.beacon.variable));
1484
1485 if (B43_WARN_ON(src_size < ie_start))
1486 return NULL;
1487
1488 dest_data = kmalloc(src_size, GFP_ATOMIC);
1489 if (unlikely(!dest_data))
1490 return NULL;
1491
1492 /* Copy the static data and all Information Elements, except the TIM. */
1493 memcpy(dest_data, src_data, ie_start);
1494 src_pos = ie_start;
1495 dest_pos = ie_start;
1496 for ( ; src_pos < src_size - 2; src_pos += elem_size) {
1497 elem_size = src_data[src_pos + 1] + 2;
1498 if (src_data[src_pos] == 5) {
1499 /* This is the TIM. */
1500 continue;
1501 }
1502 memcpy(dest_data + dest_pos, src_data + src_pos,
1503 elem_size);
1504 dest_pos += elem_size;
1505 }
1506 *dest_size = dest_pos;
1507 hdr = (struct ieee80211_hdr *)dest_data;
1508
1509 /* Set the frame control. */
1510 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1511 IEEE80211_STYPE_PROBE_RESP);
1512 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1513 dev->wl->vif, *dest_size,
1514 rate);
1515 hdr->duration_id = dur;
1516
1517 return dest_data;
1518 }
1519
1520 static void b43_write_probe_resp_template(struct b43_wldev *dev,
1521 u16 ram_offset,
1522 u16 shm_size_offset,
1523 struct ieee80211_rate *rate)
1524 {
1525 const u8 *probe_resp_data;
1526 u16 size;
1527
1528 size = dev->wl->current_beacon->len;
1529 probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1530 if (unlikely(!probe_resp_data))
1531 return;
1532
1533 /* Looks like PLCP headers plus packet timings are stored for
1534 * all possible basic rates
1535 */
1536 b43_write_probe_resp_plcp(dev, 0x31A, size, &b43_b_ratetable[0]);
1537 b43_write_probe_resp_plcp(dev, 0x32C, size, &b43_b_ratetable[1]);
1538 b43_write_probe_resp_plcp(dev, 0x33E, size, &b43_b_ratetable[2]);
1539 b43_write_probe_resp_plcp(dev, 0x350, size, &b43_b_ratetable[3]);
1540
1541 size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1542 b43_write_template_common(dev, probe_resp_data,
1543 size, ram_offset, shm_size_offset,
1544 rate->hw_value);
1545 kfree(probe_resp_data);
1546 }
1547
1548 static void b43_upload_beacon0(struct b43_wldev *dev)
1549 {
1550 struct b43_wl *wl = dev->wl;
1551
1552 if (wl->beacon0_uploaded)
1553 return;
1554 b43_write_beacon_template(dev, 0x68, 0x18);
1555 /* FIXME: Probe resp upload doesn't really belong here,
1556 * but we don't use that feature anyway. */
1557 b43_write_probe_resp_template(dev, 0x268, 0x4A,
1558 &__b43_ratetable[3]);
1559 wl->beacon0_uploaded = 1;
1560 }
1561
1562 static void b43_upload_beacon1(struct b43_wldev *dev)
1563 {
1564 struct b43_wl *wl = dev->wl;
1565
1566 if (wl->beacon1_uploaded)
1567 return;
1568 b43_write_beacon_template(dev, 0x468, 0x1A);
1569 wl->beacon1_uploaded = 1;
1570 }
1571
1572 static void handle_irq_beacon(struct b43_wldev *dev)
1573 {
1574 struct b43_wl *wl = dev->wl;
1575 u32 cmd, beacon0_valid, beacon1_valid;
1576
1577 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
1578 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
1579 return;
1580
1581 /* This is the bottom half of the asynchronous beacon update. */
1582
1583 /* Ignore interrupt in the future. */
1584 dev->irq_mask &= ~B43_IRQ_BEACON;
1585
1586 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1587 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1588 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1589
1590 /* Schedule interrupt manually, if busy. */
1591 if (beacon0_valid && beacon1_valid) {
1592 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1593 dev->irq_mask |= B43_IRQ_BEACON;
1594 return;
1595 }
1596
1597 if (unlikely(wl->beacon_templates_virgin)) {
1598 /* We never uploaded a beacon before.
1599 * Upload both templates now, but only mark one valid. */
1600 wl->beacon_templates_virgin = 0;
1601 b43_upload_beacon0(dev);
1602 b43_upload_beacon1(dev);
1603 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1604 cmd |= B43_MACCMD_BEACON0_VALID;
1605 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1606 } else {
1607 if (!beacon0_valid) {
1608 b43_upload_beacon0(dev);
1609 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1610 cmd |= B43_MACCMD_BEACON0_VALID;
1611 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1612 } else if (!beacon1_valid) {
1613 b43_upload_beacon1(dev);
1614 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1615 cmd |= B43_MACCMD_BEACON1_VALID;
1616 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1617 }
1618 }
1619 }
1620
1621 static void b43_beacon_update_trigger_work(struct work_struct *work)
1622 {
1623 struct b43_wl *wl = container_of(work, struct b43_wl,
1624 beacon_update_trigger);
1625 struct b43_wldev *dev;
1626
1627 mutex_lock(&wl->mutex);
1628 dev = wl->current_dev;
1629 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
1630 spin_lock_irq(&wl->irq_lock);
1631 /* update beacon right away or defer to irq */
1632 handle_irq_beacon(dev);
1633 /* The handler might have updated the IRQ mask. */
1634 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1635 mmiowb();
1636 spin_unlock_irq(&wl->irq_lock);
1637 }
1638 mutex_unlock(&wl->mutex);
1639 }
1640
1641 /* Asynchronously update the packet templates in template RAM.
1642 * Locking: Requires wl->irq_lock to be locked. */
1643 static void b43_update_templates(struct b43_wl *wl)
1644 {
1645 struct sk_buff *beacon;
1646
1647 /* This is the top half of the ansynchronous beacon update.
1648 * The bottom half is the beacon IRQ.
1649 * Beacon update must be asynchronous to avoid sending an
1650 * invalid beacon. This can happen for example, if the firmware
1651 * transmits a beacon while we are updating it. */
1652
1653 /* We could modify the existing beacon and set the aid bit in
1654 * the TIM field, but that would probably require resizing and
1655 * moving of data within the beacon template.
1656 * Simply request a new beacon and let mac80211 do the hard work. */
1657 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1658 if (unlikely(!beacon))
1659 return;
1660
1661 if (wl->current_beacon)
1662 dev_kfree_skb_any(wl->current_beacon);
1663 wl->current_beacon = beacon;
1664 wl->beacon0_uploaded = 0;
1665 wl->beacon1_uploaded = 0;
1666 queue_work(wl->hw->workqueue, &wl->beacon_update_trigger);
1667 }
1668
1669 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1670 {
1671 b43_time_lock(dev);
1672 if (dev->dev->id.revision >= 3) {
1673 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1674 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
1675 } else {
1676 b43_write16(dev, 0x606, (beacon_int >> 6));
1677 b43_write16(dev, 0x610, beacon_int);
1678 }
1679 b43_time_unlock(dev);
1680 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1681 }
1682
1683 static void b43_handle_firmware_panic(struct b43_wldev *dev)
1684 {
1685 u16 reason;
1686
1687 /* Read the register that contains the reason code for the panic. */
1688 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1689 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1690
1691 switch (reason) {
1692 default:
1693 b43dbg(dev->wl, "The panic reason is unknown.\n");
1694 /* fallthrough */
1695 case B43_FWPANIC_DIE:
1696 /* Do not restart the controller or firmware.
1697 * The device is nonfunctional from now on.
1698 * Restarting would result in this panic to trigger again,
1699 * so we avoid that recursion. */
1700 break;
1701 case B43_FWPANIC_RESTART:
1702 b43_controller_restart(dev, "Microcode panic");
1703 break;
1704 }
1705 }
1706
1707 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1708 {
1709 unsigned int i, cnt;
1710 u16 reason, marker_id, marker_line;
1711 __le16 *buf;
1712
1713 /* The proprietary firmware doesn't have this IRQ. */
1714 if (!dev->fw.opensource)
1715 return;
1716
1717 /* Read the register that contains the reason code for this IRQ. */
1718 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1719
1720 switch (reason) {
1721 case B43_DEBUGIRQ_PANIC:
1722 b43_handle_firmware_panic(dev);
1723 break;
1724 case B43_DEBUGIRQ_DUMP_SHM:
1725 if (!B43_DEBUG)
1726 break; /* Only with driver debugging enabled. */
1727 buf = kmalloc(4096, GFP_ATOMIC);
1728 if (!buf) {
1729 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1730 goto out;
1731 }
1732 for (i = 0; i < 4096; i += 2) {
1733 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1734 buf[i / 2] = cpu_to_le16(tmp);
1735 }
1736 b43info(dev->wl, "Shared memory dump:\n");
1737 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1738 16, 2, buf, 4096, 1);
1739 kfree(buf);
1740 break;
1741 case B43_DEBUGIRQ_DUMP_REGS:
1742 if (!B43_DEBUG)
1743 break; /* Only with driver debugging enabled. */
1744 b43info(dev->wl, "Microcode register dump:\n");
1745 for (i = 0, cnt = 0; i < 64; i++) {
1746 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1747 if (cnt == 0)
1748 printk(KERN_INFO);
1749 printk("r%02u: 0x%04X ", i, tmp);
1750 cnt++;
1751 if (cnt == 6) {
1752 printk("\n");
1753 cnt = 0;
1754 }
1755 }
1756 printk("\n");
1757 break;
1758 case B43_DEBUGIRQ_MARKER:
1759 if (!B43_DEBUG)
1760 break; /* Only with driver debugging enabled. */
1761 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1762 B43_MARKER_ID_REG);
1763 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1764 B43_MARKER_LINE_REG);
1765 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1766 "at line number %u\n",
1767 marker_id, marker_line);
1768 break;
1769 default:
1770 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1771 reason);
1772 }
1773 out:
1774 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1775 b43_shm_write16(dev, B43_SHM_SCRATCH,
1776 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
1777 }
1778
1779 /* Interrupt handler bottom-half */
1780 static void b43_interrupt_tasklet(struct b43_wldev *dev)
1781 {
1782 u32 reason;
1783 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1784 u32 merged_dma_reason = 0;
1785 int i;
1786 unsigned long flags;
1787
1788 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1789
1790 B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1791
1792 reason = dev->irq_reason;
1793 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1794 dma_reason[i] = dev->dma_reason[i];
1795 merged_dma_reason |= dma_reason[i];
1796 }
1797
1798 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1799 b43err(dev->wl, "MAC transmission error\n");
1800
1801 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1802 b43err(dev->wl, "PHY transmission error\n");
1803 rmb();
1804 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1805 atomic_set(&dev->phy.txerr_cnt,
1806 B43_PHY_TX_BADNESS_LIMIT);
1807 b43err(dev->wl, "Too many PHY TX errors, "
1808 "restarting the controller\n");
1809 b43_controller_restart(dev, "PHY TX errors");
1810 }
1811 }
1812
1813 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1814 B43_DMAIRQ_NONFATALMASK))) {
1815 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1816 b43err(dev->wl, "Fatal DMA error: "
1817 "0x%08X, 0x%08X, 0x%08X, "
1818 "0x%08X, 0x%08X, 0x%08X\n",
1819 dma_reason[0], dma_reason[1],
1820 dma_reason[2], dma_reason[3],
1821 dma_reason[4], dma_reason[5]);
1822 b43_controller_restart(dev, "DMA error");
1823 mmiowb();
1824 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1825 return;
1826 }
1827 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1828 b43err(dev->wl, "DMA error: "
1829 "0x%08X, 0x%08X, 0x%08X, "
1830 "0x%08X, 0x%08X, 0x%08X\n",
1831 dma_reason[0], dma_reason[1],
1832 dma_reason[2], dma_reason[3],
1833 dma_reason[4], dma_reason[5]);
1834 }
1835 }
1836
1837 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1838 handle_irq_ucode_debug(dev);
1839 if (reason & B43_IRQ_TBTT_INDI)
1840 handle_irq_tbtt_indication(dev);
1841 if (reason & B43_IRQ_ATIM_END)
1842 handle_irq_atim_end(dev);
1843 if (reason & B43_IRQ_BEACON)
1844 handle_irq_beacon(dev);
1845 if (reason & B43_IRQ_PMQ)
1846 handle_irq_pmq(dev);
1847 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1848 ;/* TODO */
1849 if (reason & B43_IRQ_NOISESAMPLE_OK)
1850 handle_irq_noise(dev);
1851
1852 /* Check the DMA reason registers for received data. */
1853 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1854 if (b43_using_pio_transfers(dev))
1855 b43_pio_rx(dev->pio.rx_queue);
1856 else
1857 b43_dma_rx(dev->dma.rx_ring);
1858 }
1859 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1860 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1861 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
1862 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1863 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1864
1865 if (reason & B43_IRQ_TX_OK)
1866 handle_irq_transmit_status(dev);
1867
1868 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1869 mmiowb();
1870 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1871 }
1872
1873 static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1874 {
1875 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1876
1877 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1878 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1879 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1880 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1881 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1882 /* Unused ring
1883 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1884 */
1885 }
1886
1887 /* Interrupt handler top-half */
1888 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1889 {
1890 irqreturn_t ret = IRQ_NONE;
1891 struct b43_wldev *dev = dev_id;
1892 u32 reason;
1893
1894 B43_WARN_ON(!dev);
1895
1896 spin_lock(&dev->wl->irq_lock);
1897
1898 if (unlikely(b43_status(dev) < B43_STAT_STARTED)) {
1899 /* This can only happen on shared IRQ lines. */
1900 goto out;
1901 }
1902 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1903 if (reason == 0xffffffff) /* shared IRQ */
1904 goto out;
1905 ret = IRQ_HANDLED;
1906 reason &= dev->irq_mask;
1907 if (!reason)
1908 goto out;
1909
1910 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1911 & 0x0001DC00;
1912 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1913 & 0x0000DC00;
1914 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1915 & 0x0000DC00;
1916 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1917 & 0x0001DC00;
1918 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1919 & 0x0000DC00;
1920 /* Unused ring
1921 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1922 & 0x0000DC00;
1923 */
1924
1925 b43_interrupt_ack(dev, reason);
1926 /* disable all IRQs. They are enabled again in the bottom half. */
1927 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
1928 /* save the reason code and call our bottom half. */
1929 dev->irq_reason = reason;
1930 tasklet_schedule(&dev->isr_tasklet);
1931 out:
1932 mmiowb();
1933 spin_unlock(&dev->wl->irq_lock);
1934
1935 return ret;
1936 }
1937
1938 void b43_do_release_fw(struct b43_firmware_file *fw)
1939 {
1940 release_firmware(fw->data);
1941 fw->data = NULL;
1942 fw->filename = NULL;
1943 }
1944
1945 static void b43_release_firmware(struct b43_wldev *dev)
1946 {
1947 b43_do_release_fw(&dev->fw.ucode);
1948 b43_do_release_fw(&dev->fw.pcm);
1949 b43_do_release_fw(&dev->fw.initvals);
1950 b43_do_release_fw(&dev->fw.initvals_band);
1951 }
1952
1953 static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
1954 {
1955 const char text[] =
1956 "You must go to " \
1957 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
1958 "and download the correct firmware for this driver version. " \
1959 "Please carefully read all instructions on this website.\n";
1960
1961 if (error)
1962 b43err(wl, text);
1963 else
1964 b43warn(wl, text);
1965 }
1966
1967 int b43_do_request_fw(struct b43_request_fw_context *ctx,
1968 const char *name,
1969 struct b43_firmware_file *fw)
1970 {
1971 const struct firmware *blob;
1972 struct b43_fw_header *hdr;
1973 u32 size;
1974 int err;
1975
1976 if (!name) {
1977 /* Don't fetch anything. Free possibly cached firmware. */
1978 /* FIXME: We should probably keep it anyway, to save some headache
1979 * on suspend/resume with multiband devices. */
1980 b43_do_release_fw(fw);
1981 return 0;
1982 }
1983 if (fw->filename) {
1984 if ((fw->type == ctx->req_type) &&
1985 (strcmp(fw->filename, name) == 0))
1986 return 0; /* Already have this fw. */
1987 /* Free the cached firmware first. */
1988 /* FIXME: We should probably do this later after we successfully
1989 * got the new fw. This could reduce headache with multiband devices.
1990 * We could also redesign this to cache the firmware for all possible
1991 * bands all the time. */
1992 b43_do_release_fw(fw);
1993 }
1994
1995 switch (ctx->req_type) {
1996 case B43_FWTYPE_PROPRIETARY:
1997 snprintf(ctx->fwname, sizeof(ctx->fwname),
1998 "b43%s/%s.fw",
1999 modparam_fwpostfix, name);
2000 break;
2001 case B43_FWTYPE_OPENSOURCE:
2002 snprintf(ctx->fwname, sizeof(ctx->fwname),
2003 "b43-open%s/%s.fw",
2004 modparam_fwpostfix, name);
2005 break;
2006 default:
2007 B43_WARN_ON(1);
2008 return -ENOSYS;
2009 }
2010 err = request_firmware(&blob, ctx->fwname, ctx->dev->dev->dev);
2011 if (err == -ENOENT) {
2012 snprintf(ctx->errors[ctx->req_type],
2013 sizeof(ctx->errors[ctx->req_type]),
2014 "Firmware file \"%s\" not found\n", ctx->fwname);
2015 return err;
2016 } else if (err) {
2017 snprintf(ctx->errors[ctx->req_type],
2018 sizeof(ctx->errors[ctx->req_type]),
2019 "Firmware file \"%s\" request failed (err=%d)\n",
2020 ctx->fwname, err);
2021 return err;
2022 }
2023 if (blob->size < sizeof(struct b43_fw_header))
2024 goto err_format;
2025 hdr = (struct b43_fw_header *)(blob->data);
2026 switch (hdr->type) {
2027 case B43_FW_TYPE_UCODE:
2028 case B43_FW_TYPE_PCM:
2029 size = be32_to_cpu(hdr->size);
2030 if (size != blob->size - sizeof(struct b43_fw_header))
2031 goto err_format;
2032 /* fallthrough */
2033 case B43_FW_TYPE_IV:
2034 if (hdr->ver != 1)
2035 goto err_format;
2036 break;
2037 default:
2038 goto err_format;
2039 }
2040
2041 fw->data = blob;
2042 fw->filename = name;
2043 fw->type = ctx->req_type;
2044
2045 return 0;
2046
2047 err_format:
2048 snprintf(ctx->errors[ctx->req_type],
2049 sizeof(ctx->errors[ctx->req_type]),
2050 "Firmware file \"%s\" format error.\n", ctx->fwname);
2051 release_firmware(blob);
2052
2053 return -EPROTO;
2054 }
2055
2056 static int b43_try_request_fw(struct b43_request_fw_context *ctx)
2057 {
2058 struct b43_wldev *dev = ctx->dev;
2059 struct b43_firmware *fw = &ctx->dev->fw;
2060 const u8 rev = ctx->dev->dev->id.revision;
2061 const char *filename;
2062 u32 tmshigh;
2063 int err;
2064
2065 /* Get microcode */
2066 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
2067 if ((rev >= 5) && (rev <= 10))
2068 filename = "ucode5";
2069 else if ((rev >= 11) && (rev <= 12))
2070 filename = "ucode11";
2071 else if (rev >= 13)
2072 filename = "ucode13";
2073 else
2074 goto err_no_ucode;
2075 err = b43_do_request_fw(ctx, filename, &fw->ucode);
2076 if (err)
2077 goto err_load;
2078
2079 /* Get PCM code */
2080 if ((rev >= 5) && (rev <= 10))
2081 filename = "pcm5";
2082 else if (rev >= 11)
2083 filename = NULL;
2084 else
2085 goto err_no_pcm;
2086 fw->pcm_request_failed = 0;
2087 err = b43_do_request_fw(ctx, filename, &fw->pcm);
2088 if (err == -ENOENT) {
2089 /* We did not find a PCM file? Not fatal, but
2090 * core rev <= 10 must do without hwcrypto then. */
2091 fw->pcm_request_failed = 1;
2092 } else if (err)
2093 goto err_load;
2094
2095 /* Get initvals */
2096 switch (dev->phy.type) {
2097 case B43_PHYTYPE_A:
2098 if ((rev >= 5) && (rev <= 10)) {
2099 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2100 filename = "a0g1initvals5";
2101 else
2102 filename = "a0g0initvals5";
2103 } else
2104 goto err_no_initvals;
2105 break;
2106 case B43_PHYTYPE_G:
2107 if ((rev >= 5) && (rev <= 10))
2108 filename = "b0g0initvals5";
2109 else if (rev >= 13)
2110 filename = "b0g0initvals13";
2111 else
2112 goto err_no_initvals;
2113 break;
2114 case B43_PHYTYPE_N:
2115 if ((rev >= 11) && (rev <= 12))
2116 filename = "n0initvals11";
2117 else
2118 goto err_no_initvals;
2119 break;
2120 default:
2121 goto err_no_initvals;
2122 }
2123 err = b43_do_request_fw(ctx, filename, &fw->initvals);
2124 if (err)
2125 goto err_load;
2126
2127 /* Get bandswitch initvals */
2128 switch (dev->phy.type) {
2129 case B43_PHYTYPE_A:
2130 if ((rev >= 5) && (rev <= 10)) {
2131 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2132 filename = "a0g1bsinitvals5";
2133 else
2134 filename = "a0g0bsinitvals5";
2135 } else if (rev >= 11)
2136 filename = NULL;
2137 else
2138 goto err_no_initvals;
2139 break;
2140 case B43_PHYTYPE_G:
2141 if ((rev >= 5) && (rev <= 10))
2142 filename = "b0g0bsinitvals5";
2143 else if (rev >= 11)
2144 filename = NULL;
2145 else
2146 goto err_no_initvals;
2147 break;
2148 case B43_PHYTYPE_N:
2149 if ((rev >= 11) && (rev <= 12))
2150 filename = "n0bsinitvals11";
2151 else
2152 goto err_no_initvals;
2153 break;
2154 default:
2155 goto err_no_initvals;
2156 }
2157 err = b43_do_request_fw(ctx, filename, &fw->initvals_band);
2158 if (err)
2159 goto err_load;
2160
2161 return 0;
2162
2163 err_no_ucode:
2164 err = ctx->fatal_failure = -EOPNOTSUPP;
2165 b43err(dev->wl, "The driver does not know which firmware (ucode) "
2166 "is required for your device (wl-core rev %u)\n", rev);
2167 goto error;
2168
2169 err_no_pcm:
2170 err = ctx->fatal_failure = -EOPNOTSUPP;
2171 b43err(dev->wl, "The driver does not know which firmware (PCM) "
2172 "is required for your device (wl-core rev %u)\n", rev);
2173 goto error;
2174
2175 err_no_initvals:
2176 err = ctx->fatal_failure = -EOPNOTSUPP;
2177 b43err(dev->wl, "The driver does not know which firmware (initvals) "
2178 "is required for your device (wl-core rev %u)\n", rev);
2179 goto error;
2180
2181 err_load:
2182 /* We failed to load this firmware image. The error message
2183 * already is in ctx->errors. Return and let our caller decide
2184 * what to do. */
2185 goto error;
2186
2187 error:
2188 b43_release_firmware(dev);
2189 return err;
2190 }
2191
2192 static int b43_request_firmware(struct b43_wldev *dev)
2193 {
2194 struct b43_request_fw_context *ctx;
2195 unsigned int i;
2196 int err;
2197 const char *errmsg;
2198
2199 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2200 if (!ctx)
2201 return -ENOMEM;
2202 ctx->dev = dev;
2203
2204 ctx->req_type = B43_FWTYPE_PROPRIETARY;
2205 err = b43_try_request_fw(ctx);
2206 if (!err)
2207 goto out; /* Successfully loaded it. */
2208 err = ctx->fatal_failure;
2209 if (err)
2210 goto out;
2211
2212 ctx->req_type = B43_FWTYPE_OPENSOURCE;
2213 err = b43_try_request_fw(ctx);
2214 if (!err)
2215 goto out; /* Successfully loaded it. */
2216 err = ctx->fatal_failure;
2217 if (err)
2218 goto out;
2219
2220 /* Could not find a usable firmware. Print the errors. */
2221 for (i = 0; i < B43_NR_FWTYPES; i++) {
2222 errmsg = ctx->errors[i];
2223 if (strlen(errmsg))
2224 b43err(dev->wl, errmsg);
2225 }
2226 b43_print_fw_helptext(dev->wl, 1);
2227 err = -ENOENT;
2228
2229 out:
2230 kfree(ctx);
2231 return err;
2232 }
2233
2234 static int b43_upload_microcode(struct b43_wldev *dev)
2235 {
2236 const size_t hdr_len = sizeof(struct b43_fw_header);
2237 const __be32 *data;
2238 unsigned int i, len;
2239 u16 fwrev, fwpatch, fwdate, fwtime;
2240 u32 tmp, macctl;
2241 int err = 0;
2242
2243 /* Jump the microcode PSM to offset 0 */
2244 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2245 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2246 macctl |= B43_MACCTL_PSM_JMP0;
2247 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2248 /* Zero out all microcode PSM registers and shared memory. */
2249 for (i = 0; i < 64; i++)
2250 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2251 for (i = 0; i < 4096; i += 2)
2252 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2253
2254 /* Upload Microcode. */
2255 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2256 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
2257 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2258 for (i = 0; i < len; i++) {
2259 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2260 udelay(10);
2261 }
2262
2263 if (dev->fw.pcm.data) {
2264 /* Upload PCM data. */
2265 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2266 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
2267 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2268 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2269 /* No need for autoinc bit in SHM_HW */
2270 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2271 for (i = 0; i < len; i++) {
2272 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2273 udelay(10);
2274 }
2275 }
2276
2277 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
2278
2279 /* Start the microcode PSM */
2280 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2281 macctl &= ~B43_MACCTL_PSM_JMP0;
2282 macctl |= B43_MACCTL_PSM_RUN;
2283 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2284
2285 /* Wait for the microcode to load and respond */
2286 i = 0;
2287 while (1) {
2288 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2289 if (tmp == B43_IRQ_MAC_SUSPENDED)
2290 break;
2291 i++;
2292 if (i >= 20) {
2293 b43err(dev->wl, "Microcode not responding\n");
2294 b43_print_fw_helptext(dev->wl, 1);
2295 err = -ENODEV;
2296 goto error;
2297 }
2298 msleep_interruptible(50);
2299 if (signal_pending(current)) {
2300 err = -EINTR;
2301 goto error;
2302 }
2303 }
2304 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2305
2306 /* Get and check the revisions. */
2307 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2308 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2309 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2310 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2311
2312 if (fwrev <= 0x128) {
2313 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2314 "binary drivers older than version 4.x is unsupported. "
2315 "You must upgrade your firmware files.\n");
2316 b43_print_fw_helptext(dev->wl, 1);
2317 err = -EOPNOTSUPP;
2318 goto error;
2319 }
2320 dev->fw.rev = fwrev;
2321 dev->fw.patch = fwpatch;
2322 dev->fw.opensource = (fwdate == 0xFFFF);
2323
2324 /* Default to use-all-queues. */
2325 dev->wl->hw->queues = dev->wl->mac80211_initially_registered_queues;
2326 dev->qos_enabled = !!modparam_qos;
2327 /* Default to firmware/hardware crypto acceleration. */
2328 dev->hwcrypto_enabled = 1;
2329
2330 if (dev->fw.opensource) {
2331 u16 fwcapa;
2332
2333 /* Patchlevel info is encoded in the "time" field. */
2334 dev->fw.patch = fwtime;
2335 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
2336 dev->fw.rev, dev->fw.patch);
2337
2338 fwcapa = b43_fwcapa_read(dev);
2339 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
2340 b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
2341 /* Disable hardware crypto and fall back to software crypto. */
2342 dev->hwcrypto_enabled = 0;
2343 }
2344 if (!(fwcapa & B43_FWCAPA_QOS)) {
2345 b43info(dev->wl, "QoS not supported by firmware\n");
2346 /* Disable QoS. Tweak hw->queues to 1. It will be restored before
2347 * ieee80211_unregister to make sure the networking core can
2348 * properly free possible resources. */
2349 dev->wl->hw->queues = 1;
2350 dev->qos_enabled = 0;
2351 }
2352 } else {
2353 b43info(dev->wl, "Loading firmware version %u.%u "
2354 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2355 fwrev, fwpatch,
2356 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2357 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
2358 if (dev->fw.pcm_request_failed) {
2359 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2360 "Hardware accelerated cryptography is disabled.\n");
2361 b43_print_fw_helptext(dev->wl, 0);
2362 }
2363 }
2364
2365 if (b43_is_old_txhdr_format(dev)) {
2366 /* We're over the deadline, but we keep support for old fw
2367 * until it turns out to be in major conflict with something new. */
2368 b43warn(dev->wl, "You are using an old firmware image. "
2369 "Support for old firmware will be removed soon "
2370 "(official deadline was July 2008).\n");
2371 b43_print_fw_helptext(dev->wl, 0);
2372 }
2373
2374 return 0;
2375
2376 error:
2377 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2378 macctl &= ~B43_MACCTL_PSM_RUN;
2379 macctl |= B43_MACCTL_PSM_JMP0;
2380 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2381
2382 return err;
2383 }
2384
2385 static int b43_write_initvals(struct b43_wldev *dev,
2386 const struct b43_iv *ivals,
2387 size_t count,
2388 size_t array_size)
2389 {
2390 const struct b43_iv *iv;
2391 u16 offset;
2392 size_t i;
2393 bool bit32;
2394
2395 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2396 iv = ivals;
2397 for (i = 0; i < count; i++) {
2398 if (array_size < sizeof(iv->offset_size))
2399 goto err_format;
2400 array_size -= sizeof(iv->offset_size);
2401 offset = be16_to_cpu(iv->offset_size);
2402 bit32 = !!(offset & B43_IV_32BIT);
2403 offset &= B43_IV_OFFSET_MASK;
2404 if (offset >= 0x1000)
2405 goto err_format;
2406 if (bit32) {
2407 u32 value;
2408
2409 if (array_size < sizeof(iv->data.d32))
2410 goto err_format;
2411 array_size -= sizeof(iv->data.d32);
2412
2413 value = get_unaligned_be32(&iv->data.d32);
2414 b43_write32(dev, offset, value);
2415
2416 iv = (const struct b43_iv *)((const uint8_t *)iv +
2417 sizeof(__be16) +
2418 sizeof(__be32));
2419 } else {
2420 u16 value;
2421
2422 if (array_size < sizeof(iv->data.d16))
2423 goto err_format;
2424 array_size -= sizeof(iv->data.d16);
2425
2426 value = be16_to_cpu(iv->data.d16);
2427 b43_write16(dev, offset, value);
2428
2429 iv = (const struct b43_iv *)((const uint8_t *)iv +
2430 sizeof(__be16) +
2431 sizeof(__be16));
2432 }
2433 }
2434 if (array_size)
2435 goto err_format;
2436
2437 return 0;
2438
2439 err_format:
2440 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
2441 b43_print_fw_helptext(dev->wl, 1);
2442
2443 return -EPROTO;
2444 }
2445
2446 static int b43_upload_initvals(struct b43_wldev *dev)
2447 {
2448 const size_t hdr_len = sizeof(struct b43_fw_header);
2449 const struct b43_fw_header *hdr;
2450 struct b43_firmware *fw = &dev->fw;
2451 const struct b43_iv *ivals;
2452 size_t count;
2453 int err;
2454
2455 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2456 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
2457 count = be32_to_cpu(hdr->size);
2458 err = b43_write_initvals(dev, ivals, count,
2459 fw->initvals.data->size - hdr_len);
2460 if (err)
2461 goto out;
2462 if (fw->initvals_band.data) {
2463 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2464 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
2465 count = be32_to_cpu(hdr->size);
2466 err = b43_write_initvals(dev, ivals, count,
2467 fw->initvals_band.data->size - hdr_len);
2468 if (err)
2469 goto out;
2470 }
2471 out:
2472
2473 return err;
2474 }
2475
2476 /* Initialize the GPIOs
2477 * http://bcm-specs.sipsolutions.net/GPIO
2478 */
2479 static int b43_gpio_init(struct b43_wldev *dev)
2480 {
2481 struct ssb_bus *bus = dev->dev->bus;
2482 struct ssb_device *gpiodev, *pcidev = NULL;
2483 u32 mask, set;
2484
2485 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2486 & ~B43_MACCTL_GPOUTSMSK);
2487
2488 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
2489 | 0x000F);
2490
2491 mask = 0x0000001F;
2492 set = 0x0000000F;
2493 if (dev->dev->bus->chip_id == 0x4301) {
2494 mask |= 0x0060;
2495 set |= 0x0060;
2496 }
2497 if (0 /* FIXME: conditional unknown */ ) {
2498 b43_write16(dev, B43_MMIO_GPIO_MASK,
2499 b43_read16(dev, B43_MMIO_GPIO_MASK)
2500 | 0x0100);
2501 mask |= 0x0180;
2502 set |= 0x0180;
2503 }
2504 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
2505 b43_write16(dev, B43_MMIO_GPIO_MASK,
2506 b43_read16(dev, B43_MMIO_GPIO_MASK)
2507 | 0x0200);
2508 mask |= 0x0200;
2509 set |= 0x0200;
2510 }
2511 if (dev->dev->id.revision >= 2)
2512 mask |= 0x0010; /* FIXME: This is redundant. */
2513
2514 #ifdef CONFIG_SSB_DRIVER_PCICORE
2515 pcidev = bus->pcicore.dev;
2516 #endif
2517 gpiodev = bus->chipco.dev ? : pcidev;
2518 if (!gpiodev)
2519 return 0;
2520 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2521 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2522 & mask) | set);
2523
2524 return 0;
2525 }
2526
2527 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2528 static void b43_gpio_cleanup(struct b43_wldev *dev)
2529 {
2530 struct ssb_bus *bus = dev->dev->bus;
2531 struct ssb_device *gpiodev, *pcidev = NULL;
2532
2533 #ifdef CONFIG_SSB_DRIVER_PCICORE
2534 pcidev = bus->pcicore.dev;
2535 #endif
2536 gpiodev = bus->chipco.dev ? : pcidev;
2537 if (!gpiodev)
2538 return;
2539 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2540 }
2541
2542 /* http://bcm-specs.sipsolutions.net/EnableMac */
2543 void b43_mac_enable(struct b43_wldev *dev)
2544 {
2545 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2546 u16 fwstate;
2547
2548 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2549 B43_SHM_SH_UCODESTAT);
2550 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2551 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2552 b43err(dev->wl, "b43_mac_enable(): The firmware "
2553 "should be suspended, but current state is %u\n",
2554 fwstate);
2555 }
2556 }
2557
2558 dev->mac_suspended--;
2559 B43_WARN_ON(dev->mac_suspended < 0);
2560 if (dev->mac_suspended == 0) {
2561 b43_write32(dev, B43_MMIO_MACCTL,
2562 b43_read32(dev, B43_MMIO_MACCTL)
2563 | B43_MACCTL_ENABLED);
2564 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2565 B43_IRQ_MAC_SUSPENDED);
2566 /* Commit writes */
2567 b43_read32(dev, B43_MMIO_MACCTL);
2568 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2569 b43_power_saving_ctl_bits(dev, 0);
2570 }
2571 }
2572
2573 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2574 void b43_mac_suspend(struct b43_wldev *dev)
2575 {
2576 int i;
2577 u32 tmp;
2578
2579 might_sleep();
2580 B43_WARN_ON(dev->mac_suspended < 0);
2581
2582 if (dev->mac_suspended == 0) {
2583 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2584 b43_write32(dev, B43_MMIO_MACCTL,
2585 b43_read32(dev, B43_MMIO_MACCTL)
2586 & ~B43_MACCTL_ENABLED);
2587 /* force pci to flush the write */
2588 b43_read32(dev, B43_MMIO_MACCTL);
2589 for (i = 35; i; i--) {
2590 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2591 if (tmp & B43_IRQ_MAC_SUSPENDED)
2592 goto out;
2593 udelay(10);
2594 }
2595 /* Hm, it seems this will take some time. Use msleep(). */
2596 for (i = 40; i; i--) {
2597 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2598 if (tmp & B43_IRQ_MAC_SUSPENDED)
2599 goto out;
2600 msleep(1);
2601 }
2602 b43err(dev->wl, "MAC suspend failed\n");
2603 }
2604 out:
2605 dev->mac_suspended++;
2606 }
2607
2608 static void b43_adjust_opmode(struct b43_wldev *dev)
2609 {
2610 struct b43_wl *wl = dev->wl;
2611 u32 ctl;
2612 u16 cfp_pretbtt;
2613
2614 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2615 /* Reset status to STA infrastructure mode. */
2616 ctl &= ~B43_MACCTL_AP;
2617 ctl &= ~B43_MACCTL_KEEP_CTL;
2618 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2619 ctl &= ~B43_MACCTL_KEEP_BAD;
2620 ctl &= ~B43_MACCTL_PROMISC;
2621 ctl &= ~B43_MACCTL_BEACPROMISC;
2622 ctl |= B43_MACCTL_INFRA;
2623
2624 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
2625 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
2626 ctl |= B43_MACCTL_AP;
2627 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
2628 ctl &= ~B43_MACCTL_INFRA;
2629
2630 if (wl->filter_flags & FIF_CONTROL)
2631 ctl |= B43_MACCTL_KEEP_CTL;
2632 if (wl->filter_flags & FIF_FCSFAIL)
2633 ctl |= B43_MACCTL_KEEP_BAD;
2634 if (wl->filter_flags & FIF_PLCPFAIL)
2635 ctl |= B43_MACCTL_KEEP_BADPLCP;
2636 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2637 ctl |= B43_MACCTL_PROMISC;
2638 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2639 ctl |= B43_MACCTL_BEACPROMISC;
2640
2641 /* Workaround: On old hardware the HW-MAC-address-filter
2642 * doesn't work properly, so always run promisc in filter
2643 * it in software. */
2644 if (dev->dev->id.revision <= 4)
2645 ctl |= B43_MACCTL_PROMISC;
2646
2647 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2648
2649 cfp_pretbtt = 2;
2650 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2651 if (dev->dev->bus->chip_id == 0x4306 &&
2652 dev->dev->bus->chip_rev == 3)
2653 cfp_pretbtt = 100;
2654 else
2655 cfp_pretbtt = 50;
2656 }
2657 b43_write16(dev, 0x612, cfp_pretbtt);
2658 }
2659
2660 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2661 {
2662 u16 offset;
2663
2664 if (is_ofdm) {
2665 offset = 0x480;
2666 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2667 } else {
2668 offset = 0x4C0;
2669 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2670 }
2671 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2672 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2673 }
2674
2675 static void b43_rate_memory_init(struct b43_wldev *dev)
2676 {
2677 switch (dev->phy.type) {
2678 case B43_PHYTYPE_A:
2679 case B43_PHYTYPE_G:
2680 case B43_PHYTYPE_N:
2681 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2682 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2683 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2684 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2685 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2686 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2687 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2688 if (dev->phy.type == B43_PHYTYPE_A)
2689 break;
2690 /* fallthrough */
2691 case B43_PHYTYPE_B:
2692 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2693 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2694 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2695 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2696 break;
2697 default:
2698 B43_WARN_ON(1);
2699 }
2700 }
2701
2702 /* Set the default values for the PHY TX Control Words. */
2703 static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
2704 {
2705 u16 ctl = 0;
2706
2707 ctl |= B43_TXH_PHY_ENC_CCK;
2708 ctl |= B43_TXH_PHY_ANT01AUTO;
2709 ctl |= B43_TXH_PHY_TXPWR;
2710
2711 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
2712 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
2713 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
2714 }
2715
2716 /* Set the TX-Antenna for management frames sent by firmware. */
2717 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2718 {
2719 u16 ant;
2720 u16 tmp;
2721
2722 ant = b43_antenna_to_phyctl(antenna);
2723
2724 /* For ACK/CTS */
2725 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2726 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2727 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2728 /* For Probe Resposes */
2729 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2730 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2731 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2732 }
2733
2734 /* This is the opposite of b43_chip_init() */
2735 static void b43_chip_exit(struct b43_wldev *dev)
2736 {
2737 b43_phy_exit(dev);
2738 b43_gpio_cleanup(dev);
2739 /* firmware is released later */
2740 }
2741
2742 /* Initialize the chip
2743 * http://bcm-specs.sipsolutions.net/ChipInit
2744 */
2745 static int b43_chip_init(struct b43_wldev *dev)
2746 {
2747 struct b43_phy *phy = &dev->phy;
2748 int err;
2749 u32 value32, macctl;
2750 u16 value16;
2751
2752 /* Initialize the MAC control */
2753 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
2754 if (dev->phy.gmode)
2755 macctl |= B43_MACCTL_GMODE;
2756 macctl |= B43_MACCTL_INFRA;
2757 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2758
2759 err = b43_request_firmware(dev);
2760 if (err)
2761 goto out;
2762 err = b43_upload_microcode(dev);
2763 if (err)
2764 goto out; /* firmware is released later */
2765
2766 err = b43_gpio_init(dev);
2767 if (err)
2768 goto out; /* firmware is released later */
2769
2770 err = b43_upload_initvals(dev);
2771 if (err)
2772 goto err_gpio_clean;
2773
2774 /* Turn the Analog on and initialize the PHY. */
2775 phy->ops->switch_analog(dev, 1);
2776 err = b43_phy_init(dev);
2777 if (err)
2778 goto err_gpio_clean;
2779
2780 /* Disable Interference Mitigation. */
2781 if (phy->ops->interf_mitigation)
2782 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
2783
2784 /* Select the antennae */
2785 if (phy->ops->set_rx_antenna)
2786 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2787 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2788
2789 if (phy->type == B43_PHYTYPE_B) {
2790 value16 = b43_read16(dev, 0x005E);
2791 value16 |= 0x0004;
2792 b43_write16(dev, 0x005E, value16);
2793 }
2794 b43_write32(dev, 0x0100, 0x01000000);
2795 if (dev->dev->id.revision < 5)
2796 b43_write32(dev, 0x010C, 0x01000000);
2797
2798 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2799 & ~B43_MACCTL_INFRA);
2800 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2801 | B43_MACCTL_INFRA);
2802
2803 /* Probe Response Timeout value */
2804 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2805 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2806
2807 /* Initially set the wireless operation mode. */
2808 b43_adjust_opmode(dev);
2809
2810 if (dev->dev->id.revision < 3) {
2811 b43_write16(dev, 0x060E, 0x0000);
2812 b43_write16(dev, 0x0610, 0x8000);
2813 b43_write16(dev, 0x0604, 0x0000);
2814 b43_write16(dev, 0x0606, 0x0200);
2815 } else {
2816 b43_write32(dev, 0x0188, 0x80000000);
2817 b43_write32(dev, 0x018C, 0x02000000);
2818 }
2819 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2820 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2821 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2822 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2823 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2824 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2825 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2826
2827 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2828 value32 |= 0x00100000;
2829 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2830
2831 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2832 dev->dev->bus->chipco.fast_pwrup_delay);
2833
2834 err = 0;
2835 b43dbg(dev->wl, "Chip initialized\n");
2836 out:
2837 return err;
2838
2839 err_gpio_clean:
2840 b43_gpio_cleanup(dev);
2841 return err;
2842 }
2843
2844 static void b43_periodic_every60sec(struct b43_wldev *dev)
2845 {
2846 const struct b43_phy_operations *ops = dev->phy.ops;
2847
2848 if (ops->pwork_60sec)
2849 ops->pwork_60sec(dev);
2850
2851 /* Force check the TX power emission now. */
2852 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
2853 }
2854
2855 static void b43_periodic_every30sec(struct b43_wldev *dev)
2856 {
2857 /* Update device statistics. */
2858 b43_calculate_link_quality(dev);
2859 }
2860
2861 static void b43_periodic_every15sec(struct b43_wldev *dev)
2862 {
2863 struct b43_phy *phy = &dev->phy;
2864 u16 wdr;
2865
2866 if (dev->fw.opensource) {
2867 /* Check if the firmware is still alive.
2868 * It will reset the watchdog counter to 0 in its idle loop. */
2869 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
2870 if (unlikely(wdr)) {
2871 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
2872 b43_controller_restart(dev, "Firmware watchdog");
2873 return;
2874 } else {
2875 b43_shm_write16(dev, B43_SHM_SCRATCH,
2876 B43_WATCHDOG_REG, 1);
2877 }
2878 }
2879
2880 if (phy->ops->pwork_15sec)
2881 phy->ops->pwork_15sec(dev);
2882
2883 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2884 wmb();
2885 }
2886
2887 static void do_periodic_work(struct b43_wldev *dev)
2888 {
2889 unsigned int state;
2890
2891 state = dev->periodic_state;
2892 if (state % 4 == 0)
2893 b43_periodic_every60sec(dev);
2894 if (state % 2 == 0)
2895 b43_periodic_every30sec(dev);
2896 b43_periodic_every15sec(dev);
2897 }
2898
2899 /* Periodic work locking policy:
2900 * The whole periodic work handler is protected by
2901 * wl->mutex. If another lock is needed somewhere in the
2902 * pwork callchain, it's aquired in-place, where it's needed.
2903 */
2904 static void b43_periodic_work_handler(struct work_struct *work)
2905 {
2906 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2907 periodic_work.work);
2908 struct b43_wl *wl = dev->wl;
2909 unsigned long delay;
2910
2911 mutex_lock(&wl->mutex);
2912
2913 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2914 goto out;
2915 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2916 goto out_requeue;
2917
2918 do_periodic_work(dev);
2919
2920 dev->periodic_state++;
2921 out_requeue:
2922 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2923 delay = msecs_to_jiffies(50);
2924 else
2925 delay = round_jiffies_relative(HZ * 15);
2926 queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
2927 out:
2928 mutex_unlock(&wl->mutex);
2929 }
2930
2931 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2932 {
2933 struct delayed_work *work = &dev->periodic_work;
2934
2935 dev->periodic_state = 0;
2936 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2937 queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2938 }
2939
2940 /* Check if communication with the device works correctly. */
2941 static int b43_validate_chipaccess(struct b43_wldev *dev)
2942 {
2943 u32 v, backup;
2944
2945 backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2946
2947 /* Check for read/write and endianness problems. */
2948 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2949 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2950 goto error;
2951 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2952 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
2953 goto error;
2954
2955 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup);
2956
2957 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
2958 /* The 32bit register shadows the two 16bit registers
2959 * with update sideeffects. Validate this. */
2960 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
2961 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
2962 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
2963 goto error;
2964 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
2965 goto error;
2966 }
2967 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
2968
2969 v = b43_read32(dev, B43_MMIO_MACCTL);
2970 v |= B43_MACCTL_GMODE;
2971 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
2972 goto error;
2973
2974 return 0;
2975 error:
2976 b43err(dev->wl, "Failed to validate the chipaccess\n");
2977 return -ENODEV;
2978 }
2979
2980 static void b43_security_init(struct b43_wldev *dev)
2981 {
2982 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2983 B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2984 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2985 /* KTP is a word address, but we address SHM bytewise.
2986 * So multiply by two.
2987 */
2988 dev->ktp *= 2;
2989 if (dev->dev->id.revision >= 5) {
2990 /* Number of RCMTA address slots */
2991 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2992 }
2993 b43_clear_keys(dev);
2994 }
2995
2996 #ifdef CONFIG_B43_HWRNG
2997 static int b43_rng_read(struct hwrng *rng, u32 *data)
2998 {
2999 struct b43_wl *wl = (struct b43_wl *)rng->priv;
3000 unsigned long flags;
3001
3002 /* Don't take wl->mutex here, as it could deadlock with
3003 * hwrng internal locking. It's not needed to take
3004 * wl->mutex here, anyway. */
3005
3006 spin_lock_irqsave(&wl->irq_lock, flags);
3007 *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
3008 spin_unlock_irqrestore(&wl->irq_lock, flags);
3009
3010 return (sizeof(u16));
3011 }
3012 #endif /* CONFIG_B43_HWRNG */
3013
3014 static void b43_rng_exit(struct b43_wl *wl)
3015 {
3016 #ifdef CONFIG_B43_HWRNG
3017 if (wl->rng_initialized)
3018 hwrng_unregister(&wl->rng);
3019 #endif /* CONFIG_B43_HWRNG */
3020 }
3021
3022 static int b43_rng_init(struct b43_wl *wl)
3023 {
3024 int err = 0;
3025
3026 #ifdef CONFIG_B43_HWRNG
3027 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
3028 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
3029 wl->rng.name = wl->rng_name;
3030 wl->rng.data_read = b43_rng_read;
3031 wl->rng.priv = (unsigned long)wl;
3032 wl->rng_initialized = 1;
3033 err = hwrng_register(&wl->rng);
3034 if (err) {
3035 wl->rng_initialized = 0;
3036 b43err(wl, "Failed to register the random "
3037 "number generator (%d)\n", err);
3038 }
3039 #endif /* CONFIG_B43_HWRNG */
3040
3041 return err;
3042 }
3043
3044 static int b43_op_tx(struct ieee80211_hw *hw,
3045 struct sk_buff *skb)
3046 {
3047 struct b43_wl *wl = hw_to_b43_wl(hw);
3048 struct b43_wldev *dev = wl->current_dev;
3049 unsigned long flags;
3050 int err;
3051
3052 if (unlikely(skb->len < 2 + 2 + 6)) {
3053 /* Too short, this can't be a valid frame. */
3054 goto drop_packet;
3055 }
3056 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
3057 if (unlikely(!dev))
3058 goto drop_packet;
3059
3060 /* Transmissions on seperate queues can run concurrently. */
3061 read_lock_irqsave(&wl->tx_lock, flags);
3062
3063 err = -ENODEV;
3064 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
3065 if (b43_using_pio_transfers(dev))
3066 err = b43_pio_tx(dev, skb);
3067 else
3068 err = b43_dma_tx(dev, skb);
3069 }
3070
3071 read_unlock_irqrestore(&wl->tx_lock, flags);
3072
3073 if (unlikely(err))
3074 goto drop_packet;
3075 return NETDEV_TX_OK;
3076
3077 drop_packet:
3078 /* We can not transmit this packet. Drop it. */
3079 dev_kfree_skb_any(skb);
3080 return NETDEV_TX_OK;
3081 }
3082
3083 /* Locking: wl->irq_lock */
3084 static void b43_qos_params_upload(struct b43_wldev *dev,
3085 const struct ieee80211_tx_queue_params *p,
3086 u16 shm_offset)
3087 {
3088 u16 params[B43_NR_QOSPARAMS];
3089 int bslots, tmp;
3090 unsigned int i;
3091
3092 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
3093
3094 memset(¶ms, 0, sizeof(params));
3095
3096 params[B43_QOSPARAM_TXOP] = p->txop * 32;
3097 params[B43_QOSPARAM_CWMIN] = p->cw_min;
3098 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3099 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3100 params[B43_QOSPARAM_AIFS] = p->aifs;
3101 params[B43_QOSPARAM_BSLOTS] = bslots;
3102 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
3103
3104 for (i = 0; i < ARRAY_SIZE(params); i++) {
3105 if (i == B43_QOSPARAM_STATUS) {
3106 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3107 shm_offset + (i * 2));
3108 /* Mark the parameters as updated. */
3109 tmp |= 0x100;
3110 b43_shm_write16(dev, B43_SHM_SHARED,
3111 shm_offset + (i * 2),
3112 tmp);
3113 } else {
3114 b43_shm_write16(dev, B43_SHM_SHARED,
3115 shm_offset + (i * 2),
3116 params[i]);
3117 }
3118 }
3119 }
3120
3121 /* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3122 static const u16 b43_qos_shm_offsets[] = {
3123 /* [mac80211-queue-nr] = SHM_OFFSET, */
3124 [0] = B43_QOS_VOICE,
3125 [1] = B43_QOS_VIDEO,
3126 [2] = B43_QOS_BESTEFFORT,
3127 [3] = B43_QOS_BACKGROUND,
3128 };
3129
3130 /* Update all QOS parameters in hardware. */
3131 static void b43_qos_upload_all(struct b43_wldev *dev)
3132 {
3133 struct b43_wl *wl = dev->wl;
3134 struct b43_qos_params *params;
3135 unsigned int i;
3136
3137 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3138 ARRAY_SIZE(wl->qos_params));
3139
3140 b43_mac_suspend(dev);
3141 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3142 params = &(wl->qos_params[i]);
3143 b43_qos_params_upload(dev, &(params->p),
3144 b43_qos_shm_offsets[i]);
3145 }
3146 b43_mac_enable(dev);
3147 }
3148
3149 static void b43_qos_clear(struct b43_wl *wl)
3150 {
3151 struct b43_qos_params *params;
3152 unsigned int i;
3153
3154 /* Initialize QoS parameters to sane defaults. */
3155
3156 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3157 ARRAY_SIZE(wl->qos_params));
3158
3159 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3160 params = &(wl->qos_params[i]);
3161
3162 switch (b43_qos_shm_offsets[i]) {
3163 case B43_QOS_VOICE:
3164 params->p.txop = 0;
3165 params->p.aifs = 2;
3166 params->p.cw_min = 0x0001;
3167 params->p.cw_max = 0x0001;
3168 break;
3169 case B43_QOS_VIDEO:
3170 params->p.txop = 0;
3171 params->p.aifs = 2;
3172 params->p.cw_min = 0x0001;
3173 params->p.cw_max = 0x0001;
3174 break;
3175 case B43_QOS_BESTEFFORT:
3176 params->p.txop = 0;
3177 params->p.aifs = 3;
3178 params->p.cw_min = 0x0001;
3179 params->p.cw_max = 0x03FF;
3180 break;
3181 case B43_QOS_BACKGROUND:
3182 params->p.txop = 0;
3183 params->p.aifs = 7;
3184 params->p.cw_min = 0x0001;
3185 params->p.cw_max = 0x03FF;
3186 break;
3187 default:
3188 B43_WARN_ON(1);
3189 }
3190 }
3191 }
3192
3193 /* Initialize the core's QOS capabilities */
3194 static void b43_qos_init(struct b43_wldev *dev)
3195 {
3196 /* Upload the current QOS parameters. */
3197 b43_qos_upload_all(dev);
3198
3199 /* Enable QOS support. */
3200 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3201 b43_write16(dev, B43_MMIO_IFSCTL,
3202 b43_read16(dev, B43_MMIO_IFSCTL)
3203 | B43_MMIO_IFSCTL_USE_EDCF);
3204 }
3205
3206 static int b43_op_conf_tx(struct ieee80211_hw *hw, u16 _queue,
3207 const struct ieee80211_tx_queue_params *params)
3208 {
3209 struct b43_wl *wl = hw_to_b43_wl(hw);
3210 struct b43_wldev *dev;
3211 unsigned int queue = (unsigned int)_queue;
3212 int err = -ENODEV;
3213
3214 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3215 /* Queue not available or don't support setting
3216 * params on this queue. Return success to not
3217 * confuse mac80211. */
3218 return 0;
3219 }
3220 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3221 ARRAY_SIZE(wl->qos_params));
3222
3223 mutex_lock(&wl->mutex);
3224 dev = wl->current_dev;
3225 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3226 goto out_unlock;
3227
3228 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3229 b43_mac_suspend(dev);
3230 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3231 b43_qos_shm_offsets[queue]);
3232 b43_mac_enable(dev);
3233 err = 0;
3234
3235 out_unlock:
3236 mutex_unlock(&wl->mutex);
3237
3238 return err;
3239 }
3240
3241 static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
3242 struct ieee80211_tx_queue_stats *stats)
3243 {
3244 struct b43_wl *wl = hw_to_b43_wl(hw);
3245 struct b43_wldev *dev = wl->current_dev;
3246 unsigned long flags;
3247 int err = -ENODEV;
3248
3249 if (!dev)
3250 goto out;
3251 spin_lock_irqsave(&wl->irq_lock, flags);
3252 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
3253 if (b43_using_pio_transfers(dev))
3254 b43_pio_get_tx_stats(dev, stats);
3255 else
3256 b43_dma_get_tx_stats(dev, stats);
3257 err = 0;
3258 }
3259 spin_unlock_irqrestore(&wl->irq_lock, flags);
3260 out:
3261 return err;
3262 }
3263
3264 static int b43_op_get_stats(struct ieee80211_hw *hw,
3265 struct ieee80211_low_level_stats *stats)
3266 {
3267 struct b43_wl *wl = hw_to_b43_wl(hw);
3268 unsigned long flags;
3269
3270 spin_lock_irqsave(&wl->irq_lock, flags);
3271 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
3272 spin_unlock_irqrestore(&wl->irq_lock, flags);
3273
3274 return 0;
3275 }
3276
3277 static u64 b43_op_get_tsf(struct ieee80211_hw *hw)
3278 {
3279 struct b43_wl *wl = hw_to_b43_wl(hw);
3280 struct b43_wldev *dev;
3281 u64 tsf;
3282
3283 mutex_lock(&wl->mutex);
3284 spin_lock_irq(&wl->irq_lock);
3285 dev = wl->current_dev;
3286
3287 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3288 b43_tsf_read(dev, &tsf);
3289 else
3290 tsf = 0;
3291
3292 spin_unlock_irq(&wl->irq_lock);
3293 mutex_unlock(&wl->mutex);
3294
3295 return tsf;
3296 }
3297
3298 static void b43_op_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3299 {
3300 struct b43_wl *wl = hw_to_b43_wl(hw);
3301 struct b43_wldev *dev;
3302
3303 mutex_lock(&wl->mutex);
3304 spin_lock_irq(&wl->irq_lock);
3305 dev = wl->current_dev;
3306
3307 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3308 b43_tsf_write(dev, tsf);
3309
3310 spin_unlock_irq(&wl->irq_lock);
3311 mutex_unlock(&wl->mutex);
3312 }
3313
3314 static void b43_put_phy_into_reset(struct b43_wldev *dev)
3315 {
3316 struct ssb_device *sdev = dev->dev;
3317 u32 tmslow;
3318
3319 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3320 tmslow &= ~B43_TMSLOW_GMODE;
3321 tmslow |= B43_TMSLOW_PHYRESET;
3322 tmslow |= SSB_TMSLOW_FGC;
3323 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3324 msleep(1);
3325
3326 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3327 tmslow &= ~SSB_TMSLOW_FGC;
3328 tmslow |= B43_TMSLOW_PHYRESET;
3329 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3330 msleep(1);
3331 }
3332
3333 static const char *band_to_string(enum ieee80211_band band)
3334 {
3335 switch (band) {
3336 case IEEE80211_BAND_5GHZ:
3337 return "5";
3338 case IEEE80211_BAND_2GHZ:
3339 return "2.4";
3340 default:
3341 break;
3342 }
3343 B43_WARN_ON(1);
3344 return "";
3345 }
3346
3347 /* Expects wl->mutex locked */
3348 static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
3349 {
3350 struct b43_wldev *up_dev = NULL;
3351 struct b43_wldev *down_dev;
3352 struct b43_wldev *d;
3353 int err;
3354 bool uninitialized_var(gmode);
3355 int prev_status;
3356
3357 /* Find a device and PHY which supports the band. */
3358 list_for_each_entry(d, &wl->devlist, list) {
3359 switch (chan->band) {
3360 case IEEE80211_BAND_5GHZ:
3361 if (d->phy.supports_5ghz) {
3362 up_dev = d;
3363 gmode = 0;
3364 }
3365 break;
3366 case IEEE80211_BAND_2GHZ:
3367 if (d->phy.supports_2ghz) {
3368 up_dev = d;
3369 gmode = 1;
3370 }
3371 break;
3372 default:
3373 B43_WARN_ON(1);
3374 return -EINVAL;
3375 }
3376 if (up_dev)
3377 break;
3378 }
3379 if (!up_dev) {
3380 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3381 band_to_string(chan->band));
3382 return -ENODEV;
3383 }
3384 if ((up_dev == wl->current_dev) &&
3385 (!!wl->current_dev->phy.gmode == !!gmode)) {
3386 /* This device is already running. */
3387 return 0;
3388 }
3389 b43dbg(wl, "Switching to %s-GHz band\n",
3390 band_to_string(chan->band));
3391 down_dev = wl->current_dev;
3392
3393 prev_status = b43_status(down_dev);
3394 /* Shutdown the currently running core. */
3395 if (prev_status >= B43_STAT_STARTED)
3396 b43_wireless_core_stop(down_dev);
3397 if (prev_status >= B43_STAT_INITIALIZED)
3398 b43_wireless_core_exit(down_dev);
3399
3400 if (down_dev != up_dev) {
3401 /* We switch to a different core, so we put PHY into
3402 * RESET on the old core. */
3403 b43_put_phy_into_reset(down_dev);
3404 }
3405
3406 /* Now start the new core. */
3407 up_dev->phy.gmode = gmode;
3408 if (prev_status >= B43_STAT_INITIALIZED) {
3409 err = b43_wireless_core_init(up_dev);
3410 if (err) {
3411 b43err(wl, "Fatal: Could not initialize device for "
3412 "selected %s-GHz band\n",
3413 band_to_string(chan->band));
3414 goto init_failure;
3415 }
3416 }
3417 if (prev_status >= B43_STAT_STARTED) {
3418 err = b43_wireless_core_start(up_dev);
3419 if (err) {
3420 b43err(wl, "Fatal: Coult not start device for "
3421 "selected %s-GHz band\n",
3422 band_to_string(chan->band));
3423 b43_wireless_core_exit(up_dev);
3424 goto init_failure;
3425 }
3426 }
3427 B43_WARN_ON(b43_status(up_dev) != prev_status);
3428
3429 wl->current_dev = up_dev;
3430
3431 return 0;
3432 init_failure:
3433 /* Whoops, failed to init the new core. No core is operating now. */
3434 wl->current_dev = NULL;
3435 return err;
3436 }
3437
3438 /* Write the short and long frame retry limit values. */
3439 static void b43_set_retry_limits(struct b43_wldev *dev,
3440 unsigned int short_retry,
3441 unsigned int long_retry)
3442 {
3443 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3444 * the chip-internal counter. */
3445 short_retry = min(short_retry, (unsigned int)0xF);
3446 long_retry = min(long_retry, (unsigned int)0xF);
3447
3448 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3449 short_retry);
3450 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3451 long_retry);
3452 }
3453
3454 static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
3455 {
3456 struct b43_wl *wl = hw_to_b43_wl(hw);
3457 struct b43_wldev *dev;
3458 struct b43_phy *phy;
3459 struct ieee80211_conf *conf = &hw->conf;
3460 unsigned long flags;
3461 int antenna;
3462 int err = 0;
3463
3464 mutex_lock(&wl->mutex);
3465
3466 /* Switch the band (if necessary). This might change the active core. */
3467 err = b43_switch_band(wl, conf->channel);
3468 if (err)
3469 goto out_unlock_mutex;
3470 dev = wl->current_dev;
3471 phy = &dev->phy;
3472
3473 b43_mac_suspend(dev);
3474
3475 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3476 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
3477 conf->long_frame_max_tx_count);
3478 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
3479 if (!changed)
3480 goto out_mac_enable;
3481
3482 /* Switch to the requested channel.
3483 * The firmware takes care of races with the TX handler. */
3484 if (conf->channel->hw_value != phy->channel)
3485 b43_switch_channel(dev, conf->channel->hw_value);
3486
3487 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
3488
3489 /* Adjust the desired TX power level. */
3490 if (conf->power_level != 0) {
3491 spin_lock_irqsave(&wl->irq_lock, flags);
3492 if (conf->power_level != phy->desired_txpower) {
3493 phy->desired_txpower = conf->power_level;
3494 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3495 B43_TXPWR_IGNORE_TSSI);
3496 }
3497 spin_unlock_irqrestore(&wl->irq_lock, flags);
3498 }
3499
3500 /* Antennas for RX and management frame TX. */
3501 antenna = B43_ANTENNA_DEFAULT;
3502 b43_mgmtframe_txantenna(dev, antenna);
3503 antenna = B43_ANTENNA_DEFAULT;
3504 if (phy->ops->set_rx_antenna)
3505 phy->ops->set_rx_antenna(dev, antenna);
3506
3507 if (wl->radio_enabled != phy->radio_on) {
3508 if (wl->radio_enabled) {
3509 b43_software_rfkill(dev, false);
3510 b43info(dev->wl, "Radio turned on by software\n");
3511 if (!dev->radio_hw_enable) {
3512 b43info(dev->wl, "The hardware RF-kill button "
3513 "still turns the radio physically off. "
3514 "Press the button to turn it on.\n");
3515 }
3516 } else {
3517 b43_software_rfkill(dev, true);
3518 b43info(dev->wl, "Radio turned off by software\n");
3519 }
3520 }
3521
3522 out_mac_enable:
3523 b43_mac_enable(dev);
3524 out_unlock_mutex:
3525 mutex_unlock(&wl->mutex);
3526
3527 return err;
3528 }
3529
3530 static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
3531 {
3532 struct ieee80211_supported_band *sband =
3533 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
3534 struct ieee80211_rate *rate;
3535 int i;
3536 u16 basic, direct, offset, basic_offset, rateptr;
3537
3538 for (i = 0; i < sband->n_bitrates; i++) {
3539 rate = &sband->bitrates[i];
3540
3541 if (b43_is_cck_rate(rate->hw_value)) {
3542 direct = B43_SHM_SH_CCKDIRECT;
3543 basic = B43_SHM_SH_CCKBASIC;
3544 offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3545 offset &= 0xF;
3546 } else {
3547 direct = B43_SHM_SH_OFDMDIRECT;
3548 basic = B43_SHM_SH_OFDMBASIC;
3549 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3550 offset &= 0xF;
3551 }
3552
3553 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
3554
3555 if (b43_is_cck_rate(rate->hw_value)) {
3556 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3557 basic_offset &= 0xF;
3558 } else {
3559 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3560 basic_offset &= 0xF;
3561 }
3562
3563 /*
3564 * Get the pointer that we need to point to
3565 * from the direct map
3566 */
3567 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
3568 direct + 2 * basic_offset);
3569 /* and write it to the basic map */
3570 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
3571 rateptr);
3572 }
3573 }
3574
3575 static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
3576 struct ieee80211_vif *vif,
3577 struct ieee80211_bss_conf *conf,
3578 u32 changed)
3579 {
3580 struct b43_wl *wl = hw_to_b43_wl(hw);
3581 struct b43_wldev *dev;
3582 unsigned long flags;
3583
3584 mutex_lock(&wl->mutex);
3585
3586 dev = wl->current_dev;
3587 if (!dev || b43_status(dev) < B43_STAT_STARTED)
3588 goto out_unlock_mutex;
3589
3590 B43_WARN_ON(wl->vif != vif);
3591
3592 spin_lock_irqsave(&wl->irq_lock, flags);
3593 if (changed & BSS_CHANGED_BSSID) {
3594 if (conf->bssid)
3595 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3596 else
3597 memset(wl->bssid, 0, ETH_ALEN);
3598 }
3599
3600 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3601 if (changed & BSS_CHANGED_BEACON &&
3602 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3603 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3604 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3605 b43_update_templates(wl);
3606
3607 if (changed & BSS_CHANGED_BSSID)
3608 b43_write_mac_bssid_templates(dev);
3609 }
3610 spin_unlock_irqrestore(&wl->irq_lock, flags);
3611
3612 b43_mac_suspend(dev);
3613
3614 /* Update templates for AP/mesh mode. */
3615 if (changed & BSS_CHANGED_BEACON_INT &&
3616 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3617 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3618 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3619 b43_set_beacon_int(dev, conf->beacon_int);
3620
3621 if (changed & BSS_CHANGED_BASIC_RATES)
3622 b43_update_basic_rates(dev, conf->basic_rates);
3623
3624 if (changed & BSS_CHANGED_ERP_SLOT) {
3625 if (conf->use_short_slot)
3626 b43_short_slot_timing_enable(dev);
3627 else
3628 b43_short_slot_timing_disable(dev);
3629 }
3630
3631 b43_mac_enable(dev);
3632 out_unlock_mutex:
3633 mutex_unlock(&wl->mutex);
3634 }
3635
3636 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3637 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3638 struct ieee80211_key_conf *key)
3639 {
3640 struct b43_wl *wl = hw_to_b43_wl(hw);
3641 struct b43_wldev *dev;
3642 u8 algorithm;
3643 u8 index;
3644 int err;
3645 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
3646
3647 if (modparam_nohwcrypt)
3648 return -ENOSPC; /* User disabled HW-crypto */
3649
3650 mutex_lock(&wl->mutex);
3651 spin_lock_irq(&wl->irq_lock);
3652 write_lock(&wl->tx_lock);
3653 /* Why do we need all this locking here?
3654 * mutex -> Every config operation must take it.
3655 * irq_lock -> We modify the dev->key array, which is accessed
3656 * in the IRQ handlers.
3657 * tx_lock -> We modify the dev->key array, which is accessed
3658 * in the TX handler.
3659 */
3660
3661 dev = wl->current_dev;
3662 err = -ENODEV;
3663 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
3664 goto out_unlock;
3665
3666 if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) {
3667 /* We don't have firmware for the crypto engine.
3668 * Must use software-crypto. */
3669 err = -EOPNOTSUPP;
3670 goto out_unlock;
3671 }
3672
3673 err = -EINVAL;
3674 switch (key->alg) {
3675 case ALG_WEP:
3676 if (key->keylen == WLAN_KEY_LEN_WEP40)
3677 algorithm = B43_SEC_ALGO_WEP40;
3678 else
3679 algorithm = B43_SEC_ALGO_WEP104;
3680 break;
3681 case ALG_TKIP:
3682 algorithm = B43_SEC_ALGO_TKIP;
3683 break;
3684 case ALG_CCMP:
3685 algorithm = B43_SEC_ALGO_AES;
3686 break;
3687 default:
3688 B43_WARN_ON(1);
3689 goto out_unlock;
3690 }
3691 index = (u8) (key->keyidx);
3692 if (index > 3)
3693 goto out_unlock;
3694
3695 switch (cmd) {
3696 case SET_KEY:
3697 if (algorithm == B43_SEC_ALGO_TKIP) {
3698 /* FIXME: No TKIP hardware encryption for now. */
3699 err = -EOPNOTSUPP;
3700 goto out_unlock;
3701 }
3702
3703 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
3704 if (WARN_ON(!sta)) {
3705 err = -EOPNOTSUPP;
3706 goto out_unlock;
3707 }
3708 /* Pairwise key with an assigned MAC address. */
3709 err = b43_key_write(dev, -1, algorithm,
3710 key->key, key->keylen,
3711 sta->addr, key);
3712 } else {
3713 /* Group key */
3714 err = b43_key_write(dev, index, algorithm,
3715 key->key, key->keylen, NULL, key);
3716 }
3717 if (err)
3718 goto out_unlock;
3719
3720 if (algorithm == B43_SEC_ALGO_WEP40 ||
3721 algorithm == B43_SEC_ALGO_WEP104) {
3722 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
3723 } else {
3724 b43_hf_write(dev,
3725 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
3726 }
3727 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3728 break;
3729 case DISABLE_KEY: {
3730 err = b43_key_clear(dev, key->hw_key_idx);
3731 if (err)
3732 goto out_unlock;
3733 break;
3734 }
3735 default:
3736 B43_WARN_ON(1);
3737 }
3738
3739 out_unlock:
3740 if (!err) {
3741 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
3742 "mac: %pM\n",
3743 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
3744 sta ? sta->addr : bcast_addr);
3745 b43_dump_keymemory(dev);
3746 }
3747 write_unlock(&wl->tx_lock);
3748 spin_unlock_irq(&wl->irq_lock);
3749 mutex_unlock(&wl->mutex);
3750
3751 return err;
3752 }
3753
3754 static void b43_op_configure_filter(struct ieee80211_hw *hw,
3755 unsigned int changed, unsigned int *fflags,
3756 int mc_count, struct dev_addr_list *mc_list)
3757 {
3758 struct b43_wl *wl = hw_to_b43_wl(hw);
3759 struct b43_wldev *dev = wl->current_dev;
3760 unsigned long flags;
3761
3762 if (!dev) {
3763 *fflags = 0;
3764 return;
3765 }
3766
3767 spin_lock_irqsave(&wl->irq_lock, flags);
3768 *fflags &= FIF_PROMISC_IN_BSS |
3769 FIF_ALLMULTI |
3770 FIF_FCSFAIL |
3771 FIF_PLCPFAIL |
3772 FIF_CONTROL |
3773 FIF_OTHER_BSS |
3774 FIF_BCN_PRBRESP_PROMISC;
3775
3776 changed &= FIF_PROMISC_IN_BSS |
3777 FIF_ALLMULTI |
3778 FIF_FCSFAIL |
3779 FIF_PLCPFAIL |
3780 FIF_CONTROL |
3781 FIF_OTHER_BSS |
3782 FIF_BCN_PRBRESP_PROMISC;
3783
3784 wl->filter_flags = *fflags;
3785
3786 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
3787 b43_adjust_opmode(dev);
3788 spin_unlock_irqrestore(&wl->irq_lock, flags);
3789 }
3790
3791 /* Locking: wl->mutex */
3792 static void b43_wireless_core_stop(struct b43_wldev *dev)
3793 {
3794 struct b43_wl *wl = dev->wl;
3795 unsigned long flags;
3796
3797 if (b43_status(dev) < B43_STAT_STARTED)
3798 return;
3799
3800 /* Disable and sync interrupts. We must do this before than
3801 * setting the status to INITIALIZED, as the interrupt handler
3802 * won't care about IRQs then. */
3803 spin_lock_irqsave(&wl->irq_lock, flags);
3804 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
3805 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
3806 spin_unlock_irqrestore(&wl->irq_lock, flags);
3807 b43_synchronize_irq(dev);
3808
3809 write_lock_irqsave(&wl->tx_lock, flags);
3810 b43_set_status(dev, B43_STAT_INITIALIZED);
3811 write_unlock_irqrestore(&wl->tx_lock, flags);
3812
3813 b43_pio_stop(dev);
3814 mutex_unlock(&wl->mutex);
3815 /* Must unlock as it would otherwise deadlock. No races here.
3816 * Cancel the possibly running self-rearming periodic work. */
3817 cancel_delayed_work_sync(&dev->periodic_work);
3818 mutex_lock(&wl->mutex);
3819
3820 b43_mac_suspend(dev);
3821 free_irq(dev->dev->irq, dev);
3822 b43dbg(wl, "Wireless interface stopped\n");
3823 }
3824
3825 /* Locking: wl->mutex */
3826 static int b43_wireless_core_start(struct b43_wldev *dev)
3827 {
3828 int err;
3829
3830 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3831
3832 drain_txstatus_queue(dev);
3833 err = request_irq(dev->dev->irq, b43_interrupt_handler,
3834 IRQF_SHARED, KBUILD_MODNAME, dev);
3835 if (err) {
3836 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3837 goto out;
3838 }
3839
3840 /* We are ready to run. */
3841 b43_set_status(dev, B43_STAT_STARTED);
3842
3843 /* Start data flow (TX/RX). */
3844 b43_mac_enable(dev);
3845 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
3846
3847 /* Start maintainance work */
3848 b43_periodic_tasks_setup(dev);
3849
3850 b43dbg(dev->wl, "Wireless interface started\n");
3851 out:
3852 return err;
3853 }
3854
3855 /* Get PHY and RADIO versioning numbers */
3856 static int b43_phy_versioning(struct b43_wldev *dev)
3857 {
3858 struct b43_phy *phy = &dev->phy;
3859 u32 tmp;
3860 u8 analog_type;
3861 u8 phy_type;
3862 u8 phy_rev;
3863 u16 radio_manuf;
3864 u16 radio_ver;
3865 u16 radio_rev;
3866 int unsupported = 0;
3867
3868 /* Get PHY versioning */
3869 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3870 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3871 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3872 phy_rev = (tmp & B43_PHYVER_VERSION);
3873 switch (phy_type) {
3874 case B43_PHYTYPE_A:
3875 if (phy_rev >= 4)
3876 unsupported = 1;
3877 break;
3878 case B43_PHYTYPE_B:
3879 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3880 && phy_rev != 7)
3881 unsupported = 1;
3882 break;
3883 case B43_PHYTYPE_G:
3884 if (phy_rev > 9)
3885 unsupported = 1;
3886 break;
3887 #ifdef CONFIG_B43_NPHY
3888 case B43_PHYTYPE_N:
3889 if (phy_rev > 4)
3890 unsupported = 1;
3891 break;
3892 #endif
3893 #ifdef CONFIG_B43_PHY_LP
3894 case B43_PHYTYPE_LP:
3895 if (phy_rev > 1)
3896 unsupported = 1;
3897 break;
3898 #endif
3899 default:
3900 unsupported = 1;
3901 };
3902 if (unsupported) {
3903 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3904 "(Analog %u, Type %u, Revision %u)\n",
3905 analog_type, phy_type, phy_rev);
3906 return -EOPNOTSUPP;
3907 }
3908 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3909 analog_type, phy_type, phy_rev);
3910
3911 /* Get RADIO versioning */
3912 if (dev->dev->bus->chip_id == 0x4317) {
3913 if (dev->dev->bus->chip_rev == 0)
3914 tmp = 0x3205017F;
3915 else if (dev->dev->bus->chip_rev == 1)
3916 tmp = 0x4205017F;
3917 else
3918 tmp = 0x5205017F;
3919 } else {
3920 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3921 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3922 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3923 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
3924 }
3925 radio_manuf = (tmp & 0x00000FFF);
3926 radio_ver = (tmp & 0x0FFFF000) >> 12;
3927 radio_rev = (tmp & 0xF0000000) >> 28;
3928 if (radio_manuf != 0x17F /* Broadcom */)
3929 unsupported = 1;
3930 switch (phy_type) {
3931 case B43_PHYTYPE_A:
3932 if (radio_ver != 0x2060)
3933 unsupported = 1;
3934 if (radio_rev != 1)
3935 unsupported = 1;
3936 if (radio_manuf != 0x17F)
3937 unsupported = 1;
3938 break;
3939 case B43_PHYTYPE_B:
3940 if ((radio_ver & 0xFFF0) != 0x2050)
3941 unsupported = 1;
3942 break;
3943 case B43_PHYTYPE_G:
3944 if (radio_ver != 0x2050)
3945 unsupported = 1;
3946 break;
3947 case B43_PHYTYPE_N:
3948 if (radio_ver != 0x2055 && radio_ver != 0x2056)
3949 unsupported = 1;
3950 break;
3951 case B43_PHYTYPE_LP:
3952 if (radio_ver != 0x2062)
3953 unsupported = 1;
3954 break;
3955 default:
3956 B43_WARN_ON(1);
3957 }
3958 if (unsupported) {
3959 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3960 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3961 radio_manuf, radio_ver, radio_rev);
3962 return -EOPNOTSUPP;
3963 }
3964 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3965 radio_manuf, radio_ver, radio_rev);
3966
3967 phy->radio_manuf = radio_manuf;
3968 phy->radio_ver = radio_ver;
3969 phy->radio_rev = radio_rev;
3970
3971 phy->analog = analog_type;
3972 phy->type = phy_type;
3973 phy->rev = phy_rev;
3974
3975 return 0;
3976 }
3977
3978 static void setup_struct_phy_for_init(struct b43_wldev *dev,
3979 struct b43_phy *phy)
3980 {
3981 phy->hardware_power_control = !!modparam_hwpctl;
3982 phy->next_txpwr_check_time = jiffies;
3983 /* PHY TX errors counter. */
3984 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3985
3986 #if B43_DEBUG
3987 phy->phy_locked = 0;
3988 phy->radio_locked = 0;
3989 #endif
3990 }
3991
3992 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3993 {
3994 dev->dfq_valid = 0;
3995
3996 /* Assume the radio is enabled. If it's not enabled, the state will
3997 * immediately get fixed on the first periodic work run. */
3998 dev->radio_hw_enable = 1;
3999
4000 /* Stats */
4001 memset(&dev->stats, 0, sizeof(dev->stats));
4002
4003 setup_struct_phy_for_init(dev, &dev->phy);
4004
4005 /* IRQ related flags */
4006 dev->irq_reason = 0;
4007 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
4008 dev->irq_mask = B43_IRQ_MASKTEMPLATE;
4009 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
4010 dev->irq_mask &= ~B43_IRQ_PHY_TXERR;
4011
4012 dev->mac_suspended = 1;
4013
4014 /* Noise calculation context */
4015 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
4016 }
4017
4018 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
4019 {
4020 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
4021 u64 hf;
4022
4023 if (!modparam_btcoex)
4024 return;
4025 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
4026 return;
4027 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
4028 return;
4029
4030 hf = b43_hf_read(dev);
4031 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
4032 hf |= B43_HF_BTCOEXALT;
4033 else
4034 hf |= B43_HF_BTCOEX;
4035 b43_hf_write(dev, hf);
4036 }
4037
4038 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
4039 {
4040 if (!modparam_btcoex)
4041 return;
4042 //TODO
4043 }
4044
4045 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
4046 {
4047 #ifdef CONFIG_SSB_DRIVER_PCICORE
4048 struct ssb_bus *bus = dev->dev->bus;
4049 u32 tmp;
4050
4051 if (bus->pcicore.dev &&
4052 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
4053 bus->pcicore.dev->id.revision <= 5) {
4054 /* IMCFGLO timeouts workaround. */
4055 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
4056 tmp &= ~SSB_IMCFGLO_REQTO;
4057 tmp &= ~SSB_IMCFGLO_SERTO;
4058 switch (bus->bustype) {
4059 case SSB_BUSTYPE_PCI:
4060 case SSB_BUSTYPE_PCMCIA:
4061 tmp |= 0x32;
4062 break;
4063 case SSB_BUSTYPE_SSB:
4064 tmp |= 0x53;
4065 break;
4066 }
4067 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
4068 }
4069 #endif /* CONFIG_SSB_DRIVER_PCICORE */
4070 }
4071
4072 static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
4073 {
4074 u16 pu_delay;
4075
4076 /* The time value is in microseconds. */
4077 if (dev->phy.type == B43_PHYTYPE_A)
4078 pu_delay = 3700;
4079 else
4080 pu_delay = 1050;
4081 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
4082 pu_delay = 500;
4083 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
4084 pu_delay = max(pu_delay, (u16)2400);
4085
4086 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
4087 }
4088
4089 /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
4090 static void b43_set_pretbtt(struct b43_wldev *dev)
4091 {
4092 u16 pretbtt;
4093
4094 /* The time value is in microseconds. */
4095 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
4096 pretbtt = 2;
4097 } else {
4098 if (dev->phy.type == B43_PHYTYPE_A)
4099 pretbtt = 120;
4100 else
4101 pretbtt = 250;
4102 }
4103 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
4104 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
4105 }
4106
4107 /* Shutdown a wireless core */
4108 /* Locking: wl->mutex */
4109 static void b43_wireless_core_exit(struct b43_wldev *dev)
4110 {
4111 u32 macctl;
4112
4113 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
4114 if (b43_status(dev) != B43_STAT_INITIALIZED)
4115 return;
4116 b43_set_status(dev, B43_STAT_UNINIT);
4117
4118 /* Stop the microcode PSM. */
4119 macctl = b43_read32(dev, B43_MMIO_MACCTL);
4120 macctl &= ~B43_MACCTL_PSM_RUN;
4121 macctl |= B43_MACCTL_PSM_JMP0;
4122 b43_write32(dev, B43_MMIO_MACCTL, macctl);
4123
4124 if (!dev->suspend_in_progress) {
4125 b43_leds_exit(dev);
4126 b43_rng_exit(dev->wl);
4127 }
4128 b43_dma_free(dev);
4129 b43_pio_free(dev);
4130 b43_chip_exit(dev);
4131 dev->phy.ops->switch_analog(dev, 0);
4132 if (dev->wl->current_beacon) {
4133 dev_kfree_skb_any(dev->wl->current_beacon);
4134 dev->wl->current_beacon = NULL;
4135 }
4136
4137 ssb_device_disable(dev->dev, 0);
4138 ssb_bus_may_powerdown(dev->dev->bus);
4139 }
4140
4141 /* Initialize a wireless core */
4142 static int b43_wireless_core_init(struct b43_wldev *dev)
4143 {
4144 struct b43_wl *wl = dev->wl;
4145 struct ssb_bus *bus = dev->dev->bus;
4146 struct ssb_sprom *sprom = &bus->sprom;
4147 struct b43_phy *phy = &dev->phy;
4148 int err;
4149 u64 hf;
4150 u32 tmp;
4151
4152 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4153
4154 err = ssb_bus_powerup(bus, 0);
4155 if (err)
4156 goto out;
4157 if (!ssb_device_is_enabled(dev->dev)) {
4158 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
4159 b43_wireless_core_reset(dev, tmp);
4160 }
4161
4162 /* Reset all data structures. */
4163 setup_struct_wldev_for_init(dev);
4164 phy->ops->prepare_structs(dev);
4165
4166 /* Enable IRQ routing to this device. */
4167 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
4168
4169 b43_imcfglo_timeouts_workaround(dev);
4170 b43_bluetooth_coext_disable(dev);
4171 if (phy->ops->prepare_hardware) {
4172 err = phy->ops->prepare_hardware(dev);
4173 if (err)
4174 goto err_busdown;
4175 }
4176 err = b43_chip_init(dev);
4177 if (err)
4178 goto err_busdown;
4179 b43_shm_write16(dev, B43_SHM_SHARED,
4180 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
4181 hf = b43_hf_read(dev);
4182 if (phy->type == B43_PHYTYPE_G) {
4183 hf |= B43_HF_SYMW;
4184 if (phy->rev == 1)
4185 hf |= B43_HF_GDCW;
4186 if (sprom->boardflags_lo & B43_BFL_PACTRL)
4187 hf |= B43_HF_OFDMPABOOST;
4188 }
4189 if (phy->radio_ver == 0x2050) {
4190 if (phy->radio_rev == 6)
4191 hf |= B43_HF_4318TSSI;
4192 if (phy->radio_rev < 6)
4193 hf |= B43_HF_VCORECALC;
4194 }
4195 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
4196 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
4197 #ifdef CONFIG_SSB_DRIVER_PCICORE
4198 if ((bus->bustype == SSB_BUSTYPE_PCI) &&
4199 (bus->pcicore.dev->id.revision <= 10))
4200 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */
4201 #endif
4202 hf &= ~B43_HF_SKCFPUP;
4203 b43_hf_write(dev, hf);
4204
4205 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4206 B43_DEFAULT_LONG_RETRY_LIMIT);
4207 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4208 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4209
4210 /* Disable sending probe responses from firmware.
4211 * Setting the MaxTime to one usec will always trigger
4212 * a timeout, so we never send any probe resp.
4213 * A timeout of zero is infinite. */
4214 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4215
4216 b43_rate_memory_init(dev);
4217 b43_set_phytxctl_defaults(dev);
4218
4219 /* Minimum Contention Window */
4220 if (phy->type == B43_PHYTYPE_B) {
4221 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
4222 } else {
4223 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
4224 }
4225 /* Maximum Contention Window */
4226 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4227
4228 if ((dev->dev->bus->bustype == SSB_BUSTYPE_PCMCIA) || B43_FORCE_PIO) {
4229 dev->__using_pio_transfers = 1;
4230 err = b43_pio_init(dev);
4231 } else {
4232 dev->__using_pio_transfers = 0;
4233 err = b43_dma_init(dev);
4234 }
4235 if (err)
4236 goto err_chip_exit;
4237 b43_qos_init(dev);
4238 b43_set_synth_pu_delay(dev, 1);
4239 b43_bluetooth_coext_enable(dev);
4240
4241 ssb_bus_powerup(bus, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
4242 b43_upload_card_macaddress(dev);
4243 b43_security_init(dev);
4244 if (!dev->suspend_in_progress)
4245 b43_rng_init(wl);
4246
4247 b43_set_status(dev, B43_STAT_INITIALIZED);
4248
4249 if (!dev->suspend_in_progress)
4250 b43_leds_init(dev);
4251 out:
4252 return err;
4253
4254 err_chip_exit:
4255 b43_chip_exit(dev);
4256 err_busdown:
4257 ssb_bus_may_powerdown(bus);
4258 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4259 return err;
4260 }
4261
4262 static int b43_op_add_interface(struct ieee80211_hw *hw,
4263 struct ieee80211_if_init_conf *conf)
4264 {
4265 struct b43_wl *wl = hw_to_b43_wl(hw);
4266 struct b43_wldev *dev;
4267 unsigned long flags;
4268 int err = -EOPNOTSUPP;
4269
4270 /* TODO: allow WDS/AP devices to coexist */
4271
4272 if (conf->type != NL80211_IFTYPE_AP &&
4273 conf->type != NL80211_IFTYPE_MESH_POINT &&
4274 conf->type != NL80211_IFTYPE_STATION &&
4275 conf->type != NL80211_IFTYPE_WDS &&
4276 conf->type != NL80211_IFTYPE_ADHOC)
4277 return -EOPNOTSUPP;
4278
4279 mutex_lock(&wl->mutex);
4280 if (wl->operating)
4281 goto out_mutex_unlock;
4282
4283 b43dbg(wl, "Adding Interface type %d\n", conf->type);
4284
4285 dev = wl->current_dev;
4286 wl->operating = 1;
4287 wl->vif = conf->vif;
4288 wl->if_type = conf->type;
4289 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
4290
4291 spin_lock_irqsave(&wl->irq_lock, flags);
4292 b43_adjust_opmode(dev);
4293 b43_set_pretbtt(dev);
4294 b43_set_synth_pu_delay(dev, 0);
4295 b43_upload_card_macaddress(dev);
4296 spin_unlock_irqrestore(&wl->irq_lock, flags);
4297
4298 err = 0;
4299 out_mutex_unlock:
4300 mutex_unlock(&wl->mutex);
4301
4302 return err;
4303 }
4304
4305 static void b43_op_remove_interface(struct ieee80211_hw *hw,
4306 struct ieee80211_if_init_conf *conf)
4307 {
4308 struct b43_wl *wl = hw_to_b43_wl(hw);
4309 struct b43_wldev *dev = wl->current_dev;
4310 unsigned long flags;
4311
4312 b43dbg(wl, "Removing Interface type %d\n", conf->type);
4313
4314 mutex_lock(&wl->mutex);
4315
4316 B43_WARN_ON(!wl->operating);
4317 B43_WARN_ON(wl->vif != conf->vif);
4318 wl->vif = NULL;
4319
4320 wl->operating = 0;
4321
4322 spin_lock_irqsave(&wl->irq_lock, flags);
4323 b43_adjust_opmode(dev);
4324 memset(wl->mac_addr, 0, ETH_ALEN);
4325 b43_upload_card_macaddress(dev);
4326 spin_unlock_irqrestore(&wl->irq_lock, flags);
4327
4328 mutex_unlock(&wl->mutex);
4329 }
4330
4331 static int b43_op_start(struct ieee80211_hw *hw)
4332 {
4333 struct b43_wl *wl = hw_to_b43_wl(hw);
4334 struct b43_wldev *dev = wl->current_dev;
4335 int did_init = 0;
4336 int err = 0;
4337
4338 /* Kill all old instance specific information to make sure
4339 * the card won't use it in the short timeframe between start
4340 * and mac80211 reconfiguring it. */
4341 memset(wl->bssid, 0, ETH_ALEN);
4342 memset(wl->mac_addr, 0, ETH_ALEN);
4343 wl->filter_flags = 0;
4344 wl->radiotap_enabled = 0;
4345 b43_qos_clear(wl);
4346 wl->beacon0_uploaded = 0;
4347 wl->beacon1_uploaded = 0;
4348 wl->beacon_templates_virgin = 1;
4349 wl->radio_enabled = 1;
4350
4351 mutex_lock(&wl->mutex);
4352
4353 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4354 err = b43_wireless_core_init(dev);
4355 if (err)
4356 goto out_mutex_unlock;
4357 did_init = 1;
4358 }
4359
4360 if (b43_status(dev) < B43_STAT_STARTED) {
4361 err = b43_wireless_core_start(dev);
4362 if (err) {
4363 if (did_init)
4364 b43_wireless_core_exit(dev);
4365 goto out_mutex_unlock;
4366 }
4367 }
4368
4369 /* XXX: only do if device doesn't support rfkill irq */
4370 wiphy_rfkill_start_polling(hw->wiphy);
4371
4372 out_mutex_unlock:
4373 mutex_unlock(&wl->mutex);
4374
4375 return err;
4376 }
4377
4378 static void b43_op_stop(struct ieee80211_hw *hw)
4379 {
4380 struct b43_wl *wl = hw_to_b43_wl(hw);
4381 struct b43_wldev *dev = wl->current_dev;
4382
4383 cancel_work_sync(&(wl->beacon_update_trigger));
4384
4385 mutex_lock(&wl->mutex);
4386 if (b43_status(dev) >= B43_STAT_STARTED)
4387 b43_wireless_core_stop(dev);
4388 b43_wireless_core_exit(dev);
4389 wl->radio_enabled = 0;
4390 mutex_unlock(&wl->mutex);
4391
4392 cancel_work_sync(&(wl->txpower_adjust_work));
4393 }
4394
4395 static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
4396 struct ieee80211_sta *sta, bool set)
4397 {
4398 struct b43_wl *wl = hw_to_b43_wl(hw);
4399 unsigned long flags;
4400
4401 spin_lock_irqsave(&wl->irq_lock, flags);
4402 b43_update_templates(wl);
4403 spin_unlock_irqrestore(&wl->irq_lock, flags);
4404
4405 return 0;
4406 }
4407
4408 static void b43_op_sta_notify(struct ieee80211_hw *hw,
4409 struct ieee80211_vif *vif,
4410 enum sta_notify_cmd notify_cmd,
4411 struct ieee80211_sta *sta)
4412 {
4413 struct b43_wl *wl = hw_to_b43_wl(hw);
4414
4415 B43_WARN_ON(!vif || wl->vif != vif);
4416 }
4417
4418 static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw)
4419 {
4420 struct b43_wl *wl = hw_to_b43_wl(hw);
4421 struct b43_wldev *dev;
4422
4423 mutex_lock(&wl->mutex);
4424 dev = wl->current_dev;
4425 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4426 /* Disable CFP update during scan on other channels. */
4427 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP);
4428 }
4429 mutex_unlock(&wl->mutex);
4430 }
4431
4432 static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw)
4433 {
4434 struct b43_wl *wl = hw_to_b43_wl(hw);
4435 struct b43_wldev *dev;
4436
4437 mutex_lock(&wl->mutex);
4438 dev = wl->current_dev;
4439 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4440 /* Re-enable CFP update. */
4441 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP);
4442 }
4443 mutex_unlock(&wl->mutex);
4444 }
4445
4446 static const struct ieee80211_ops b43_hw_ops = {
4447 .tx = b43_op_tx,
4448 .conf_tx = b43_op_conf_tx,
4449 .add_interface = b43_op_add_interface,
4450 .remove_interface = b43_op_remove_interface,
4451 .config = b43_op_config,
4452 .bss_info_changed = b43_op_bss_info_changed,
4453 .configure_filter = b43_op_configure_filter,
4454 .set_key = b43_op_set_key,
4455 .get_stats = b43_op_get_stats,
4456 .get_tx_stats = b43_op_get_tx_stats,
4457 .get_tsf = b43_op_get_tsf,
4458 .set_tsf = b43_op_set_tsf,
4459 .start = b43_op_start,
4460 .stop = b43_op_stop,
4461 .set_tim = b43_op_beacon_set_tim,
4462 .sta_notify = b43_op_sta_notify,
4463 .sw_scan_start = b43_op_sw_scan_start_notifier,
4464 .sw_scan_complete = b43_op_sw_scan_complete_notifier,
4465 .rfkill_poll = b43_rfkill_poll,
4466 };
4467
4468 /* Hard-reset the chip. Do not call this directly.
4469 * Use b43_controller_restart()
4470 */
4471 static void b43_chip_reset(struct work_struct *work)
4472 {
4473 struct b43_wldev *dev =
4474 container_of(work, struct b43_wldev, restart_work);
4475 struct b43_wl *wl = dev->wl;
4476 int err = 0;
4477 int prev_status;
4478
4479 mutex_lock(&wl->mutex);
4480
4481 prev_status = b43_status(dev);
4482 /* Bring the device down... */
4483 if (prev_status >= B43_STAT_STARTED)
4484 b43_wireless_core_stop(dev);
4485 if (prev_status >= B43_STAT_INITIALIZED)
4486 b43_wireless_core_exit(dev);
4487
4488 /* ...and up again. */
4489 if (prev_status >= B43_STAT_INITIALIZED) {
4490 err = b43_wireless_core_init(dev);
4491 if (err)
4492 goto out;
4493 }
4494 if (prev_status >= B43_STAT_STARTED) {
4495 err = b43_wireless_core_start(dev);
4496 if (err) {
4497 b43_wireless_core_exit(dev);
4498 goto out;
4499 }
4500 }
4501 out:
4502 if (err)
4503 wl->current_dev = NULL; /* Failed to init the dev. */
4504 mutex_unlock(&wl->mutex);
4505 if (err)
4506 b43err(wl, "Controller restart FAILED\n");
4507 else
4508 b43info(wl, "Controller restarted\n");
4509 }
4510
4511 static int b43_setup_bands(struct b43_wldev *dev,
4512 bool have_2ghz_phy, bool have_5ghz_phy)
4513 {
4514 struct ieee80211_hw *hw = dev->wl->hw;
4515
4516 if (have_2ghz_phy)
4517 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
4518 if (dev->phy.type == B43_PHYTYPE_N) {
4519 if (have_5ghz_phy)
4520 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
4521 } else {
4522 if (have_5ghz_phy)
4523 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
4524 }
4525
4526 dev->phy.supports_2ghz = have_2ghz_phy;
4527 dev->phy.supports_5ghz = have_5ghz_phy;
4528
4529 return 0;
4530 }
4531
4532 static void b43_wireless_core_detach(struct b43_wldev *dev)
4533 {
4534 /* We release firmware that late to not be required to re-request
4535 * is all the time when we reinit the core. */
4536 b43_release_firmware(dev);
4537 b43_phy_free(dev);
4538 }
4539
4540 static int b43_wireless_core_attach(struct b43_wldev *dev)
4541 {
4542 struct b43_wl *wl = dev->wl;
4543 struct ssb_bus *bus = dev->dev->bus;
4544 struct pci_dev *pdev = bus->host_pci;
4545 int err;
4546 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
4547 u32 tmp;
4548
4549 /* Do NOT do any device initialization here.
4550 * Do it in wireless_core_init() instead.
4551 * This function is for gathering basic information about the HW, only.
4552 * Also some structs may be set up here. But most likely you want to have
4553 * that in core_init(), too.
4554 */
4555
4556 err = ssb_bus_powerup(bus, 0);
4557 if (err) {
4558 b43err(wl, "Bus powerup failed\n");
4559 goto out;
4560 }
4561 /* Get the PHY type. */
4562 if (dev->dev->id.revision >= 5) {
4563 u32 tmshigh;
4564
4565 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
4566 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
4567 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
4568 } else
4569 B43_WARN_ON(1);
4570
4571 dev->phy.gmode = have_2ghz_phy;
4572 dev->phy.radio_on = 1;
4573 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4574 b43_wireless_core_reset(dev, tmp);
4575
4576 err = b43_phy_versioning(dev);
4577 if (err)
4578 goto err_powerdown;
4579 /* Check if this device supports multiband. */
4580 if (!pdev ||
4581 (pdev->device != 0x4312 &&
4582 pdev->device != 0x4319 && pdev->device != 0x4324)) {
4583 /* No multiband support. */
4584 have_2ghz_phy = 0;
4585 have_5ghz_phy = 0;
4586 switch (dev->phy.type) {
4587 case B43_PHYTYPE_A:
4588 have_5ghz_phy = 1;
4589 break;
4590 case B43_PHYTYPE_G:
4591 case B43_PHYTYPE_N:
4592 case B43_PHYTYPE_LP:
4593 have_2ghz_phy = 1;
4594 break;
4595 default:
4596 B43_WARN_ON(1);
4597 }
4598 }
4599 if (dev->phy.type == B43_PHYTYPE_A) {
4600 /* FIXME */
4601 b43err(wl, "IEEE 802.11a devices are unsupported\n");
4602 err = -EOPNOTSUPP;
4603 goto err_powerdown;
4604 }
4605 if (1 /* disable A-PHY */) {
4606 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
4607 if (dev->phy.type != B43_PHYTYPE_N) {
4608 have_2ghz_phy = 1;
4609 have_5ghz_phy = 0;
4610 }
4611 }
4612
4613 err = b43_phy_allocate(dev);
4614 if (err)
4615 goto err_powerdown;
4616
4617 dev->phy.gmode = have_2ghz_phy;
4618 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4619 b43_wireless_core_reset(dev, tmp);
4620
4621 err = b43_validate_chipaccess(dev);
4622 if (err)
4623 goto err_phy_free;
4624 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
4625 if (err)
4626 goto err_phy_free;
4627
4628 /* Now set some default "current_dev" */
4629 if (!wl->current_dev)
4630 wl->current_dev = dev;
4631 INIT_WORK(&dev->restart_work, b43_chip_reset);
4632
4633 dev->phy.ops->switch_analog(dev, 0);
4634 ssb_device_disable(dev->dev, 0);
4635 ssb_bus_may_powerdown(bus);
4636
4637 out:
4638 return err;
4639
4640 err_phy_free:
4641 b43_phy_free(dev);
4642 err_powerdown:
4643 ssb_bus_may_powerdown(bus);
4644 return err;
4645 }
4646
4647 static void b43_one_core_detach(struct ssb_device *dev)
4648 {
4649 struct b43_wldev *wldev;
4650 struct b43_wl *wl;
4651
4652 /* Do not cancel ieee80211-workqueue based work here.
4653 * See comment in b43_remove(). */
4654
4655 wldev = ssb_get_drvdata(dev);
4656 wl = wldev->wl;
4657 b43_debugfs_remove_device(wldev);
4658 b43_wireless_core_detach(wldev);
4659 list_del(&wldev->list);
4660 wl->nr_devs--;
4661 ssb_set_drvdata(dev, NULL);
4662 kfree(wldev);
4663 }
4664
4665 static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
4666 {
4667 struct b43_wldev *wldev;
4668 struct pci_dev *pdev;
4669 int err = -ENOMEM;
4670
4671 if (!list_empty(&wl->devlist)) {
4672 /* We are not the first core on this chip. */
4673 pdev = dev->bus->host_pci;
4674 /* Only special chips support more than one wireless
4675 * core, although some of the other chips have more than
4676 * one wireless core as well. Check for this and
4677 * bail out early.
4678 */
4679 if (!pdev ||
4680 ((pdev->device != 0x4321) &&
4681 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
4682 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
4683 return -ENODEV;
4684 }
4685 }
4686
4687 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
4688 if (!wldev)
4689 goto out;
4690
4691 wldev->dev = dev;
4692 wldev->wl = wl;
4693 b43_set_status(wldev, B43_STAT_UNINIT);
4694 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
4695 tasklet_init(&wldev->isr_tasklet,
4696 (void (*)(unsigned long))b43_interrupt_tasklet,
4697 (unsigned long)wldev);
4698 INIT_LIST_HEAD(&wldev->list);
4699
4700 err = b43_wireless_core_attach(wldev);
4701 if (err)
4702 goto err_kfree_wldev;
4703
4704 list_add(&wldev->list, &wl->devlist);
4705 wl->nr_devs++;
4706 ssb_set_drvdata(dev, wldev);
4707 b43_debugfs_add_device(wldev);
4708
4709 out:
4710 return err;
4711
4712 err_kfree_wldev:
4713 kfree(wldev);
4714 return err;
4715 }
4716
4717 #define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
4718 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
4719 (pdev->device == _device) && \
4720 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
4721 (pdev->subsystem_device == _subdevice) )
4722
4723 static void b43_sprom_fixup(struct ssb_bus *bus)
4724 {
4725 struct pci_dev *pdev;
4726
4727 /* boardflags workarounds */
4728 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
4729 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
4730 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
4731 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
4732 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
4733 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
4734 if (bus->bustype == SSB_BUSTYPE_PCI) {
4735 pdev = bus->host_pci;
4736 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
4737 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
4738 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
4739 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
4740 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
4741 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
4742 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
4743 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
4744 }
4745 }
4746
4747 static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
4748 {
4749 struct ieee80211_hw *hw = wl->hw;
4750
4751 ssb_set_devtypedata(dev, NULL);
4752 ieee80211_free_hw(hw);
4753 }
4754
4755 static int b43_wireless_init(struct ssb_device *dev)
4756 {
4757 struct ssb_sprom *sprom = &dev->bus->sprom;
4758 struct ieee80211_hw *hw;
4759 struct b43_wl *wl;
4760 int err = -ENOMEM;
4761
4762 b43_sprom_fixup(dev->bus);
4763
4764 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
4765 if (!hw) {
4766 b43err(NULL, "Could not allocate ieee80211 device\n");
4767 goto out;
4768 }
4769 wl = hw_to_b43_wl(hw);
4770
4771 /* fill hw info */
4772 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
4773 IEEE80211_HW_SIGNAL_DBM |
4774 IEEE80211_HW_NOISE_DBM;
4775
4776 hw->wiphy->interface_modes =
4777 BIT(NL80211_IFTYPE_AP) |
4778 BIT(NL80211_IFTYPE_MESH_POINT) |
4779 BIT(NL80211_IFTYPE_STATION) |
4780 BIT(NL80211_IFTYPE_WDS) |
4781 BIT(NL80211_IFTYPE_ADHOC);
4782
4783 hw->queues = modparam_qos ? 4 : 1;
4784 wl->mac80211_initially_registered_queues = hw->queues;
4785 hw->max_rates = 2;
4786 SET_IEEE80211_DEV(hw, dev->dev);
4787 if (is_valid_ether_addr(sprom->et1mac))
4788 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
4789 else
4790 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
4791
4792 /* Initialize struct b43_wl */
4793 wl->hw = hw;
4794 spin_lock_init(&wl->irq_lock);
4795 rwlock_init(&wl->tx_lock);
4796 spin_lock_init(&wl->leds_lock);
4797 spin_lock_init(&wl->shm_lock);
4798 mutex_init(&wl->mutex);
4799 INIT_LIST_HEAD(&wl->devlist);
4800 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
4801 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
4802
4803 ssb_set_devtypedata(dev, wl);
4804 b43info(wl, "Broadcom %04X WLAN found (core revision %u)\n",
4805 dev->bus->chip_id, dev->id.revision);
4806 err = 0;
4807 out:
4808 return err;
4809 }
4810
4811 static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
4812 {
4813 struct b43_wl *wl;
4814 int err;
4815 int first = 0;
4816
4817 wl = ssb_get_devtypedata(dev);
4818 if (!wl) {
4819 /* Probing the first core. Must setup common struct b43_wl */
4820 first = 1;
4821 err = b43_wireless_init(dev);
4822 if (err)
4823 goto out;
4824 wl = ssb_get_devtypedata(dev);
4825 B43_WARN_ON(!wl);
4826 }
4827 err = b43_one_core_attach(dev, wl);
4828 if (err)
4829 goto err_wireless_exit;
4830
4831 if (first) {
4832 err = ieee80211_register_hw(wl->hw);
4833 if (err)
4834 goto err_one_core_detach;
4835 }
4836
4837 out:
4838 return err;
4839
4840 err_one_core_detach:
4841 b43_one_core_detach(dev);
4842 err_wireless_exit:
4843 if (first)
4844 b43_wireless_exit(dev, wl);
4845 return err;
4846 }
4847
4848 static void b43_remove(struct ssb_device *dev)
4849 {
4850 struct b43_wl *wl = ssb_get_devtypedata(dev);
4851 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4852
4853 /* We must cancel any work here before unregistering from ieee80211,
4854 * as the ieee80211 unreg will destroy the workqueue. */
4855 cancel_work_sync(&wldev->restart_work);
4856
4857 B43_WARN_ON(!wl);
4858 if (wl->current_dev == wldev) {
4859 /* Restore the queues count before unregistering, because firmware detect
4860 * might have modified it. Restoring is important, so the networking
4861 * stack can properly free resources. */
4862 wl->hw->queues = wl->mac80211_initially_registered_queues;
4863 ieee80211_unregister_hw(wl->hw);
4864 }
4865
4866 b43_one_core_detach(dev);
4867
4868 if (list_empty(&wl->devlist)) {
4869 /* Last core on the chip unregistered.
4870 * We can destroy common struct b43_wl.
4871 */
4872 b43_wireless_exit(dev, wl);
4873 }
4874 }
4875
4876 /* Perform a hardware reset. This can be called from any context. */
4877 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
4878 {
4879 /* Must avoid requeueing, if we are in shutdown. */
4880 if (b43_status(dev) < B43_STAT_INITIALIZED)
4881 return;
4882 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
4883 queue_work(dev->wl->hw->workqueue, &dev->restart_work);
4884 }
4885
4886 #ifdef CONFIG_PM
4887
4888 static int b43_suspend(struct ssb_device *dev, pm_message_t state)
4889 {
4890 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4891 struct b43_wl *wl = wldev->wl;
4892
4893 b43dbg(wl, "Suspending...\n");
4894
4895 mutex_lock(&wl->mutex);
4896 wldev->suspend_in_progress = true;
4897 wldev->suspend_init_status = b43_status(wldev);
4898 if (wldev->suspend_init_status >= B43_STAT_STARTED)
4899 b43_wireless_core_stop(wldev);
4900 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
4901 b43_wireless_core_exit(wldev);
4902 mutex_unlock(&wl->mutex);
4903
4904 b43dbg(wl, "Device suspended.\n");
4905
4906 return 0;
4907 }
4908
4909 static int b43_resume(struct ssb_device *dev)
4910 {
4911 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4912 struct b43_wl *wl = wldev->wl;
4913 int err = 0;
4914
4915 b43dbg(wl, "Resuming...\n");
4916
4917 mutex_lock(&wl->mutex);
4918 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4919 err = b43_wireless_core_init(wldev);
4920 if (err) {
4921 b43err(wl, "Resume failed at core init\n");
4922 goto out;
4923 }
4924 }
4925 if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4926 err = b43_wireless_core_start(wldev);
4927 if (err) {
4928 b43_leds_exit(wldev);
4929 b43_rng_exit(wldev->wl);
4930 b43_wireless_core_exit(wldev);
4931 b43err(wl, "Resume failed at core start\n");
4932 goto out;
4933 }
4934 }
4935 b43dbg(wl, "Device resumed.\n");
4936 out:
4937 wldev->suspend_in_progress = false;
4938 mutex_unlock(&wl->mutex);
4939 return err;
4940 }
4941
4942 #else /* CONFIG_PM */
4943 # define b43_suspend NULL
4944 # define b43_resume NULL
4945 #endif /* CONFIG_PM */
4946
4947 static struct ssb_driver b43_ssb_driver = {
4948 .name = KBUILD_MODNAME,
4949 .id_table = b43_ssb_tbl,
4950 .probe = b43_probe,
4951 .remove = b43_remove,
4952 .suspend = b43_suspend,
4953 .resume = b43_resume,
4954 };
4955
4956 static void b43_print_driverinfo(void)
4957 {
4958 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
4959 *feat_leds = "";
4960
4961 #ifdef CONFIG_B43_PCI_AUTOSELECT
4962 feat_pci = "P";
4963 #endif
4964 #ifdef CONFIG_B43_PCMCIA
4965 feat_pcmcia = "M";
4966 #endif
4967 #ifdef CONFIG_B43_NPHY
4968 feat_nphy = "N";
4969 #endif
4970 #ifdef CONFIG_B43_LEDS
4971 feat_leds = "L";
4972 #endif
4973 printk(KERN_INFO "Broadcom 43xx driver loaded "
4974 "[ Features: %s%s%s%s, Firmware-ID: "
4975 B43_SUPPORTED_FIRMWARE_ID " ]\n",
4976 feat_pci, feat_pcmcia, feat_nphy,
4977 feat_leds);
4978 }
4979
4980 static int __init b43_init(void)
4981 {
4982 int err;
4983
4984 b43_debugfs_init();
4985 err = b43_pcmcia_init();
4986 if (err)
4987 goto err_dfs_exit;
4988 err = ssb_driver_register(&b43_ssb_driver);
4989 if (err)
4990 goto err_pcmcia_exit;
4991 b43_print_driverinfo();
4992
4993 return err;
4994
4995 err_pcmcia_exit:
4996 b43_pcmcia_exit();
4997 err_dfs_exit:
4998 b43_debugfs_exit();
4999 return err;
5000 }
5001
5002 static void __exit b43_exit(void)
5003 {
5004 ssb_driver_unregister(&b43_ssb_driver);
5005 b43_pcmcia_exit();
5006 b43_debugfs_exit();
5007 }
5008
5009 module_init(b43_init)
5010 module_exit(b43_exit)
5011
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