1 #ifndef B43_H_
2 #define B43_H_
3
4 #include <linux/kernel.h>
5 #include <linux/spinlock.h>
6 #include <linux/interrupt.h>
7 #include <linux/hw_random.h>
8 #include <linux/ssb/ssb.h>
9 #include <net/mac80211.h>
10
11 #include "debugfs.h"
12 #include "leds.h"
13 #include "rfkill.h"
14 #include "lo.h"
15 #include "phy_common.h"
16
17
18 /* The unique identifier of the firmware that's officially supported by
19 * this driver version. */
20 #define B43_SUPPORTED_FIRMWARE_ID "FW13"
21
22
23 #ifdef CONFIG_B43_DEBUG
24 # define B43_DEBUG 1
25 #else
26 # define B43_DEBUG 0
27 #endif
28
29 #define B43_RX_MAX_SSI 60
30
31 /* MMIO offsets */
32 #define B43_MMIO_DMA0_REASON 0x20
33 #define B43_MMIO_DMA0_IRQ_MASK 0x24
34 #define B43_MMIO_DMA1_REASON 0x28
35 #define B43_MMIO_DMA1_IRQ_MASK 0x2C
36 #define B43_MMIO_DMA2_REASON 0x30
37 #define B43_MMIO_DMA2_IRQ_MASK 0x34
38 #define B43_MMIO_DMA3_REASON 0x38
39 #define B43_MMIO_DMA3_IRQ_MASK 0x3C
40 #define B43_MMIO_DMA4_REASON 0x40
41 #define B43_MMIO_DMA4_IRQ_MASK 0x44
42 #define B43_MMIO_DMA5_REASON 0x48
43 #define B43_MMIO_DMA5_IRQ_MASK 0x4C
44 #define B43_MMIO_MACCTL 0x120 /* MAC control */
45 #define B43_MMIO_MACCMD 0x124 /* MAC command */
46 #define B43_MMIO_GEN_IRQ_REASON 0x128
47 #define B43_MMIO_GEN_IRQ_MASK 0x12C
48 #define B43_MMIO_RAM_CONTROL 0x130
49 #define B43_MMIO_RAM_DATA 0x134
50 #define B43_MMIO_PS_STATUS 0x140
51 #define B43_MMIO_RADIO_HWENABLED_HI 0x158
52 #define B43_MMIO_SHM_CONTROL 0x160
53 #define B43_MMIO_SHM_DATA 0x164
54 #define B43_MMIO_SHM_DATA_UNALIGNED 0x166
55 #define B43_MMIO_XMITSTAT_0 0x170
56 #define B43_MMIO_XMITSTAT_1 0x174
57 #define B43_MMIO_REV3PLUS_TSF_LOW 0x180 /* core rev >= 3 only */
58 #define B43_MMIO_REV3PLUS_TSF_HIGH 0x184 /* core rev >= 3 only */
59 #define B43_MMIO_TSF_CFP_REP 0x188
60 #define B43_MMIO_TSF_CFP_START 0x18C
61 #define B43_MMIO_TSF_CFP_MAXDUR 0x190
62
63 /* 32-bit DMA */
64 #define B43_MMIO_DMA32_BASE0 0x200
65 #define B43_MMIO_DMA32_BASE1 0x220
66 #define B43_MMIO_DMA32_BASE2 0x240
67 #define B43_MMIO_DMA32_BASE3 0x260
68 #define B43_MMIO_DMA32_BASE4 0x280
69 #define B43_MMIO_DMA32_BASE5 0x2A0
70 /* 64-bit DMA */
71 #define B43_MMIO_DMA64_BASE0 0x200
72 #define B43_MMIO_DMA64_BASE1 0x240
73 #define B43_MMIO_DMA64_BASE2 0x280
74 #define B43_MMIO_DMA64_BASE3 0x2C0
75 #define B43_MMIO_DMA64_BASE4 0x300
76 #define B43_MMIO_DMA64_BASE5 0x340
77
78 /* PIO on core rev < 11 */
79 #define B43_MMIO_PIO_BASE0 0x300
80 #define B43_MMIO_PIO_BASE1 0x310
81 #define B43_MMIO_PIO_BASE2 0x320
82 #define B43_MMIO_PIO_BASE3 0x330
83 #define B43_MMIO_PIO_BASE4 0x340
84 #define B43_MMIO_PIO_BASE5 0x350
85 #define B43_MMIO_PIO_BASE6 0x360
86 #define B43_MMIO_PIO_BASE7 0x370
87 /* PIO on core rev >= 11 */
88 #define B43_MMIO_PIO11_BASE0 0x200
89 #define B43_MMIO_PIO11_BASE1 0x240
90 #define B43_MMIO_PIO11_BASE2 0x280
91 #define B43_MMIO_PIO11_BASE3 0x2C0
92 #define B43_MMIO_PIO11_BASE4 0x300
93 #define B43_MMIO_PIO11_BASE5 0x340
94
95 #define B43_MMIO_PHY_VER 0x3E0
96 #define B43_MMIO_PHY_RADIO 0x3E2
97 #define B43_MMIO_PHY0 0x3E6
98 #define B43_MMIO_ANTENNA 0x3E8
99 #define B43_MMIO_CHANNEL 0x3F0
100 #define B43_MMIO_CHANNEL_EXT 0x3F4
101 #define B43_MMIO_RADIO_CONTROL 0x3F6
102 #define B43_MMIO_RADIO_DATA_HIGH 0x3F8
103 #define B43_MMIO_RADIO_DATA_LOW 0x3FA
104 #define B43_MMIO_PHY_CONTROL 0x3FC
105 #define B43_MMIO_PHY_DATA 0x3FE
106 #define B43_MMIO_MACFILTER_CONTROL 0x420
107 #define B43_MMIO_MACFILTER_DATA 0x422
108 #define B43_MMIO_RCMTA_COUNT 0x43C
109 #define B43_MMIO_RADIO_HWENABLED_LO 0x49A
110 #define B43_MMIO_GPIO_CONTROL 0x49C
111 #define B43_MMIO_GPIO_MASK 0x49E
112 #define B43_MMIO_TSF_CFP_START_LOW 0x604
113 #define B43_MMIO_TSF_CFP_START_HIGH 0x606
114 #define B43_MMIO_TSF_CFP_PRETBTT 0x612
115 #define B43_MMIO_TSF_0 0x632 /* core rev < 3 only */
116 #define B43_MMIO_TSF_1 0x634 /* core rev < 3 only */
117 #define B43_MMIO_TSF_2 0x636 /* core rev < 3 only */
118 #define B43_MMIO_TSF_3 0x638 /* core rev < 3 only */
119 #define B43_MMIO_RNG 0x65A
120 #define B43_MMIO_IFSSLOT 0x684 /* Interframe slot time */
121 #define B43_MMIO_IFSCTL 0x688 /* Interframe space control */
122 #define B43_MMIO_IFSCTL_USE_EDCF 0x0004
123 #define B43_MMIO_POWERUP_DELAY 0x6A8
124 #define B43_MMIO_BTCOEX_CTL 0x6B4 /* Bluetooth Coexistence Control */
125 #define B43_MMIO_BTCOEX_STAT 0x6B6 /* Bluetooth Coexistence Status */
126 #define B43_MMIO_BTCOEX_TXCTL 0x6B8 /* Bluetooth Coexistence Transmit Control */
127
128 /* SPROM boardflags_lo values */
129 #define B43_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
130 #define B43_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
131 #define B43_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */
132 #define B43_BFL_RSSI 0x0008 /* software calculates nrssi slope. */
133 #define B43_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */
134 #define B43_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */
135 #define B43_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */
136 #define B43_BFL_ENETADM 0x0080 /* has ADMtek switch */
137 #define B43_BFL_ENETVLAN 0x0100 /* can do vlan */
138 #define B43_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */
139 #define B43_BFL_NOPCI 0x0400 /* leaves PCI floating */
140 #define B43_BFL_FEM 0x0800 /* supports the Front End Module */
141 #define B43_BFL_EXTLNA 0x1000 /* has an external LNA */
142 #define B43_BFL_HGPA 0x2000 /* had high gain PA */
143 #define B43_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
144 #define B43_BFL_ALTIQ 0x8000 /* alternate I/Q settings */
145
146 /* GPIO register offset, in both ChipCommon and PCI core. */
147 #define B43_GPIO_CONTROL 0x6c
148
149 /* SHM Routing */
150 enum {
151 B43_SHM_UCODE, /* Microcode memory */
152 B43_SHM_SHARED, /* Shared memory */
153 B43_SHM_SCRATCH, /* Scratch memory */
154 B43_SHM_HW, /* Internal hardware register */
155 B43_SHM_RCMTA, /* Receive match transmitter address (rev >= 5 only) */
156 };
157 /* SHM Routing modifiers */
158 #define B43_SHM_AUTOINC_R 0x0200 /* Auto-increment address on read */
159 #define B43_SHM_AUTOINC_W 0x0100 /* Auto-increment address on write */
160 #define B43_SHM_AUTOINC_RW (B43_SHM_AUTOINC_R | \
161 B43_SHM_AUTOINC_W)
162
163 /* Misc SHM_SHARED offsets */
164 #define B43_SHM_SH_WLCOREREV 0x0016 /* 802.11 core revision */
165 #define B43_SHM_SH_PCTLWDPOS 0x0008
166 #define B43_SHM_SH_RXPADOFF 0x0034 /* RX Padding data offset (PIO only) */
167 #define B43_SHM_SH_FWCAPA 0x0042 /* Firmware capabilities (Opensource firmware only) */
168 #define B43_SHM_SH_PHYVER 0x0050 /* PHY version */
169 #define B43_SHM_SH_PHYTYPE 0x0052 /* PHY type */
170 #define B43_SHM_SH_ANTSWAP 0x005C /* Antenna swap threshold */
171 #define B43_SHM_SH_HOSTFLO 0x005E /* Hostflags for ucode options (low) */
172 #define B43_SHM_SH_HOSTFMI 0x0060 /* Hostflags for ucode options (middle) */
173 #define B43_SHM_SH_HOSTFHI 0x0062 /* Hostflags for ucode options (high) */
174 #define B43_SHM_SH_RFATT 0x0064 /* Current radio attenuation value */
175 #define B43_SHM_SH_RADAR 0x0066 /* Radar register */
176 #define B43_SHM_SH_PHYTXNOI 0x006E /* PHY noise directly after TX (lower 8bit only) */
177 #define B43_SHM_SH_RFRXSP1 0x0072 /* RF RX SP Register 1 */
178 #define B43_SHM_SH_CHAN 0x00A0 /* Current channel (low 8bit only) */
179 #define B43_SHM_SH_CHAN_5GHZ 0x0100 /* Bit set, if 5Ghz channel */
180 #define B43_SHM_SH_BCMCFIFOID 0x0108 /* Last posted cookie to the bcast/mcast FIFO */
181 /* TSSI information */
182 #define B43_SHM_SH_TSSI_CCK 0x0058 /* TSSI for last 4 CCK frames (32bit) */
183 #define B43_SHM_SH_TSSI_OFDM_A 0x0068 /* TSSI for last 4 OFDM frames (32bit) */
184 #define B43_SHM_SH_TSSI_OFDM_G 0x0070 /* TSSI for last 4 OFDM frames (32bit) */
185 #define B43_TSSI_MAX 0x7F /* Max value for one TSSI value */
186 /* SHM_SHARED TX FIFO variables */
187 #define B43_SHM_SH_SIZE01 0x0098 /* TX FIFO size for FIFO 0 (low) and 1 (high) */
188 #define B43_SHM_SH_SIZE23 0x009A /* TX FIFO size for FIFO 2 and 3 */
189 #define B43_SHM_SH_SIZE45 0x009C /* TX FIFO size for FIFO 4 and 5 */
190 #define B43_SHM_SH_SIZE67 0x009E /* TX FIFO size for FIFO 6 and 7 */
191 /* SHM_SHARED background noise */
192 #define B43_SHM_SH_JSSI0 0x0088 /* Measure JSSI 0 */
193 #define B43_SHM_SH_JSSI1 0x008A /* Measure JSSI 1 */
194 #define B43_SHM_SH_JSSIAUX 0x008C /* Measure JSSI AUX */
195 /* SHM_SHARED crypto engine */
196 #define B43_SHM_SH_DEFAULTIV 0x003C /* Default IV location */
197 #define B43_SHM_SH_NRRXTRANS 0x003E /* # of soft RX transmitter addresses (max 8) */
198 #define B43_SHM_SH_KTP 0x0056 /* Key table pointer */
199 #define B43_SHM_SH_TKIPTSCTTAK 0x0318
200 #define B43_SHM_SH_KEYIDXBLOCK 0x05D4 /* Key index/algorithm block (v4 firmware) */
201 #define B43_SHM_SH_PSM 0x05F4 /* PSM transmitter address match block (rev < 5) */
202 /* SHM_SHARED WME variables */
203 #define B43_SHM_SH_EDCFSTAT 0x000E /* EDCF status */
204 #define B43_SHM_SH_TXFCUR 0x0030 /* TXF current index */
205 #define B43_SHM_SH_EDCFQ 0x0240 /* EDCF Q info */
206 /* SHM_SHARED powersave mode related */
207 #define B43_SHM_SH_SLOTT 0x0010 /* Slot time */
208 #define B43_SHM_SH_DTIMPER 0x0012 /* DTIM period */
209 #define B43_SHM_SH_NOSLPZNATDTIM 0x004C /* NOSLPZNAT DTIM */
210 /* SHM_SHARED beacon/AP variables */
211 #define B43_SHM_SH_BTL0 0x0018 /* Beacon template length 0 */
212 #define B43_SHM_SH_BTL1 0x001A /* Beacon template length 1 */
213 #define B43_SHM_SH_BTSFOFF 0x001C /* Beacon TSF offset */
214 #define B43_SHM_SH_TIMBPOS 0x001E /* TIM B position in beacon */
215 #define B43_SHM_SH_DTIMP 0x0012 /* DTIP period */
216 #define B43_SHM_SH_MCASTCOOKIE 0x00A8 /* Last bcast/mcast frame ID */
217 #define B43_SHM_SH_SFFBLIM 0x0044 /* Short frame fallback retry limit */
218 #define B43_SHM_SH_LFFBLIM 0x0046 /* Long frame fallback retry limit */
219 #define B43_SHM_SH_BEACPHYCTL 0x0054 /* Beacon PHY TX control word (see PHY TX control) */
220 #define B43_SHM_SH_EXTNPHYCTL 0x00B0 /* Extended bytes for beacon PHY control (N) */
221 /* SHM_SHARED ACK/CTS control */
222 #define B43_SHM_SH_ACKCTSPHYCTL 0x0022 /* ACK/CTS PHY control word (see PHY TX control) */
223 /* SHM_SHARED probe response variables */
224 #define B43_SHM_SH_PRSSID 0x0160 /* Probe Response SSID */
225 #define B43_SHM_SH_PRSSIDLEN 0x0048 /* Probe Response SSID length */
226 #define B43_SHM_SH_PRTLEN 0x004A /* Probe Response template length */
227 #define B43_SHM_SH_PRMAXTIME 0x0074 /* Probe Response max time */
228 #define B43_SHM_SH_PRPHYCTL 0x0188 /* Probe Response PHY TX control word */
229 /* SHM_SHARED rate tables */
230 #define B43_SHM_SH_OFDMDIRECT 0x01C0 /* Pointer to OFDM direct map */
231 #define B43_SHM_SH_OFDMBASIC 0x01E0 /* Pointer to OFDM basic rate map */
232 #define B43_SHM_SH_CCKDIRECT 0x0200 /* Pointer to CCK direct map */
233 #define B43_SHM_SH_CCKBASIC 0x0220 /* Pointer to CCK basic rate map */
234 /* SHM_SHARED microcode soft registers */
235 #define B43_SHM_SH_UCODEREV 0x0000 /* Microcode revision */
236 #define B43_SHM_SH_UCODEPATCH 0x0002 /* Microcode patchlevel */
237 #define B43_SHM_SH_UCODEDATE 0x0004 /* Microcode date */
238 #define B43_SHM_SH_UCODETIME 0x0006 /* Microcode time */
239 #define B43_SHM_SH_UCODESTAT 0x0040 /* Microcode debug status code */
240 #define B43_SHM_SH_UCODESTAT_INVALID 0
241 #define B43_SHM_SH_UCODESTAT_INIT 1
242 #define B43_SHM_SH_UCODESTAT_ACTIVE 2
243 #define B43_SHM_SH_UCODESTAT_SUSP 3 /* suspended */
244 #define B43_SHM_SH_UCODESTAT_SLEEP 4 /* asleep (PS) */
245 #define B43_SHM_SH_MAXBFRAMES 0x0080 /* Maximum number of frames in a burst */
246 #define B43_SHM_SH_SPUWKUP 0x0094 /* pre-wakeup for synth PU in us */
247 #define B43_SHM_SH_PRETBTT 0x0096 /* pre-TBTT in us */
248
249 /* SHM_SCRATCH offsets */
250 #define B43_SHM_SC_MINCONT 0x0003 /* Minimum contention window */
251 #define B43_SHM_SC_MAXCONT 0x0004 /* Maximum contention window */
252 #define B43_SHM_SC_CURCONT 0x0005 /* Current contention window */
253 #define B43_SHM_SC_SRLIMIT 0x0006 /* Short retry count limit */
254 #define B43_SHM_SC_LRLIMIT 0x0007 /* Long retry count limit */
255 #define B43_SHM_SC_DTIMC 0x0008 /* Current DTIM count */
256 #define B43_SHM_SC_BTL0LEN 0x0015 /* Beacon 0 template length */
257 #define B43_SHM_SC_BTL1LEN 0x0016 /* Beacon 1 template length */
258 #define B43_SHM_SC_SCFB 0x0017 /* Short frame transmit count threshold for rate fallback */
259 #define B43_SHM_SC_LCFB 0x0018 /* Long frame transmit count threshold for rate fallback */
260
261 /* Hardware Radio Enable masks */
262 #define B43_MMIO_RADIO_HWENABLED_HI_MASK (1 << 16)
263 #define B43_MMIO_RADIO_HWENABLED_LO_MASK (1 << 4)
264
265 /* HostFlags. See b43_hf_read/write() */
266 #define B43_HF_ANTDIVHELP 0x000000000001ULL /* ucode antenna div helper */
267 #define B43_HF_SYMW 0x000000000002ULL /* G-PHY SYM workaround */
268 #define B43_HF_RXPULLW 0x000000000004ULL /* RX pullup workaround */
269 #define B43_HF_CCKBOOST 0x000000000008ULL /* 4dB CCK power boost (exclusive with OFDM boost) */
270 #define B43_HF_BTCOEX 0x000000000010ULL /* Bluetooth coexistance */
271 #define B43_HF_GDCW 0x000000000020ULL /* G-PHY DC canceller filter bw workaround */
272 #define B43_HF_OFDMPABOOST 0x000000000040ULL /* Enable PA gain boost for OFDM */
273 #define B43_HF_ACPR 0x000000000080ULL /* Disable for Japan, channel 14 */
274 #define B43_HF_EDCF 0x000000000100ULL /* on if WME and MAC suspended */
275 #define B43_HF_TSSIRPSMW 0x000000000200ULL /* TSSI reset PSM ucode workaround */
276 #define B43_HF_20IN40IQW 0x000000000200ULL /* 20 in 40 MHz I/Q workaround (rev >= 13 only) */
277 #define B43_HF_DSCRQ 0x000000000400ULL /* Disable slow clock request in ucode */
278 #define B43_HF_ACIW 0x000000000800ULL /* ACI workaround: shift bits by 2 on PHY CRS */
279 #define B43_HF_2060W 0x000000001000ULL /* 2060 radio workaround */
280 #define B43_HF_RADARW 0x000000002000ULL /* Radar workaround */
281 #define B43_HF_USEDEFKEYS 0x000000004000ULL /* Enable use of default keys */
282 #define B43_HF_AFTERBURNER 0x000000008000ULL /* Afterburner enabled */
283 #define B43_HF_BT4PRIOCOEX 0x000000010000ULL /* Bluetooth 4-priority coexistance */
284 #define B43_HF_FWKUP 0x000000020000ULL /* Fast wake-up ucode */
285 #define B43_HF_VCORECALC 0x000000040000ULL /* Force VCO recalculation when powering up synthpu */
286 #define B43_HF_PCISCW 0x000000080000ULL /* PCI slow clock workaround */
287 #define B43_HF_4318TSSI 0x000000200000ULL /* 4318 TSSI */
288 #define B43_HF_FBCMCFIFO 0x000000400000ULL /* Flush bcast/mcast FIFO immediately */
289 #define B43_HF_HWPCTL 0x000000800000ULL /* Enable hardwarre power control */
290 #define B43_HF_BTCOEXALT 0x000001000000ULL /* Bluetooth coexistance in alternate pins */
291 #define B43_HF_TXBTCHECK 0x000002000000ULL /* Bluetooth check during transmission */
292 #define B43_HF_SKCFPUP 0x000004000000ULL /* Skip CFP update */
293 #define B43_HF_N40W 0x000008000000ULL /* N PHY 40 MHz workaround (rev >= 13 only) */
294 #define B43_HF_ANTSEL 0x000020000000ULL /* Antenna selection (for testing antenna div.) */
295 #define B43_HF_BT3COEXT 0x000020000000ULL /* Bluetooth 3-wire coexistence (rev >= 13 only) */
296 #define B43_HF_BTCANT 0x000040000000ULL /* Bluetooth coexistence (antenna mode) (rev >= 13 only) */
297 #define B43_HF_ANTSELEN 0x000100000000ULL /* Antenna selection enabled (rev >= 13 only) */
298 #define B43_HF_ANTSELMODE 0x000200000000ULL /* Antenna selection mode (rev >= 13 only) */
299 #define B43_HF_MLADVW 0x001000000000ULL /* N PHY ML ADV workaround (rev >= 13 only) */
300 #define B43_HF_PR45960W 0x080000000000ULL /* PR 45960 workaround (rev >= 13 only) */
301
302 /* Firmware capabilities field in SHM (Opensource firmware only) */
303 #define B43_FWCAPA_HWCRYPTO 0x0001
304 #define B43_FWCAPA_QOS 0x0002
305
306 /* MacFilter offsets. */
307 #define B43_MACFILTER_SELF 0x0000
308 #define B43_MACFILTER_BSSID 0x0003
309
310 /* PowerControl */
311 #define B43_PCTL_IN 0xB0
312 #define B43_PCTL_OUT 0xB4
313 #define B43_PCTL_OUTENABLE 0xB8
314 #define B43_PCTL_XTAL_POWERUP 0x40
315 #define B43_PCTL_PLL_POWERDOWN 0x80
316
317 /* PowerControl Clock Modes */
318 #define B43_PCTL_CLK_FAST 0x00
319 #define B43_PCTL_CLK_SLOW 0x01
320 #define B43_PCTL_CLK_DYNAMIC 0x02
321
322 #define B43_PCTL_FORCE_SLOW 0x0800
323 #define B43_PCTL_FORCE_PLL 0x1000
324 #define B43_PCTL_DYN_XTAL 0x2000
325
326 /* PHYVersioning */
327 #define B43_PHYTYPE_A 0x00
328 #define B43_PHYTYPE_B 0x01
329 #define B43_PHYTYPE_G 0x02
330 #define B43_PHYTYPE_N 0x04
331 #define B43_PHYTYPE_LP 0x05
332
333 /* PHYRegisters */
334 #define B43_PHY_ILT_A_CTRL 0x0072
335 #define B43_PHY_ILT_A_DATA1 0x0073
336 #define B43_PHY_ILT_A_DATA2 0x0074
337 #define B43_PHY_G_LO_CONTROL 0x0810
338 #define B43_PHY_ILT_G_CTRL 0x0472
339 #define B43_PHY_ILT_G_DATA1 0x0473
340 #define B43_PHY_ILT_G_DATA2 0x0474
341 #define B43_PHY_A_PCTL 0x007B
342 #define B43_PHY_G_PCTL 0x0029
343 #define B43_PHY_A_CRS 0x0029
344 #define B43_PHY_RADIO_BITFIELD 0x0401
345 #define B43_PHY_G_CRS 0x0429
346 #define B43_PHY_NRSSILT_CTRL 0x0803
347 #define B43_PHY_NRSSILT_DATA 0x0804
348
349 /* RadioRegisters */
350 #define B43_RADIOCTL_ID 0x01
351
352 /* MAC Control bitfield */
353 #define B43_MACCTL_ENABLED 0x00000001 /* MAC Enabled */
354 #define B43_MACCTL_PSM_RUN 0x00000002 /* Run Microcode */
355 #define B43_MACCTL_PSM_JMP0 0x00000004 /* Microcode jump to 0 */
356 #define B43_MACCTL_SHM_ENABLED 0x00000100 /* SHM Enabled */
357 #define B43_MACCTL_SHM_UPPER 0x00000200 /* SHM Upper */
358 #define B43_MACCTL_IHR_ENABLED 0x00000400 /* IHR Region Enabled */
359 #define B43_MACCTL_PSM_DBG 0x00002000 /* Microcode debugging enabled */
360 #define B43_MACCTL_GPOUTSMSK 0x0000C000 /* GPOUT Select Mask */
361 #define B43_MACCTL_BE 0x00010000 /* Big Endian mode */
362 #define B43_MACCTL_INFRA 0x00020000 /* Infrastructure mode */
363 #define B43_MACCTL_AP 0x00040000 /* AccessPoint mode */
364 #define B43_MACCTL_RADIOLOCK 0x00080000 /* Radio lock */
365 #define B43_MACCTL_BEACPROMISC 0x00100000 /* Beacon Promiscuous */
366 #define B43_MACCTL_KEEP_BADPLCP 0x00200000 /* Keep frames with bad PLCP */
367 #define B43_MACCTL_KEEP_CTL 0x00400000 /* Keep control frames */
368 #define B43_MACCTL_KEEP_BAD 0x00800000 /* Keep bad frames (FCS) */
369 #define B43_MACCTL_PROMISC 0x01000000 /* Promiscuous mode */
370 #define B43_MACCTL_HWPS 0x02000000 /* Hardware Power Saving */
371 #define B43_MACCTL_AWAKE 0x04000000 /* Device is awake */
372 #define B43_MACCTL_CLOSEDNET 0x08000000 /* Closed net (no SSID bcast) */
373 #define B43_MACCTL_TBTTHOLD 0x10000000 /* TBTT Hold */
374 #define B43_MACCTL_DISCTXSTAT 0x20000000 /* Discard TX status */
375 #define B43_MACCTL_DISCPMQ 0x40000000 /* Discard Power Management Queue */
376 #define B43_MACCTL_GMODE 0x80000000 /* G Mode */
377
378 /* MAC Command bitfield */
379 #define B43_MACCMD_BEACON0_VALID 0x00000001 /* Beacon 0 in template RAM is busy/valid */
380 #define B43_MACCMD_BEACON1_VALID 0x00000002 /* Beacon 1 in template RAM is busy/valid */
381 #define B43_MACCMD_DFQ_VALID 0x00000004 /* Directed frame queue valid (IBSS PS mode, ATIM) */
382 #define B43_MACCMD_CCA 0x00000008 /* Clear channel assessment */
383 #define B43_MACCMD_BGNOISE 0x00000010 /* Background noise */
384
385 /* 802.11 core specific TM State Low (SSB_TMSLOW) flags */
386 #define B43_TMSLOW_GMODE 0x20000000 /* G Mode Enable */
387 #define B43_TMSLOW_PHYCLKSPEED 0x00C00000 /* PHY clock speed mask (N-PHY only) */
388 #define B43_TMSLOW_PHYCLKSPEED_40MHZ 0x00000000 /* 40 MHz PHY */
389 #define B43_TMSLOW_PHYCLKSPEED_80MHZ 0x00400000 /* 80 MHz PHY */
390 #define B43_TMSLOW_PHYCLKSPEED_160MHZ 0x00800000 /* 160 MHz PHY */
391 #define B43_TMSLOW_PLLREFSEL 0x00200000 /* PLL Frequency Reference Select (rev >= 5) */
392 #define B43_TMSLOW_MACPHYCLKEN 0x00100000 /* MAC PHY Clock Control Enable (rev >= 5) */
393 #define B43_TMSLOW_PHYRESET 0x00080000 /* PHY Reset */
394 #define B43_TMSLOW_PHYCLKEN 0x00040000 /* PHY Clock Enable */
395
396 /* 802.11 core specific TM State High (SSB_TMSHIGH) flags */
397 #define B43_TMSHIGH_DUALBAND_PHY 0x00080000 /* Dualband PHY available */
398 #define B43_TMSHIGH_FCLOCK 0x00040000 /* Fast Clock Available (rev >= 5) */
399 #define B43_TMSHIGH_HAVE_5GHZ_PHY 0x00020000 /* 5 GHz PHY available (rev >= 5) */
400 #define B43_TMSHIGH_HAVE_2GHZ_PHY 0x00010000 /* 2.4 GHz PHY available (rev >= 5) */
401
402 /* Generic-Interrupt reasons. */
403 #define B43_IRQ_MAC_SUSPENDED 0x00000001
404 #define B43_IRQ_BEACON 0x00000002
405 #define B43_IRQ_TBTT_INDI 0x00000004
406 #define B43_IRQ_BEACON_TX_OK 0x00000008
407 #define B43_IRQ_BEACON_CANCEL 0x00000010
408 #define B43_IRQ_ATIM_END 0x00000020
409 #define B43_IRQ_PMQ 0x00000040
410 #define B43_IRQ_PIO_WORKAROUND 0x00000100
411 #define B43_IRQ_MAC_TXERR 0x00000200
412 #define B43_IRQ_PHY_TXERR 0x00000800
413 #define B43_IRQ_PMEVENT 0x00001000
414 #define B43_IRQ_TIMER0 0x00002000
415 #define B43_IRQ_TIMER1 0x00004000
416 #define B43_IRQ_DMA 0x00008000
417 #define B43_IRQ_TXFIFO_FLUSH_OK 0x00010000
418 #define B43_IRQ_CCA_MEASURE_OK 0x00020000
419 #define B43_IRQ_NOISESAMPLE_OK 0x00040000
420 #define B43_IRQ_UCODE_DEBUG 0x08000000
421 #define B43_IRQ_RFKILL 0x10000000
422 #define B43_IRQ_TX_OK 0x20000000
423 #define B43_IRQ_PHY_G_CHANGED 0x40000000
424 #define B43_IRQ_TIMEOUT 0x80000000
425
426 #define B43_IRQ_ALL 0xFFFFFFFF
427 #define B43_IRQ_MASKTEMPLATE (B43_IRQ_TBTT_INDI | \
428 B43_IRQ_ATIM_END | \
429 B43_IRQ_PMQ | \
430 B43_IRQ_MAC_TXERR | \
431 B43_IRQ_PHY_TXERR | \
432 B43_IRQ_DMA | \
433 B43_IRQ_TXFIFO_FLUSH_OK | \
434 B43_IRQ_NOISESAMPLE_OK | \
435 B43_IRQ_UCODE_DEBUG | \
436 B43_IRQ_RFKILL | \
437 B43_IRQ_TX_OK)
438
439 /* The firmware register to fetch the debug-IRQ reason from. */
440 #define B43_DEBUGIRQ_REASON_REG 63
441 /* Debug-IRQ reasons. */
442 #define B43_DEBUGIRQ_PANIC 0 /* The firmware panic'ed */
443 #define B43_DEBUGIRQ_DUMP_SHM 1 /* Dump shared SHM */
444 #define B43_DEBUGIRQ_DUMP_REGS 2 /* Dump the microcode registers */
445 #define B43_DEBUGIRQ_MARKER 3 /* A "marker" was thrown by the firmware. */
446 #define B43_DEBUGIRQ_ACK 0xFFFF /* The host writes that to ACK the IRQ */
447
448 /* The firmware register that contains the "marker" line. */
449 #define B43_MARKER_ID_REG 2
450 #define B43_MARKER_LINE_REG 3
451
452 /* The firmware register to fetch the panic reason from. */
453 #define B43_FWPANIC_REASON_REG 3
454 /* Firmware panic reason codes */
455 #define B43_FWPANIC_DIE 0 /* Firmware died. Don't auto-restart it. */
456 #define B43_FWPANIC_RESTART 1 /* Firmware died. Schedule a controller reset. */
457
458 /* The firmware register that contains the watchdog counter. */
459 #define B43_WATCHDOG_REG 1
460
461 /* Device specific rate values.
462 * The actual values defined here are (rate_in_mbps * 2).
463 * Some code depends on this. Don't change it. */
464 #define B43_CCK_RATE_1MB 0x02
465 #define B43_CCK_RATE_2MB 0x04
466 #define B43_CCK_RATE_5MB 0x0B
467 #define B43_CCK_RATE_11MB 0x16
468 #define B43_OFDM_RATE_6MB 0x0C
469 #define B43_OFDM_RATE_9MB 0x12
470 #define B43_OFDM_RATE_12MB 0x18
471 #define B43_OFDM_RATE_18MB 0x24
472 #define B43_OFDM_RATE_24MB 0x30
473 #define B43_OFDM_RATE_36MB 0x48
474 #define B43_OFDM_RATE_48MB 0x60
475 #define B43_OFDM_RATE_54MB 0x6C
476 /* Convert a b43 rate value to a rate in 100kbps */
477 #define B43_RATE_TO_BASE100KBPS(rate) (((rate) * 10) / 2)
478
479 #define B43_DEFAULT_SHORT_RETRY_LIMIT 7
480 #define B43_DEFAULT_LONG_RETRY_LIMIT 4
481
482 #define B43_PHY_TX_BADNESS_LIMIT 1000
483
484 /* Max size of a security key */
485 #define B43_SEC_KEYSIZE 16
486 /* Security algorithms. */
487 enum {
488 B43_SEC_ALGO_NONE = 0, /* unencrypted, as of TX header. */
489 B43_SEC_ALGO_WEP40,
490 B43_SEC_ALGO_TKIP,
491 B43_SEC_ALGO_AES,
492 B43_SEC_ALGO_WEP104,
493 B43_SEC_ALGO_AES_LEGACY,
494 };
495
496 struct b43_dmaring;
497
498 /* The firmware file header */
499 #define B43_FW_TYPE_UCODE 'u'
500 #define B43_FW_TYPE_PCM 'p'
501 #define B43_FW_TYPE_IV 'i'
502 struct b43_fw_header {
503 /* File type */
504 u8 type;
505 /* File format version */
506 u8 ver;
507 u8 __padding[2];
508 /* Size of the data. For ucode and PCM this is in bytes.
509 * For IV this is number-of-ivs. */
510 __be32 size;
511 } __attribute__((__packed__));
512
513 /* Initial Value file format */
514 #define B43_IV_OFFSET_MASK 0x7FFF
515 #define B43_IV_32BIT 0x8000
516 struct b43_iv {
517 __be16 offset_size;
518 union {
519 __be16 d16;
520 __be32 d32;
521 } data __attribute__((__packed__));
522 } __attribute__((__packed__));
523
524
525 /* Data structures for DMA transmission, per 80211 core. */
526 struct b43_dma {
527 struct b43_dmaring *tx_ring_AC_BK; /* Background */
528 struct b43_dmaring *tx_ring_AC_BE; /* Best Effort */
529 struct b43_dmaring *tx_ring_AC_VI; /* Video */
530 struct b43_dmaring *tx_ring_AC_VO; /* Voice */
531 struct b43_dmaring *tx_ring_mcast; /* Multicast */
532
533 struct b43_dmaring *rx_ring;
534 };
535
536 struct b43_pio_txqueue;
537 struct b43_pio_rxqueue;
538
539 /* Data structures for PIO transmission, per 80211 core. */
540 struct b43_pio {
541 struct b43_pio_txqueue *tx_queue_AC_BK; /* Background */
542 struct b43_pio_txqueue *tx_queue_AC_BE; /* Best Effort */
543 struct b43_pio_txqueue *tx_queue_AC_VI; /* Video */
544 struct b43_pio_txqueue *tx_queue_AC_VO; /* Voice */
545 struct b43_pio_txqueue *tx_queue_mcast; /* Multicast */
546
547 struct b43_pio_rxqueue *rx_queue;
548 };
549
550 /* Context information for a noise calculation (Link Quality). */
551 struct b43_noise_calculation {
552 bool calculation_running;
553 u8 nr_samples;
554 s8 samples[8][4];
555 };
556
557 struct b43_stats {
558 u8 link_noise;
559 };
560
561 struct b43_key {
562 /* If keyconf is NULL, this key is disabled.
563 * keyconf is a cookie. Don't derefenrence it outside of the set_key
564 * path, because b43 doesn't own it. */
565 struct ieee80211_key_conf *keyconf;
566 u8 algorithm;
567 };
568
569 /* SHM offsets to the QOS data structures for the 4 different queues. */
570 #define B43_QOS_PARAMS(queue) (B43_SHM_SH_EDCFQ + \
571 (B43_NR_QOSPARAMS * sizeof(u16) * (queue)))
572 #define B43_QOS_BACKGROUND B43_QOS_PARAMS(0)
573 #define B43_QOS_BESTEFFORT B43_QOS_PARAMS(1)
574 #define B43_QOS_VIDEO B43_QOS_PARAMS(2)
575 #define B43_QOS_VOICE B43_QOS_PARAMS(3)
576
577 /* QOS parameter hardware data structure offsets. */
578 #define B43_NR_QOSPARAMS 16
579 enum {
580 B43_QOSPARAM_TXOP = 0,
581 B43_QOSPARAM_CWMIN,
582 B43_QOSPARAM_CWMAX,
583 B43_QOSPARAM_CWCUR,
584 B43_QOSPARAM_AIFS,
585 B43_QOSPARAM_BSLOTS,
586 B43_QOSPARAM_REGGAP,
587 B43_QOSPARAM_STATUS,
588 };
589
590 /* QOS parameters for a queue. */
591 struct b43_qos_params {
592 /* The QOS parameters */
593 struct ieee80211_tx_queue_params p;
594 };
595
596 struct b43_wldev;
597
598 /* Data structure for the WLAN parts (802.11 cores) of the b43 chip. */
599 struct b43_wl {
600 /* Pointer to the active wireless device on this chip */
601 struct b43_wldev *current_dev;
602 /* Pointer to the ieee80211 hardware data structure */
603 struct ieee80211_hw *hw;
604
605 /* The number of queues that were registered with the mac80211 subsystem
606 * initially. This is a backup copy of hw->queues in case hw->queues has
607 * to be dynamically lowered at runtime (Firmware does not support QoS).
608 * hw->queues has to be restored to the original value before unregistering
609 * from the mac80211 subsystem. */
610 u16 mac80211_initially_registered_queues;
611
612 struct mutex mutex;
613 spinlock_t irq_lock;
614 /* R/W lock for data transmission.
615 * Transmissions on 2+ queues can run concurrently, but somebody else
616 * might sync with TX by write_lock_irqsave()'ing. */
617 rwlock_t tx_lock;
618 /* Lock for LEDs access. */
619 spinlock_t leds_lock;
620 /* Lock for SHM access. */
621 spinlock_t shm_lock;
622
623 /* We can only have one operating interface (802.11 core)
624 * at a time. General information about this interface follows.
625 */
626
627 struct ieee80211_vif *vif;
628 /* The MAC address of the operating interface. */
629 u8 mac_addr[ETH_ALEN];
630 /* Current BSSID */
631 u8 bssid[ETH_ALEN];
632 /* Interface type. (IEEE80211_IF_TYPE_XXX) */
633 int if_type;
634 /* Is the card operating in AP, STA or IBSS mode? */
635 bool operating;
636 /* filter flags */
637 unsigned int filter_flags;
638 /* Stats about the wireless interface */
639 struct ieee80211_low_level_stats ieee_stats;
640
641 #ifdef CONFIG_B43_HWRNG
642 struct hwrng rng;
643 bool rng_initialized;
644 char rng_name[30 + 1];
645 #endif /* CONFIG_B43_HWRNG */
646
647 /* List of all wireless devices on this chip */
648 struct list_head devlist;
649 u8 nr_devs;
650
651 bool radiotap_enabled;
652 bool radio_enabled;
653
654 /* The beacon we are currently using (AP or IBSS mode).
655 * This beacon stuff is protected by the irq_lock. */
656 struct sk_buff *current_beacon;
657 bool beacon0_uploaded;
658 bool beacon1_uploaded;
659 bool beacon_templates_virgin; /* Never wrote the templates? */
660 struct work_struct beacon_update_trigger;
661
662 /* The current QOS parameters for the 4 queues. */
663 struct b43_qos_params qos_params[4];
664
665 /* Work for adjustment of the transmission power.
666 * This is scheduled when we determine that the actual TX output
667 * power doesn't match what we want. */
668 struct work_struct txpower_adjust_work;
669 };
670
671 /* The type of the firmware file. */
672 enum b43_firmware_file_type {
673 B43_FWTYPE_PROPRIETARY,
674 B43_FWTYPE_OPENSOURCE,
675 B43_NR_FWTYPES,
676 };
677
678 /* Context data for fetching firmware. */
679 struct b43_request_fw_context {
680 /* The device we are requesting the fw for. */
681 struct b43_wldev *dev;
682 /* The type of firmware to request. */
683 enum b43_firmware_file_type req_type;
684 /* Error messages for each firmware type. */
685 char errors[B43_NR_FWTYPES][128];
686 /* Temporary buffer for storing the firmware name. */
687 char fwname[64];
688 /* A fatal error occured while requesting. Firmware reqest
689 * can not continue, as any other reqest will also fail. */
690 int fatal_failure;
691 };
692
693 /* In-memory representation of a cached microcode file. */
694 struct b43_firmware_file {
695 const char *filename;
696 const struct firmware *data;
697 /* Type of the firmware file name. Note that this does only indicate
698 * the type by the firmware name. NOT the file contents.
699 * If you want to check for proprietary vs opensource, use (struct b43_firmware)->opensource
700 * instead! The (struct b43_firmware)->opensource flag is derived from the actual firmware
701 * binary code, not just the filename.
702 */
703 enum b43_firmware_file_type type;
704 };
705
706 /* Pointers to the firmware data and meta information about it. */
707 struct b43_firmware {
708 /* Microcode */
709 struct b43_firmware_file ucode;
710 /* PCM code */
711 struct b43_firmware_file pcm;
712 /* Initial MMIO values for the firmware */
713 struct b43_firmware_file initvals;
714 /* Initial MMIO values for the firmware, band-specific */
715 struct b43_firmware_file initvals_band;
716
717 /* Firmware revision */
718 u16 rev;
719 /* Firmware patchlevel */
720 u16 patch;
721
722 /* Set to true, if we are using an opensource firmware.
723 * Use this to check for proprietary vs opensource. */
724 bool opensource;
725 /* Set to true, if the core needs a PCM firmware, but
726 * we failed to load one. This is always false for
727 * core rev > 10, as these don't need PCM firmware. */
728 bool pcm_request_failed;
729 };
730
731 /* Device (802.11 core) initialization status. */
732 enum {
733 B43_STAT_UNINIT = 0, /* Uninitialized. */
734 B43_STAT_INITIALIZED = 1, /* Initialized, but not started, yet. */
735 B43_STAT_STARTED = 2, /* Up and running. */
736 };
737 #define b43_status(wldev) atomic_read(&(wldev)->__init_status)
738 #define b43_set_status(wldev, stat) do { \
739 atomic_set(&(wldev)->__init_status, (stat)); \
740 smp_wmb(); \
741 } while (0)
742
743 /* XXX--- HOW LOCKING WORKS IN B43 ---XXX
744 *
745 * You should always acquire both, wl->mutex and wl->irq_lock unless:
746 * - You don't need to acquire wl->irq_lock, if the interface is stopped.
747 * - You don't need to acquire wl->mutex in the IRQ handler, IRQ tasklet
748 * and packet TX path (and _ONLY_ there.)
749 */
750
751 /* Data structure for one wireless device (802.11 core) */
752 struct b43_wldev {
753 struct ssb_device *dev;
754 struct b43_wl *wl;
755
756 /* The device initialization status.
757 * Use b43_status() to query. */
758 atomic_t __init_status;
759 /* Saved init status for handling suspend. */
760 int suspend_init_status;
761
762 bool bad_frames_preempt; /* Use "Bad Frames Preemption" (default off) */
763 bool dfq_valid; /* Directed frame queue valid (IBSS PS mode, ATIM) */
764 bool radio_hw_enable; /* saved state of radio hardware enabled state */
765 bool suspend_in_progress; /* TRUE, if we are in a suspend/resume cycle */
766 bool qos_enabled; /* TRUE, if QoS is used. */
767 bool hwcrypto_enabled; /* TRUE, if HW crypto acceleration is enabled. */
768
769 /* PHY/Radio device. */
770 struct b43_phy phy;
771
772 union {
773 /* DMA engines. */
774 struct b43_dma dma;
775 /* PIO engines. */
776 struct b43_pio pio;
777 };
778 /* Use b43_using_pio_transfers() to check whether we are using
779 * DMA or PIO data transfers. */
780 bool __using_pio_transfers;
781
782 /* Various statistics about the physical device. */
783 struct b43_stats stats;
784
785 /* The device LEDs. */
786 struct b43_led led_tx;
787 struct b43_led led_rx;
788 struct b43_led led_assoc;
789 struct b43_led led_radio;
790
791 /* Reason code of the last interrupt. */
792 u32 irq_reason;
793 u32 dma_reason[6];
794 /* The currently active generic-interrupt mask. */
795 u32 irq_mask;
796 /* Link Quality calculation context. */
797 struct b43_noise_calculation noisecalc;
798 /* if > 0 MAC is suspended. if == 0 MAC is enabled. */
799 int mac_suspended;
800
801 /* Interrupt Service Routine tasklet (bottom-half) */
802 struct tasklet_struct isr_tasklet;
803
804 /* Periodic tasks */
805 struct delayed_work periodic_work;
806 unsigned int periodic_state;
807
808 struct work_struct restart_work;
809
810 /* encryption/decryption */
811 u16 ktp; /* Key table pointer */
812 u8 max_nr_keys;
813 struct b43_key key[58];
814
815 /* Firmware data */
816 struct b43_firmware fw;
817
818 /* Devicelist in struct b43_wl (all 802.11 cores) */
819 struct list_head list;
820
821 /* Debugging stuff follows. */
822 #ifdef CONFIG_B43_DEBUG
823 struct b43_dfsentry *dfsentry;
824 #endif
825 };
826
827 static inline struct b43_wl *hw_to_b43_wl(struct ieee80211_hw *hw)
828 {
829 return hw->priv;
830 }
831
832 static inline struct b43_wldev *dev_to_b43_wldev(struct device *dev)
833 {
834 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
835 return ssb_get_drvdata(ssb_dev);
836 }
837
838 /* Is the device operating in a specified mode (IEEE80211_IF_TYPE_XXX). */
839 static inline int b43_is_mode(struct b43_wl *wl, int type)
840 {
841 return (wl->operating && wl->if_type == type);
842 }
843
844 /**
845 * b43_current_band - Returns the currently used band.
846 * Returns one of IEEE80211_BAND_2GHZ and IEEE80211_BAND_5GHZ.
847 */
848 static inline enum ieee80211_band b43_current_band(struct b43_wl *wl)
849 {
850 return wl->hw->conf.channel->band;
851 }
852
853 static inline u16 b43_read16(struct b43_wldev *dev, u16 offset)
854 {
855 return ssb_read16(dev->dev, offset);
856 }
857
858 static inline void b43_write16(struct b43_wldev *dev, u16 offset, u16 value)
859 {
860 ssb_write16(dev->dev, offset, value);
861 }
862
863 static inline u32 b43_read32(struct b43_wldev *dev, u16 offset)
864 {
865 return ssb_read32(dev->dev, offset);
866 }
867
868 static inline void b43_write32(struct b43_wldev *dev, u16 offset, u32 value)
869 {
870 ssb_write32(dev->dev, offset, value);
871 }
872
873 static inline bool b43_using_pio_transfers(struct b43_wldev *dev)
874 {
875 #ifdef CONFIG_B43_PIO
876 return dev->__using_pio_transfers;
877 #else
878 return 0;
879 #endif
880 }
881
882 #ifdef CONFIG_B43_FORCE_PIO
883 # define B43_FORCE_PIO 1
884 #else
885 # define B43_FORCE_PIO 0
886 #endif
887
888
889 /* Message printing */
890 void b43info(struct b43_wl *wl, const char *fmt, ...)
891 __attribute__ ((format(printf, 2, 3)));
892 void b43err(struct b43_wl *wl, const char *fmt, ...)
893 __attribute__ ((format(printf, 2, 3)));
894 void b43warn(struct b43_wl *wl, const char *fmt, ...)
895 __attribute__ ((format(printf, 2, 3)));
896 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
897 __attribute__ ((format(printf, 2, 3)));
898
899
900 /* A WARN_ON variant that vanishes when b43 debugging is disabled.
901 * This _also_ evaluates the arg with debugging disabled. */
902 #if B43_DEBUG
903 # define B43_WARN_ON(x) WARN_ON(x)
904 #else
905 static inline bool __b43_warn_on_dummy(bool x) { return x; }
906 # define B43_WARN_ON(x) __b43_warn_on_dummy(unlikely(!!(x)))
907 #endif
908
909 /* Convert an integer to a Q5.2 value */
910 #define INT_TO_Q52(i) ((i) << 2)
911 /* Convert a Q5.2 value to an integer (precision loss!) */
912 #define Q52_TO_INT(q52) ((q52) >> 2)
913 /* Macros for printing a value in Q5.2 format */
914 #define Q52_FMT "%u.%u"
915 #define Q52_ARG(q52) Q52_TO_INT(q52), ((((q52) & 0x3) * 100) / 4)
916
917 #endif /* B43_H_ */
918
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