1 /*-
2 * Copyright (c) 2002-2007 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
15 * 3. Neither the names of the above-listed copyright holders nor the names
16 * of any contributors may be used to endorse or promote products derived
17 * from this software without specific prior written permission.
18 *
19 * Alternatively, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") version 2 as published by the Free
21 * Software Foundation.
22 *
23 * NO WARRANTY
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
34 * THE POSSIBILITY OF SUCH DAMAGES.
35 *
36 */
37
38 /*
39 * Defintions for the Atheros Wireless LAN controller driver.
40 */
41 #ifndef _DEV_ATH_ATHVAR_H
42 #define _DEV_ATH_ATHVAR_H
43
44 #include <linux/interrupt.h>
45 #include <linux/list.h>
46 #include <linux/wireless.h>
47 #include <linux/if_ether.h>
48 #include <linux/leds.h>
49 #include <linux/rfkill.h>
50
51 #include "ath5k.h"
52 #include "debug.h"
53
54 #define ATH_RXBUF 40 /* number of RX buffers */
55 #define ATH_TXBUF 200 /* number of TX buffers */
56 #define ATH_BCBUF 1 /* number of beacon buffers */
57
58 struct ath5k_buf {
59 struct list_head list;
60 struct ath5k_desc *desc; /* virtual addr of desc */
61 dma_addr_t daddr; /* physical addr of desc */
62 struct sk_buff *skb; /* skbuff for buf */
63 dma_addr_t skbaddr;/* physical addr of skb data */
64 };
65
66 /*
67 * Data transmit queue state. One of these exists for each
68 * hardware transmit queue. Packets sent to us from above
69 * are assigned to queues based on their priority. Not all
70 * devices support a complete set of hardware transmit queues.
71 * For those devices the array sc_ac2q will map multiple
72 * priorities to fewer hardware queues (typically all to one
73 * hardware queue).
74 */
75 struct ath5k_txq {
76 unsigned int qnum; /* hardware q number */
77 u32 *link; /* link ptr in last TX desc */
78 struct list_head q; /* transmit queue */
79 spinlock_t lock; /* lock on q and link */
80 bool setup;
81 };
82
83 #define ATH5K_LED_MAX_NAME_LEN 31
84
85 /*
86 * State for LED triggers
87 */
88 struct ath5k_led
89 {
90 char name[ATH5K_LED_MAX_NAME_LEN + 1]; /* name of the LED in sysfs */
91 struct ath5k_softc *sc; /* driver state */
92 struct led_classdev led_dev; /* led classdev */
93 };
94
95 /* Rfkill */
96 struct ath5k_rfkill {
97 /* GPIO PIN for rfkill */
98 u16 gpio;
99 /* polarity of rfkill GPIO PIN */
100 bool polarity;
101 /* RFKILL toggle tasklet */
102 struct tasklet_struct toggleq;
103 };
104
105 #if CHAN_DEBUG
106 #define ATH_CHAN_MAX (26+26+26+200+200)
107 #else
108 #define ATH_CHAN_MAX (14+14+14+252+20)
109 #endif
110
111 /* Software Carrier, keeps track of the driver state
112 * associated with an instance of a device */
113 struct ath5k_softc {
114 struct pci_dev *pdev; /* for dma mapping */
115 void __iomem *iobase; /* address of the device */
116 struct mutex lock; /* dev-level lock */
117 /* FIXME: how many does it really need? */
118 struct ieee80211_tx_queue_stats tx_stats[16];
119 struct ieee80211_low_level_stats ll_stats;
120 struct ieee80211_hw *hw; /* IEEE 802.11 common */
121 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
122 struct ieee80211_channel channels[ATH_CHAN_MAX];
123 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
124 s8 rate_idx[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
125 enum nl80211_iftype opmode;
126 struct ath5k_hw *ah; /* Atheros HW */
127
128 struct ieee80211_supported_band *curband;
129
130 #ifdef CONFIG_ATH5K_DEBUG
131 struct ath5k_dbg_info debug; /* debug info */
132 #endif /* CONFIG_ATH5K_DEBUG */
133
134 struct ath5k_buf *bufptr; /* allocated buffer ptr */
135 struct ath5k_desc *desc; /* TX/RX descriptors */
136 dma_addr_t desc_daddr; /* DMA (physical) address */
137 size_t desc_len; /* size of TX/RX descriptors */
138 u16 cachelsz; /* cache line size */
139
140 DECLARE_BITMAP(status, 5);
141 #define ATH_STAT_INVALID 0 /* disable hardware accesses */
142 #define ATH_STAT_MRRETRY 1 /* multi-rate retry support */
143 #define ATH_STAT_PROMISC 2
144 #define ATH_STAT_LEDSOFT 3 /* enable LED gpio status */
145 #define ATH_STAT_STARTED 4 /* opened & irqs enabled */
146
147 unsigned int filter_flags; /* HW flags, AR5K_RX_FILTER_* */
148 unsigned int curmode; /* current phy mode */
149 struct ieee80211_channel *curchan; /* current h/w channel */
150
151 struct ieee80211_vif *vif;
152
153 enum ath5k_int imask; /* interrupt mask copy */
154
155 DECLARE_BITMAP(keymap, AR5K_KEYCACHE_SIZE); /* key use bit map */
156
157 u8 bssidmask[ETH_ALEN];
158
159 unsigned int led_pin, /* GPIO pin for driving LED */
160 led_on; /* pin setting for LED on */
161
162 struct tasklet_struct restq; /* reset tasklet */
163
164 unsigned int rxbufsize; /* rx size based on mtu */
165 struct list_head rxbuf; /* receive buffer */
166 spinlock_t rxbuflock;
167 u32 *rxlink; /* link ptr in last RX desc */
168 struct tasklet_struct rxtq; /* rx intr tasklet */
169 struct ath5k_led rx_led; /* rx led */
170
171 struct list_head txbuf; /* transmit buffer */
172 spinlock_t txbuflock;
173 unsigned int txbuf_len; /* buf count in txbuf list */
174 struct ath5k_txq txqs[2]; /* beacon and tx */
175
176 struct ath5k_txq *txq; /* beacon and tx*/
177 struct tasklet_struct txtq; /* tx intr tasklet */
178 struct ath5k_led tx_led; /* tx led */
179
180 struct ath5k_rfkill rf_kill;
181
182 spinlock_t block; /* protects beacon */
183 struct tasklet_struct beacontq; /* beacon intr tasklet */
184 struct ath5k_buf *bbuf; /* beacon buffer */
185 unsigned int bhalq, /* SW q for outgoing beacons */
186 bmisscount, /* missed beacon transmits */
187 bintval, /* beacon interval in TU */
188 bsent;
189 unsigned int nexttbtt; /* next beacon time in TU */
190
191 struct timer_list calib_tim; /* calibration timer */
192 int power_level; /* Requested tx power in dbm */
193 bool assoc; /* assocate state */
194 };
195
196 #define ath5k_hw_hasbssidmask(_ah) \
197 (ath5k_hw_get_capability(_ah, AR5K_CAP_BSSIDMASK, 0, NULL) == 0)
198 #define ath5k_hw_hasveol(_ah) \
199 (ath5k_hw_get_capability(_ah, AR5K_CAP_VEOL, 0, NULL) == 0)
200
201 #endif
202
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