1 /*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
46 #include <linux/if.h>
47 #include <linux/io.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/pci.h>
51 #include <linux/ethtool.h>
52 #include <linux/uaccess.h>
53
54 #include <net/ieee80211_radiotap.h>
55
56 #include <asm/unaligned.h>
57
58 #include "base.h"
59 #include "reg.h"
60 #include "debug.h"
61
62 static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
63 static int modparam_nohwcrypt;
64 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
65 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
66
67 static int modparam_all_channels;
68 module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
69 MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
70
71
72 /******************\
73 * Internal defines *
74 \******************/
75
76 /* Module info */
77 MODULE_AUTHOR("Jiri Slaby");
78 MODULE_AUTHOR("Nick Kossifidis");
79 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
80 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
81 MODULE_LICENSE("Dual BSD/GPL");
82 MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
83
84
85 /* Known PCI ids */
86 static const struct pci_device_id ath5k_pci_id_table[] = {
87 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
88 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
89 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
90 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
91 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
92 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
93 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
94 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
95 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
96 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
102 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
103 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* PCI-E cards */
104 { PCI_VDEVICE(ATHEROS, 0x001d), .driver_data = AR5K_AR5212 }, /* 2417 Nala */
105 { 0 }
106 };
107 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
108
109 /* Known SREVs */
110 static const struct ath5k_srev_name srev_names[] = {
111 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
112 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
113 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
114 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
115 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
116 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
117 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
118 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
119 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
120 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
121 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
122 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
123 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
124 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
125 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
126 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
127 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
128 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
129 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
130 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
131 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
132 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
133 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
134 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
135 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
136 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
137 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
138 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
139 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
140 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
141 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
142 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
143 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
144 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
145 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
146 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
147 };
148
149 static const struct ieee80211_rate ath5k_rates[] = {
150 { .bitrate = 10,
151 .hw_value = ATH5K_RATE_CODE_1M, },
152 { .bitrate = 20,
153 .hw_value = ATH5K_RATE_CODE_2M,
154 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
155 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
156 { .bitrate = 55,
157 .hw_value = ATH5K_RATE_CODE_5_5M,
158 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
159 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
160 { .bitrate = 110,
161 .hw_value = ATH5K_RATE_CODE_11M,
162 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
163 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
164 { .bitrate = 60,
165 .hw_value = ATH5K_RATE_CODE_6M,
166 .flags = 0 },
167 { .bitrate = 90,
168 .hw_value = ATH5K_RATE_CODE_9M,
169 .flags = 0 },
170 { .bitrate = 120,
171 .hw_value = ATH5K_RATE_CODE_12M,
172 .flags = 0 },
173 { .bitrate = 180,
174 .hw_value = ATH5K_RATE_CODE_18M,
175 .flags = 0 },
176 { .bitrate = 240,
177 .hw_value = ATH5K_RATE_CODE_24M,
178 .flags = 0 },
179 { .bitrate = 360,
180 .hw_value = ATH5K_RATE_CODE_36M,
181 .flags = 0 },
182 { .bitrate = 480,
183 .hw_value = ATH5K_RATE_CODE_48M,
184 .flags = 0 },
185 { .bitrate = 540,
186 .hw_value = ATH5K_RATE_CODE_54M,
187 .flags = 0 },
188 /* XR missing */
189 };
190
191 /*
192 * Prototypes - PCI stack related functions
193 */
194 static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
195 const struct pci_device_id *id);
196 static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
197 #ifdef CONFIG_PM
198 static int ath5k_pci_suspend(struct pci_dev *pdev,
199 pm_message_t state);
200 static int ath5k_pci_resume(struct pci_dev *pdev);
201 #else
202 #define ath5k_pci_suspend NULL
203 #define ath5k_pci_resume NULL
204 #endif /* CONFIG_PM */
205
206 static struct pci_driver ath5k_pci_driver = {
207 .name = KBUILD_MODNAME,
208 .id_table = ath5k_pci_id_table,
209 .probe = ath5k_pci_probe,
210 .remove = __devexit_p(ath5k_pci_remove),
211 .suspend = ath5k_pci_suspend,
212 .resume = ath5k_pci_resume,
213 };
214
215
216
217 /*
218 * Prototypes - MAC 802.11 stack related functions
219 */
220 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
221 static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan);
222 static int ath5k_reset_wake(struct ath5k_softc *sc);
223 static int ath5k_start(struct ieee80211_hw *hw);
224 static void ath5k_stop(struct ieee80211_hw *hw);
225 static int ath5k_add_interface(struct ieee80211_hw *hw,
226 struct ieee80211_if_init_conf *conf);
227 static void ath5k_remove_interface(struct ieee80211_hw *hw,
228 struct ieee80211_if_init_conf *conf);
229 static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
230 static void ath5k_configure_filter(struct ieee80211_hw *hw,
231 unsigned int changed_flags,
232 unsigned int *new_flags,
233 int mc_count, struct dev_mc_list *mclist);
234 static int ath5k_set_key(struct ieee80211_hw *hw,
235 enum set_key_cmd cmd,
236 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
237 struct ieee80211_key_conf *key);
238 static int ath5k_get_stats(struct ieee80211_hw *hw,
239 struct ieee80211_low_level_stats *stats);
240 static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
241 struct ieee80211_tx_queue_stats *stats);
242 static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
243 static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
244 static void ath5k_reset_tsf(struct ieee80211_hw *hw);
245 static int ath5k_beacon_update(struct ieee80211_hw *hw,
246 struct ieee80211_vif *vif);
247 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
248 struct ieee80211_vif *vif,
249 struct ieee80211_bss_conf *bss_conf,
250 u32 changes);
251
252 static const struct ieee80211_ops ath5k_hw_ops = {
253 .tx = ath5k_tx,
254 .start = ath5k_start,
255 .stop = ath5k_stop,
256 .add_interface = ath5k_add_interface,
257 .remove_interface = ath5k_remove_interface,
258 .config = ath5k_config,
259 .configure_filter = ath5k_configure_filter,
260 .set_key = ath5k_set_key,
261 .get_stats = ath5k_get_stats,
262 .conf_tx = NULL,
263 .get_tx_stats = ath5k_get_tx_stats,
264 .get_tsf = ath5k_get_tsf,
265 .set_tsf = ath5k_set_tsf,
266 .reset_tsf = ath5k_reset_tsf,
267 .bss_info_changed = ath5k_bss_info_changed,
268 };
269
270 /*
271 * Prototypes - Internal functions
272 */
273 /* Attach detach */
274 static int ath5k_attach(struct pci_dev *pdev,
275 struct ieee80211_hw *hw);
276 static void ath5k_detach(struct pci_dev *pdev,
277 struct ieee80211_hw *hw);
278 /* Channel/mode setup */
279 static inline short ath5k_ieee2mhz(short chan);
280 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
281 struct ieee80211_channel *channels,
282 unsigned int mode,
283 unsigned int max);
284 static int ath5k_setup_bands(struct ieee80211_hw *hw);
285 static int ath5k_chan_set(struct ath5k_softc *sc,
286 struct ieee80211_channel *chan);
287 static void ath5k_setcurmode(struct ath5k_softc *sc,
288 unsigned int mode);
289 static void ath5k_mode_setup(struct ath5k_softc *sc);
290
291 /* Descriptor setup */
292 static int ath5k_desc_alloc(struct ath5k_softc *sc,
293 struct pci_dev *pdev);
294 static void ath5k_desc_free(struct ath5k_softc *sc,
295 struct pci_dev *pdev);
296 /* Buffers setup */
297 static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
298 struct ath5k_buf *bf);
299 static int ath5k_txbuf_setup(struct ath5k_softc *sc,
300 struct ath5k_buf *bf);
301 static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
302 struct ath5k_buf *bf)
303 {
304 BUG_ON(!bf);
305 if (!bf->skb)
306 return;
307 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
308 PCI_DMA_TODEVICE);
309 dev_kfree_skb_any(bf->skb);
310 bf->skb = NULL;
311 }
312
313 static inline void ath5k_rxbuf_free(struct ath5k_softc *sc,
314 struct ath5k_buf *bf)
315 {
316 BUG_ON(!bf);
317 if (!bf->skb)
318 return;
319 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
320 PCI_DMA_FROMDEVICE);
321 dev_kfree_skb_any(bf->skb);
322 bf->skb = NULL;
323 }
324
325
326 /* Queues setup */
327 static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
328 int qtype, int subtype);
329 static int ath5k_beaconq_setup(struct ath5k_hw *ah);
330 static int ath5k_beaconq_config(struct ath5k_softc *sc);
331 static void ath5k_txq_drainq(struct ath5k_softc *sc,
332 struct ath5k_txq *txq);
333 static void ath5k_txq_cleanup(struct ath5k_softc *sc);
334 static void ath5k_txq_release(struct ath5k_softc *sc);
335 /* Rx handling */
336 static int ath5k_rx_start(struct ath5k_softc *sc);
337 static void ath5k_rx_stop(struct ath5k_softc *sc);
338 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
339 struct ath5k_desc *ds,
340 struct sk_buff *skb,
341 struct ath5k_rx_status *rs);
342 static void ath5k_tasklet_rx(unsigned long data);
343 /* Tx handling */
344 static void ath5k_tx_processq(struct ath5k_softc *sc,
345 struct ath5k_txq *txq);
346 static void ath5k_tasklet_tx(unsigned long data);
347 /* Beacon handling */
348 static int ath5k_beacon_setup(struct ath5k_softc *sc,
349 struct ath5k_buf *bf);
350 static void ath5k_beacon_send(struct ath5k_softc *sc);
351 static void ath5k_beacon_config(struct ath5k_softc *sc);
352 static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
353 static void ath5k_tasklet_beacon(unsigned long data);
354
355 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
356 {
357 u64 tsf = ath5k_hw_get_tsf64(ah);
358
359 if ((tsf & 0x7fff) < rstamp)
360 tsf -= 0x8000;
361
362 return (tsf & ~0x7fff) | rstamp;
363 }
364
365 /* Interrupt handling */
366 static int ath5k_init(struct ath5k_softc *sc);
367 static int ath5k_stop_locked(struct ath5k_softc *sc);
368 static int ath5k_stop_hw(struct ath5k_softc *sc);
369 static irqreturn_t ath5k_intr(int irq, void *dev_id);
370 static void ath5k_tasklet_reset(unsigned long data);
371
372 static void ath5k_calibrate(unsigned long data);
373
374 /*
375 * Module init/exit functions
376 */
377 static int __init
378 init_ath5k_pci(void)
379 {
380 int ret;
381
382 ath5k_debug_init();
383
384 ret = pci_register_driver(&ath5k_pci_driver);
385 if (ret) {
386 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
387 return ret;
388 }
389
390 return 0;
391 }
392
393 static void __exit
394 exit_ath5k_pci(void)
395 {
396 pci_unregister_driver(&ath5k_pci_driver);
397
398 ath5k_debug_finish();
399 }
400
401 module_init(init_ath5k_pci);
402 module_exit(exit_ath5k_pci);
403
404
405 /********************\
406 * PCI Initialization *
407 \********************/
408
409 static const char *
410 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
411 {
412 const char *name = "xxxxx";
413 unsigned int i;
414
415 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
416 if (srev_names[i].sr_type != type)
417 continue;
418
419 if ((val & 0xf0) == srev_names[i].sr_val)
420 name = srev_names[i].sr_name;
421
422 if ((val & 0xff) == srev_names[i].sr_val) {
423 name = srev_names[i].sr_name;
424 break;
425 }
426 }
427
428 return name;
429 }
430
431 static int __devinit
432 ath5k_pci_probe(struct pci_dev *pdev,
433 const struct pci_device_id *id)
434 {
435 void __iomem *mem;
436 struct ath5k_softc *sc;
437 struct ieee80211_hw *hw;
438 int ret;
439 u8 csz;
440
441 ret = pci_enable_device(pdev);
442 if (ret) {
443 dev_err(&pdev->dev, "can't enable device\n");
444 goto err;
445 }
446
447 /* XXX 32-bit addressing only */
448 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
449 if (ret) {
450 dev_err(&pdev->dev, "32-bit DMA not available\n");
451 goto err_dis;
452 }
453
454 /*
455 * Cache line size is used to size and align various
456 * structures used to communicate with the hardware.
457 */
458 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
459 if (csz == 0) {
460 /*
461 * Linux 2.4.18 (at least) writes the cache line size
462 * register as a 16-bit wide register which is wrong.
463 * We must have this setup properly for rx buffer
464 * DMA to work so force a reasonable value here if it
465 * comes up zero.
466 */
467 csz = L1_CACHE_BYTES / sizeof(u32);
468 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
469 }
470 /*
471 * The default setting of latency timer yields poor results,
472 * set it to the value used by other systems. It may be worth
473 * tweaking this setting more.
474 */
475 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
476
477 /* Enable bus mastering */
478 pci_set_master(pdev);
479
480 /*
481 * Disable the RETRY_TIMEOUT register (0x41) to keep
482 * PCI Tx retries from interfering with C3 CPU state.
483 */
484 pci_write_config_byte(pdev, 0x41, 0);
485
486 ret = pci_request_region(pdev, 0, "ath5k");
487 if (ret) {
488 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
489 goto err_dis;
490 }
491
492 mem = pci_iomap(pdev, 0, 0);
493 if (!mem) {
494 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
495 ret = -EIO;
496 goto err_reg;
497 }
498
499 /*
500 * Allocate hw (mac80211 main struct)
501 * and hw->priv (driver private data)
502 */
503 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
504 if (hw == NULL) {
505 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
506 ret = -ENOMEM;
507 goto err_map;
508 }
509
510 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
511
512 /* Initialize driver private data */
513 SET_IEEE80211_DEV(hw, &pdev->dev);
514 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
515 IEEE80211_HW_SIGNAL_DBM |
516 IEEE80211_HW_NOISE_DBM;
517
518 hw->wiphy->interface_modes =
519 BIT(NL80211_IFTYPE_AP) |
520 BIT(NL80211_IFTYPE_STATION) |
521 BIT(NL80211_IFTYPE_ADHOC) |
522 BIT(NL80211_IFTYPE_MESH_POINT);
523
524 hw->extra_tx_headroom = 2;
525 hw->channel_change_time = 5000;
526 sc = hw->priv;
527 sc->hw = hw;
528 sc->pdev = pdev;
529
530 ath5k_debug_init_device(sc);
531
532 /*
533 * Mark the device as detached to avoid processing
534 * interrupts until setup is complete.
535 */
536 __set_bit(ATH_STAT_INVALID, sc->status);
537
538 sc->iobase = mem; /* So we can unmap it on detach */
539 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
540 sc->opmode = NL80211_IFTYPE_STATION;
541 sc->bintval = 1000;
542 mutex_init(&sc->lock);
543 spin_lock_init(&sc->rxbuflock);
544 spin_lock_init(&sc->txbuflock);
545 spin_lock_init(&sc->block);
546
547 /* Set private data */
548 pci_set_drvdata(pdev, hw);
549
550 /* Setup interrupt handler */
551 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
552 if (ret) {
553 ATH5K_ERR(sc, "request_irq failed\n");
554 goto err_free;
555 }
556
557 /* Initialize device */
558 sc->ah = ath5k_hw_attach(sc, id->driver_data);
559 if (IS_ERR(sc->ah)) {
560 ret = PTR_ERR(sc->ah);
561 goto err_irq;
562 }
563
564 /* set up multi-rate retry capabilities */
565 if (sc->ah->ah_version == AR5K_AR5212) {
566 hw->max_rates = 4;
567 hw->max_rate_tries = 11;
568 }
569
570 /* Finish private driver data initialization */
571 ret = ath5k_attach(pdev, hw);
572 if (ret)
573 goto err_ah;
574
575 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
576 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
577 sc->ah->ah_mac_srev,
578 sc->ah->ah_phy_revision);
579
580 if (!sc->ah->ah_single_chip) {
581 /* Single chip radio (!RF5111) */
582 if (sc->ah->ah_radio_5ghz_revision &&
583 !sc->ah->ah_radio_2ghz_revision) {
584 /* No 5GHz support -> report 2GHz radio */
585 if (!test_bit(AR5K_MODE_11A,
586 sc->ah->ah_capabilities.cap_mode)) {
587 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
588 ath5k_chip_name(AR5K_VERSION_RAD,
589 sc->ah->ah_radio_5ghz_revision),
590 sc->ah->ah_radio_5ghz_revision);
591 /* No 2GHz support (5110 and some
592 * 5Ghz only cards) -> report 5Ghz radio */
593 } else if (!test_bit(AR5K_MODE_11B,
594 sc->ah->ah_capabilities.cap_mode)) {
595 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
596 ath5k_chip_name(AR5K_VERSION_RAD,
597 sc->ah->ah_radio_5ghz_revision),
598 sc->ah->ah_radio_5ghz_revision);
599 /* Multiband radio */
600 } else {
601 ATH5K_INFO(sc, "RF%s multiband radio found"
602 " (0x%x)\n",
603 ath5k_chip_name(AR5K_VERSION_RAD,
604 sc->ah->ah_radio_5ghz_revision),
605 sc->ah->ah_radio_5ghz_revision);
606 }
607 }
608 /* Multi chip radio (RF5111 - RF2111) ->
609 * report both 2GHz/5GHz radios */
610 else if (sc->ah->ah_radio_5ghz_revision &&
611 sc->ah->ah_radio_2ghz_revision){
612 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
613 ath5k_chip_name(AR5K_VERSION_RAD,
614 sc->ah->ah_radio_5ghz_revision),
615 sc->ah->ah_radio_5ghz_revision);
616 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
617 ath5k_chip_name(AR5K_VERSION_RAD,
618 sc->ah->ah_radio_2ghz_revision),
619 sc->ah->ah_radio_2ghz_revision);
620 }
621 }
622
623
624 /* ready to process interrupts */
625 __clear_bit(ATH_STAT_INVALID, sc->status);
626
627 return 0;
628 err_ah:
629 ath5k_hw_detach(sc->ah);
630 err_irq:
631 free_irq(pdev->irq, sc);
632 err_free:
633 ieee80211_free_hw(hw);
634 err_map:
635 pci_iounmap(pdev, mem);
636 err_reg:
637 pci_release_region(pdev, 0);
638 err_dis:
639 pci_disable_device(pdev);
640 err:
641 return ret;
642 }
643
644 static void __devexit
645 ath5k_pci_remove(struct pci_dev *pdev)
646 {
647 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
648 struct ath5k_softc *sc = hw->priv;
649
650 ath5k_debug_finish_device(sc);
651 ath5k_detach(pdev, hw);
652 ath5k_hw_detach(sc->ah);
653 free_irq(pdev->irq, sc);
654 pci_iounmap(pdev, sc->iobase);
655 pci_release_region(pdev, 0);
656 pci_disable_device(pdev);
657 ieee80211_free_hw(hw);
658 }
659
660 #ifdef CONFIG_PM
661 static int
662 ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
663 {
664 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
665 struct ath5k_softc *sc = hw->priv;
666
667 ath5k_led_off(sc);
668
669 pci_save_state(pdev);
670 pci_disable_device(pdev);
671 pci_set_power_state(pdev, PCI_D3hot);
672
673 return 0;
674 }
675
676 static int
677 ath5k_pci_resume(struct pci_dev *pdev)
678 {
679 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
680 struct ath5k_softc *sc = hw->priv;
681 int err;
682
683 pci_restore_state(pdev);
684
685 err = pci_enable_device(pdev);
686 if (err)
687 return err;
688
689 /*
690 * Suspend/Resume resets the PCI configuration space, so we have to
691 * re-disable the RETRY_TIMEOUT register (0x41) to keep
692 * PCI Tx retries from interfering with C3 CPU state
693 */
694 pci_write_config_byte(pdev, 0x41, 0);
695
696 ath5k_led_enable(sc);
697 return 0;
698 }
699 #endif /* CONFIG_PM */
700
701
702 /***********************\
703 * Driver Initialization *
704 \***********************/
705
706 static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
707 {
708 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
709 struct ath5k_softc *sc = hw->priv;
710 struct ath_regulatory *reg = &sc->ah->ah_regulatory;
711
712 return ath_reg_notifier_apply(wiphy, request, reg);
713 }
714
715 static int
716 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
717 {
718 struct ath5k_softc *sc = hw->priv;
719 struct ath5k_hw *ah = sc->ah;
720 u8 mac[ETH_ALEN] = {};
721 int ret;
722
723 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
724
725 /*
726 * Check if the MAC has multi-rate retry support.
727 * We do this by trying to setup a fake extended
728 * descriptor. MAC's that don't have support will
729 * return false w/o doing anything. MAC's that do
730 * support it will return true w/o doing anything.
731 */
732 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
733 if (ret < 0)
734 goto err;
735 if (ret > 0)
736 __set_bit(ATH_STAT_MRRETRY, sc->status);
737
738 /*
739 * Collect the channel list. The 802.11 layer
740 * is resposible for filtering this list based
741 * on settings like the phy mode and regulatory
742 * domain restrictions.
743 */
744 ret = ath5k_setup_bands(hw);
745 if (ret) {
746 ATH5K_ERR(sc, "can't get channels\n");
747 goto err;
748 }
749
750 /* NB: setup here so ath5k_rate_update is happy */
751 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
752 ath5k_setcurmode(sc, AR5K_MODE_11A);
753 else
754 ath5k_setcurmode(sc, AR5K_MODE_11B);
755
756 /*
757 * Allocate tx+rx descriptors and populate the lists.
758 */
759 ret = ath5k_desc_alloc(sc, pdev);
760 if (ret) {
761 ATH5K_ERR(sc, "can't allocate descriptors\n");
762 goto err;
763 }
764
765 /*
766 * Allocate hardware transmit queues: one queue for
767 * beacon frames and one data queue for each QoS
768 * priority. Note that hw functions handle reseting
769 * these queues at the needed time.
770 */
771 ret = ath5k_beaconq_setup(ah);
772 if (ret < 0) {
773 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
774 goto err_desc;
775 }
776 sc->bhalq = ret;
777
778 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
779 if (IS_ERR(sc->txq)) {
780 ATH5K_ERR(sc, "can't setup xmit queue\n");
781 ret = PTR_ERR(sc->txq);
782 goto err_bhal;
783 }
784
785 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
786 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
787 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
788 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
789 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
790
791 ret = ath5k_eeprom_read_mac(ah, mac);
792 if (ret) {
793 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
794 sc->pdev->device);
795 goto err_queues;
796 }
797
798 SET_IEEE80211_PERM_ADDR(hw, mac);
799 /* All MAC address bits matter for ACKs */
800 memset(sc->bssidmask, 0xff, ETH_ALEN);
801 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
802
803 ah->ah_regulatory.current_rd =
804 ah->ah_capabilities.cap_eeprom.ee_regdomain;
805 ret = ath_regd_init(&ah->ah_regulatory, hw->wiphy, ath5k_reg_notifier);
806 if (ret) {
807 ATH5K_ERR(sc, "can't initialize regulatory system\n");
808 goto err_queues;
809 }
810
811 ret = ieee80211_register_hw(hw);
812 if (ret) {
813 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
814 goto err_queues;
815 }
816
817 if (!ath_is_world_regd(&sc->ah->ah_regulatory))
818 regulatory_hint(hw->wiphy, sc->ah->ah_regulatory.alpha2);
819
820 ath5k_init_leds(sc);
821
822 return 0;
823 err_queues:
824 ath5k_txq_release(sc);
825 err_bhal:
826 ath5k_hw_release_tx_queue(ah, sc->bhalq);
827 err_desc:
828 ath5k_desc_free(sc, pdev);
829 err:
830 return ret;
831 }
832
833 static void
834 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
835 {
836 struct ath5k_softc *sc = hw->priv;
837
838 /*
839 * NB: the order of these is important:
840 * o call the 802.11 layer before detaching ath5k_hw to
841 * insure callbacks into the driver to delete global
842 * key cache entries can be handled
843 * o reclaim the tx queue data structures after calling
844 * the 802.11 layer as we'll get called back to reclaim
845 * node state and potentially want to use them
846 * o to cleanup the tx queues the hal is called, so detach
847 * it last
848 * XXX: ??? detach ath5k_hw ???
849 * Other than that, it's straightforward...
850 */
851 ieee80211_unregister_hw(hw);
852 ath5k_desc_free(sc, pdev);
853 ath5k_txq_release(sc);
854 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
855 ath5k_unregister_leds(sc);
856
857 /*
858 * NB: can't reclaim these until after ieee80211_ifdetach
859 * returns because we'll get called back to reclaim node
860 * state and potentially want to use them.
861 */
862 }
863
864
865
866
867 /********************\
868 * Channel/mode setup *
869 \********************/
870
871 /*
872 * Convert IEEE channel number to MHz frequency.
873 */
874 static inline short
875 ath5k_ieee2mhz(short chan)
876 {
877 if (chan <= 14 || chan >= 27)
878 return ieee80211chan2mhz(chan);
879 else
880 return 2212 + chan * 20;
881 }
882
883 /*
884 * Returns true for the channel numbers used without all_channels modparam.
885 */
886 static bool ath5k_is_standard_channel(short chan)
887 {
888 return ((chan <= 14) ||
889 /* UNII 1,2 */
890 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
891 /* midband */
892 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
893 /* UNII-3 */
894 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
895 }
896
897 static unsigned int
898 ath5k_copy_channels(struct ath5k_hw *ah,
899 struct ieee80211_channel *channels,
900 unsigned int mode,
901 unsigned int max)
902 {
903 unsigned int i, count, size, chfreq, freq, ch;
904
905 if (!test_bit(mode, ah->ah_modes))
906 return 0;
907
908 switch (mode) {
909 case AR5K_MODE_11A:
910 case AR5K_MODE_11A_TURBO:
911 /* 1..220, but 2GHz frequencies are filtered by check_channel */
912 size = 220 ;
913 chfreq = CHANNEL_5GHZ;
914 break;
915 case AR5K_MODE_11B:
916 case AR5K_MODE_11G:
917 case AR5K_MODE_11G_TURBO:
918 size = 26;
919 chfreq = CHANNEL_2GHZ;
920 break;
921 default:
922 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
923 return 0;
924 }
925
926 for (i = 0, count = 0; i < size && max > 0; i++) {
927 ch = i + 1 ;
928 freq = ath5k_ieee2mhz(ch);
929
930 /* Check if channel is supported by the chipset */
931 if (!ath5k_channel_ok(ah, freq, chfreq))
932 continue;
933
934 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
935 continue;
936
937 /* Write channel info and increment counter */
938 channels[count].center_freq = freq;
939 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
940 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
941 switch (mode) {
942 case AR5K_MODE_11A:
943 case AR5K_MODE_11G:
944 channels[count].hw_value = chfreq | CHANNEL_OFDM;
945 break;
946 case AR5K_MODE_11A_TURBO:
947 case AR5K_MODE_11G_TURBO:
948 channels[count].hw_value = chfreq |
949 CHANNEL_OFDM | CHANNEL_TURBO;
950 break;
951 case AR5K_MODE_11B:
952 channels[count].hw_value = CHANNEL_B;
953 }
954
955 count++;
956 max--;
957 }
958
959 return count;
960 }
961
962 static void
963 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
964 {
965 u8 i;
966
967 for (i = 0; i < AR5K_MAX_RATES; i++)
968 sc->rate_idx[b->band][i] = -1;
969
970 for (i = 0; i < b->n_bitrates; i++) {
971 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
972 if (b->bitrates[i].hw_value_short)
973 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
974 }
975 }
976
977 static int
978 ath5k_setup_bands(struct ieee80211_hw *hw)
979 {
980 struct ath5k_softc *sc = hw->priv;
981 struct ath5k_hw *ah = sc->ah;
982 struct ieee80211_supported_band *sband;
983 int max_c, count_c = 0;
984 int i;
985
986 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
987 max_c = ARRAY_SIZE(sc->channels);
988
989 /* 2GHz band */
990 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
991 sband->band = IEEE80211_BAND_2GHZ;
992 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
993
994 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
995 /* G mode */
996 memcpy(sband->bitrates, &ath5k_rates[0],
997 sizeof(struct ieee80211_rate) * 12);
998 sband->n_bitrates = 12;
999
1000 sband->channels = sc->channels;
1001 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1002 AR5K_MODE_11G, max_c);
1003
1004 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1005 count_c = sband->n_channels;
1006 max_c -= count_c;
1007 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
1008 /* B mode */
1009 memcpy(sband->bitrates, &ath5k_rates[0],
1010 sizeof(struct ieee80211_rate) * 4);
1011 sband->n_bitrates = 4;
1012
1013 /* 5211 only supports B rates and uses 4bit rate codes
1014 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
1015 * fix them up here:
1016 */
1017 if (ah->ah_version == AR5K_AR5211) {
1018 for (i = 0; i < 4; i++) {
1019 sband->bitrates[i].hw_value =
1020 sband->bitrates[i].hw_value & 0xF;
1021 sband->bitrates[i].hw_value_short =
1022 sband->bitrates[i].hw_value_short & 0xF;
1023 }
1024 }
1025
1026 sband->channels = sc->channels;
1027 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1028 AR5K_MODE_11B, max_c);
1029
1030 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1031 count_c = sband->n_channels;
1032 max_c -= count_c;
1033 }
1034 ath5k_setup_rate_idx(sc, sband);
1035
1036 /* 5GHz band, A mode */
1037 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
1038 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1039 sband->band = IEEE80211_BAND_5GHZ;
1040 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
1041
1042 memcpy(sband->bitrates, &ath5k_rates[4],
1043 sizeof(struct ieee80211_rate) * 8);
1044 sband->n_bitrates = 8;
1045
1046 sband->channels = &sc->channels[count_c];
1047 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1048 AR5K_MODE_11A, max_c);
1049
1050 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1051 }
1052 ath5k_setup_rate_idx(sc, sband);
1053
1054 ath5k_debug_dump_bands(sc);
1055
1056 return 0;
1057 }
1058
1059 /*
1060 * Set/change channels. If the channel is really being changed,
1061 * it's done by reseting the chip. To accomplish this we must
1062 * first cleanup any pending DMA, then restart stuff after a la
1063 * ath5k_init.
1064 *
1065 * Called with sc->lock.
1066 */
1067 static int
1068 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1069 {
1070 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1071 sc->curchan->center_freq, chan->center_freq);
1072
1073 if (chan->center_freq != sc->curchan->center_freq ||
1074 chan->hw_value != sc->curchan->hw_value) {
1075
1076 /*
1077 * To switch channels clear any pending DMA operations;
1078 * wait long enough for the RX fifo to drain, reset the
1079 * hardware at the new frequency, and then re-enable
1080 * the relevant bits of the h/w.
1081 */
1082 return ath5k_reset(sc, chan);
1083 }
1084
1085 return 0;
1086 }
1087
1088 static void
1089 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1090 {
1091 sc->curmode = mode;
1092
1093 if (mode == AR5K_MODE_11A) {
1094 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1095 } else {
1096 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1097 }
1098 }
1099
1100 static void
1101 ath5k_mode_setup(struct ath5k_softc *sc)
1102 {
1103 struct ath5k_hw *ah = sc->ah;
1104 u32 rfilt;
1105
1106 /* configure rx filter */
1107 rfilt = sc->filter_flags;
1108 ath5k_hw_set_rx_filter(ah, rfilt);
1109
1110 if (ath5k_hw_hasbssidmask(ah))
1111 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1112
1113 /* configure operational mode */
1114 ath5k_hw_set_opmode(ah);
1115
1116 ath5k_hw_set_mcast_filter(ah, 0, 0);
1117 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1118 }
1119
1120 static inline int
1121 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1122 {
1123 int rix;
1124
1125 /* return base rate on errors */
1126 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
1127 "hw_rix out of bounds: %x\n", hw_rix))
1128 return 0;
1129
1130 rix = sc->rate_idx[sc->curband->band][hw_rix];
1131 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
1132 rix = 0;
1133
1134 return rix;
1135 }
1136
1137 /***************\
1138 * Buffers setup *
1139 \***************/
1140
1141 static
1142 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
1143 {
1144 struct sk_buff *skb;
1145 unsigned int off;
1146
1147 /*
1148 * Allocate buffer with headroom_needed space for the
1149 * fake physical layer header at the start.
1150 */
1151 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1152
1153 if (!skb) {
1154 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1155 sc->rxbufsize + sc->cachelsz - 1);
1156 return NULL;
1157 }
1158 /*
1159 * Cache-line-align. This is important (for the
1160 * 5210 at least) as not doing so causes bogus data
1161 * in rx'd frames.
1162 */
1163 off = ((unsigned long)skb->data) % sc->cachelsz;
1164 if (off != 0)
1165 skb_reserve(skb, sc->cachelsz - off);
1166
1167 *skb_addr = pci_map_single(sc->pdev,
1168 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1169 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
1170 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1171 dev_kfree_skb(skb);
1172 return NULL;
1173 }
1174 return skb;
1175 }
1176
1177 static int
1178 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1179 {
1180 struct ath5k_hw *ah = sc->ah;
1181 struct sk_buff *skb = bf->skb;
1182 struct ath5k_desc *ds;
1183
1184 if (!skb) {
1185 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
1186 if (!skb)
1187 return -ENOMEM;
1188 bf->skb = skb;
1189 }
1190
1191 /*
1192 * Setup descriptors. For receive we always terminate
1193 * the descriptor list with a self-linked entry so we'll
1194 * not get overrun under high load (as can happen with a
1195 * 5212 when ANI processing enables PHY error frames).
1196 *
1197 * To insure the last descriptor is self-linked we create
1198 * each descriptor as self-linked and add it to the end. As
1199 * each additional descriptor is added the previous self-linked
1200 * entry is ``fixed'' naturally. This should be safe even
1201 * if DMA is happening. When processing RX interrupts we
1202 * never remove/process the last, self-linked, entry on the
1203 * descriptor list. This insures the hardware always has
1204 * someplace to write a new frame.
1205 */
1206 ds = bf->desc;
1207 ds->ds_link = bf->daddr; /* link to self */
1208 ds->ds_data = bf->skbaddr;
1209 ah->ah_setup_rx_desc(ah, ds,
1210 skb_tailroom(skb), /* buffer size */
1211 0);
1212
1213 if (sc->rxlink != NULL)
1214 *sc->rxlink = bf->daddr;
1215 sc->rxlink = &ds->ds_link;
1216 return 0;
1217 }
1218
1219 static int
1220 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1221 {
1222 struct ath5k_hw *ah = sc->ah;
1223 struct ath5k_txq *txq = sc->txq;
1224 struct ath5k_desc *ds = bf->desc;
1225 struct sk_buff *skb = bf->skb;
1226 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1227 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1228 struct ieee80211_rate *rate;
1229 unsigned int mrr_rate[3], mrr_tries[3];
1230 int i, ret;
1231 u16 hw_rate;
1232 u16 cts_rate = 0;
1233 u16 duration = 0;
1234 u8 rc_flags;
1235
1236 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1237
1238 /* XXX endianness */
1239 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1240 PCI_DMA_TODEVICE);
1241
1242 rate = ieee80211_get_tx_rate(sc->hw, info);
1243
1244 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
1245 flags |= AR5K_TXDESC_NOACK;
1246
1247 rc_flags = info->control.rates[0].flags;
1248 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
1249 rate->hw_value_short : rate->hw_value;
1250
1251 pktlen = skb->len;
1252
1253 /* FIXME: If we are in g mode and rate is a CCK rate
1254 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1255 * from tx power (value is in dB units already) */
1256 if (info->control.hw_key) {
1257 keyidx = info->control.hw_key->hw_key_idx;
1258 pktlen += info->control.hw_key->icv_len;
1259 }
1260 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1261 flags |= AR5K_TXDESC_RTSENA;
1262 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1263 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
1264 sc->vif, pktlen, info));
1265 }
1266 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1267 flags |= AR5K_TXDESC_CTSENA;
1268 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1269 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
1270 sc->vif, pktlen, info));
1271 }
1272 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1273 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
1274 (sc->power_level * 2),
1275 hw_rate,
1276 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
1277 cts_rate, duration);
1278 if (ret)
1279 goto err_unmap;
1280
1281 memset(mrr_rate, 0, sizeof(mrr_rate));
1282 memset(mrr_tries, 0, sizeof(mrr_tries));
1283 for (i = 0; i < 3; i++) {
1284 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1285 if (!rate)
1286 break;
1287
1288 mrr_rate[i] = rate->hw_value;
1289 mrr_tries[i] = info->control.rates[i + 1].count;
1290 }
1291
1292 ah->ah_setup_mrr_tx_desc(ah, ds,
1293 mrr_rate[0], mrr_tries[0],
1294 mrr_rate[1], mrr_tries[1],
1295 mrr_rate[2], mrr_tries[2]);
1296
1297 ds->ds_link = 0;
1298 ds->ds_data = bf->skbaddr;
1299
1300 spin_lock_bh(&txq->lock);
1301 list_add_tail(&bf->list, &txq->q);
1302 sc->tx_stats[txq->qnum].len++;
1303 if (txq->link == NULL) /* is this first packet? */
1304 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
1305 else /* no, so only link it */
1306 *txq->link = bf->daddr;
1307
1308 txq->link = &ds->ds_link;
1309 ath5k_hw_start_tx_dma(ah, txq->qnum);
1310 mmiowb();
1311 spin_unlock_bh(&txq->lock);
1312
1313 return 0;
1314 err_unmap:
1315 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1316 return ret;
1317 }
1318
1319 /*******************\
1320 * Descriptors setup *
1321 \*******************/
1322
1323 static int
1324 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1325 {
1326 struct ath5k_desc *ds;
1327 struct ath5k_buf *bf;
1328 dma_addr_t da;
1329 unsigned int i;
1330 int ret;
1331
1332 /* allocate descriptors */
1333 sc->desc_len = sizeof(struct ath5k_desc) *
1334 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1335 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1336 if (sc->desc == NULL) {
1337 ATH5K_ERR(sc, "can't allocate descriptors\n");
1338 ret = -ENOMEM;
1339 goto err;
1340 }
1341 ds = sc->desc;
1342 da = sc->desc_daddr;
1343 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1344 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1345
1346 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1347 sizeof(struct ath5k_buf), GFP_KERNEL);
1348 if (bf == NULL) {
1349 ATH5K_ERR(sc, "can't allocate bufptr\n");
1350 ret = -ENOMEM;
1351 goto err_free;
1352 }
1353 sc->bufptr = bf;
1354
1355 INIT_LIST_HEAD(&sc->rxbuf);
1356 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1357 bf->desc = ds;
1358 bf->daddr = da;
1359 list_add_tail(&bf->list, &sc->rxbuf);
1360 }
1361
1362 INIT_LIST_HEAD(&sc->txbuf);
1363 sc->txbuf_len = ATH_TXBUF;
1364 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1365 da += sizeof(*ds)) {
1366 bf->desc = ds;
1367 bf->daddr = da;
1368 list_add_tail(&bf->list, &sc->txbuf);
1369 }
1370
1371 /* beacon buffer */
1372 bf->desc = ds;
1373 bf->daddr = da;
1374 sc->bbuf = bf;
1375
1376 return 0;
1377 err_free:
1378 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1379 err:
1380 sc->desc = NULL;
1381 return ret;
1382 }
1383
1384 static void
1385 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1386 {
1387 struct ath5k_buf *bf;
1388
1389 ath5k_txbuf_free(sc, sc->bbuf);
1390 list_for_each_entry(bf, &sc->txbuf, list)
1391 ath5k_txbuf_free(sc, bf);
1392 list_for_each_entry(bf, &sc->rxbuf, list)
1393 ath5k_rxbuf_free(sc, bf);
1394
1395 /* Free memory associated with all descriptors */
1396 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1397
1398 kfree(sc->bufptr);
1399 sc->bufptr = NULL;
1400 }
1401
1402
1403
1404
1405
1406 /**************\
1407 * Queues setup *
1408 \**************/
1409
1410 static struct ath5k_txq *
1411 ath5k_txq_setup(struct ath5k_softc *sc,
1412 int qtype, int subtype)
1413 {
1414 struct ath5k_hw *ah = sc->ah;
1415 struct ath5k_txq *txq;
1416 struct ath5k_txq_info qi = {
1417 .tqi_subtype = subtype,
1418 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1419 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1420 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1421 };
1422 int qnum;
1423
1424 /*
1425 * Enable interrupts only for EOL and DESC conditions.
1426 * We mark tx descriptors to receive a DESC interrupt
1427 * when a tx queue gets deep; otherwise waiting for the
1428 * EOL to reap descriptors. Note that this is done to
1429 * reduce interrupt load and this only defers reaping
1430 * descriptors, never transmitting frames. Aside from
1431 * reducing interrupts this also permits more concurrency.
1432 * The only potential downside is if the tx queue backs
1433 * up in which case the top half of the kernel may backup
1434 * due to a lack of tx descriptors.
1435 */
1436 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1437 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1438 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1439 if (qnum < 0) {
1440 /*
1441 * NB: don't print a message, this happens
1442 * normally on parts with too few tx queues
1443 */
1444 return ERR_PTR(qnum);
1445 }
1446 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1447 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1448 qnum, ARRAY_SIZE(sc->txqs));
1449 ath5k_hw_release_tx_queue(ah, qnum);
1450 return ERR_PTR(-EINVAL);
1451 }
1452 txq = &sc->txqs[qnum];
1453 if (!txq->setup) {
1454 txq->qnum = qnum;
1455 txq->link = NULL;
1456 INIT_LIST_HEAD(&txq->q);
1457 spin_lock_init(&txq->lock);
1458 txq->setup = true;
1459 }
1460 return &sc->txqs[qnum];
1461 }
1462
1463 static int
1464 ath5k_beaconq_setup(struct ath5k_hw *ah)
1465 {
1466 struct ath5k_txq_info qi = {
1467 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1468 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1469 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1470 /* NB: for dynamic turbo, don't enable any other interrupts */
1471 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1472 };
1473
1474 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1475 }
1476
1477 static int
1478 ath5k_beaconq_config(struct ath5k_softc *sc)
1479 {
1480 struct ath5k_hw *ah = sc->ah;
1481 struct ath5k_txq_info qi;
1482 int ret;
1483
1484 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1485 if (ret)
1486 return ret;
1487 if (sc->opmode == NL80211_IFTYPE_AP ||
1488 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1489 /*
1490 * Always burst out beacon and CAB traffic
1491 * (aifs = cwmin = cwmax = 0)
1492 */
1493 qi.tqi_aifs = 0;
1494 qi.tqi_cw_min = 0;
1495 qi.tqi_cw_max = 0;
1496 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1497 /*
1498 * Adhoc mode; backoff between 0 and (2 * cw_min).
1499 */
1500 qi.tqi_aifs = 0;
1501 qi.tqi_cw_min = 0;
1502 qi.tqi_cw_max = 2 * ah->ah_cw_min;
1503 }
1504
1505 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1506 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1507 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1508
1509 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1510 if (ret) {
1511 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1512 "hardware queue!\n", __func__);
1513 return ret;
1514 }
1515
1516 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1517 }
1518
1519 static void
1520 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1521 {
1522 struct ath5k_buf *bf, *bf0;
1523
1524 /*
1525 * NB: this assumes output has been stopped and
1526 * we do not need to block ath5k_tx_tasklet
1527 */
1528 spin_lock_bh(&txq->lock);
1529 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1530 ath5k_debug_printtxbuf(sc, bf);
1531
1532 ath5k_txbuf_free(sc, bf);
1533
1534 spin_lock_bh(&sc->txbuflock);
1535 sc->tx_stats[txq->qnum].len--;
1536 list_move_tail(&bf->list, &sc->txbuf);
1537 sc->txbuf_len++;
1538 spin_unlock_bh(&sc->txbuflock);
1539 }
1540 txq->link = NULL;
1541 spin_unlock_bh(&txq->lock);
1542 }
1543
1544 /*
1545 * Drain the transmit queues and reclaim resources.
1546 */
1547 static void
1548 ath5k_txq_cleanup(struct ath5k_softc *sc)
1549 {
1550 struct ath5k_hw *ah = sc->ah;
1551 unsigned int i;
1552
1553 /* XXX return value */
1554 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1555 /* don't touch the hardware if marked invalid */
1556 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1557 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1558 ath5k_hw_get_txdp(ah, sc->bhalq));
1559 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1560 if (sc->txqs[i].setup) {
1561 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1562 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1563 "link %p\n",
1564 sc->txqs[i].qnum,
1565 ath5k_hw_get_txdp(ah,
1566 sc->txqs[i].qnum),
1567 sc->txqs[i].link);
1568 }
1569 }
1570 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
1571
1572 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1573 if (sc->txqs[i].setup)
1574 ath5k_txq_drainq(sc, &sc->txqs[i]);
1575 }
1576
1577 static void
1578 ath5k_txq_release(struct ath5k_softc *sc)
1579 {
1580 struct ath5k_txq *txq = sc->txqs;
1581 unsigned int i;
1582
1583 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1584 if (txq->setup) {
1585 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1586 txq->setup = false;
1587 }
1588 }
1589
1590
1591
1592
1593 /*************\
1594 * RX Handling *
1595 \*************/
1596
1597 /*
1598 * Enable the receive h/w following a reset.
1599 */
1600 static int
1601 ath5k_rx_start(struct ath5k_softc *sc)
1602 {
1603 struct ath5k_hw *ah = sc->ah;
1604 struct ath5k_buf *bf;
1605 int ret;
1606
1607 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1608
1609 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1610 sc->cachelsz, sc->rxbufsize);
1611
1612 spin_lock_bh(&sc->rxbuflock);
1613 sc->rxlink = NULL;
1614 list_for_each_entry(bf, &sc->rxbuf, list) {
1615 ret = ath5k_rxbuf_setup(sc, bf);
1616 if (ret != 0) {
1617 spin_unlock_bh(&sc->rxbuflock);
1618 goto err;
1619 }
1620 }
1621 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1622 ath5k_hw_set_rxdp(ah, bf->daddr);
1623 spin_unlock_bh(&sc->rxbuflock);
1624
1625 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
1626 ath5k_mode_setup(sc); /* set filters, etc. */
1627 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1628
1629 return 0;
1630 err:
1631 return ret;
1632 }
1633
1634 /*
1635 * Disable the receive h/w in preparation for a reset.
1636 */
1637 static void
1638 ath5k_rx_stop(struct ath5k_softc *sc)
1639 {
1640 struct ath5k_hw *ah = sc->ah;
1641
1642 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
1643 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1644 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1645
1646 ath5k_debug_printrxbuffs(sc, ah);
1647
1648 sc->rxlink = NULL; /* just in case */
1649 }
1650
1651 static unsigned int
1652 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1653 struct sk_buff *skb, struct ath5k_rx_status *rs)
1654 {
1655 struct ieee80211_hdr *hdr = (void *)skb->data;
1656 unsigned int keyix, hlen;
1657
1658 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1659 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1660 return RX_FLAG_DECRYPTED;
1661
1662 /* Apparently when a default key is used to decrypt the packet
1663 the hw does not set the index used to decrypt. In such cases
1664 get the index from the packet. */
1665 hlen = ieee80211_hdrlen(hdr->frame_control);
1666 if (ieee80211_has_protected(hdr->frame_control) &&
1667 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1668 skb->len >= hlen + 4) {
1669 keyix = skb->data[hlen + 3] >> 6;
1670
1671 if (test_bit(keyix, sc->keymap))
1672 return RX_FLAG_DECRYPTED;
1673 }
1674
1675 return 0;
1676 }
1677
1678
1679 static void
1680 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1681 struct ieee80211_rx_status *rxs)
1682 {
1683 u64 tsf, bc_tstamp;
1684 u32 hw_tu;
1685 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1686
1687 if (ieee80211_is_beacon(mgmt->frame_control) &&
1688 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1689 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1690 /*
1691 * Received an IBSS beacon with the same BSSID. Hardware *must*
1692 * have updated the local TSF. We have to work around various
1693 * hardware bugs, though...
1694 */
1695 tsf = ath5k_hw_get_tsf64(sc->ah);
1696 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1697 hw_tu = TSF_TO_TU(tsf);
1698
1699 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1700 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1701 (unsigned long long)bc_tstamp,
1702 (unsigned long long)rxs->mactime,
1703 (unsigned long long)(rxs->mactime - bc_tstamp),
1704 (unsigned long long)tsf);
1705
1706 /*
1707 * Sometimes the HW will give us a wrong tstamp in the rx
1708 * status, causing the timestamp extension to go wrong.
1709 * (This seems to happen especially with beacon frames bigger
1710 * than 78 byte (incl. FCS))
1711 * But we know that the receive timestamp must be later than the
1712 * timestamp of the beacon since HW must have synced to that.
1713 *
1714 * NOTE: here we assume mactime to be after the frame was
1715 * received, not like mac80211 which defines it at the start.
1716 */
1717 if (bc_tstamp > rxs->mactime) {
1718 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1719 "fixing mactime from %llx to %llx\n",
1720 (unsigned long long)rxs->mactime,
1721 (unsigned long long)tsf);
1722 rxs->mactime = tsf;
1723 }
1724
1725 /*
1726 * Local TSF might have moved higher than our beacon timers,
1727 * in that case we have to update them to continue sending
1728 * beacons. This also takes care of synchronizing beacon sending
1729 * times with other stations.
1730 */
1731 if (hw_tu >= sc->nexttbtt)
1732 ath5k_beacon_update_timers(sc, bc_tstamp);
1733 }
1734 }
1735
1736 static void
1737 ath5k_tasklet_rx(unsigned long data)
1738 {
1739 struct ieee80211_rx_status rxs = {};
1740 struct ath5k_rx_status rs = {};
1741 struct sk_buff *skb, *next_skb;
1742 dma_addr_t next_skb_addr;
1743 struct ath5k_softc *sc = (void *)data;
1744 struct ath5k_buf *bf;
1745 struct ath5k_desc *ds;
1746 int ret;
1747 int hdrlen;
1748 int padsize;
1749
1750 spin_lock(&sc->rxbuflock);
1751 if (list_empty(&sc->rxbuf)) {
1752 ATH5K_WARN(sc, "empty rx buf pool\n");
1753 goto unlock;
1754 }
1755 do {
1756 rxs.flag = 0;
1757
1758 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1759 BUG_ON(bf->skb == NULL);
1760 skb = bf->skb;
1761 ds = bf->desc;
1762
1763 /* bail if HW is still using self-linked descriptor */
1764 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1765 break;
1766
1767 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1768 if (unlikely(ret == -EINPROGRESS))
1769 break;
1770 else if (unlikely(ret)) {
1771 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1772 spin_unlock(&sc->rxbuflock);
1773 return;
1774 }
1775
1776 if (unlikely(rs.rs_more)) {
1777 ATH5K_WARN(sc, "unsupported jumbo\n");
1778 goto next;
1779 }
1780
1781 if (unlikely(rs.rs_status)) {
1782 if (rs.rs_status & AR5K_RXERR_PHY)
1783 goto next;
1784 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
1785 /*
1786 * Decrypt error. If the error occurred
1787 * because there was no hardware key, then
1788 * let the frame through so the upper layers
1789 * can process it. This is necessary for 5210
1790 * parts which have no way to setup a ``clear''
1791 * key cache entry.
1792 *
1793 * XXX do key cache faulting
1794 */
1795 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1796 !(rs.rs_status & AR5K_RXERR_CRC))
1797 goto accept;
1798 }
1799 if (rs.rs_status & AR5K_RXERR_MIC) {
1800 rxs.flag |= RX_FLAG_MMIC_ERROR;
1801 goto accept;
1802 }
1803
1804 /* let crypto-error packets fall through in MNTR */
1805 if ((rs.rs_status &
1806 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1807 sc->opmode != NL80211_IFTYPE_MONITOR)
1808 goto next;
1809 }
1810 accept:
1811 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1812
1813 /*
1814 * If we can't replace bf->skb with a new skb under memory
1815 * pressure, just skip this packet
1816 */
1817 if (!next_skb)
1818 goto next;
1819
1820 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1821 PCI_DMA_FROMDEVICE);
1822 skb_put(skb, rs.rs_datalen);
1823
1824 /* The MAC header is padded to have 32-bit boundary if the
1825 * packet payload is non-zero. The general calculation for
1826 * padsize would take into account odd header lengths:
1827 * padsize = (4 - hdrlen % 4) % 4; However, since only
1828 * even-length headers are used, padding can only be 0 or 2
1829 * bytes and we can optimize this a bit. In addition, we must
1830 * not try to remove padding from short control frames that do
1831 * not have payload. */
1832 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1833 padsize = ath5k_pad_size(hdrlen);
1834 if (padsize) {
1835 memmove(skb->data + padsize, skb->data, hdrlen);
1836 skb_pull(skb, padsize);
1837 }
1838
1839 /*
1840 * always extend the mac timestamp, since this information is
1841 * also needed for proper IBSS merging.
1842 *
1843 * XXX: it might be too late to do it here, since rs_tstamp is
1844 * 15bit only. that means TSF extension has to be done within
1845 * 32768usec (about 32ms). it might be necessary to move this to
1846 * the interrupt handler, like it is done in madwifi.
1847 *
1848 * Unfortunately we don't know when the hardware takes the rx
1849 * timestamp (beginning of phy frame, data frame, end of rx?).
1850 * The only thing we know is that it is hardware specific...
1851 * On AR5213 it seems the rx timestamp is at the end of the
1852 * frame, but i'm not sure.
1853 *
1854 * NOTE: mac80211 defines mactime at the beginning of the first
1855 * data symbol. Since we don't have any time references it's
1856 * impossible to comply to that. This affects IBSS merge only
1857 * right now, so it's not too bad...
1858 */
1859 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
1860 rxs.flag |= RX_FLAG_TSFT;
1861
1862 rxs.freq = sc->curchan->center_freq;
1863 rxs.band = sc->curband->band;
1864
1865 rxs.noise = sc->ah->ah_noise_floor;
1866 rxs.signal = rxs.noise + rs.rs_rssi;
1867
1868 /* An rssi of 35 indicates you should be able use
1869 * 54 Mbps reliably. A more elaborate scheme can be used
1870 * here but it requires a map of SNR/throughput for each
1871 * possible mode used */
1872 rxs.qual = rs.rs_rssi * 100 / 35;
1873
1874 /* rssi can be more than 35 though, anything above that
1875 * should be considered at 100% */
1876 if (rxs.qual > 100)
1877 rxs.qual = 100;
1878
1879 rxs.antenna = rs.rs_antenna;
1880 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1881 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
1882
1883 if (rxs.rate_idx >= 0 && rs.rs_rate ==
1884 sc->curband->bitrates[rxs.rate_idx].hw_value_short)
1885 rxs.flag |= RX_FLAG_SHORTPRE;
1886
1887 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1888
1889 /* check beacons in IBSS mode */
1890 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1891 ath5k_check_ibss_tsf(sc, skb, &rxs);
1892
1893 __ieee80211_rx(sc->hw, skb, &rxs);
1894
1895 bf->skb = next_skb;
1896 bf->skbaddr = next_skb_addr;
1897 next:
1898 list_move_tail(&bf->list, &sc->rxbuf);
1899 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1900 unlock:
1901 spin_unlock(&sc->rxbuflock);
1902 }
1903
1904
1905
1906
1907 /*************\
1908 * TX Handling *
1909 \*************/
1910
1911 static void
1912 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1913 {
1914 struct ath5k_tx_status ts = {};
1915 struct ath5k_buf *bf, *bf0;
1916 struct ath5k_desc *ds;
1917 struct sk_buff *skb;
1918 struct ieee80211_tx_info *info;
1919 int i, ret;
1920
1921 spin_lock(&txq->lock);
1922 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1923 ds = bf->desc;
1924
1925 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1926 if (unlikely(ret == -EINPROGRESS))
1927 break;
1928 else if (unlikely(ret)) {
1929 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1930 ret, txq->qnum);
1931 break;
1932 }
1933
1934 skb = bf->skb;
1935 info = IEEE80211_SKB_CB(skb);
1936 bf->skb = NULL;
1937
1938 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1939 PCI_DMA_TODEVICE);
1940
1941 ieee80211_tx_info_clear_status(info);
1942 for (i = 0; i < 4; i++) {
1943 struct ieee80211_tx_rate *r =
1944 &info->status.rates[i];
1945
1946 if (ts.ts_rate[i]) {
1947 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
1948 r->count = ts.ts_retry[i];
1949 } else {
1950 r->idx = -1;
1951 r->count = 0;
1952 }
1953 }
1954
1955 /* count the successful attempt as well */
1956 info->status.rates[ts.ts_final_idx].count++;
1957
1958 if (unlikely(ts.ts_status)) {
1959 sc->ll_stats.dot11ACKFailureCount++;
1960 if (ts.ts_status & AR5K_TXERR_FILT)
1961 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1962 } else {
1963 info->flags |= IEEE80211_TX_STAT_ACK;
1964 info->status.ack_signal = ts.ts_rssi;
1965 }
1966
1967 ieee80211_tx_status(sc->hw, skb);
1968 sc->tx_stats[txq->qnum].count++;
1969
1970 spin_lock(&sc->txbuflock);
1971 sc->tx_stats[txq->qnum].len--;
1972 list_move_tail(&bf->list, &sc->txbuf);
1973 sc->txbuf_len++;
1974 spin_unlock(&sc->txbuflock);
1975 }
1976 if (likely(list_empty(&txq->q)))
1977 txq->link = NULL;
1978 spin_unlock(&txq->lock);
1979 if (sc->txbuf_len > ATH_TXBUF / 5)
1980 ieee80211_wake_queues(sc->hw);
1981 }
1982
1983 static void
1984 ath5k_tasklet_tx(unsigned long data)
1985 {
1986 struct ath5k_softc *sc = (void *)data;
1987
1988 ath5k_tx_processq(sc, sc->txq);
1989 }
1990
1991
1992 /*****************\
1993 * Beacon handling *
1994 \*****************/
1995
1996 /*
1997 * Setup the beacon frame for transmit.
1998 */
1999 static int
2000 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
2001 {
2002 struct sk_buff *skb = bf->skb;
2003 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2004 struct ath5k_hw *ah = sc->ah;
2005 struct ath5k_desc *ds;
2006 int ret = 0;
2007 u8 antenna;
2008 u32 flags;
2009
2010 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
2011 PCI_DMA_TODEVICE);
2012 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
2013 "skbaddr %llx\n", skb, skb->data, skb->len,
2014 (unsigned long long)bf->skbaddr);
2015 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
2016 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
2017 return -EIO;
2018 }
2019
2020 ds = bf->desc;
2021 antenna = ah->ah_tx_ant;
2022
2023 flags = AR5K_TXDESC_NOACK;
2024 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
2025 ds->ds_link = bf->daddr; /* self-linked */
2026 flags |= AR5K_TXDESC_VEOL;
2027 } else
2028 ds->ds_link = 0;
2029
2030 /*
2031 * If we use multiple antennas on AP and use
2032 * the Sectored AP scenario, switch antenna every
2033 * 4 beacons to make sure everybody hears our AP.
2034 * When a client tries to associate, hw will keep
2035 * track of the tx antenna to be used for this client
2036 * automaticaly, based on ACKed packets.
2037 *
2038 * Note: AP still listens and transmits RTS on the
2039 * default antenna which is supposed to be an omni.
2040 *
2041 * Note2: On sectored scenarios it's possible to have
2042 * multiple antennas (1omni -the default- and 14 sectors)
2043 * so if we choose to actually support this mode we need
2044 * to allow user to set how many antennas we have and tweak
2045 * the code below to send beacons on all of them.
2046 */
2047 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
2048 antenna = sc->bsent & 4 ? 2 : 1;
2049
2050
2051 /* FIXME: If we are in g mode and rate is a CCK rate
2052 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
2053 * from tx power (value is in dB units already) */
2054 ds->ds_data = bf->skbaddr;
2055 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
2056 ieee80211_get_hdrlen_from_skb(skb),
2057 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
2058 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2059 1, AR5K_TXKEYIX_INVALID,
2060 antenna, flags, 0, 0);
2061 if (ret)
2062 goto err_unmap;
2063
2064 return 0;
2065 err_unmap:
2066 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2067 return ret;
2068 }
2069
2070 static void ath5k_beacon_disable(struct ath5k_softc *sc)
2071 {
2072 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2073 ath5k_hw_set_imr(sc->ah, sc->imask);
2074 ath5k_hw_stop_tx_dma(sc->ah, sc->bhalq);
2075 }
2076
2077 /*
2078 * Transmit a beacon frame at SWBA. Dynamic updates to the
2079 * frame contents are done as needed and the slot time is
2080 * also adjusted based on current state.
2081 *
2082 * This is called from software irq context (beacontq or restq
2083 * tasklets) or user context from ath5k_beacon_config.
2084 */
2085 static void
2086 ath5k_beacon_send(struct ath5k_softc *sc)
2087 {
2088 struct ath5k_buf *bf = sc->bbuf;
2089 struct ath5k_hw *ah = sc->ah;
2090
2091 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
2092
2093 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
2094 sc->opmode == NL80211_IFTYPE_MONITOR)) {
2095 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2096 return;
2097 }
2098 /*
2099 * Check if the previous beacon has gone out. If
2100 * not don't don't try to post another, skip this
2101 * period and wait for the next. Missed beacons
2102 * indicate a problem and should not occur. If we
2103 * miss too many consecutive beacons reset the device.
2104 */
2105 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2106 sc->bmisscount++;
2107 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2108 "missed %u consecutive beacons\n", sc->bmisscount);
2109 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
2110 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2111 "stuck beacon time (%u missed)\n",
2112 sc->bmisscount);
2113 tasklet_schedule(&sc->restq);
2114 }
2115 return;
2116 }
2117 if (unlikely(sc->bmisscount != 0)) {
2118 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2119 "resume beacon xmit after %u misses\n",
2120 sc->bmisscount);
2121 sc->bmisscount = 0;
2122 }
2123
2124 /*
2125 * Stop any current dma and put the new frame on the queue.
2126 * This should never fail since we check above that no frames
2127 * are still pending on the queue.
2128 */
2129 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2130 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
2131 /* NB: hw still stops DMA, so proceed */
2132 }
2133
2134 /* refresh the beacon for AP mode */
2135 if (sc->opmode == NL80211_IFTYPE_AP)
2136 ath5k_beacon_update(sc->hw, sc->vif);
2137
2138 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2139 ath5k_hw_start_tx_dma(ah, sc->bhalq);
2140 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
2141 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2142
2143 sc->bsent++;
2144 }
2145
2146
2147 /**
2148 * ath5k_beacon_update_timers - update beacon timers
2149 *
2150 * @sc: struct ath5k_softc pointer we are operating on
2151 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2152 * beacon timer update based on the current HW TSF.
2153 *
2154 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2155 * of a received beacon or the current local hardware TSF and write it to the
2156 * beacon timer registers.
2157 *
2158 * This is called in a variety of situations, e.g. when a beacon is received,
2159 * when a TSF update has been detected, but also when an new IBSS is created or
2160 * when we otherwise know we have to update the timers, but we keep it in this
2161 * function to have it all together in one place.
2162 */
2163 static void
2164 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2165 {
2166 struct ath5k_hw *ah = sc->ah;
2167 u32 nexttbtt, intval, hw_tu, bc_tu;
2168 u64 hw_tsf;
2169
2170 intval = sc->bintval & AR5K_BEACON_PERIOD;
2171 if (WARN_ON(!intval))
2172 return;
2173
2174 /* beacon TSF converted to TU */
2175 bc_tu = TSF_TO_TU(bc_tsf);
2176
2177 /* current TSF converted to TU */
2178 hw_tsf = ath5k_hw_get_tsf64(ah);
2179 hw_tu = TSF_TO_TU(hw_tsf);
2180
2181 #define FUDGE 3
2182 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2183 if (bc_tsf == -1) {
2184 /*
2185 * no beacons received, called internally.
2186 * just need to refresh timers based on HW TSF.
2187 */
2188 nexttbtt = roundup(hw_tu + FUDGE, intval);
2189 } else if (bc_tsf == 0) {
2190 /*
2191 * no beacon received, probably called by ath5k_reset_tsf().
2192 * reset TSF to start with 0.
2193 */
2194 nexttbtt = intval;
2195 intval |= AR5K_BEACON_RESET_TSF;
2196 } else if (bc_tsf > hw_tsf) {
2197 /*
2198 * beacon received, SW merge happend but HW TSF not yet updated.
2199 * not possible to reconfigure timers yet, but next time we
2200 * receive a beacon with the same BSSID, the hardware will
2201 * automatically update the TSF and then we need to reconfigure
2202 * the timers.
2203 */
2204 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2205 "need to wait for HW TSF sync\n");
2206 return;
2207 } else {
2208 /*
2209 * most important case for beacon synchronization between STA.
2210 *
2211 * beacon received and HW TSF has been already updated by HW.
2212 * update next TBTT based on the TSF of the beacon, but make
2213 * sure it is ahead of our local TSF timer.
2214 */
2215 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2216 }
2217 #undef FUDGE
2218
2219 sc->nexttbtt = nexttbtt;
2220
2221 intval |= AR5K_BEACON_ENA;
2222 ath5k_hw_init_beacon(ah, nexttbtt, intval);
2223
2224 /*
2225 * debugging output last in order to preserve the time critical aspect
2226 * of this function
2227 */
2228 if (bc_tsf == -1)
2229 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2230 "reconfigured timers based on HW TSF\n");
2231 else if (bc_tsf == 0)
2232 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2233 "reset HW TSF and timers\n");
2234 else
2235 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2236 "updated timers based on beacon TSF\n");
2237
2238 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2239 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2240 (unsigned long long) bc_tsf,
2241 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2242 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2243 intval & AR5K_BEACON_PERIOD,
2244 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2245 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2246 }
2247
2248
2249 /**
2250 * ath5k_beacon_config - Configure the beacon queues and interrupts
2251 *
2252 * @sc: struct ath5k_softc pointer we are operating on
2253 *
2254 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2255 * interrupts to detect TSF updates only.
2256 */
2257 static void
2258 ath5k_beacon_config(struct ath5k_softc *sc)
2259 {
2260 struct ath5k_hw *ah = sc->ah;
2261 unsigned long flags;
2262
2263 ath5k_hw_set_imr(ah, 0);
2264 sc->bmisscount = 0;
2265 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2266
2267 if (sc->opmode == NL80211_IFTYPE_ADHOC ||
2268 sc->opmode == NL80211_IFTYPE_MESH_POINT ||
2269 sc->opmode == NL80211_IFTYPE_AP) {
2270 /*
2271 * In IBSS mode we use a self-linked tx descriptor and let the
2272 * hardware send the beacons automatically. We have to load it
2273 * only once here.
2274 * We use the SWBA interrupt only to keep track of the beacon
2275 * timers in order to detect automatic TSF updates.
2276 */
2277 ath5k_beaconq_config(sc);
2278
2279 sc->imask |= AR5K_INT_SWBA;
2280
2281 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2282 if (ath5k_hw_hasveol(ah)) {
2283 spin_lock_irqsave(&sc->block, flags);
2284 ath5k_beacon_send(sc);
2285 spin_unlock_irqrestore(&sc->block, flags);
2286 }
2287 } else
2288 ath5k_beacon_update_timers(sc, -1);
2289 }
2290
2291 ath5k_hw_set_imr(ah, sc->imask);
2292 }
2293
2294 static void ath5k_tasklet_beacon(unsigned long data)
2295 {
2296 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2297
2298 /*
2299 * Software beacon alert--time to send a beacon.
2300 *
2301 * In IBSS mode we use this interrupt just to
2302 * keep track of the next TBTT (target beacon
2303 * transmission time) in order to detect wether
2304 * automatic TSF updates happened.
2305 */
2306 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2307 /* XXX: only if VEOL suppported */
2308 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2309 sc->nexttbtt += sc->bintval;
2310 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2311 "SWBA nexttbtt: %x hw_tu: %x "
2312 "TSF: %llx\n",
2313 sc->nexttbtt,
2314 TSF_TO_TU(tsf),
2315 (unsigned long long) tsf);
2316 } else {
2317 spin_lock(&sc->block);
2318 ath5k_beacon_send(sc);
2319 spin_unlock(&sc->block);
2320 }
2321 }
2322
2323
2324 /********************\
2325 * Interrupt handling *
2326 \********************/
2327
2328 static int
2329 ath5k_init(struct ath5k_softc *sc)
2330 {
2331 struct ath5k_hw *ah = sc->ah;
2332 int ret, i;
2333
2334 mutex_lock(&sc->lock);
2335
2336 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2337
2338 /*
2339 * Stop anything previously setup. This is safe
2340 * no matter this is the first time through or not.
2341 */
2342 ath5k_stop_locked(sc);
2343
2344 /*
2345 * The basic interface to setting the hardware in a good
2346 * state is ``reset''. On return the hardware is known to
2347 * be powered up and with interrupts disabled. This must
2348 * be followed by initialization of the appropriate bits
2349 * and then setup of the interrupt mask.
2350 */
2351 sc->curchan = sc->hw->conf.channel;
2352 sc->curband = &sc->sbands[sc->curchan->band];
2353 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2354 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2355 AR5K_INT_FATAL | AR5K_INT_GLOBAL;
2356 ret = ath5k_reset(sc, NULL);
2357 if (ret)
2358 goto done;
2359
2360 ath5k_rfkill_hw_start(ah);
2361
2362 /*
2363 * Reset the key cache since some parts do not reset the
2364 * contents on initial power up or resume from suspend.
2365 */
2366 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2367 ath5k_hw_reset_key(ah, i);
2368
2369 /* Set ack to be sent at low bit-rates */
2370 ath5k_hw_set_ack_bitrate_high(ah, false);
2371
2372 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2373 msecs_to_jiffies(ath5k_calinterval * 1000)));
2374
2375 ret = 0;
2376 done:
2377 mmiowb();
2378 mutex_unlock(&sc->lock);
2379 return ret;
2380 }
2381
2382 static int
2383 ath5k_stop_locked(struct ath5k_softc *sc)
2384 {
2385 struct ath5k_hw *ah = sc->ah;
2386
2387 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2388 test_bit(ATH_STAT_INVALID, sc->status));
2389
2390 /*
2391 * Shutdown the hardware and driver:
2392 * stop output from above
2393 * disable interrupts
2394 * turn off timers
2395 * turn off the radio
2396 * clear transmit machinery
2397 * clear receive machinery
2398 * drain and release tx queues
2399 * reclaim beacon resources
2400 * power down hardware
2401 *
2402 * Note that some of this work is not possible if the
2403 * hardware is gone (invalid).
2404 */
2405 ieee80211_stop_queues(sc->hw);
2406
2407 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2408 ath5k_led_off(sc);
2409 ath5k_hw_set_imr(ah, 0);
2410 synchronize_irq(sc->pdev->irq);
2411 }
2412 ath5k_txq_cleanup(sc);
2413 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2414 ath5k_rx_stop(sc);
2415 ath5k_hw_phy_disable(ah);
2416 } else
2417 sc->rxlink = NULL;
2418
2419 return 0;
2420 }
2421
2422 /*
2423 * Stop the device, grabbing the top-level lock to protect
2424 * against concurrent entry through ath5k_init (which can happen
2425 * if another thread does a system call and the thread doing the
2426 * stop is preempted).
2427 */
2428 static int
2429 ath5k_stop_hw(struct ath5k_softc *sc)
2430 {
2431 int ret;
2432
2433 mutex_lock(&sc->lock);
2434 ret = ath5k_stop_locked(sc);
2435 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2436 /*
2437 * Don't set the card in full sleep mode!
2438 *
2439 * a) When the device is in this state it must be carefully
2440 * woken up or references to registers in the PCI clock
2441 * domain may freeze the bus (and system). This varies
2442 * by chip and is mostly an issue with newer parts
2443 * (madwifi sources mentioned srev >= 0x78) that go to
2444 * sleep more quickly.
2445 *
2446 * b) On older chips full sleep results a weird behaviour
2447 * during wakeup. I tested various cards with srev < 0x78
2448 * and they don't wake up after module reload, a second
2449 * module reload is needed to bring the card up again.
2450 *
2451 * Until we figure out what's going on don't enable
2452 * full chip reset on any chip (this is what Legacy HAL
2453 * and Sam's HAL do anyway). Instead Perform a full reset
2454 * on the device (same as initial state after attach) and
2455 * leave it idle (keep MAC/BB on warm reset) */
2456 ret = ath5k_hw_on_hold(sc->ah);
2457
2458 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2459 "putting device to sleep\n");
2460 }
2461 ath5k_txbuf_free(sc, sc->bbuf);
2462
2463 mmiowb();
2464 mutex_unlock(&sc->lock);
2465
2466 del_timer_sync(&sc->calib_tim);
2467 tasklet_kill(&sc->rxtq);
2468 tasklet_kill(&sc->txtq);
2469 tasklet_kill(&sc->restq);
2470 tasklet_kill(&sc->beacontq);
2471
2472 ath5k_rfkill_hw_stop(sc->ah);
2473
2474 return ret;
2475 }
2476
2477 static irqreturn_t
2478 ath5k_intr(int irq, void *dev_id)
2479 {
2480 struct ath5k_softc *sc = dev_id;
2481 struct ath5k_hw *ah = sc->ah;
2482 enum ath5k_int status;
2483 unsigned int counter = 1000;
2484
2485 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2486 !ath5k_hw_is_intr_pending(ah)))
2487 return IRQ_NONE;
2488
2489 do {
2490 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2491 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2492 status, sc->imask);
2493 if (unlikely(status & AR5K_INT_FATAL)) {
2494 /*
2495 * Fatal errors are unrecoverable.
2496 * Typically these are caused by DMA errors.
2497 */
2498 tasklet_schedule(&sc->restq);
2499 } else if (unlikely(status & AR5K_INT_RXORN)) {
2500 tasklet_schedule(&sc->restq);
2501 } else {
2502 if (status & AR5K_INT_SWBA) {
2503 tasklet_hi_schedule(&sc->beacontq);
2504 }
2505 if (status & AR5K_INT_RXEOL) {
2506 /*
2507 * NB: the hardware should re-read the link when
2508 * RXE bit is written, but it doesn't work at
2509 * least on older hardware revs.
2510 */
2511 sc->rxlink = NULL;
2512 }
2513 if (status & AR5K_INT_TXURN) {
2514 /* bump tx trigger level */
2515 ath5k_hw_update_tx_triglevel(ah, true);
2516 }
2517 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2518 tasklet_schedule(&sc->rxtq);
2519 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2520 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
2521 tasklet_schedule(&sc->txtq);
2522 if (status & AR5K_INT_BMISS) {
2523 /* TODO */
2524 }
2525 if (status & AR5K_INT_MIB) {
2526 /*
2527 * These stats are also used for ANI i think
2528 * so how about updating them more often ?
2529 */
2530 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
2531 }
2532 if (status & AR5K_INT_GPIO)
2533 tasklet_schedule(&sc->rf_kill.toggleq);
2534
2535 }
2536 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
2537
2538 if (unlikely(!counter))
2539 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2540
2541 return IRQ_HANDLED;
2542 }
2543
2544 static void
2545 ath5k_tasklet_reset(unsigned long data)
2546 {
2547 struct ath5k_softc *sc = (void *)data;
2548
2549 ath5k_reset_wake(sc);
2550 }
2551
2552 /*
2553 * Periodically recalibrate the PHY to account
2554 * for temperature/environment changes.
2555 */
2556 static void
2557 ath5k_calibrate(unsigned long data)
2558 {
2559 struct ath5k_softc *sc = (void *)data;
2560 struct ath5k_hw *ah = sc->ah;
2561
2562 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2563 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2564 sc->curchan->hw_value);
2565
2566 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2567 /*
2568 * Rfgain is out of bounds, reset the chip
2569 * to load new gain values.
2570 */
2571 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2572 ath5k_reset_wake(sc);
2573 }
2574 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2575 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2576 ieee80211_frequency_to_channel(
2577 sc->curchan->center_freq));
2578
2579 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2580 msecs_to_jiffies(ath5k_calinterval * 1000)));
2581 }
2582
2583
2584 /********************\
2585 * Mac80211 functions *
2586 \********************/
2587
2588 static int
2589 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2590 {
2591 struct ath5k_softc *sc = hw->priv;
2592 struct ath5k_buf *bf;
2593 unsigned long flags;
2594 int hdrlen;
2595 int padsize;
2596
2597 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2598
2599 if (sc->opmode == NL80211_IFTYPE_MONITOR)
2600 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2601
2602 /*
2603 * the hardware expects the header padded to 4 byte boundaries
2604 * if this is not the case we add the padding after the header
2605 */
2606 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2607 padsize = ath5k_pad_size(hdrlen);
2608 if (padsize) {
2609
2610 if (skb_headroom(skb) < padsize) {
2611 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2612 " headroom to pad %d\n", hdrlen, padsize);
2613 goto drop_packet;
2614 }
2615 skb_push(skb, padsize);
2616 memmove(skb->data, skb->data+padsize, hdrlen);
2617 }
2618
2619 spin_lock_irqsave(&sc->txbuflock, flags);
2620 if (list_empty(&sc->txbuf)) {
2621 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2622 spin_unlock_irqrestore(&sc->txbuflock, flags);
2623 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
2624 goto drop_packet;
2625 }
2626 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2627 list_del(&bf->list);
2628 sc->txbuf_len--;
2629 if (list_empty(&sc->txbuf))
2630 ieee80211_stop_queues(hw);
2631 spin_unlock_irqrestore(&sc->txbuflock, flags);
2632
2633 bf->skb = skb;
2634
2635 if (ath5k_txbuf_setup(sc, bf)) {
2636 bf->skb = NULL;
2637 spin_lock_irqsave(&sc->txbuflock, flags);
2638 list_add_tail(&bf->list, &sc->txbuf);
2639 sc->txbuf_len++;
2640 spin_unlock_irqrestore(&sc->txbuflock, flags);
2641 goto drop_packet;
2642 }
2643 return NETDEV_TX_OK;
2644
2645 drop_packet:
2646 dev_kfree_skb_any(skb);
2647 return NETDEV_TX_OK;
2648 }
2649
2650 /*
2651 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2652 * and change to the given channel.
2653 */
2654 static int
2655 ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan)
2656 {
2657 struct ath5k_hw *ah = sc->ah;
2658 int ret;
2659
2660 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2661
2662 if (chan) {
2663 ath5k_hw_set_imr(ah, 0);
2664 ath5k_txq_cleanup(sc);
2665 ath5k_rx_stop(sc);
2666
2667 sc->curchan = chan;
2668 sc->curband = &sc->sbands[chan->band];
2669 }
2670 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL);
2671 if (ret) {
2672 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2673 goto err;
2674 }
2675
2676 ret = ath5k_rx_start(sc);
2677 if (ret) {
2678 ATH5K_ERR(sc, "can't start recv logic\n");
2679 goto err;
2680 }
2681
2682 /*
2683 * Change channels and update the h/w rate map if we're switching;
2684 * e.g. 11a to 11b/g.
2685 *
2686 * We may be doing a reset in response to an ioctl that changes the
2687 * channel so update any state that might change as a result.
2688 *
2689 * XXX needed?
2690 */
2691 /* ath5k_chan_change(sc, c); */
2692
2693 ath5k_beacon_config(sc);
2694 /* intrs are enabled by ath5k_beacon_config */
2695
2696 return 0;
2697 err:
2698 return ret;
2699 }
2700
2701 static int
2702 ath5k_reset_wake(struct ath5k_softc *sc)
2703 {
2704 int ret;
2705
2706 ret = ath5k_reset(sc, sc->curchan);
2707 if (!ret)
2708 ieee80211_wake_queues(sc->hw);
2709
2710 return ret;
2711 }
2712
2713 static int ath5k_start(struct ieee80211_hw *hw)
2714 {
2715 return ath5k_init(hw->priv);
2716 }
2717
2718 static void ath5k_stop(struct ieee80211_hw *hw)
2719 {
2720 ath5k_stop_hw(hw->priv);
2721 }
2722
2723 static int ath5k_add_interface(struct ieee80211_hw *hw,
2724 struct ieee80211_if_init_conf *conf)
2725 {
2726 struct ath5k_softc *sc = hw->priv;
2727 int ret;
2728
2729 mutex_lock(&sc->lock);
2730 if (sc->vif) {
2731 ret = 0;
2732 goto end;
2733 }
2734
2735 sc->vif = conf->vif;
2736
2737 switch (conf->type) {
2738 case NL80211_IFTYPE_AP:
2739 case NL80211_IFTYPE_STATION:
2740 case NL80211_IFTYPE_ADHOC:
2741 case NL80211_IFTYPE_MESH_POINT:
2742 case NL80211_IFTYPE_MONITOR:
2743 sc->opmode = conf->type;
2744 break;
2745 default:
2746 ret = -EOPNOTSUPP;
2747 goto end;
2748 }
2749
2750 ath5k_hw_set_lladdr(sc->ah, conf->mac_addr);
2751
2752 ret = 0;
2753 end:
2754 mutex_unlock(&sc->lock);
2755 return ret;
2756 }
2757
2758 static void
2759 ath5k_remove_interface(struct ieee80211_hw *hw,
2760 struct ieee80211_if_init_conf *conf)
2761 {
2762 struct ath5k_softc *sc = hw->priv;
2763 u8 mac[ETH_ALEN] = {};
2764
2765 mutex_lock(&sc->lock);
2766 if (sc->vif != conf->vif)
2767 goto end;
2768
2769 ath5k_hw_set_lladdr(sc->ah, mac);
2770 ath5k_beacon_disable(sc);
2771 sc->vif = NULL;
2772 end:
2773 mutex_unlock(&sc->lock);
2774 }
2775
2776 /*
2777 * TODO: Phy disable/diversity etc
2778 */
2779 static int
2780 ath5k_config(struct ieee80211_hw *hw, u32 changed)
2781 {
2782 struct ath5k_softc *sc = hw->priv;
2783 struct ath5k_hw *ah = sc->ah;
2784 struct ieee80211_conf *conf = &hw->conf;
2785 int ret = 0;
2786
2787 mutex_lock(&sc->lock);
2788
2789 ret = ath5k_chan_set(sc, conf->channel);
2790 if (ret < 0)
2791 goto unlock;
2792
2793 if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
2794 (sc->power_level != conf->power_level)) {
2795 sc->power_level = conf->power_level;
2796
2797 /* Half dB steps */
2798 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
2799 }
2800
2801 /* TODO:
2802 * 1) Move this on config_interface and handle each case
2803 * separately eg. when we have only one STA vif, use
2804 * AR5K_ANTMODE_SINGLE_AP
2805 *
2806 * 2) Allow the user to change antenna mode eg. when only
2807 * one antenna is present
2808 *
2809 * 3) Allow the user to set default/tx antenna when possible
2810 *
2811 * 4) Default mode should handle 90% of the cases, together
2812 * with fixed a/b and single AP modes we should be able to
2813 * handle 99%. Sectored modes are extreme cases and i still
2814 * haven't found a usage for them. If we decide to support them,
2815 * then we must allow the user to set how many tx antennas we
2816 * have available
2817 */
2818 ath5k_hw_set_antenna_mode(ah, AR5K_ANTMODE_DEFAULT);
2819
2820 unlock:
2821 mutex_unlock(&sc->lock);
2822 return ret;
2823 }
2824
2825 #define SUPPORTED_FIF_FLAGS \
2826 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2827 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2828 FIF_BCN_PRBRESP_PROMISC
2829 /*
2830 * o always accept unicast, broadcast, and multicast traffic
2831 * o multicast traffic for all BSSIDs will be enabled if mac80211
2832 * says it should be
2833 * o maintain current state of phy ofdm or phy cck error reception.
2834 * If the hardware detects any of these type of errors then
2835 * ath5k_hw_get_rx_filter() will pass to us the respective
2836 * hardware filters to be able to receive these type of frames.
2837 * o probe request frames are accepted only when operating in
2838 * hostap, adhoc, or monitor modes
2839 * o enable promiscuous mode according to the interface state
2840 * o accept beacons:
2841 * - when operating in adhoc mode so the 802.11 layer creates
2842 * node table entries for peers,
2843 * - when operating in station mode for collecting rssi data when
2844 * the station is otherwise quiet, or
2845 * - when scanning
2846 */
2847 static void ath5k_configure_filter(struct ieee80211_hw *hw,
2848 unsigned int changed_flags,
2849 unsigned int *new_flags,
2850 int mc_count, struct dev_mc_list *mclist)
2851 {
2852 struct ath5k_softc *sc = hw->priv;
2853 struct ath5k_hw *ah = sc->ah;
2854 u32 mfilt[2], val, rfilt;
2855 u8 pos;
2856 int i;
2857
2858 mfilt[0] = 0;
2859 mfilt[1] = 0;
2860
2861 /* Only deal with supported flags */
2862 changed_flags &= SUPPORTED_FIF_FLAGS;
2863 *new_flags &= SUPPORTED_FIF_FLAGS;
2864
2865 /* If HW detects any phy or radar errors, leave those filters on.
2866 * Also, always enable Unicast, Broadcasts and Multicast
2867 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2868 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2869 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2870 AR5K_RX_FILTER_MCAST);
2871
2872 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2873 if (*new_flags & FIF_PROMISC_IN_BSS) {
2874 rfilt |= AR5K_RX_FILTER_PROM;
2875 __set_bit(ATH_STAT_PROMISC, sc->status);
2876 } else {
2877 __clear_bit(ATH_STAT_PROMISC, sc->status);
2878 }
2879 }
2880
2881 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2882 if (*new_flags & FIF_ALLMULTI) {
2883 mfilt[0] = ~0;
2884 mfilt[1] = ~0;
2885 } else {
2886 for (i = 0; i < mc_count; i++) {
2887 if (!mclist)
2888 break;
2889 /* calculate XOR of eight 6-bit values */
2890 val = get_unaligned_le32(mclist->dmi_addr + 0);
2891 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2892 val = get_unaligned_le32(mclist->dmi_addr + 3);
2893 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2894 pos &= 0x3f;
2895 mfilt[pos / 32] |= (1 << (pos % 32));
2896 /* XXX: we might be able to just do this instead,
2897 * but not sure, needs testing, if we do use this we'd
2898 * neet to inform below to not reset the mcast */
2899 /* ath5k_hw_set_mcast_filterindex(ah,
2900 * mclist->dmi_addr[5]); */
2901 mclist = mclist->next;
2902 }
2903 }
2904
2905 /* This is the best we can do */
2906 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2907 rfilt |= AR5K_RX_FILTER_PHYERR;
2908
2909 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2910 * and probes for any BSSID, this needs testing */
2911 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2912 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2913
2914 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2915 * set we should only pass on control frames for this
2916 * station. This needs testing. I believe right now this
2917 * enables *all* control frames, which is OK.. but
2918 * but we should see if we can improve on granularity */
2919 if (*new_flags & FIF_CONTROL)
2920 rfilt |= AR5K_RX_FILTER_CONTROL;
2921
2922 /* Additional settings per mode -- this is per ath5k */
2923
2924 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2925
2926 if (sc->opmode == NL80211_IFTYPE_MONITOR)
2927 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2928 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2929 if (sc->opmode != NL80211_IFTYPE_STATION)
2930 rfilt |= AR5K_RX_FILTER_PROBEREQ;
2931 if (sc->opmode != NL80211_IFTYPE_AP &&
2932 sc->opmode != NL80211_IFTYPE_MESH_POINT &&
2933 test_bit(ATH_STAT_PROMISC, sc->status))
2934 rfilt |= AR5K_RX_FILTER_PROM;
2935 if ((sc->opmode == NL80211_IFTYPE_STATION && sc->assoc) ||
2936 sc->opmode == NL80211_IFTYPE_ADHOC ||
2937 sc->opmode == NL80211_IFTYPE_AP)
2938 rfilt |= AR5K_RX_FILTER_BEACON;
2939 if (sc->opmode == NL80211_IFTYPE_MESH_POINT)
2940 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2941 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2942
2943 /* Set filters */
2944 ath5k_hw_set_rx_filter(ah, rfilt);
2945
2946 /* Set multicast bits */
2947 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2948 /* Set the cached hw filter flags, this will alter actually
2949 * be set in HW */
2950 sc->filter_flags = rfilt;
2951 }
2952
2953 static int
2954 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2955 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
2956 struct ieee80211_key_conf *key)
2957 {
2958 struct ath5k_softc *sc = hw->priv;
2959 int ret = 0;
2960
2961 if (modparam_nohwcrypt)
2962 return -EOPNOTSUPP;
2963
2964 if (sc->opmode == NL80211_IFTYPE_AP)
2965 return -EOPNOTSUPP;
2966
2967 switch (key->alg) {
2968 case ALG_WEP:
2969 case ALG_TKIP:
2970 break;
2971 case ALG_CCMP:
2972 return -EOPNOTSUPP;
2973 default:
2974 WARN_ON(1);
2975 return -EINVAL;
2976 }
2977
2978 mutex_lock(&sc->lock);
2979
2980 switch (cmd) {
2981 case SET_KEY:
2982 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
2983 sta ? sta->addr : NULL);
2984 if (ret) {
2985 ATH5K_ERR(sc, "can't set the key\n");
2986 goto unlock;
2987 }
2988 __set_bit(key->keyidx, sc->keymap);
2989 key->hw_key_idx = key->keyidx;
2990 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
2991 IEEE80211_KEY_FLAG_GENERATE_MMIC);
2992 break;
2993 case DISABLE_KEY:
2994 ath5k_hw_reset_key(sc->ah, key->keyidx);
2995 __clear_bit(key->keyidx, sc->keymap);
2996 break;
2997 default:
2998 ret = -EINVAL;
2999 goto unlock;
3000 }
3001
3002 unlock:
3003 mmiowb();
3004 mutex_unlock(&sc->lock);
3005 return ret;
3006 }
3007
3008 static int
3009 ath5k_get_stats(struct ieee80211_hw *hw,
3010 struct ieee80211_low_level_stats *stats)
3011 {
3012 struct ath5k_softc *sc = hw->priv;
3013 struct ath5k_hw *ah = sc->ah;
3014
3015 /* Force update */
3016 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
3017
3018 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3019
3020 return 0;
3021 }
3022
3023 static int
3024 ath5k_get_tx_stats(struct ieee80211_hw *hw,
3025 struct ieee80211_tx_queue_stats *stats)
3026 {
3027 struct ath5k_softc *sc = hw->priv;
3028
3029 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
3030
3031 return 0;
3032 }
3033
3034 static u64
3035 ath5k_get_tsf(struct ieee80211_hw *hw)
3036 {
3037 struct ath5k_softc *sc = hw->priv;
3038
3039 return ath5k_hw_get_tsf64(sc->ah);
3040 }
3041
3042 static void
3043 ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3044 {
3045 struct ath5k_softc *sc = hw->priv;
3046
3047 ath5k_hw_set_tsf64(sc->ah, tsf);
3048 }
3049
3050 static void
3051 ath5k_reset_tsf(struct ieee80211_hw *hw)
3052 {
3053 struct ath5k_softc *sc = hw->priv;
3054
3055 /*
3056 * in IBSS mode we need to update the beacon timers too.
3057 * this will also reset the TSF if we call it with 0
3058 */
3059 if (sc->opmode == NL80211_IFTYPE_ADHOC)
3060 ath5k_beacon_update_timers(sc, 0);
3061 else
3062 ath5k_hw_reset_tsf(sc->ah);
3063 }
3064
3065 /*
3066 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
3067 * this is called only once at config_bss time, for AP we do it every
3068 * SWBA interrupt so that the TIM will reflect buffered frames.
3069 *
3070 * Called with the beacon lock.
3071 */
3072 static int
3073 ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
3074 {
3075 int ret;
3076 struct ath5k_softc *sc = hw->priv;
3077 struct sk_buff *skb;
3078
3079 if (WARN_ON(!vif)) {
3080 ret = -EINVAL;
3081 goto out;
3082 }
3083
3084 skb = ieee80211_beacon_get(hw, vif);
3085
3086 if (!skb) {
3087 ret = -ENOMEM;
3088 goto out;
3089 }
3090
3091 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3092
3093 ath5k_txbuf_free(sc, sc->bbuf);
3094 sc->bbuf->skb = skb;
3095 ret = ath5k_beacon_setup(sc, sc->bbuf);
3096 if (ret)
3097 sc->bbuf->skb = NULL;
3098 out:
3099 return ret;
3100 }
3101
3102 /*
3103 * Update the beacon and reconfigure the beacon queues.
3104 */
3105 static void
3106 ath5k_beacon_reconfig(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
3107 {
3108 int ret;
3109 unsigned long flags;
3110 struct ath5k_softc *sc = hw->priv;
3111
3112 spin_lock_irqsave(&sc->block, flags);
3113 ret = ath5k_beacon_update(hw, vif);
3114 spin_unlock_irqrestore(&sc->block, flags);
3115 if (ret == 0) {
3116 ath5k_beacon_config(sc);
3117 mmiowb();
3118 }
3119 }
3120
3121 static void
3122 set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3123 {
3124 struct ath5k_softc *sc = hw->priv;
3125 struct ath5k_hw *ah = sc->ah;
3126 u32 rfilt;
3127 rfilt = ath5k_hw_get_rx_filter(ah);
3128 if (enable)
3129 rfilt |= AR5K_RX_FILTER_BEACON;
3130 else
3131 rfilt &= ~AR5K_RX_FILTER_BEACON;
3132 ath5k_hw_set_rx_filter(ah, rfilt);
3133 sc->filter_flags = rfilt;
3134 }
3135
3136 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3137 struct ieee80211_vif *vif,
3138 struct ieee80211_bss_conf *bss_conf,
3139 u32 changes)
3140 {
3141 struct ath5k_softc *sc = hw->priv;
3142 struct ath5k_hw *ah = sc->ah;
3143
3144 mutex_lock(&sc->lock);
3145 if (WARN_ON(sc->vif != vif))
3146 goto unlock;
3147
3148 if (changes & BSS_CHANGED_BSSID) {
3149 /* Cache for later use during resets */
3150 memcpy(ah->ah_bssid, bss_conf->bssid, ETH_ALEN);
3151 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
3152 * a clean way of letting us retrieve this yet. */
3153 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
3154 mmiowb();
3155 }
3156
3157 if (changes & BSS_CHANGED_BEACON_INT)
3158 sc->bintval = bss_conf->beacon_int;
3159
3160 if (changes & BSS_CHANGED_ASSOC) {
3161 sc->assoc = bss_conf->assoc;
3162 if (sc->opmode == NL80211_IFTYPE_STATION)
3163 set_beacon_filter(hw, sc->assoc);
3164 }
3165
3166 if (changes & BSS_CHANGED_BEACON &&
3167 (vif->type == NL80211_IFTYPE_ADHOC ||
3168 vif->type == NL80211_IFTYPE_MESH_POINT ||
3169 vif->type == NL80211_IFTYPE_AP)) {
3170 ath5k_beacon_reconfig(hw, vif);
3171 }
3172
3173 unlock:
3174 mutex_unlock(&sc->lock);
3175 }
3176
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