1 /*
2 * Atheros AR9170 driver
3 *
4 * MAC programming
5 *
6 * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, see
20 * http://www.gnu.org/licenses/.
21 *
22 * This file incorporates work covered by the following copyright and
23 * permission notice:
24 * Copyright (c) 2007-2008 Atheros Communications, Inc.
25 *
26 * Permission to use, copy, modify, and/or distribute this software for any
27 * purpose with or without fee is hereby granted, provided that the above
28 * copyright notice and this permission notice appear in all copies.
29 *
30 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
31 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
32 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
33 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
34 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
35 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
36 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
37 */
38 #include "ar9170.h"
39 #include "cmd.h"
40
41 int ar9170_set_dyn_sifs_ack(struct ar9170 *ar)
42 {
43 u32 val;
44
45 if (conf_is_ht40(&ar->hw->conf))
46 val = 0x010a;
47 else {
48 if (ar->hw->conf.channel->band == IEEE80211_BAND_2GHZ)
49 val = 0x105;
50 else
51 val = 0x104;
52 }
53
54 return ar9170_write_reg(ar, AR9170_MAC_REG_DYNAMIC_SIFS_ACK, val);
55 }
56
57 int ar9170_set_slot_time(struct ar9170 *ar)
58 {
59 u32 slottime = 20;
60
61 if (!ar->vif)
62 return 0;
63
64 if ((ar->hw->conf.channel->band == IEEE80211_BAND_5GHZ) ||
65 ar->vif->bss_conf.use_short_slot)
66 slottime = 9;
67
68 return ar9170_write_reg(ar, AR9170_MAC_REG_SLOT_TIME, slottime << 10);
69 }
70
71 int ar9170_set_basic_rates(struct ar9170 *ar)
72 {
73 u8 cck, ofdm;
74
75 if (!ar->vif)
76 return 0;
77
78 ofdm = ar->vif->bss_conf.basic_rates >> 4;
79
80 /* FIXME: is still necessary? */
81 if (ar->hw->conf.channel->band == IEEE80211_BAND_5GHZ)
82 cck = 0;
83 else
84 cck = ar->vif->bss_conf.basic_rates & 0xf;
85
86 return ar9170_write_reg(ar, AR9170_MAC_REG_BASIC_RATE,
87 ofdm << 8 | cck);
88 }
89
90 int ar9170_set_qos(struct ar9170 *ar)
91 {
92 ar9170_regwrite_begin(ar);
93
94 ar9170_regwrite(AR9170_MAC_REG_AC0_CW, ar->edcf[0].cw_min |
95 (ar->edcf[0].cw_max << 16));
96 ar9170_regwrite(AR9170_MAC_REG_AC1_CW, ar->edcf[1].cw_min |
97 (ar->edcf[1].cw_max << 16));
98 ar9170_regwrite(AR9170_MAC_REG_AC2_CW, ar->edcf[2].cw_min |
99 (ar->edcf[2].cw_max << 16));
100 ar9170_regwrite(AR9170_MAC_REG_AC3_CW, ar->edcf[3].cw_min |
101 (ar->edcf[3].cw_max << 16));
102 ar9170_regwrite(AR9170_MAC_REG_AC4_CW, ar->edcf[4].cw_min |
103 (ar->edcf[4].cw_max << 16));
104
105 ar9170_regwrite(AR9170_MAC_REG_AC1_AC0_AIFS,
106 ((ar->edcf[0].aifs * 9 + 10)) |
107 ((ar->edcf[1].aifs * 9 + 10) << 12) |
108 ((ar->edcf[2].aifs * 9 + 10) << 24));
109 ar9170_regwrite(AR9170_MAC_REG_AC3_AC2_AIFS,
110 ((ar->edcf[2].aifs * 9 + 10) >> 8) |
111 ((ar->edcf[3].aifs * 9 + 10) << 4) |
112 ((ar->edcf[4].aifs * 9 + 10) << 16));
113
114 ar9170_regwrite(AR9170_MAC_REG_AC1_AC0_TXOP,
115 ar->edcf[0].txop | ar->edcf[1].txop << 16);
116 ar9170_regwrite(AR9170_MAC_REG_AC3_AC2_TXOP,
117 ar->edcf[1].txop | ar->edcf[3].txop << 16);
118
119 ar9170_regwrite_finish();
120
121 return ar9170_regwrite_result();
122 }
123
124 static int ar9170_set_ampdu_density(struct ar9170 *ar, u8 mpdudensity)
125 {
126 u32 val;
127
128 /* don't allow AMPDU density > 8us */
129 if (mpdudensity > 6)
130 return -EINVAL;
131
132 /* Watch out! Otus uses slightly different density values. */
133 val = 0x140a00 | (mpdudensity ? (mpdudensity + 1) : 0);
134
135 ar9170_regwrite_begin(ar);
136 ar9170_regwrite(AR9170_MAC_REG_AMPDU_DENSITY, val);
137 ar9170_regwrite_finish();
138
139 return ar9170_regwrite_result();
140 }
141
142 int ar9170_init_mac(struct ar9170 *ar)
143 {
144 ar9170_regwrite_begin(ar);
145
146 ar9170_regwrite(AR9170_MAC_REG_ACK_EXTENSION, 0x40);
147
148 ar9170_regwrite(AR9170_MAC_REG_RETRY_MAX, 0);
149
150 /* enable MMIC */
151 ar9170_regwrite(AR9170_MAC_REG_SNIFFER,
152 AR9170_MAC_REG_SNIFFER_DEFAULTS);
153
154 ar9170_regwrite(AR9170_MAC_REG_RX_THRESHOLD, 0xc1f80);
155
156 ar9170_regwrite(AR9170_MAC_REG_RX_PE_DELAY, 0x70);
157 ar9170_regwrite(AR9170_MAC_REG_EIFS_AND_SIFS, 0xa144000);
158 ar9170_regwrite(AR9170_MAC_REG_SLOT_TIME, 9 << 10);
159
160 /* CF-END mode */
161 ar9170_regwrite(0x1c3b2c, 0x19000000);
162
163 /* NAV protects ACK only (in TXOP) */
164 ar9170_regwrite(0x1c3b38, 0x201);
165
166 /* Set Beacon PHY CTRL's TPC to 0x7, TA1=1 */
167 /* OTUS set AM to 0x1 */
168 ar9170_regwrite(AR9170_MAC_REG_BCN_HT1, 0x8000170);
169
170 ar9170_regwrite(AR9170_MAC_REG_BACKOFF_PROTECT, 0x105);
171
172 /* AGG test code*/
173 /* Aggregation MAX number and timeout */
174 ar9170_regwrite(0x1c3b9c, 0x10000a);
175
176 ar9170_regwrite(AR9170_MAC_REG_FRAMETYPE_FILTER,
177 AR9170_MAC_REG_FTF_DEFAULTS);
178
179 /* Enable deaggregator, response in sniffer mode */
180 ar9170_regwrite(0x1c3c40, 0x1 | 1<<30);
181
182 /* rate sets */
183 ar9170_regwrite(AR9170_MAC_REG_BASIC_RATE, 0x150f);
184 ar9170_regwrite(AR9170_MAC_REG_MANDATORY_RATE, 0x150f);
185 ar9170_regwrite(AR9170_MAC_REG_RTS_CTS_RATE, 0x10b01bb);
186
187 /* MIMO response control */
188 ar9170_regwrite(0x1c3694, 0x4003C1E);/* bit 26~28 otus-AM */
189
190 /* switch MAC to OTUS interface */
191 ar9170_regwrite(0x1c3600, 0x3);
192
193 ar9170_regwrite(AR9170_MAC_REG_AMPDU_RX_THRESH, 0xffff);
194
195 /* set PHY register read timeout (??) */
196 ar9170_regwrite(AR9170_MAC_REG_MISC_680, 0xf00008);
197
198 /* Disable Rx TimeOut, workaround for BB. */
199 ar9170_regwrite(AR9170_MAC_REG_RX_TIMEOUT, 0x0);
200
201 /* Set CPU clock frequency to 88/80MHz */
202 ar9170_regwrite(AR9170_PWR_REG_CLOCK_SEL,
203 AR9170_PWR_CLK_AHB_80_88MHZ |
204 AR9170_PWR_CLK_DAC_160_INV_DLY);
205
206 /* Set WLAN DMA interrupt mode: generate int per packet */
207 ar9170_regwrite(AR9170_MAC_REG_TXRX_MPI, 0x110011);
208
209 ar9170_regwrite(AR9170_MAC_REG_FCS_SELECT,
210 AR9170_MAC_FCS_FIFO_PROT);
211
212 /* Disables the CF_END frame, undocumented register */
213 ar9170_regwrite(AR9170_MAC_REG_TXOP_NOT_ENOUGH_IND,
214 0x141E0F48);
215
216 ar9170_regwrite_finish();
217
218 return ar9170_regwrite_result();
219 }
220
221 static int ar9170_set_mac_reg(struct ar9170 *ar, const u32 reg, const u8 *mac)
222 {
223 static const u8 zero[ETH_ALEN] = { 0 };
224
225 if (!mac)
226 mac = zero;
227
228 ar9170_regwrite_begin(ar);
229
230 ar9170_regwrite(reg,
231 (mac[3] << 24) | (mac[2] << 16) |
232 (mac[1] << 8) | mac[0]);
233
234 ar9170_regwrite(reg + 4, (mac[5] << 8) | mac[4]);
235
236 ar9170_regwrite_finish();
237
238 return ar9170_regwrite_result();
239 }
240
241 int ar9170_update_multicast(struct ar9170 *ar)
242 {
243 int err;
244
245 ar9170_regwrite_begin(ar);
246 ar9170_regwrite(AR9170_MAC_REG_GROUP_HASH_TBL_H,
247 ar->want_mc_hash >> 32);
248 ar9170_regwrite(AR9170_MAC_REG_GROUP_HASH_TBL_L,
249 ar->want_mc_hash);
250
251 ar9170_regwrite_finish();
252 err = ar9170_regwrite_result();
253
254 if (err)
255 return err;
256
257 ar->cur_mc_hash = ar->want_mc_hash;
258
259 return 0;
260 }
261
262 int ar9170_update_frame_filter(struct ar9170 *ar)
263 {
264 int err;
265
266 err = ar9170_write_reg(ar, AR9170_MAC_REG_FRAMETYPE_FILTER,
267 ar->want_filter);
268
269 if (err)
270 return err;
271
272 ar->cur_filter = ar->want_filter;
273
274 return 0;
275 }
276
277 static int ar9170_set_promiscouous(struct ar9170 *ar)
278 {
279 u32 encr_mode, sniffer;
280 int err;
281
282 err = ar9170_read_reg(ar, AR9170_MAC_REG_SNIFFER, &sniffer);
283 if (err)
284 return err;
285
286 err = ar9170_read_reg(ar, AR9170_MAC_REG_ENCRYPTION, &encr_mode);
287 if (err)
288 return err;
289
290 if (ar->sniffer_enabled) {
291 sniffer |= AR9170_MAC_REG_SNIFFER_ENABLE_PROMISC;
292
293 /*
294 * Rx decryption works in place.
295 *
296 * If we don't disable it, the hardware will render all
297 * encrypted frames which are encrypted with an unknown
298 * key useless.
299 */
300
301 encr_mode |= AR9170_MAC_REG_ENCRYPTION_RX_SOFTWARE;
302 ar->sniffer_enabled = true;
303 } else {
304 sniffer &= ~AR9170_MAC_REG_SNIFFER_ENABLE_PROMISC;
305
306 if (ar->rx_software_decryption)
307 encr_mode |= AR9170_MAC_REG_ENCRYPTION_RX_SOFTWARE;
308 else
309 encr_mode &= ~AR9170_MAC_REG_ENCRYPTION_RX_SOFTWARE;
310 }
311
312 ar9170_regwrite_begin(ar);
313 ar9170_regwrite(AR9170_MAC_REG_ENCRYPTION, encr_mode);
314 ar9170_regwrite(AR9170_MAC_REG_SNIFFER, sniffer);
315 ar9170_regwrite_finish();
316
317 return ar9170_regwrite_result();
318 }
319
320 int ar9170_set_operating_mode(struct ar9170 *ar)
321 {
322 u32 pm_mode = AR9170_MAC_REG_POWERMGT_DEFAULTS;
323 u8 *mac_addr, *bssid;
324 int err;
325
326 if (ar->vif) {
327 mac_addr = ar->mac_addr;
328 bssid = ar->bssid;
329
330 switch (ar->vif->type) {
331 case NL80211_IFTYPE_MESH_POINT:
332 case NL80211_IFTYPE_ADHOC:
333 pm_mode |= AR9170_MAC_REG_POWERMGT_IBSS;
334 break;
335 case NL80211_IFTYPE_AP:
336 pm_mode |= AR9170_MAC_REG_POWERMGT_AP;
337 break;
338 case NL80211_IFTYPE_WDS:
339 pm_mode |= AR9170_MAC_REG_POWERMGT_AP_WDS;
340 break;
341 case NL80211_IFTYPE_MONITOR:
342 ar->sniffer_enabled = true;
343 ar->rx_software_decryption = true;
344 break;
345 default:
346 pm_mode |= AR9170_MAC_REG_POWERMGT_STA;
347 break;
348 }
349 } else {
350 mac_addr = NULL;
351 bssid = NULL;
352 }
353
354 err = ar9170_set_mac_reg(ar, AR9170_MAC_REG_MAC_ADDR_L, mac_addr);
355 if (err)
356 return err;
357
358 err = ar9170_set_mac_reg(ar, AR9170_MAC_REG_BSSID_L, bssid);
359 if (err)
360 return err;
361
362 err = ar9170_set_promiscouous(ar);
363 if (err)
364 return err;
365
366 /* set AMPDU density to 8us. */
367 err = ar9170_set_ampdu_density(ar, 6);
368 if (err)
369 return err;
370
371 ar9170_regwrite_begin(ar);
372
373 ar9170_regwrite(AR9170_MAC_REG_POWERMANAGEMENT, pm_mode);
374 ar9170_regwrite_finish();
375
376 return ar9170_regwrite_result();
377 }
378
379 int ar9170_set_hwretry_limit(struct ar9170 *ar, unsigned int max_retry)
380 {
381 u32 tmp = min_t(u32, 0x33333, max_retry * 0x11111);
382
383 return ar9170_write_reg(ar, AR9170_MAC_REG_RETRY_MAX, tmp);
384 }
385
386 int ar9170_set_beacon_timers(struct ar9170 *ar)
387 {
388 u32 v = 0;
389 u32 pretbtt = 0;
390
391 if (ar->vif) {
392 v |= ar->vif->bss_conf.beacon_int;
393
394 switch (ar->vif->type) {
395 case NL80211_IFTYPE_MESH_POINT:
396 case NL80211_IFTYPE_ADHOC:
397 v |= BIT(25);
398 break;
399 case NL80211_IFTYPE_AP:
400 v |= BIT(24);
401 pretbtt = (ar->vif->bss_conf.beacon_int - 6) << 16;
402 break;
403 default:
404 break;
405 }
406
407 v |= ar->vif->bss_conf.dtim_period << 16;
408 }
409
410 ar9170_regwrite_begin(ar);
411
412 ar9170_regwrite(AR9170_MAC_REG_PRETBTT, pretbtt);
413 ar9170_regwrite(AR9170_MAC_REG_BCN_PERIOD, v);
414 ar9170_regwrite_finish();
415 return ar9170_regwrite_result();
416 }
417
418 int ar9170_update_beacon(struct ar9170 *ar)
419 {
420 struct sk_buff *skb;
421 __le32 *data, *old = NULL;
422 u32 word;
423 int i;
424
425 skb = ieee80211_beacon_get(ar->hw, ar->vif);
426 if (!skb)
427 return -ENOMEM;
428
429 data = (__le32 *)skb->data;
430 if (ar->beacon)
431 old = (__le32 *)ar->beacon->data;
432
433 ar9170_regwrite_begin(ar);
434 for (i = 0; i < DIV_ROUND_UP(skb->len, 4); i++) {
435 /*
436 * XXX: This accesses beyond skb data for up
437 * to the last 3 bytes!!
438 */
439
440 if (old && (data[i] == old[i]))
441 continue;
442
443 word = le32_to_cpu(data[i]);
444 ar9170_regwrite(AR9170_BEACON_BUFFER_ADDRESS + 4 * i, word);
445 }
446
447 /* XXX: use skb->cb info */
448 if (ar->hw->conf.channel->band == IEEE80211_BAND_2GHZ)
449 ar9170_regwrite(AR9170_MAC_REG_BCN_PLCP,
450 ((skb->len + 4) << (3 + 16)) + 0x0400);
451 else
452 ar9170_regwrite(AR9170_MAC_REG_BCN_PLCP,
453 ((skb->len + 4) << 16) + 0x001b);
454
455 ar9170_regwrite(AR9170_MAC_REG_BCN_LENGTH, skb->len + 4);
456 ar9170_regwrite(AR9170_MAC_REG_BCN_ADDR, AR9170_BEACON_BUFFER_ADDRESS);
457 ar9170_regwrite(AR9170_MAC_REG_BCN_CTRL, 1);
458
459 ar9170_regwrite_finish();
460
461 dev_kfree_skb(ar->beacon);
462 ar->beacon = skb;
463
464 return ar9170_regwrite_result();
465 }
466
467 void ar9170_new_beacon(struct work_struct *work)
468 {
469 struct ar9170 *ar = container_of(work, struct ar9170,
470 beacon_work);
471 struct sk_buff *skb;
472
473 if (unlikely(!IS_STARTED(ar)))
474 return ;
475
476 mutex_lock(&ar->mutex);
477
478 if (!ar->vif)
479 goto out;
480
481 ar9170_update_beacon(ar);
482
483 rcu_read_lock();
484 while ((skb = ieee80211_get_buffered_bc(ar->hw, ar->vif)))
485 ar9170_op_tx(ar->hw, skb);
486
487 rcu_read_unlock();
488
489 out:
490 mutex_unlock(&ar->mutex);
491 }
492
493 int ar9170_upload_key(struct ar9170 *ar, u8 id, const u8 *mac, u8 ktype,
494 u8 keyidx, u8 *keydata, int keylen)
495 {
496 __le32 vals[7];
497 static const u8 bcast[ETH_ALEN] =
498 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
499 u8 dummy;
500
501 mac = mac ? : bcast;
502
503 vals[0] = cpu_to_le32((keyidx << 16) + id);
504 vals[1] = cpu_to_le32(mac[1] << 24 | mac[0] << 16 | ktype);
505 vals[2] = cpu_to_le32(mac[5] << 24 | mac[4] << 16 |
506 mac[3] << 8 | mac[2]);
507 memset(&vals[3], 0, 16);
508 if (keydata)
509 memcpy(&vals[3], keydata, keylen);
510
511 return ar->exec_cmd(ar, AR9170_CMD_EKEY,
512 sizeof(vals), (u8 *)vals,
513 1, &dummy);
514 }
515
516 int ar9170_disable_key(struct ar9170 *ar, u8 id)
517 {
518 __le32 val = cpu_to_le32(id);
519 u8 dummy;
520
521 return ar->exec_cmd(ar, AR9170_CMD_EKEY,
522 sizeof(val), (u8 *)&val,
523 1, &dummy);
524 }
525
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