1 /*
2 * wanXL serial card driver for Linux
3 * host part
4 *
5 * Copyright (C) 2003 Krzysztof Halasa <khc@pm.waw.pl>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of version 2 of the GNU General Public License
9 * as published by the Free Software Foundation.
10 *
11 * Status:
12 * - Only DTE (external clock) support with NRZ and NRZI encodings
13 * - wanXL100 will require minor driver modifications, no access to hw
14 */
15
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/slab.h>
19 #include <linux/sched.h>
20 #include <linux/types.h>
21 #include <linux/fcntl.h>
22 #include <linux/string.h>
23 #include <linux/errno.h>
24 #include <linux/init.h>
25 #include <linux/ioport.h>
26 #include <linux/netdevice.h>
27 #include <linux/hdlc.h>
28 #include <linux/pci.h>
29 #include <asm/io.h>
30 #include <asm/delay.h>
31
32 #include "wanxl.h"
33
34 static const char* version = "wanXL serial card driver version: 0.48";
35
36 #define PLX_CTL_RESET 0x40000000 /* adapter reset */
37
38 #undef DEBUG_PKT
39 #undef DEBUG_PCI
40
41 /* MAILBOX #1 - PUTS COMMANDS */
42 #define MBX1_CMD_ABORTJ 0x85000000 /* Abort and Jump */
43 #ifdef __LITTLE_ENDIAN
44 #define MBX1_CMD_BSWAP 0x8C000001 /* little-endian Byte Swap Mode */
45 #else
46 #define MBX1_CMD_BSWAP 0x8C000000 /* big-endian Byte Swap Mode */
47 #endif
48
49 /* MAILBOX #2 - DRAM SIZE */
50 #define MBX2_MEMSZ_MASK 0xFFFF0000 /* PUTS Memory Size Register mask */
51
52
53 typedef struct {
54 struct net_device *dev;
55 struct card_t *card;
56 spinlock_t lock; /* for wanxl_xmit */
57 int node; /* physical port #0 - 3 */
58 unsigned int clock_type;
59 int tx_in, tx_out;
60 struct sk_buff *tx_skbs[TX_BUFFERS];
61 }port_t;
62
63
64 typedef struct {
65 desc_t rx_descs[RX_QUEUE_LENGTH];
66 port_status_t port_status[4];
67 }card_status_t;
68
69
70 typedef struct card_t {
71 int n_ports; /* 1, 2 or 4 ports */
72 u8 irq;
73
74 u8 __iomem *plx; /* PLX PCI9060 virtual base address */
75 struct pci_dev *pdev; /* for pdev->slot_name */
76 int rx_in;
77 struct sk_buff *rx_skbs[RX_QUEUE_LENGTH];
78 card_status_t *status; /* shared between host and card */
79 dma_addr_t status_address;
80 port_t ports[0]; /* 1 - 4 port_t structures follow */
81 }card_t;
82
83
84
85 static inline port_t* dev_to_port(struct net_device *dev)
86 {
87 return (port_t *)dev_to_hdlc(dev)->priv;
88 }
89
90
91 static inline const char* card_name(struct pci_dev *pdev)
92 {
93 return pdev->slot_name;
94 }
95
96
97 static inline port_status_t* get_status(port_t *port)
98 {
99 return &port->card->status->port_status[port->node];
100 }
101
102
103 #ifdef DEBUG_PCI
104 static inline dma_addr_t pci_map_single_debug(struct pci_dev *pdev, void *ptr,
105 size_t size, int direction)
106 {
107 dma_addr_t addr = pci_map_single(pdev, ptr, size, direction);
108 if (addr + size > 0x100000000LL)
109 printk(KERN_CRIT "wanXL %s: pci_map_single() returned memory"
110 " at 0x%LX!\n", card_name(pdev),
111 (unsigned long long)addr);
112 return addr;
113 }
114
115 #undef pci_map_single
116 #define pci_map_single pci_map_single_debug
117 #endif
118
119
120 /* Cable and/or personality module change interrupt service */
121 static inline void wanxl_cable_intr(port_t *port)
122 {
123 u32 value = get_status(port)->cable;
124 int valid = 1;
125 const char *cable, *pm, *dte = "", *dsr = "", *dcd = "";
126
127 switch(value & 0x7) {
128 case STATUS_CABLE_V35: cable = "V.35"; break;
129 case STATUS_CABLE_X21: cable = "X.21"; break;
130 case STATUS_CABLE_V24: cable = "V.24"; break;
131 case STATUS_CABLE_EIA530: cable = "EIA530"; break;
132 case STATUS_CABLE_NONE: cable = "no"; break;
133 default: cable = "invalid";
134 }
135
136 switch((value >> STATUS_CABLE_PM_SHIFT) & 0x7) {
137 case STATUS_CABLE_V35: pm = "V.35"; break;
138 case STATUS_CABLE_X21: pm = "X.21"; break;
139 case STATUS_CABLE_V24: pm = "V.24"; break;
140 case STATUS_CABLE_EIA530: pm = "EIA530"; break;
141 case STATUS_CABLE_NONE: pm = "no personality"; valid = 0; break;
142 default: pm = "invalid personality"; valid = 0;
143 }
144
145 if (valid) {
146 if ((value & 7) == ((value >> STATUS_CABLE_PM_SHIFT) & 7)) {
147 dsr = (value & STATUS_CABLE_DSR) ? ", DSR ON" :
148 ", DSR off";
149 dcd = (value & STATUS_CABLE_DCD) ? ", carrier ON" :
150 ", carrier off";
151 }
152 dte = (value & STATUS_CABLE_DCE) ? " DCE" : " DTE";
153 }
154 printk(KERN_INFO "%s: %s%s module, %s cable%s%s\n",
155 port->dev->name, pm, dte, cable, dsr, dcd);
156
157 hdlc_set_carrier(value & STATUS_CABLE_DCD, port->dev);
158 }
159
160
161
162 /* Transmit complete interrupt service */
163 static inline void wanxl_tx_intr(port_t *port)
164 {
165 struct net_device *dev = port->dev;
166 struct net_device_stats *stats = hdlc_stats(dev);
167 while (1) {
168 desc_t *desc = &get_status(port)->tx_descs[port->tx_in];
169 struct sk_buff *skb = port->tx_skbs[port->tx_in];
170
171 switch (desc->stat) {
172 case PACKET_FULL:
173 case PACKET_EMPTY:
174 netif_wake_queue(dev);
175 return;
176
177 case PACKET_UNDERRUN:
178 stats->tx_errors++;
179 stats->tx_fifo_errors++;
180 break;
181
182 default:
183 stats->tx_packets++;
184 stats->tx_bytes += skb->len;
185 }
186 desc->stat = PACKET_EMPTY; /* Free descriptor */
187 pci_unmap_single(port->card->pdev, desc->address, skb->len,
188 PCI_DMA_TODEVICE);
189 dev_kfree_skb_irq(skb);
190 port->tx_in = (port->tx_in + 1) % TX_BUFFERS;
191 }
192 }
193
194
195
196 /* Receive complete interrupt service */
197 static inline void wanxl_rx_intr(card_t *card)
198 {
199 desc_t *desc;
200 while (desc = &card->status->rx_descs[card->rx_in],
201 desc->stat != PACKET_EMPTY) {
202 if ((desc->stat & PACKET_PORT_MASK) > card->n_ports)
203 printk(KERN_CRIT "wanXL %s: received packet for"
204 " nonexistent port\n", card_name(card->pdev));
205 else {
206 struct sk_buff *skb = card->rx_skbs[card->rx_in];
207 port_t *port = &card->ports[desc->stat &
208 PACKET_PORT_MASK];
209 struct net_device *dev = port->dev;
210 struct net_device_stats *stats = hdlc_stats(dev);
211
212 if (!skb)
213 stats->rx_dropped++;
214 else {
215 pci_unmap_single(card->pdev, desc->address,
216 BUFFER_LENGTH,
217 PCI_DMA_FROMDEVICE);
218 skb_put(skb, desc->length);
219
220 #ifdef DEBUG_PKT
221 printk(KERN_DEBUG "%s RX(%i):", dev->name,
222 skb->len);
223 debug_frame(skb);
224 #endif
225 stats->rx_packets++;
226 stats->rx_bytes += skb->len;
227 dev->last_rx = jiffies;
228 skb->protocol = hdlc_type_trans(skb, dev);
229 netif_rx(skb);
230 skb = NULL;
231 }
232
233 if (!skb) {
234 skb = dev_alloc_skb(BUFFER_LENGTH);
235 desc->address = skb ?
236 pci_map_single(card->pdev, skb->data,
237 BUFFER_LENGTH,
238 PCI_DMA_FROMDEVICE) : 0;
239 card->rx_skbs[card->rx_in] = skb;
240 }
241 }
242 desc->stat = PACKET_EMPTY; /* Free descriptor */
243 card->rx_in = (card->rx_in + 1) % RX_QUEUE_LENGTH;
244 }
245 }
246
247
248
249 static irqreturn_t wanxl_intr(int irq, void* dev_id, struct pt_regs *regs)
250 {
251 card_t *card = dev_id;
252 int i;
253 u32 stat;
254 int handled = 0;
255
256
257 while((stat = readl(card->plx + PLX_DOORBELL_FROM_CARD)) != 0) {
258 handled = 1;
259 writel(stat, card->plx + PLX_DOORBELL_FROM_CARD);
260
261 for (i = 0; i < card->n_ports; i++) {
262 if (stat & (1 << (DOORBELL_FROM_CARD_TX_0 + i)))
263 wanxl_tx_intr(&card->ports[i]);
264 if (stat & (1 << (DOORBELL_FROM_CARD_CABLE_0 + i)))
265 wanxl_cable_intr(&card->ports[i]);
266 }
267 if (stat & (1 << DOORBELL_FROM_CARD_RX))
268 wanxl_rx_intr(card);
269 }
270
271 return IRQ_RETVAL(handled);
272 }
273
274
275
276 static int wanxl_xmit(struct sk_buff *skb, struct net_device *dev)
277 {
278 port_t *port = dev_to_port(dev);
279 desc_t *desc;
280
281 spin_lock(&port->lock);
282
283 desc = &get_status(port)->tx_descs[port->tx_out];
284 if (desc->stat != PACKET_EMPTY) {
285 /* should never happen - previous xmit should stop queue */
286 #ifdef DEBUG_PKT
287 printk(KERN_DEBUG "%s: transmitter buffer full\n", dev->name);
288 #endif
289 netif_stop_queue(dev);
290 spin_unlock_irq(&port->lock);
291 return 1; /* request packet to be queued */
292 }
293
294 #ifdef DEBUG_PKT
295 printk(KERN_DEBUG "%s TX(%i):", dev->name, skb->len);
296 debug_frame(skb);
297 #endif
298
299 port->tx_skbs[port->tx_out] = skb;
300 desc->address = pci_map_single(port->card->pdev, skb->data, skb->len,
301 PCI_DMA_TODEVICE);
302 desc->length = skb->len;
303 desc->stat = PACKET_FULL;
304 writel(1 << (DOORBELL_TO_CARD_TX_0 + port->node),
305 port->card->plx + PLX_DOORBELL_TO_CARD);
306 dev->trans_start = jiffies;
307
308 port->tx_out = (port->tx_out + 1) % TX_BUFFERS;
309
310 if (get_status(port)->tx_descs[port->tx_out].stat != PACKET_EMPTY) {
311 netif_stop_queue(dev);
312 #ifdef DEBUG_PKT
313 printk(KERN_DEBUG "%s: transmitter buffer full\n", dev->name);
314 #endif
315 }
316
317 spin_unlock(&port->lock);
318 return 0;
319 }
320
321
322
323 static int wanxl_attach(struct net_device *dev, unsigned short encoding,
324 unsigned short parity)
325 {
326 port_t *port = dev_to_port(dev);
327
328 if (encoding != ENCODING_NRZ &&
329 encoding != ENCODING_NRZI)
330 return -EINVAL;
331
332 if (parity != PARITY_NONE &&
333 parity != PARITY_CRC32_PR1_CCITT &&
334 parity != PARITY_CRC16_PR1_CCITT &&
335 parity != PARITY_CRC32_PR0_CCITT &&
336 parity != PARITY_CRC16_PR0_CCITT)
337 return -EINVAL;
338
339 get_status(port)->encoding = encoding;
340 get_status(port)->parity = parity;
341 return 0;
342 }
343
344
345
346 static int wanxl_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
347 {
348 const size_t size = sizeof(sync_serial_settings);
349 sync_serial_settings line;
350 port_t *port = dev_to_port(dev);
351
352 if (cmd != SIOCWANDEV)
353 return hdlc_ioctl(dev, ifr, cmd);
354
355 switch (ifr->ifr_settings.type) {
356 case IF_GET_IFACE:
357 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
358 if (ifr->ifr_settings.size < size) {
359 ifr->ifr_settings.size = size; /* data size wanted */
360 return -ENOBUFS;
361 }
362 line.clock_type = get_status(port)->clocking;
363 line.clock_rate = 0;
364 line.loopback = 0;
365
366 if (copy_to_user(ifr->ifr_settings.ifs_ifsu.sync, &line, size))
367 return -EFAULT;
368 return 0;
369
370 case IF_IFACE_SYNC_SERIAL:
371 if (!capable(CAP_NET_ADMIN))
372 return -EPERM;
373 if (dev->flags & IFF_UP)
374 return -EBUSY;
375
376 if (copy_from_user(&line, ifr->ifr_settings.ifs_ifsu.sync,
377 size))
378 return -EFAULT;
379
380 if (line.clock_type != CLOCK_EXT &&
381 line.clock_type != CLOCK_TXFROMRX)
382 return -EINVAL; /* No such clock setting */
383
384 if (line.loopback != 0)
385 return -EINVAL;
386
387 get_status(port)->clocking = line.clock_type;
388 return 0;
389
390 default:
391 return hdlc_ioctl(dev, ifr, cmd);
392 }
393 }
394
395
396
397 static int wanxl_open(struct net_device *dev)
398 {
399 port_t *port = dev_to_port(dev);
400 u8 __iomem *dbr = port->card->plx + PLX_DOORBELL_TO_CARD;
401 unsigned long timeout;
402 int i;
403
404 if (get_status(port)->open) {
405 printk(KERN_ERR "%s: port already open\n", dev->name);
406 return -EIO;
407 }
408 if ((i = hdlc_open(dev)) != 0)
409 return i;
410
411 port->tx_in = port->tx_out = 0;
412 for (i = 0; i < TX_BUFFERS; i++)
413 get_status(port)->tx_descs[i].stat = PACKET_EMPTY;
414 /* signal the card */
415 writel(1 << (DOORBELL_TO_CARD_OPEN_0 + port->node), dbr);
416
417 timeout = jiffies + HZ;
418 do
419 if (get_status(port)->open) {
420 netif_start_queue(dev);
421 return 0;
422 }
423 while (time_after(timeout, jiffies));
424
425 printk(KERN_ERR "%s: unable to open port\n", dev->name);
426 /* ask the card to close the port, should it be still alive */
427 writel(1 << (DOORBELL_TO_CARD_CLOSE_0 + port->node), dbr);
428 return -EFAULT;
429 }
430
431
432
433 static int wanxl_close(struct net_device *dev)
434 {
435 port_t *port = dev_to_port(dev);
436 unsigned long timeout;
437 int i;
438
439 hdlc_close(dev);
440 /* signal the card */
441 writel(1 << (DOORBELL_TO_CARD_CLOSE_0 + port->node),
442 port->card->plx + PLX_DOORBELL_TO_CARD);
443
444 timeout = jiffies + HZ;
445 do
446 if (!get_status(port)->open)
447 break;
448 while (time_after(timeout, jiffies));
449
450 if (get_status(port)->open)
451 printk(KERN_ERR "%s: unable to close port\n", dev->name);
452
453 netif_stop_queue(dev);
454
455 for (i = 0; i < TX_BUFFERS; i++) {
456 desc_t *desc = &get_status(port)->tx_descs[i];
457
458 if (desc->stat != PACKET_EMPTY) {
459 desc->stat = PACKET_EMPTY;
460 pci_unmap_single(port->card->pdev, desc->address,
461 port->tx_skbs[i]->len,
462 PCI_DMA_TODEVICE);
463 dev_kfree_skb(port->tx_skbs[i]);
464 }
465 }
466 return 0;
467 }
468
469
470
471 static struct net_device_stats *wanxl_get_stats(struct net_device *dev)
472 {
473 struct net_device_stats *stats = hdlc_stats(dev);
474 port_t *port = dev_to_port(dev);
475
476 stats->rx_over_errors = get_status(port)->rx_overruns;
477 stats->rx_frame_errors = get_status(port)->rx_frame_errors;
478 stats->rx_errors = stats->rx_over_errors + stats->rx_frame_errors;
479 return stats;
480 }
481
482
483
484 static int wanxl_puts_command(card_t *card, u32 cmd)
485 {
486 unsigned long timeout = jiffies + 5 * HZ;
487
488 writel(cmd, card->plx + PLX_MAILBOX_1);
489 do {
490 if (readl(card->plx + PLX_MAILBOX_1) == 0)
491 return 0;
492
493 schedule();
494 }while (time_after(timeout, jiffies));
495
496 return -1;
497 }
498
499
500
501 static void wanxl_reset(card_t *card)
502 {
503 u32 old_value = readl(card->plx + PLX_CONTROL) & ~PLX_CTL_RESET;
504
505 writel(0x80, card->plx + PLX_MAILBOX_0);
506 writel(old_value | PLX_CTL_RESET, card->plx + PLX_CONTROL);
507 readl(card->plx + PLX_CONTROL); /* wait for posted write */
508 udelay(1);
509 writel(old_value, card->plx + PLX_CONTROL);
510 readl(card->plx + PLX_CONTROL); /* wait for posted write */
511 }
512
513
514
515 static void wanxl_pci_remove_one(struct pci_dev *pdev)
516 {
517 card_t *card = pci_get_drvdata(pdev);
518 int i;
519
520 for (i = 0; i < card->n_ports; i++) {
521 unregister_hdlc_device(card->ports[i].dev);
522 free_netdev(card->ports[i].dev);
523 }
524
525 /* unregister and free all host resources */
526 if (card->irq)
527 free_irq(card->irq, card);
528
529 wanxl_reset(card);
530
531 for (i = 0; i < RX_QUEUE_LENGTH; i++)
532 if (card->rx_skbs[i]) {
533 pci_unmap_single(card->pdev,
534 card->status->rx_descs[i].address,
535 BUFFER_LENGTH, PCI_DMA_FROMDEVICE);
536 dev_kfree_skb(card->rx_skbs[i]);
537 }
538
539 if (card->plx)
540 iounmap(card->plx);
541
542 if (card->status)
543 pci_free_consistent(pdev, sizeof(card_status_t),
544 card->status, card->status_address);
545
546 pci_release_regions(pdev);
547 pci_disable_device(pdev);
548 pci_set_drvdata(pdev, NULL);
549 kfree(card);
550 }
551
552
553 #include "wanxlfw.inc"
554
555 static int __devinit wanxl_pci_init_one(struct pci_dev *pdev,
556 const struct pci_device_id *ent)
557 {
558 card_t *card;
559 u32 ramsize, stat;
560 unsigned long timeout;
561 u32 plx_phy; /* PLX PCI base address */
562 u32 mem_phy; /* memory PCI base addr */
563 u8 __iomem *mem; /* memory virtual base addr */
564 int i, ports, alloc_size;
565
566 #ifndef MODULE
567 static int printed_version;
568 if (!printed_version) {
569 printed_version++;
570 printk(KERN_INFO "%s\n", version);
571 }
572 #endif
573
574 i = pci_enable_device(pdev);
575 if (i)
576 return i;
577
578 /* QUICC can only access first 256 MB of host RAM directly,
579 but PLX9060 DMA does 32-bits for actual packet data transfers */
580
581 /* FIXME when PCI/DMA subsystems are fixed.
582 We set both dma_mask and consistent_dma_mask to 28 bits
583 and pray pci_alloc_consistent() will use this info. It should
584 work on most platforms */
585 if (pci_set_consistent_dma_mask(pdev, 0x0FFFFFFF) ||
586 pci_set_dma_mask(pdev, 0x0FFFFFFF)) {
587 printk(KERN_ERR "wanXL: No usable DMA configuration\n");
588 return -EIO;
589 }
590
591 i = pci_request_regions(pdev, "wanXL");
592 if (i) {
593 pci_disable_device(pdev);
594 return i;
595 }
596
597 switch (pdev->device) {
598 case PCI_DEVICE_ID_SBE_WANXL100: ports = 1; break;
599 case PCI_DEVICE_ID_SBE_WANXL200: ports = 2; break;
600 default: ports = 4;
601 }
602
603 alloc_size = sizeof(card_t) + ports * sizeof(port_t);
604 card = kmalloc(alloc_size, GFP_KERNEL);
605 if (card == NULL) {
606 printk(KERN_ERR "wanXL %s: unable to allocate memory\n",
607 card_name(pdev));
608 pci_release_regions(pdev);
609 pci_disable_device(pdev);
610 return -ENOBUFS;
611 }
612 memset(card, 0, alloc_size);
613
614 pci_set_drvdata(pdev, card);
615 card->pdev = pdev;
616
617 card->status = pci_alloc_consistent(pdev, sizeof(card_status_t),
618 &card->status_address);
619 if (card->status == NULL) {
620 wanxl_pci_remove_one(pdev);
621 return -ENOBUFS;
622 }
623
624 #ifdef DEBUG_PCI
625 printk(KERN_DEBUG "wanXL %s: pci_alloc_consistent() returned memory"
626 " at 0x%LX\n", card_name(pdev),
627 (unsigned long long)card->status_address);
628 #endif
629
630 /* FIXME when PCI/DMA subsystems are fixed.
631 We set both dma_mask and consistent_dma_mask back to 32 bits
632 to indicate the card can do 32-bit DMA addressing */
633 if (pci_set_consistent_dma_mask(pdev, 0xFFFFFFFF) ||
634 pci_set_dma_mask(pdev, 0xFFFFFFFF)) {
635 printk(KERN_ERR "wanXL: No usable DMA configuration\n");
636 wanxl_pci_remove_one(pdev);
637 return -EIO;
638 }
639
640 /* set up PLX mapping */
641 plx_phy = pci_resource_start(pdev, 0);
642 card->plx = ioremap_nocache(plx_phy, 0x70);
643
644 #if RESET_WHILE_LOADING
645 wanxl_reset(card);
646 #endif
647
648 timeout = jiffies + 20 * HZ;
649 while ((stat = readl(card->plx + PLX_MAILBOX_0)) != 0) {
650 if (time_before(timeout, jiffies)) {
651 printk(KERN_WARNING "wanXL %s: timeout waiting for"
652 " PUTS to complete\n", card_name(pdev));
653 wanxl_pci_remove_one(pdev);
654 return -ENODEV;
655 }
656
657 switch(stat & 0xC0) {
658 case 0x00: /* hmm - PUTS completed with non-zero code? */
659 case 0x80: /* PUTS still testing the hardware */
660 break;
661
662 default:
663 printk(KERN_WARNING "wanXL %s: PUTS test 0x%X"
664 " failed\n", card_name(pdev), stat & 0x30);
665 wanxl_pci_remove_one(pdev);
666 return -ENODEV;
667 }
668
669 schedule();
670 }
671
672 /* get on-board memory size (PUTS detects no more than 4 MB) */
673 ramsize = readl(card->plx + PLX_MAILBOX_2) & MBX2_MEMSZ_MASK;
674
675 /* set up on-board RAM mapping */
676 mem_phy = pci_resource_start(pdev, 2);
677
678
679 /* sanity check the board's reported memory size */
680 if (ramsize < BUFFERS_ADDR +
681 (TX_BUFFERS + RX_BUFFERS) * BUFFER_LENGTH * ports) {
682 printk(KERN_WARNING "wanXL %s: no enough on-board RAM"
683 " (%u bytes detected, %u bytes required)\n",
684 card_name(pdev), ramsize, BUFFERS_ADDR +
685 (TX_BUFFERS + RX_BUFFERS) * BUFFER_LENGTH * ports);
686 wanxl_pci_remove_one(pdev);
687 return -ENODEV;
688 }
689
690 if (wanxl_puts_command(card, MBX1_CMD_BSWAP)) {
691 printk(KERN_WARNING "wanXL %s: unable to Set Byte Swap"
692 " Mode\n", card_name(pdev));
693 wanxl_pci_remove_one(pdev);
694 return -ENODEV;
695 }
696
697 for (i = 0; i < RX_QUEUE_LENGTH; i++) {
698 struct sk_buff *skb = dev_alloc_skb(BUFFER_LENGTH);
699 card->rx_skbs[i] = skb;
700 if (skb)
701 card->status->rx_descs[i].address =
702 pci_map_single(card->pdev, skb->data,
703 BUFFER_LENGTH,
704 PCI_DMA_FROMDEVICE);
705 }
706
707 mem = ioremap_nocache(mem_phy, PDM_OFFSET + sizeof(firmware));
708 for (i = 0; i < sizeof(firmware); i += 4)
709 writel(htonl(*(u32*)(firmware + i)), mem + PDM_OFFSET + i);
710
711 for (i = 0; i < ports; i++)
712 writel(card->status_address +
713 (void *)&card->status->port_status[i] -
714 (void *)card->status, mem + PDM_OFFSET + 4 + i * 4);
715 writel(card->status_address, mem + PDM_OFFSET + 20);
716 writel(PDM_OFFSET, mem);
717 iounmap(mem);
718
719 writel(0, card->plx + PLX_MAILBOX_5);
720
721 if (wanxl_puts_command(card, MBX1_CMD_ABORTJ)) {
722 printk(KERN_WARNING "wanXL %s: unable to Abort and Jump\n",
723 card_name(pdev));
724 wanxl_pci_remove_one(pdev);
725 return -ENODEV;
726 }
727
728 stat = 0;
729 timeout = jiffies + 5 * HZ;
730 do {
731 if ((stat = readl(card->plx + PLX_MAILBOX_5)) != 0)
732 break;
733 schedule();
734 }while (time_after(timeout, jiffies));
735
736 if (!stat) {
737 printk(KERN_WARNING "wanXL %s: timeout while initializing card"
738 "firmware\n", card_name(pdev));
739 wanxl_pci_remove_one(pdev);
740 return -ENODEV;
741 }
742
743 #if DETECT_RAM
744 ramsize = stat;
745 #endif
746
747 printk(KERN_INFO "wanXL %s: at 0x%X, %u KB of RAM at 0x%X, irq %u\n",
748 card_name(pdev), plx_phy, ramsize / 1024, mem_phy, pdev->irq);
749
750 /* Allocate IRQ */
751 if (request_irq(pdev->irq, wanxl_intr, SA_SHIRQ, "wanXL", card)) {
752 printk(KERN_WARNING "wanXL %s: could not allocate IRQ%i.\n",
753 card_name(pdev), pdev->irq);
754 wanxl_pci_remove_one(pdev);
755 return -EBUSY;
756 }
757 card->irq = pdev->irq;
758
759 for (i = 0; i < ports; i++) {
760 hdlc_device *hdlc;
761 port_t *port = &card->ports[i];
762 struct net_device *dev = alloc_hdlcdev(port);
763 if (!dev) {
764 printk(KERN_ERR "wanXL %s: unable to allocate"
765 " memory\n", card_name(pdev));
766 wanxl_pci_remove_one(pdev);
767 return -ENOMEM;
768 }
769
770 port->dev = dev;
771 hdlc = dev_to_hdlc(dev);
772 spin_lock_init(&port->lock);
773 SET_MODULE_OWNER(dev);
774 dev->tx_queue_len = 50;
775 dev->do_ioctl = wanxl_ioctl;
776 dev->open = wanxl_open;
777 dev->stop = wanxl_close;
778 hdlc->attach = wanxl_attach;
779 hdlc->xmit = wanxl_xmit;
780 dev->get_stats = wanxl_get_stats;
781 port->card = card;
782 port->node = i;
783 get_status(port)->clocking = CLOCK_EXT;
784 if (register_hdlc_device(dev)) {
785 printk(KERN_ERR "wanXL %s: unable to register hdlc"
786 " device\n", card_name(pdev));
787 free_netdev(dev);
788 wanxl_pci_remove_one(pdev);
789 return -ENOBUFS;
790 }
791 card->n_ports++;
792 }
793
794 printk(KERN_INFO "wanXL %s: port", card_name(pdev));
795 for (i = 0; i < ports; i++)
796 printk("%s #%i: %s", i ? "," : "", i,
797 card->ports[i].dev->name);
798 printk("\n");
799
800 for (i = 0; i < ports; i++)
801 wanxl_cable_intr(&card->ports[i]); /* get carrier status etc.*/
802
803 return 0;
804 }
805
806 static struct pci_device_id wanxl_pci_tbl[] __devinitdata = {
807 { PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_SBE_WANXL100, PCI_ANY_ID,
808 PCI_ANY_ID, 0, 0, 0 },
809 { PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_SBE_WANXL200, PCI_ANY_ID,
810 PCI_ANY_ID, 0, 0, 0 },
811 { PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_SBE_WANXL400, PCI_ANY_ID,
812 PCI_ANY_ID, 0, 0, 0 },
813 { 0, }
814 };
815
816
817 static struct pci_driver wanxl_pci_driver = {
818 .name = "wanXL",
819 .id_table = wanxl_pci_tbl,
820 .probe = wanxl_pci_init_one,
821 .remove = wanxl_pci_remove_one,
822 };
823
824
825 static int __init wanxl_init_module(void)
826 {
827 #ifdef MODULE
828 printk(KERN_INFO "%s\n", version);
829 #endif
830 return pci_module_init(&wanxl_pci_driver);
831 }
832
833 static void __exit wanxl_cleanup_module(void)
834 {
835 pci_unregister_driver(&wanxl_pci_driver);
836 }
837
838
839 MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>");
840 MODULE_DESCRIPTION("SBE Inc. wanXL serial port driver");
841 MODULE_LICENSE("GPL v2");
842 MODULE_DEVICE_TABLE(pci, wanxl_pci_tbl);
843
844 module_init(wanxl_init_module);
845 module_exit(wanxl_cleanup_module);
846
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