1 /*
2 * Moxa C101 synchronous serial card driver for Linux
3 *
4 * Copyright (C) 2000-2003 Krzysztof Halasa <khc@pm.waw.pl>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License
8 * as published by the Free Software Foundation.
9 *
10 * For information see http://hq.pm.waw.pl/hdlc/
11 *
12 * Sources of information:
13 * Hitachi HD64570 SCA User's Manual
14 * Moxa C101 User's Manual
15 */
16
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/slab.h>
20 #include <linux/types.h>
21 #include <linux/string.h>
22 #include <linux/errno.h>
23 #include <linux/init.h>
24 #include <linux/moduleparam.h>
25 #include <linux/netdevice.h>
26 #include <linux/hdlc.h>
27 #include <linux/delay.h>
28 #include <asm/io.h>
29
30 #include "hd64570.h"
31
32
33 static const char* version = "Moxa C101 driver version: 1.15";
34 static const char* devname = "C101";
35
36 #undef DEBUG_PKT
37 #define DEBUG_RINGS
38
39 #define C101_PAGE 0x1D00
40 #define C101_DTR 0x1E00
41 #define C101_SCA 0x1F00
42 #define C101_WINDOW_SIZE 0x2000
43 #define C101_MAPPED_RAM_SIZE 0x4000
44
45 #define RAM_SIZE (256 * 1024)
46 #define TX_RING_BUFFERS 10
47 #define RX_RING_BUFFERS ((RAM_SIZE - C101_WINDOW_SIZE) / \
48 (sizeof(pkt_desc) + HDLC_MAX_MRU) - TX_RING_BUFFERS)
49
50 #define CLOCK_BASE 9830400 /* 9.8304 MHz */
51 #define PAGE0_ALWAYS_MAPPED
52
53 static char *hw; /* pointer to hw=xxx command line string */
54
55
56 typedef struct card_s {
57 struct net_device *dev;
58 spinlock_t lock; /* TX lock */
59 u8 __iomem *win0base; /* ISA window base address */
60 u32 phy_winbase; /* ISA physical base address */
61 sync_serial_settings settings;
62 int rxpart; /* partial frame received, next frame invalid*/
63 unsigned short encoding;
64 unsigned short parity;
65 u16 rx_ring_buffers; /* number of buffers in a ring */
66 u16 tx_ring_buffers;
67 u16 buff_offset; /* offset of first buffer of first channel */
68 u16 rxin; /* rx ring buffer 'in' pointer */
69 u16 txin; /* tx ring buffer 'in' and 'last' pointers */
70 u16 txlast;
71 u8 rxs, txs, tmc; /* SCA registers */
72 u8 irq; /* IRQ (3-15) */
73 u8 page;
74
75 struct card_s *next_card;
76 }card_t;
77
78 typedef card_t port_t;
79
80 static card_t *first_card;
81 static card_t **new_card = &first_card;
82
83
84 #define sca_in(reg, card) readb((card)->win0base + C101_SCA + (reg))
85 #define sca_out(value, reg, card) writeb(value, (card)->win0base + C101_SCA + (reg))
86 #define sca_inw(reg, card) readw((card)->win0base + C101_SCA + (reg))
87
88 /* EDA address register must be set in EDAL, EDAH order - 8 bit ISA bus */
89 #define sca_outw(value, reg, card) do { \
90 writeb(value & 0xFF, (card)->win0base + C101_SCA + (reg)); \
91 writeb((value >> 8 ) & 0xFF, (card)->win0base + C101_SCA + (reg+1));\
92 } while(0)
93
94 #define port_to_card(port) (port)
95 #define log_node(port) (0)
96 #define phy_node(port) (0)
97 #define winsize(card) (C101_WINDOW_SIZE)
98 #define win0base(card) ((card)->win0base)
99 #define winbase(card) ((card)->win0base + 0x2000)
100 #define get_port(card, port) (card)
101 static void sca_msci_intr(port_t *port);
102
103
104 static inline u8 sca_get_page(card_t *card)
105 {
106 return card->page;
107 }
108
109 static inline void openwin(card_t *card, u8 page)
110 {
111 card->page = page;
112 writeb(page, card->win0base + C101_PAGE);
113 }
114
115
116 #include "hd6457x.c"
117
118
119 static void sca_msci_intr(port_t *port)
120 {
121 struct net_device *dev = port_to_dev(port);
122 card_t* card = port_to_card(port);
123 u8 stat = sca_in(MSCI1_OFFSET + ST1, card); /* read MSCI ST1 status */
124
125 /* Reset MSCI TX underrun status bit */
126 sca_out(stat & ST1_UDRN, MSCI0_OFFSET + ST1, card);
127
128 if (stat & ST1_UDRN) {
129 struct net_device_stats *stats = hdlc_stats(dev);
130 stats->tx_errors++; /* TX Underrun error detected */
131 stats->tx_fifo_errors++;
132 }
133
134 /* Reset MSCI CDCD status bit - uses ch#2 DCD input */
135 sca_out(stat & ST1_CDCD, MSCI1_OFFSET + ST1, card);
136
137 if (stat & ST1_CDCD)
138 hdlc_set_carrier(!(sca_in(MSCI1_OFFSET + ST3, card) & ST3_DCD),
139 dev);
140 }
141
142
143 static void c101_set_iface(port_t *port)
144 {
145 u8 rxs = port->rxs & CLK_BRG_MASK;
146 u8 txs = port->txs & CLK_BRG_MASK;
147
148 switch(port->settings.clock_type) {
149 case CLOCK_INT:
150 rxs |= CLK_BRG_RX; /* TX clock */
151 txs |= CLK_RXCLK_TX; /* BRG output */
152 break;
153
154 case CLOCK_TXINT:
155 rxs |= CLK_LINE_RX; /* RXC input */
156 txs |= CLK_BRG_TX; /* BRG output */
157 break;
158
159 case CLOCK_TXFROMRX:
160 rxs |= CLK_LINE_RX; /* RXC input */
161 txs |= CLK_RXCLK_TX; /* RX clock */
162 break;
163
164 default: /* EXTernal clock */
165 rxs |= CLK_LINE_RX; /* RXC input */
166 txs |= CLK_LINE_TX; /* TXC input */
167 }
168
169 port->rxs = rxs;
170 port->txs = txs;
171 sca_out(rxs, MSCI1_OFFSET + RXS, port);
172 sca_out(txs, MSCI1_OFFSET + TXS, port);
173 sca_set_port(port);
174 }
175
176
177 static int c101_open(struct net_device *dev)
178 {
179 port_t *port = dev_to_port(dev);
180 int result;
181
182 result = hdlc_open(dev);
183 if (result)
184 return result;
185
186 writeb(1, port->win0base + C101_DTR);
187 sca_out(0, MSCI1_OFFSET + CTL, port); /* RTS uses ch#2 output */
188 sca_open(dev);
189 /* DCD is connected to port 2 !@#$%^& - disable MSCI0 CDCD interrupt */
190 sca_out(IE1_UDRN, MSCI0_OFFSET + IE1, port);
191 sca_out(IE0_TXINT, MSCI0_OFFSET + IE0, port);
192
193 hdlc_set_carrier(!(sca_in(MSCI1_OFFSET + ST3, port) & ST3_DCD), dev);
194 printk(KERN_DEBUG "0x%X\n", sca_in(MSCI1_OFFSET + ST3, port));
195
196 /* enable MSCI1 CDCD interrupt */
197 sca_out(IE1_CDCD, MSCI1_OFFSET + IE1, port);
198 sca_out(IE0_RXINTA, MSCI1_OFFSET + IE0, port);
199 sca_out(0x48, IER0, port); /* TXINT #0 and RXINT #1 */
200 c101_set_iface(port);
201 return 0;
202 }
203
204
205 static int c101_close(struct net_device *dev)
206 {
207 port_t *port = dev_to_port(dev);
208
209 sca_close(dev);
210 writeb(0, port->win0base + C101_DTR);
211 sca_out(CTL_NORTS, MSCI1_OFFSET + CTL, port);
212 hdlc_close(dev);
213 return 0;
214 }
215
216
217 static int c101_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
218 {
219 const size_t size = sizeof(sync_serial_settings);
220 sync_serial_settings new_line;
221 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
222 port_t *port = dev_to_port(dev);
223
224 #ifdef DEBUG_RINGS
225 if (cmd == SIOCDEVPRIVATE) {
226 sca_dump_rings(dev);
227 printk(KERN_DEBUG "MSCI1: ST: %02x %02x %02x %02x\n",
228 sca_in(MSCI1_OFFSET + ST0, port),
229 sca_in(MSCI1_OFFSET + ST1, port),
230 sca_in(MSCI1_OFFSET + ST2, port),
231 sca_in(MSCI1_OFFSET + ST3, port));
232 return 0;
233 }
234 #endif
235 if (cmd != SIOCWANDEV)
236 return hdlc_ioctl(dev, ifr, cmd);
237
238 switch(ifr->ifr_settings.type) {
239 case IF_GET_IFACE:
240 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
241 if (ifr->ifr_settings.size < size) {
242 ifr->ifr_settings.size = size; /* data size wanted */
243 return -ENOBUFS;
244 }
245 if (copy_to_user(line, &port->settings, size))
246 return -EFAULT;
247 return 0;
248
249 case IF_IFACE_SYNC_SERIAL:
250 if(!capable(CAP_NET_ADMIN))
251 return -EPERM;
252
253 if (copy_from_user(&new_line, line, size))
254 return -EFAULT;
255
256 if (new_line.clock_type != CLOCK_EXT &&
257 new_line.clock_type != CLOCK_TXFROMRX &&
258 new_line.clock_type != CLOCK_INT &&
259 new_line.clock_type != CLOCK_TXINT)
260 return -EINVAL; /* No such clock setting */
261
262 if (new_line.loopback != 0 && new_line.loopback != 1)
263 return -EINVAL;
264
265 memcpy(&port->settings, &new_line, size); /* Update settings */
266 c101_set_iface(port);
267 return 0;
268
269 default:
270 return hdlc_ioctl(dev, ifr, cmd);
271 }
272 }
273
274
275
276 static void c101_destroy_card(card_t *card)
277 {
278 readb(card->win0base + C101_PAGE); /* Resets SCA? */
279
280 if (card->irq)
281 free_irq(card->irq, card);
282
283 if (card->win0base) {
284 iounmap(card->win0base);
285 release_mem_region(card->phy_winbase, C101_MAPPED_RAM_SIZE);
286 }
287
288 free_netdev(card->dev);
289
290 kfree(card);
291 }
292
293
294
295 static int __init c101_run(unsigned long irq, unsigned long winbase)
296 {
297 struct net_device *dev;
298 hdlc_device *hdlc;
299 card_t *card;
300 int result;
301
302 if (irq<3 || irq>15 || irq == 6) /* FIXME */ {
303 printk(KERN_ERR "c101: invalid IRQ value\n");
304 return -ENODEV;
305 }
306
307 if (winbase < 0xC0000 || winbase > 0xDFFFF || (winbase & 0x3FFF) !=0) {
308 printk(KERN_ERR "c101: invalid RAM value\n");
309 return -ENODEV;
310 }
311
312 card = kmalloc(sizeof(card_t), GFP_KERNEL);
313 if (card == NULL) {
314 printk(KERN_ERR "c101: unable to allocate memory\n");
315 return -ENOBUFS;
316 }
317 memset(card, 0, sizeof(card_t));
318
319 card->dev = alloc_hdlcdev(card);
320 if (!card->dev) {
321 printk(KERN_ERR "c101: unable to allocate memory\n");
322 kfree(card);
323 return -ENOBUFS;
324 }
325
326 if (request_irq(irq, sca_intr, 0, devname, card)) {
327 printk(KERN_ERR "c101: could not allocate IRQ\n");
328 c101_destroy_card(card);
329 return(-EBUSY);
330 }
331 card->irq = irq;
332
333 if (!request_mem_region(winbase, C101_MAPPED_RAM_SIZE, devname)) {
334 printk(KERN_ERR "c101: could not request RAM window\n");
335 c101_destroy_card(card);
336 return(-EBUSY);
337 }
338 card->phy_winbase = winbase;
339 card->win0base = ioremap(winbase, C101_MAPPED_RAM_SIZE);
340 if (!card->win0base) {
341 printk(KERN_ERR "c101: could not map I/O address\n");
342 c101_destroy_card(card);
343 return -EBUSY;
344 }
345
346 card->tx_ring_buffers = TX_RING_BUFFERS;
347 card->rx_ring_buffers = RX_RING_BUFFERS;
348 card->buff_offset = C101_WINDOW_SIZE; /* Bytes 1D00-1FFF reserved */
349
350 readb(card->win0base + C101_PAGE); /* Resets SCA? */
351 udelay(100);
352 writeb(0, card->win0base + C101_PAGE);
353 writeb(0, card->win0base + C101_DTR); /* Power-up for RAM? */
354
355 sca_init(card, 0);
356
357 dev = port_to_dev(card);
358 hdlc = dev_to_hdlc(dev);
359
360 spin_lock_init(&card->lock);
361 SET_MODULE_OWNER(dev);
362 dev->irq = irq;
363 dev->mem_start = winbase;
364 dev->mem_end = winbase + C101_MAPPED_RAM_SIZE - 1;
365 dev->tx_queue_len = 50;
366 dev->do_ioctl = c101_ioctl;
367 dev->open = c101_open;
368 dev->stop = c101_close;
369 hdlc->attach = sca_attach;
370 hdlc->xmit = sca_xmit;
371 card->settings.clock_type = CLOCK_EXT;
372
373 result = register_hdlc_device(dev);
374 if (result) {
375 printk(KERN_WARNING "c101: unable to register hdlc device\n");
376 c101_destroy_card(card);
377 return result;
378 }
379
380 sca_init_sync_port(card); /* Set up C101 memory */
381 hdlc_set_carrier(!(sca_in(MSCI1_OFFSET + ST3, card) & ST3_DCD), dev);
382
383 printk(KERN_INFO "%s: Moxa C101 on IRQ%u,"
384 " using %u TX + %u RX packets rings\n",
385 dev->name, card->irq,
386 card->tx_ring_buffers, card->rx_ring_buffers);
387
388 *new_card = card;
389 new_card = &card->next_card;
390 return 0;
391 }
392
393
394
395 static int __init c101_init(void)
396 {
397 if (hw == NULL) {
398 #ifdef MODULE
399 printk(KERN_INFO "c101: no card initialized\n");
400 #endif
401 return -ENOSYS; /* no parameters specified, abort */
402 }
403
404 printk(KERN_INFO "%s\n", version);
405
406 do {
407 unsigned long irq, ram;
408
409 irq = simple_strtoul(hw, &hw, 0);
410
411 if (*hw++ != ',')
412 break;
413 ram = simple_strtoul(hw, &hw, 0);
414
415 if (*hw == ':' || *hw == '\x')
416 c101_run(irq, ram);
417
418 if (*hw == '\x')
419 return first_card ? 0 : -ENOSYS;
420 }while(*hw++ == ':');
421
422 printk(KERN_ERR "c101: invalid hardware parameters\n");
423 return first_card ? 0 : -ENOSYS;
424 }
425
426
427 static void __exit c101_cleanup(void)
428 {
429 card_t *card = first_card;
430
431 while (card) {
432 card_t *ptr = card;
433 card = card->next_card;
434 unregister_hdlc_device(port_to_dev(ptr));
435 c101_destroy_card(ptr);
436 }
437 }
438
439
440 module_init(c101_init);
441 module_exit(c101_cleanup);
442
443 MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>");
444 MODULE_DESCRIPTION("Moxa C101 serial port driver");
445 MODULE_LICENSE("GPL v2");
446 module_param(hw, charp, 0444); /* hw=irq,ram:irq,... */
447
|
This page was automatically generated by the
LXR engine.
|