1 #ifndef TLAN_H
2 #define TLAN_H
3 /********************************************************************
4 *
5 * Linux ThunderLAN Driver
6 *
7 * tlan.h
8 * by James Banks
9 *
10 * (C) 1997-1998 Caldera, Inc.
11 * (C) 1999-2001 Torben Mathiasen
12 *
13 * This software may be used and distributed according to the terms
14 * of the GNU General Public License, incorporated herein by reference.
15 *
16 ** This file is best viewed/edited with tabstop=4, colums>=132
17 *
18 *
19 * Dec 10, 1999 Torben Mathiasen <torben.mathiasen@compaq.com>
20 * New Maintainer
21 *
22 ********************************************************************/
23
24
25 #include <asm/io.h>
26 #include <asm/types.h>
27 #include <linux/netdevice.h>
28
29
30
31 /*****************************************************************
32 * TLan Definitions
33 *
34 ****************************************************************/
35
36 #define FALSE 0
37 #define TRUE 1
38
39 #define TLAN_MIN_FRAME_SIZE 64
40 #define TLAN_MAX_FRAME_SIZE 1600
41
42 #define TLAN_NUM_RX_LISTS 32
43 #define TLAN_NUM_TX_LISTS 64
44
45 #define TLAN_IGNORE 0
46 #define TLAN_RECORD 1
47
48 #define TLAN_DBG(lvl, format, args...) if (debug&lvl) printk(KERN_DEBUG "TLAN: " format, ##args );
49 #define TLAN_DEBUG_GNRL 0x0001
50 #define TLAN_DEBUG_TX 0x0002
51 #define TLAN_DEBUG_RX 0x0004
52 #define TLAN_DEBUG_LIST 0x0008
53 #define TLAN_DEBUG_PROBE 0x0010
54
55 #define TX_TIMEOUT (10*HZ) /* We need time for auto-neg */
56 #define MAX_TLAN_BOARDS 8 /* Max number of boards installed at a time */
57
58
59 /*****************************************************************
60 * Device Identification Definitions
61 *
62 ****************************************************************/
63
64 #define PCI_DEVICE_ID_NETELLIGENT_10_T2 0xB012
65 #define PCI_DEVICE_ID_NETELLIGENT_10_100_WS_5100 0xB030
66 #ifndef PCI_DEVICE_ID_OLICOM_OC2183
67 #define PCI_DEVICE_ID_OLICOM_OC2183 0x0013
68 #endif
69 #ifndef PCI_DEVICE_ID_OLICOM_OC2325
70 #define PCI_DEVICE_ID_OLICOM_OC2325 0x0012
71 #endif
72 #ifndef PCI_DEVICE_ID_OLICOM_OC2326
73 #define PCI_DEVICE_ID_OLICOM_OC2326 0x0014
74 #endif
75
76 typedef struct tlan_adapter_entry {
77 u16 vendorId;
78 u16 deviceId;
79 char *deviceLabel;
80 u32 flags;
81 u16 addrOfs;
82 } TLanAdapterEntry;
83
84 #define TLAN_ADAPTER_NONE 0x00000000
85 #define TLAN_ADAPTER_UNMANAGED_PHY 0x00000001
86 #define TLAN_ADAPTER_BIT_RATE_PHY 0x00000002
87 #define TLAN_ADAPTER_USE_INTERN_10 0x00000004
88 #define TLAN_ADAPTER_ACTIVITY_LED 0x00000008
89
90 #define TLAN_SPEED_DEFAULT 0
91 #define TLAN_SPEED_10 10
92 #define TLAN_SPEED_100 100
93
94 #define TLAN_DUPLEX_DEFAULT 0
95 #define TLAN_DUPLEX_HALF 1
96 #define TLAN_DUPLEX_FULL 2
97
98
99
100 /*****************************************************************
101 * EISA Definitions
102 *
103 ****************************************************************/
104
105 #define EISA_ID 0xc80 /* EISA ID Registers */
106 #define EISA_ID0 0xc80 /* EISA ID Register 0 */
107 #define EISA_ID1 0xc81 /* EISA ID Register 1 */
108 #define EISA_ID2 0xc82 /* EISA ID Register 2 */
109 #define EISA_ID3 0xc83 /* EISA ID Register 3 */
110 #define EISA_CR 0xc84 /* EISA Control Register */
111 #define EISA_REG0 0xc88 /* EISA Configuration Register 0 */
112 #define EISA_REG1 0xc89 /* EISA Configuration Register 1 */
113 #define EISA_REG2 0xc8a /* EISA Configuration Register 2 */
114 #define EISA_REG3 0xc8f /* EISA Configuration Register 3 */
115 #define EISA_APROM 0xc90 /* Ethernet Address PROM */
116
117
118
119 /*****************************************************************
120 * Rx/Tx List Definitions
121 *
122 ****************************************************************/
123
124 #define TLAN_BUFFERS_PER_LIST 10
125 #define TLAN_LAST_BUFFER 0x80000000
126 #define TLAN_CSTAT_UNUSED 0x8000
127 #define TLAN_CSTAT_FRM_CMP 0x4000
128 #define TLAN_CSTAT_READY 0x3000
129 #define TLAN_CSTAT_EOC 0x0800
130 #define TLAN_CSTAT_RX_ERROR 0x0400
131 #define TLAN_CSTAT_PASS_CRC 0x0200
132 #define TLAN_CSTAT_DP_PR 0x0100
133
134
135 typedef struct tlan_buffer_ref_tag {
136 u32 count;
137 u32 address;
138 } TLanBufferRef;
139
140
141 typedef struct tlan_list_tag {
142 u32 forward;
143 u16 cStat;
144 u16 frameSize;
145 TLanBufferRef buffer[TLAN_BUFFERS_PER_LIST];
146 } TLanList;
147
148
149 typedef u8 TLanBuffer[TLAN_MAX_FRAME_SIZE];
150
151
152
153
154 /*****************************************************************
155 * PHY definitions
156 *
157 ****************************************************************/
158
159 #define TLAN_PHY_MAX_ADDR 0x1F
160 #define TLAN_PHY_NONE 0x20
161
162
163
164
165 /*****************************************************************
166 * TLAN Private Information Structure
167 *
168 ****************************************************************/
169
170 typedef struct tlan_private_tag {
171 struct net_device *nextDevice;
172 struct pci_dev *pciDev;
173 struct net_device *dev;
174 void *dmaStorage;
175 dma_addr_t dmaStorageDMA;
176 unsigned int dmaSize;
177 u8 *padBuffer;
178 TLanList *rxList;
179 dma_addr_t rxListDMA;
180 u8 *rxBuffer;
181 dma_addr_t rxBufferDMA;
182 u32 rxHead;
183 u32 rxTail;
184 u32 rxEocCount;
185 TLanList *txList;
186 dma_addr_t txListDMA;
187 u8 *txBuffer;
188 dma_addr_t txBufferDMA;
189 u32 txHead;
190 u32 txInProgress;
191 u32 txTail;
192 u32 txBusyCount;
193 u32 phyOnline;
194 u32 timerSetAt;
195 u32 timerType;
196 struct timer_list timer;
197 struct net_device_stats stats;
198 struct board *adapter;
199 u32 adapterRev;
200 u32 aui;
201 u32 debug;
202 u32 duplex;
203 u32 phy[2];
204 u32 phyNum;
205 u32 speed;
206 u8 tlanRev;
207 u8 tlanFullDuplex;
208 char devName[8];
209 spinlock_t lock;
210 u8 link;
211 u8 is_eisa;
212 struct work_struct tlan_tqueue;
213 u8 neg_be_verbose;
214 } TLanPrivateInfo;
215
216
217
218
219 /*****************************************************************
220 * TLan Driver Timer Definitions
221 *
222 ****************************************************************/
223
224 #define TLAN_TIMER_LINK_BEAT 1
225 #define TLAN_TIMER_ACTIVITY 2
226 #define TLAN_TIMER_PHY_PDOWN 3
227 #define TLAN_TIMER_PHY_PUP 4
228 #define TLAN_TIMER_PHY_RESET 5
229 #define TLAN_TIMER_PHY_START_LINK 6
230 #define TLAN_TIMER_PHY_FINISH_AN 7
231 #define TLAN_TIMER_FINISH_RESET 8
232
233 #define TLAN_TIMER_ACT_DELAY (HZ/10)
234
235
236
237
238 /*****************************************************************
239 * TLan Driver Eeprom Definitions
240 *
241 ****************************************************************/
242
243 #define TLAN_EEPROM_ACK 0
244 #define TLAN_EEPROM_STOP 1
245
246
247
248
249 /*****************************************************************
250 * Host Register Offsets and Contents
251 *
252 ****************************************************************/
253
254 #define TLAN_HOST_CMD 0x00
255 #define TLAN_HC_GO 0x80000000
256 #define TLAN_HC_STOP 0x40000000
257 #define TLAN_HC_ACK 0x20000000
258 #define TLAN_HC_CS_MASK 0x1FE00000
259 #define TLAN_HC_EOC 0x00100000
260 #define TLAN_HC_RT 0x00080000
261 #define TLAN_HC_NES 0x00040000
262 #define TLAN_HC_AD_RST 0x00008000
263 #define TLAN_HC_LD_TMR 0x00004000
264 #define TLAN_HC_LD_THR 0x00002000
265 #define TLAN_HC_REQ_INT 0x00001000
266 #define TLAN_HC_INT_OFF 0x00000800
267 #define TLAN_HC_INT_ON 0x00000400
268 #define TLAN_HC_AC_MASK 0x000000FF
269 #define TLAN_CH_PARM 0x04
270 #define TLAN_DIO_ADR 0x08
271 #define TLAN_DA_ADR_INC 0x8000
272 #define TLAN_DA_RAM_ADR 0x4000
273 #define TLAN_HOST_INT 0x0A
274 #define TLAN_HI_IV_MASK 0x1FE0
275 #define TLAN_HI_IT_MASK 0x001C
276 #define TLAN_DIO_DATA 0x0C
277
278
279 /* ThunderLAN Internal Register DIO Offsets */
280
281 #define TLAN_NET_CMD 0x00
282 #define TLAN_NET_CMD_NRESET 0x80
283 #define TLAN_NET_CMD_NWRAP 0x40
284 #define TLAN_NET_CMD_CSF 0x20
285 #define TLAN_NET_CMD_CAF 0x10
286 #define TLAN_NET_CMD_NOBRX 0x08
287 #define TLAN_NET_CMD_DUPLEX 0x04
288 #define TLAN_NET_CMD_TRFRAM 0x02
289 #define TLAN_NET_CMD_TXPACE 0x01
290 #define TLAN_NET_SIO 0x01
291 #define TLAN_NET_SIO_MINTEN 0x80
292 #define TLAN_NET_SIO_ECLOK 0x40
293 #define TLAN_NET_SIO_ETXEN 0x20
294 #define TLAN_NET_SIO_EDATA 0x10
295 #define TLAN_NET_SIO_NMRST 0x08
296 #define TLAN_NET_SIO_MCLK 0x04
297 #define TLAN_NET_SIO_MTXEN 0x02
298 #define TLAN_NET_SIO_MDATA 0x01
299 #define TLAN_NET_STS 0x02
300 #define TLAN_NET_STS_MIRQ 0x80
301 #define TLAN_NET_STS_HBEAT 0x40
302 #define TLAN_NET_STS_TXSTOP 0x20
303 #define TLAN_NET_STS_RXSTOP 0x10
304 #define TLAN_NET_STS_RSRVD 0x0F
305 #define TLAN_NET_MASK 0x03
306 #define TLAN_NET_MASK_MASK7 0x80
307 #define TLAN_NET_MASK_MASK6 0x40
308 #define TLAN_NET_MASK_MASK5 0x20
309 #define TLAN_NET_MASK_MASK4 0x10
310 #define TLAN_NET_MASK_RSRVD 0x0F
311 #define TLAN_NET_CONFIG 0x04
312 #define TLAN_NET_CFG_RCLK 0x8000
313 #define TLAN_NET_CFG_TCLK 0x4000
314 #define TLAN_NET_CFG_BIT 0x2000
315 #define TLAN_NET_CFG_RXCRC 0x1000
316 #define TLAN_NET_CFG_PEF 0x0800
317 #define TLAN_NET_CFG_1FRAG 0x0400
318 #define TLAN_NET_CFG_1CHAN 0x0200
319 #define TLAN_NET_CFG_MTEST 0x0100
320 #define TLAN_NET_CFG_PHY_EN 0x0080
321 #define TLAN_NET_CFG_MSMASK 0x007F
322 #define TLAN_MAN_TEST 0x06
323 #define TLAN_DEF_VENDOR_ID 0x08
324 #define TLAN_DEF_DEVICE_ID 0x0A
325 #define TLAN_DEF_REVISION 0x0C
326 #define TLAN_DEF_SUBCLASS 0x0D
327 #define TLAN_DEF_MIN_LAT 0x0E
328 #define TLAN_DEF_MAX_LAT 0x0F
329 #define TLAN_AREG_0 0x10
330 #define TLAN_AREG_1 0x16
331 #define TLAN_AREG_2 0x1C
332 #define TLAN_AREG_3 0x22
333 #define TLAN_HASH_1 0x28
334 #define TLAN_HASH_2 0x2C
335 #define TLAN_GOOD_TX_FRMS 0x30
336 #define TLAN_TX_UNDERUNS 0x33
337 #define TLAN_GOOD_RX_FRMS 0x34
338 #define TLAN_RX_OVERRUNS 0x37
339 #define TLAN_DEFERRED_TX 0x38
340 #define TLAN_CRC_ERRORS 0x3A
341 #define TLAN_CODE_ERRORS 0x3B
342 #define TLAN_MULTICOL_FRMS 0x3C
343 #define TLAN_SINGLECOL_FRMS 0x3E
344 #define TLAN_EXCESSCOL_FRMS 0x40
345 #define TLAN_LATE_COLS 0x41
346 #define TLAN_CARRIER_LOSS 0x42
347 #define TLAN_ACOMMIT 0x43
348 #define TLAN_LED_REG 0x44
349 #define TLAN_LED_ACT 0x10
350 #define TLAN_LED_LINK 0x01
351 #define TLAN_BSIZE_REG 0x45
352 #define TLAN_MAX_RX 0x46
353 #define TLAN_INT_DIS 0x48
354 #define TLAN_ID_TX_EOC 0x04
355 #define TLAN_ID_RX_EOF 0x02
356 #define TLAN_ID_RX_EOC 0x01
357
358
359
360 /* ThunderLAN Interrupt Codes */
361
362 #define TLAN_INT_NUMBER_OF_INTS 8
363
364 #define TLAN_INT_NONE 0x0000
365 #define TLAN_INT_TX_EOF 0x0001
366 #define TLAN_INT_STAT_OVERFLOW 0x0002
367 #define TLAN_INT_RX_EOF 0x0003
368 #define TLAN_INT_DUMMY 0x0004
369 #define TLAN_INT_TX_EOC 0x0005
370 #define TLAN_INT_STATUS_CHECK 0x0006
371 #define TLAN_INT_RX_EOC 0x0007
372
373
374
375 /* ThunderLAN MII Registers */
376
377 /* Generic MII/PHY Registers */
378
379 #define MII_GEN_CTL 0x00
380 #define MII_GC_RESET 0x8000
381 #define MII_GC_LOOPBK 0x4000
382 #define MII_GC_SPEEDSEL 0x2000
383 #define MII_GC_AUTOENB 0x1000
384 #define MII_GC_PDOWN 0x0800
385 #define MII_GC_ISOLATE 0x0400
386 #define MII_GC_AUTORSRT 0x0200
387 #define MII_GC_DUPLEX 0x0100
388 #define MII_GC_COLTEST 0x0080
389 #define MII_GC_RESERVED 0x007F
390 #define MII_GEN_STS 0x01
391 #define MII_GS_100BT4 0x8000
392 #define MII_GS_100BTXFD 0x4000
393 #define MII_GS_100BTXHD 0x2000
394 #define MII_GS_10BTFD 0x1000
395 #define MII_GS_10BTHD 0x0800
396 #define MII_GS_RESERVED 0x07C0
397 #define MII_GS_AUTOCMPLT 0x0020
398 #define MII_GS_RFLT 0x0010
399 #define MII_GS_AUTONEG 0x0008
400 #define MII_GS_LINK 0x0004
401 #define MII_GS_JABBER 0x0002
402 #define MII_GS_EXTCAP 0x0001
403 #define MII_GEN_ID_HI 0x02
404 #define MII_GEN_ID_LO 0x03
405 #define MII_GIL_OUI 0xFC00
406 #define MII_GIL_MODEL 0x03F0
407 #define MII_GIL_REVISION 0x000F
408 #define MII_AN_ADV 0x04
409 #define MII_AN_LPA 0x05
410 #define MII_AN_EXP 0x06
411
412 /* ThunderLAN Specific MII/PHY Registers */
413
414 #define TLAN_TLPHY_ID 0x10
415 #define TLAN_TLPHY_CTL 0x11
416 #define TLAN_TC_IGLINK 0x8000
417 #define TLAN_TC_SWAPOL 0x4000
418 #define TLAN_TC_AUISEL 0x2000
419 #define TLAN_TC_SQEEN 0x1000
420 #define TLAN_TC_MTEST 0x0800
421 #define TLAN_TC_RESERVED 0x07F8
422 #define TLAN_TC_NFEW 0x0004
423 #define TLAN_TC_INTEN 0x0002
424 #define TLAN_TC_TINT 0x0001
425 #define TLAN_TLPHY_STS 0x12
426 #define TLAN_TS_MINT 0x8000
427 #define TLAN_TS_PHOK 0x4000
428 #define TLAN_TS_POLOK 0x2000
429 #define TLAN_TS_TPENERGY 0x1000
430 #define TLAN_TS_RESERVED 0x0FFF
431 #define TLAN_TLPHY_PAR 0x19
432 #define TLAN_PHY_CIM_STAT 0x0020
433 #define TLAN_PHY_SPEED_100 0x0040
434 #define TLAN_PHY_DUPLEX_FULL 0x0080
435 #define TLAN_PHY_AN_EN_STAT 0x0400
436
437 /* National Sem. & Level1 PHY id's */
438 #define NAT_SEM_ID1 0x2000
439 #define NAT_SEM_ID2 0x5C01
440 #define LEVEL1_ID1 0x7810
441 #define LEVEL1_ID2 0x0000
442
443 #define CIRC_INC( a, b ) if ( ++a >= b ) a = 0
444
445 /* Routines to access internal registers. */
446
447 static inline u8 TLan_DioRead8(u16 base_addr, u16 internal_addr)
448 {
449 outw(internal_addr, base_addr + TLAN_DIO_ADR);
450 return (inb((base_addr + TLAN_DIO_DATA) + (internal_addr & 0x3)));
451
452 } /* TLan_DioRead8 */
453
454
455
456
457 static inline u16 TLan_DioRead16(u16 base_addr, u16 internal_addr)
458 {
459 outw(internal_addr, base_addr + TLAN_DIO_ADR);
460 return (inw((base_addr + TLAN_DIO_DATA) + (internal_addr & 0x2)));
461
462 } /* TLan_DioRead16 */
463
464
465
466
467 static inline u32 TLan_DioRead32(u16 base_addr, u16 internal_addr)
468 {
469 outw(internal_addr, base_addr + TLAN_DIO_ADR);
470 return (inl(base_addr + TLAN_DIO_DATA));
471
472 } /* TLan_DioRead32 */
473
474
475
476
477 static inline void TLan_DioWrite8(u16 base_addr, u16 internal_addr, u8 data)
478 {
479 outw(internal_addr, base_addr + TLAN_DIO_ADR);
480 outb(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x3));
481
482 }
483
484
485
486
487 static inline void TLan_DioWrite16(u16 base_addr, u16 internal_addr, u16 data)
488 {
489 outw(internal_addr, base_addr + TLAN_DIO_ADR);
490 outw(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x2));
491
492 }
493
494
495
496
497 static inline void TLan_DioWrite32(u16 base_addr, u16 internal_addr, u32 data)
498 {
499 outw(internal_addr, base_addr + TLAN_DIO_ADR);
500 outl(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x2));
501
502 }
503
504 #define TLan_ClearBit( bit, port ) outb_p(inb_p(port) & ~bit, port)
505 #define TLan_GetBit( bit, port ) ((int) (inb_p(port) & bit))
506 #define TLan_SetBit( bit, port ) outb_p(inb_p(port) | bit, port)
507
508 /*
509 * given 6 bytes, view them as 8 6-bit numbers and return the XOR of those
510 * the code below is about seven times as fast as the original code
511 *
512 * The original code was:
513 *
514 * u32 xor( u32 a, u32 b ) { return ( ( a && ! b ) || ( ! a && b ) ); }
515 *
516 * #define XOR8( a, b, c, d, e, f, g, h ) \
517 * xor( a, xor( b, xor( c, xor( d, xor( e, xor( f, xor( g, h ) ) ) ) ) ) )
518 * #define DA( a, bit ) ( ( (u8) a[bit/8] ) & ( (u8) ( 1 << bit%8 ) ) )
519 *
520 * hash = XOR8( DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), DA(a,36), DA(a,42) );
521 * hash |= XOR8( DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), DA(a,37), DA(a,43) ) << 1;
522 * hash |= XOR8( DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), DA(a,38), DA(a,44) ) << 2;
523 * hash |= XOR8( DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), DA(a,39), DA(a,45) ) << 3;
524 * hash |= XOR8( DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), DA(a,40), DA(a,46) ) << 4;
525 * hash |= XOR8( DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), DA(a,41), DA(a,47) ) << 5;
526 *
527 */
528 static inline u32 TLan_HashFunc( const u8 *a )
529 {
530 u8 hash;
531
532 hash = (a[0]^a[3]); /* & 077 */
533 hash ^= ((a[0]^a[3])>>6); /* & 003 */
534 hash ^= ((a[1]^a[4])<<2); /* & 074 */
535 hash ^= ((a[1]^a[4])>>4); /* & 017 */
536 hash ^= ((a[2]^a[5])<<4); /* & 060 */
537 hash ^= ((a[2]^a[5])>>2); /* & 077 */
538
539 return (hash & 077);
540 }
541 #endif
542
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