1 /*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2007 Broadcom Corporation.
8 *
9 * Firmware is:
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
16 */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
26 #include <linux/in.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/if_vlan.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/workqueue.h>
39 #include <linux/prefetch.h>
40 #include <linux/dma-mapping.h>
41
42 #include <net/checksum.h>
43 #include <net/ip.h>
44
45 #include <asm/system.h>
46 #include <asm/io.h>
47 #include <asm/byteorder.h>
48 #include <asm/uaccess.h>
49
50 #ifdef CONFIG_SPARC
51 #include <asm/idprom.h>
52 #include <asm/prom.h>
53 #endif
54
55 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
56 #define TG3_VLAN_TAG_USED 1
57 #else
58 #define TG3_VLAN_TAG_USED 0
59 #endif
60
61 #define TG3_TSO_SUPPORT 1
62
63 #include "tg3.h"
64
65 #define DRV_MODULE_NAME "tg3"
66 #define PFX DRV_MODULE_NAME ": "
67 #define DRV_MODULE_VERSION "3.91"
68 #define DRV_MODULE_RELDATE "April 18, 2008"
69
70 #define TG3_DEF_MAC_MODE 0
71 #define TG3_DEF_RX_MODE 0
72 #define TG3_DEF_TX_MODE 0
73 #define TG3_DEF_MSG_ENABLE \
74 (NETIF_MSG_DRV | \
75 NETIF_MSG_PROBE | \
76 NETIF_MSG_LINK | \
77 NETIF_MSG_TIMER | \
78 NETIF_MSG_IFDOWN | \
79 NETIF_MSG_IFUP | \
80 NETIF_MSG_RX_ERR | \
81 NETIF_MSG_TX_ERR)
82
83 /* length of time before we decide the hardware is borked,
84 * and dev->tx_timeout() should be called to fix the problem
85 */
86 #define TG3_TX_TIMEOUT (5 * HZ)
87
88 /* hardware minimum and maximum for a single frame's data payload */
89 #define TG3_MIN_MTU 60
90 #define TG3_MAX_MTU(tp) \
91 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
92
93 /* These numbers seem to be hard coded in the NIC firmware somehow.
94 * You can't change the ring sizes, but you can change where you place
95 * them in the NIC onboard memory.
96 */
97 #define TG3_RX_RING_SIZE 512
98 #define TG3_DEF_RX_RING_PENDING 200
99 #define TG3_RX_JUMBO_RING_SIZE 256
100 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
101
102 /* Do not place this n-ring entries value into the tp struct itself,
103 * we really want to expose these constants to GCC so that modulo et
104 * al. operations are done with shifts and masks instead of with
105 * hw multiply/modulo instructions. Another solution would be to
106 * replace things like '% foo' with '& (foo - 1)'.
107 */
108 #define TG3_RX_RCB_RING_SIZE(tp) \
109 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
110
111 #define TG3_TX_RING_SIZE 512
112 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
113
114 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
115 TG3_RX_RING_SIZE)
116 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
117 TG3_RX_JUMBO_RING_SIZE)
118 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
119 TG3_RX_RCB_RING_SIZE(tp))
120 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
121 TG3_TX_RING_SIZE)
122 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
123
124 #define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
125 #define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
126
127 /* minimum number of free TX descriptors required to wake up TX process */
128 #define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
129
130 /* number of ETHTOOL_GSTATS u64's */
131 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
132
133 #define TG3_NUM_TEST 6
134
135 static char version[] __devinitdata =
136 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
137
138 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
139 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
140 MODULE_LICENSE("GPL");
141 MODULE_VERSION(DRV_MODULE_VERSION);
142
143 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
144 module_param(tg3_debug, int, 0);
145 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
146
147 static struct pci_device_id tg3_pci_tbl[] = {
148 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
149 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
150 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
151 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
152 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
153 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
154 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
155 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
156 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
157 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
158 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
159 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
160 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
161 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
162 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
163 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
164 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
165 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
166 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
167 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
168 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
206 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
207 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
208 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
209 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
210 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
211 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
212 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
213 {}
214 };
215
216 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
217
218 static const struct {
219 const char string[ETH_GSTRING_LEN];
220 } ethtool_stats_keys[TG3_NUM_STATS] = {
221 { "rx_octets" },
222 { "rx_fragments" },
223 { "rx_ucast_packets" },
224 { "rx_mcast_packets" },
225 { "rx_bcast_packets" },
226 { "rx_fcs_errors" },
227 { "rx_align_errors" },
228 { "rx_xon_pause_rcvd" },
229 { "rx_xoff_pause_rcvd" },
230 { "rx_mac_ctrl_rcvd" },
231 { "rx_xoff_entered" },
232 { "rx_frame_too_long_errors" },
233 { "rx_jabbers" },
234 { "rx_undersize_packets" },
235 { "rx_in_length_errors" },
236 { "rx_out_length_errors" },
237 { "rx_64_or_less_octet_packets" },
238 { "rx_65_to_127_octet_packets" },
239 { "rx_128_to_255_octet_packets" },
240 { "rx_256_to_511_octet_packets" },
241 { "rx_512_to_1023_octet_packets" },
242 { "rx_1024_to_1522_octet_packets" },
243 { "rx_1523_to_2047_octet_packets" },
244 { "rx_2048_to_4095_octet_packets" },
245 { "rx_4096_to_8191_octet_packets" },
246 { "rx_8192_to_9022_octet_packets" },
247
248 { "tx_octets" },
249 { "tx_collisions" },
250
251 { "tx_xon_sent" },
252 { "tx_xoff_sent" },
253 { "tx_flow_control" },
254 { "tx_mac_errors" },
255 { "tx_single_collisions" },
256 { "tx_mult_collisions" },
257 { "tx_deferred" },
258 { "tx_excessive_collisions" },
259 { "tx_late_collisions" },
260 { "tx_collide_2times" },
261 { "tx_collide_3times" },
262 { "tx_collide_4times" },
263 { "tx_collide_5times" },
264 { "tx_collide_6times" },
265 { "tx_collide_7times" },
266 { "tx_collide_8times" },
267 { "tx_collide_9times" },
268 { "tx_collide_10times" },
269 { "tx_collide_11times" },
270 { "tx_collide_12times" },
271 { "tx_collide_13times" },
272 { "tx_collide_14times" },
273 { "tx_collide_15times" },
274 { "tx_ucast_packets" },
275 { "tx_mcast_packets" },
276 { "tx_bcast_packets" },
277 { "tx_carrier_sense_errors" },
278 { "tx_discards" },
279 { "tx_errors" },
280
281 { "dma_writeq_full" },
282 { "dma_write_prioq_full" },
283 { "rxbds_empty" },
284 { "rx_discards" },
285 { "rx_errors" },
286 { "rx_threshold_hit" },
287
288 { "dma_readq_full" },
289 { "dma_read_prioq_full" },
290 { "tx_comp_queue_full" },
291
292 { "ring_set_send_prod_index" },
293 { "ring_status_update" },
294 { "nic_irqs" },
295 { "nic_avoided_irqs" },
296 { "nic_tx_threshold_hit" }
297 };
298
299 static const struct {
300 const char string[ETH_GSTRING_LEN];
301 } ethtool_test_keys[TG3_NUM_TEST] = {
302 { "nvram test (online) " },
303 { "link test (online) " },
304 { "register test (offline)" },
305 { "memory test (offline)" },
306 { "loopback test (offline)" },
307 { "interrupt test (offline)" },
308 };
309
310 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
311 {
312 writel(val, tp->regs + off);
313 }
314
315 static u32 tg3_read32(struct tg3 *tp, u32 off)
316 {
317 return (readl(tp->regs + off));
318 }
319
320 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
321 {
322 writel(val, tp->aperegs + off);
323 }
324
325 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
326 {
327 return (readl(tp->aperegs + off));
328 }
329
330 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
331 {
332 unsigned long flags;
333
334 spin_lock_irqsave(&tp->indirect_lock, flags);
335 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
336 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
337 spin_unlock_irqrestore(&tp->indirect_lock, flags);
338 }
339
340 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
341 {
342 writel(val, tp->regs + off);
343 readl(tp->regs + off);
344 }
345
346 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
347 {
348 unsigned long flags;
349 u32 val;
350
351 spin_lock_irqsave(&tp->indirect_lock, flags);
352 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
353 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
354 spin_unlock_irqrestore(&tp->indirect_lock, flags);
355 return val;
356 }
357
358 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
359 {
360 unsigned long flags;
361
362 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
363 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
364 TG3_64BIT_REG_LOW, val);
365 return;
366 }
367 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
368 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
369 TG3_64BIT_REG_LOW, val);
370 return;
371 }
372
373 spin_lock_irqsave(&tp->indirect_lock, flags);
374 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
375 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
376 spin_unlock_irqrestore(&tp->indirect_lock, flags);
377
378 /* In indirect mode when disabling interrupts, we also need
379 * to clear the interrupt bit in the GRC local ctrl register.
380 */
381 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
382 (val == 0x1)) {
383 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
384 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
385 }
386 }
387
388 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
389 {
390 unsigned long flags;
391 u32 val;
392
393 spin_lock_irqsave(&tp->indirect_lock, flags);
394 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
395 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
396 spin_unlock_irqrestore(&tp->indirect_lock, flags);
397 return val;
398 }
399
400 /* usec_wait specifies the wait time in usec when writing to certain registers
401 * where it is unsafe to read back the register without some delay.
402 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
403 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
404 */
405 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
406 {
407 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
408 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
409 /* Non-posted methods */
410 tp->write32(tp, off, val);
411 else {
412 /* Posted method */
413 tg3_write32(tp, off, val);
414 if (usec_wait)
415 udelay(usec_wait);
416 tp->read32(tp, off);
417 }
418 /* Wait again after the read for the posted method to guarantee that
419 * the wait time is met.
420 */
421 if (usec_wait)
422 udelay(usec_wait);
423 }
424
425 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
426 {
427 tp->write32_mbox(tp, off, val);
428 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
429 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
430 tp->read32_mbox(tp, off);
431 }
432
433 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
434 {
435 void __iomem *mbox = tp->regs + off;
436 writel(val, mbox);
437 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
438 writel(val, mbox);
439 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
440 readl(mbox);
441 }
442
443 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
444 {
445 return (readl(tp->regs + off + GRCMBOX_BASE));
446 }
447
448 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
449 {
450 writel(val, tp->regs + off + GRCMBOX_BASE);
451 }
452
453 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
454 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
455 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
456 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
457 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
458
459 #define tw32(reg,val) tp->write32(tp, reg, val)
460 #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
461 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
462 #define tr32(reg) tp->read32(tp, reg)
463
464 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
465 {
466 unsigned long flags;
467
468 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
469 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
470 return;
471
472 spin_lock_irqsave(&tp->indirect_lock, flags);
473 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
474 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
475 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
476
477 /* Always leave this as zero. */
478 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
479 } else {
480 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
481 tw32_f(TG3PCI_MEM_WIN_DATA, val);
482
483 /* Always leave this as zero. */
484 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
485 }
486 spin_unlock_irqrestore(&tp->indirect_lock, flags);
487 }
488
489 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
490 {
491 unsigned long flags;
492
493 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
494 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
495 *val = 0;
496 return;
497 }
498
499 spin_lock_irqsave(&tp->indirect_lock, flags);
500 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
501 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
502 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
503
504 /* Always leave this as zero. */
505 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
506 } else {
507 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
508 *val = tr32(TG3PCI_MEM_WIN_DATA);
509
510 /* Always leave this as zero. */
511 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
512 }
513 spin_unlock_irqrestore(&tp->indirect_lock, flags);
514 }
515
516 static void tg3_ape_lock_init(struct tg3 *tp)
517 {
518 int i;
519
520 /* Make sure the driver hasn't any stale locks. */
521 for (i = 0; i < 8; i++)
522 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
523 APE_LOCK_GRANT_DRIVER);
524 }
525
526 static int tg3_ape_lock(struct tg3 *tp, int locknum)
527 {
528 int i, off;
529 int ret = 0;
530 u32 status;
531
532 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
533 return 0;
534
535 switch (locknum) {
536 case TG3_APE_LOCK_MEM:
537 break;
538 default:
539 return -EINVAL;
540 }
541
542 off = 4 * locknum;
543
544 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
545
546 /* Wait for up to 1 millisecond to acquire lock. */
547 for (i = 0; i < 100; i++) {
548 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
549 if (status == APE_LOCK_GRANT_DRIVER)
550 break;
551 udelay(10);
552 }
553
554 if (status != APE_LOCK_GRANT_DRIVER) {
555 /* Revoke the lock request. */
556 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
557 APE_LOCK_GRANT_DRIVER);
558
559 ret = -EBUSY;
560 }
561
562 return ret;
563 }
564
565 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
566 {
567 int off;
568
569 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
570 return;
571
572 switch (locknum) {
573 case TG3_APE_LOCK_MEM:
574 break;
575 default:
576 return;
577 }
578
579 off = 4 * locknum;
580 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
581 }
582
583 static void tg3_disable_ints(struct tg3 *tp)
584 {
585 tw32(TG3PCI_MISC_HOST_CTRL,
586 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
587 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
588 }
589
590 static inline void tg3_cond_int(struct tg3 *tp)
591 {
592 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
593 (tp->hw_status->status & SD_STATUS_UPDATED))
594 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
595 else
596 tw32(HOSTCC_MODE, tp->coalesce_mode |
597 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
598 }
599
600 static void tg3_enable_ints(struct tg3 *tp)
601 {
602 tp->irq_sync = 0;
603 wmb();
604
605 tw32(TG3PCI_MISC_HOST_CTRL,
606 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
607 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
608 (tp->last_tag << 24));
609 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
610 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
611 (tp->last_tag << 24));
612 tg3_cond_int(tp);
613 }
614
615 static inline unsigned int tg3_has_work(struct tg3 *tp)
616 {
617 struct tg3_hw_status *sblk = tp->hw_status;
618 unsigned int work_exists = 0;
619
620 /* check for phy events */
621 if (!(tp->tg3_flags &
622 (TG3_FLAG_USE_LINKCHG_REG |
623 TG3_FLAG_POLL_SERDES))) {
624 if (sblk->status & SD_STATUS_LINK_CHG)
625 work_exists = 1;
626 }
627 /* check for RX/TX work to do */
628 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
629 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
630 work_exists = 1;
631
632 return work_exists;
633 }
634
635 /* tg3_restart_ints
636 * similar to tg3_enable_ints, but it accurately determines whether there
637 * is new work pending and can return without flushing the PIO write
638 * which reenables interrupts
639 */
640 static void tg3_restart_ints(struct tg3 *tp)
641 {
642 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
643 tp->last_tag << 24);
644 mmiowb();
645
646 /* When doing tagged status, this work check is unnecessary.
647 * The last_tag we write above tells the chip which piece of
648 * work we've completed.
649 */
650 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
651 tg3_has_work(tp))
652 tw32(HOSTCC_MODE, tp->coalesce_mode |
653 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
654 }
655
656 static inline void tg3_netif_stop(struct tg3 *tp)
657 {
658 tp->dev->trans_start = jiffies; /* prevent tx timeout */
659 napi_disable(&tp->napi);
660 netif_tx_disable(tp->dev);
661 }
662
663 static inline void tg3_netif_start(struct tg3 *tp)
664 {
665 netif_wake_queue(tp->dev);
666 /* NOTE: unconditional netif_wake_queue is only appropriate
667 * so long as all callers are assured to have free tx slots
668 * (such as after tg3_init_hw)
669 */
670 napi_enable(&tp->napi);
671 tp->hw_status->status |= SD_STATUS_UPDATED;
672 tg3_enable_ints(tp);
673 }
674
675 static void tg3_switch_clocks(struct tg3 *tp)
676 {
677 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
678 u32 orig_clock_ctrl;
679
680 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
681 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
682 return;
683
684 orig_clock_ctrl = clock_ctrl;
685 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
686 CLOCK_CTRL_CLKRUN_OENABLE |
687 0x1f);
688 tp->pci_clock_ctrl = clock_ctrl;
689
690 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
691 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
692 tw32_wait_f(TG3PCI_CLOCK_CTRL,
693 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
694 }
695 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
696 tw32_wait_f(TG3PCI_CLOCK_CTRL,
697 clock_ctrl |
698 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
699 40);
700 tw32_wait_f(TG3PCI_CLOCK_CTRL,
701 clock_ctrl | (CLOCK_CTRL_ALTCLK),
702 40);
703 }
704 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
705 }
706
707 #define PHY_BUSY_LOOPS 5000
708
709 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
710 {
711 u32 frame_val;
712 unsigned int loops;
713 int ret;
714
715 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
716 tw32_f(MAC_MI_MODE,
717 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
718 udelay(80);
719 }
720
721 *val = 0x0;
722
723 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
724 MI_COM_PHY_ADDR_MASK);
725 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
726 MI_COM_REG_ADDR_MASK);
727 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
728
729 tw32_f(MAC_MI_COM, frame_val);
730
731 loops = PHY_BUSY_LOOPS;
732 while (loops != 0) {
733 udelay(10);
734 frame_val = tr32(MAC_MI_COM);
735
736 if ((frame_val & MI_COM_BUSY) == 0) {
737 udelay(5);
738 frame_val = tr32(MAC_MI_COM);
739 break;
740 }
741 loops -= 1;
742 }
743
744 ret = -EBUSY;
745 if (loops != 0) {
746 *val = frame_val & MI_COM_DATA_MASK;
747 ret = 0;
748 }
749
750 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
751 tw32_f(MAC_MI_MODE, tp->mi_mode);
752 udelay(80);
753 }
754
755 return ret;
756 }
757
758 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
759 {
760 u32 frame_val;
761 unsigned int loops;
762 int ret;
763
764 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
765 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
766 return 0;
767
768 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
769 tw32_f(MAC_MI_MODE,
770 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
771 udelay(80);
772 }
773
774 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
775 MI_COM_PHY_ADDR_MASK);
776 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
777 MI_COM_REG_ADDR_MASK);
778 frame_val |= (val & MI_COM_DATA_MASK);
779 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
780
781 tw32_f(MAC_MI_COM, frame_val);
782
783 loops = PHY_BUSY_LOOPS;
784 while (loops != 0) {
785 udelay(10);
786 frame_val = tr32(MAC_MI_COM);
787 if ((frame_val & MI_COM_BUSY) == 0) {
788 udelay(5);
789 frame_val = tr32(MAC_MI_COM);
790 break;
791 }
792 loops -= 1;
793 }
794
795 ret = -EBUSY;
796 if (loops != 0)
797 ret = 0;
798
799 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
800 tw32_f(MAC_MI_MODE, tp->mi_mode);
801 udelay(80);
802 }
803
804 return ret;
805 }
806
807 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
808 {
809 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
810 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
811 }
812
813 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
814 {
815 u32 phy;
816
817 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
818 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
819 return;
820
821 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
822 u32 ephy;
823
824 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
825 tg3_writephy(tp, MII_TG3_EPHY_TEST,
826 ephy | MII_TG3_EPHY_SHADOW_EN);
827 if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
828 if (enable)
829 phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
830 else
831 phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
832 tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
833 }
834 tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
835 }
836 } else {
837 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
838 MII_TG3_AUXCTL_SHDWSEL_MISC;
839 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
840 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
841 if (enable)
842 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
843 else
844 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
845 phy |= MII_TG3_AUXCTL_MISC_WREN;
846 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
847 }
848 }
849 }
850
851 static void tg3_phy_set_wirespeed(struct tg3 *tp)
852 {
853 u32 val;
854
855 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
856 return;
857
858 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
859 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
860 tg3_writephy(tp, MII_TG3_AUX_CTRL,
861 (val | (1 << 15) | (1 << 4)));
862 }
863
864 static int tg3_bmcr_reset(struct tg3 *tp)
865 {
866 u32 phy_control;
867 int limit, err;
868
869 /* OK, reset it, and poll the BMCR_RESET bit until it
870 * clears or we time out.
871 */
872 phy_control = BMCR_RESET;
873 err = tg3_writephy(tp, MII_BMCR, phy_control);
874 if (err != 0)
875 return -EBUSY;
876
877 limit = 5000;
878 while (limit--) {
879 err = tg3_readphy(tp, MII_BMCR, &phy_control);
880 if (err != 0)
881 return -EBUSY;
882
883 if ((phy_control & BMCR_RESET) == 0) {
884 udelay(40);
885 break;
886 }
887 udelay(10);
888 }
889 if (limit <= 0)
890 return -EBUSY;
891
892 return 0;
893 }
894
895 static void tg3_phy_apply_otp(struct tg3 *tp)
896 {
897 u32 otp, phy;
898
899 if (!tp->phy_otp)
900 return;
901
902 otp = tp->phy_otp;
903
904 /* Enable SM_DSP clock and tx 6dB coding. */
905 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
906 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
907 MII_TG3_AUXCTL_ACTL_TX_6DB;
908 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
909
910 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
911 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
912 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
913
914 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
915 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
916 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
917
918 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
919 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
920 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
921
922 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
923 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
924
925 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
926 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
927
928 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
929 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
930 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
931
932 /* Turn off SM_DSP clock. */
933 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
934 MII_TG3_AUXCTL_ACTL_TX_6DB;
935 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
936 }
937
938 static int tg3_wait_macro_done(struct tg3 *tp)
939 {
940 int limit = 100;
941
942 while (limit--) {
943 u32 tmp32;
944
945 if (!tg3_readphy(tp, 0x16, &tmp32)) {
946 if ((tmp32 & 0x1000) == 0)
947 break;
948 }
949 }
950 if (limit <= 0)
951 return -EBUSY;
952
953 return 0;
954 }
955
956 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
957 {
958 static const u32 test_pat[4][6] = {
959 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
960 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
961 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
962 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
963 };
964 int chan;
965
966 for (chan = 0; chan < 4; chan++) {
967 int i;
968
969 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
970 (chan * 0x2000) | 0x0200);
971 tg3_writephy(tp, 0x16, 0x0002);
972
973 for (i = 0; i < 6; i++)
974 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
975 test_pat[chan][i]);
976
977 tg3_writephy(tp, 0x16, 0x0202);
978 if (tg3_wait_macro_done(tp)) {
979 *resetp = 1;
980 return -EBUSY;
981 }
982
983 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
984 (chan * 0x2000) | 0x0200);
985 tg3_writephy(tp, 0x16, 0x0082);
986 if (tg3_wait_macro_done(tp)) {
987 *resetp = 1;
988 return -EBUSY;
989 }
990
991 tg3_writephy(tp, 0x16, 0x0802);
992 if (tg3_wait_macro_done(tp)) {
993 *resetp = 1;
994 return -EBUSY;
995 }
996
997 for (i = 0; i < 6; i += 2) {
998 u32 low, high;
999
1000 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1001 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1002 tg3_wait_macro_done(tp)) {
1003 *resetp = 1;
1004 return -EBUSY;
1005 }
1006 low &= 0x7fff;
1007 high &= 0x000f;
1008 if (low != test_pat[chan][i] ||
1009 high != test_pat[chan][i+1]) {
1010 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1011 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1012 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1013
1014 return -EBUSY;
1015 }
1016 }
1017 }
1018
1019 return 0;
1020 }
1021
1022 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1023 {
1024 int chan;
1025
1026 for (chan = 0; chan < 4; chan++) {
1027 int i;
1028
1029 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1030 (chan * 0x2000) | 0x0200);
1031 tg3_writephy(tp, 0x16, 0x0002);
1032 for (i = 0; i < 6; i++)
1033 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1034 tg3_writephy(tp, 0x16, 0x0202);
1035 if (tg3_wait_macro_done(tp))
1036 return -EBUSY;
1037 }
1038
1039 return 0;
1040 }
1041
1042 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1043 {
1044 u32 reg32, phy9_orig;
1045 int retries, do_phy_reset, err;
1046
1047 retries = 10;
1048 do_phy_reset = 1;
1049 do {
1050 if (do_phy_reset) {
1051 err = tg3_bmcr_reset(tp);
1052 if (err)
1053 return err;
1054 do_phy_reset = 0;
1055 }
1056
1057 /* Disable transmitter and interrupt. */
1058 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
1059 continue;
1060
1061 reg32 |= 0x3000;
1062 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1063
1064 /* Set full-duplex, 1000 mbps. */
1065 tg3_writephy(tp, MII_BMCR,
1066 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1067
1068 /* Set to master mode. */
1069 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1070 continue;
1071
1072 tg3_writephy(tp, MII_TG3_CTRL,
1073 (MII_TG3_CTRL_AS_MASTER |
1074 MII_TG3_CTRL_ENABLE_AS_MASTER));
1075
1076 /* Enable SM_DSP_CLOCK and 6dB. */
1077 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1078
1079 /* Block the PHY control access. */
1080 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1081 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1082
1083 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1084 if (!err)
1085 break;
1086 } while (--retries);
1087
1088 err = tg3_phy_reset_chanpat(tp);
1089 if (err)
1090 return err;
1091
1092 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1093 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1094
1095 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1096 tg3_writephy(tp, 0x16, 0x0000);
1097
1098 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1099 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1100 /* Set Extended packet length bit for jumbo frames */
1101 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1102 }
1103 else {
1104 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1105 }
1106
1107 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1108
1109 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) {
1110 reg32 &= ~0x3000;
1111 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1112 } else if (!err)
1113 err = -EBUSY;
1114
1115 return err;
1116 }
1117
1118 static void tg3_link_report(struct tg3 *);
1119
1120 /* This will reset the tigon3 PHY if there is no valid
1121 * link unless the FORCE argument is non-zero.
1122 */
1123 static int tg3_phy_reset(struct tg3 *tp)
1124 {
1125 u32 cpmuctrl;
1126 u32 phy_status;
1127 int err;
1128
1129 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1130 u32 val;
1131
1132 val = tr32(GRC_MISC_CFG);
1133 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1134 udelay(40);
1135 }
1136 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1137 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1138 if (err != 0)
1139 return -EBUSY;
1140
1141 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1142 netif_carrier_off(tp->dev);
1143 tg3_link_report(tp);
1144 }
1145
1146 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1147 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1148 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1149 err = tg3_phy_reset_5703_4_5(tp);
1150 if (err)
1151 return err;
1152 goto out;
1153 }
1154
1155 cpmuctrl = 0;
1156 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1157 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1158 cpmuctrl = tr32(TG3_CPMU_CTRL);
1159 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1160 tw32(TG3_CPMU_CTRL,
1161 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1162 }
1163
1164 err = tg3_bmcr_reset(tp);
1165 if (err)
1166 return err;
1167
1168 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1169 u32 phy;
1170
1171 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1172 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1173
1174 tw32(TG3_CPMU_CTRL, cpmuctrl);
1175 }
1176
1177 if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) {
1178 u32 val;
1179
1180 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1181 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1182 CPMU_LSPD_1000MB_MACCLK_12_5) {
1183 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1184 udelay(40);
1185 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1186 }
1187
1188 /* Disable GPHY autopowerdown. */
1189 tg3_writephy(tp, MII_TG3_MISC_SHDW,
1190 MII_TG3_MISC_SHDW_WREN |
1191 MII_TG3_MISC_SHDW_APD_SEL |
1192 MII_TG3_MISC_SHDW_APD_WKTM_84MS);
1193 }
1194
1195 tg3_phy_apply_otp(tp);
1196
1197 out:
1198 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1199 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1200 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1201 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1202 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1203 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1204 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1205 }
1206 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1207 tg3_writephy(tp, 0x1c, 0x8d68);
1208 tg3_writephy(tp, 0x1c, 0x8d68);
1209 }
1210 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1211 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1212 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1213 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1214 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1215 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1216 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1217 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1218 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1219 }
1220 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1221 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1222 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1223 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1224 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1225 tg3_writephy(tp, MII_TG3_TEST1,
1226 MII_TG3_TEST1_TRIM_EN | 0x4);
1227 } else
1228 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1229 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1230 }
1231 /* Set Extended packet length bit (bit 14) on all chips that */
1232 /* support jumbo frames */
1233 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1234 /* Cannot do read-modify-write on 5401 */
1235 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1236 } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1237 u32 phy_reg;
1238
1239 /* Set bit 14 with read-modify-write to preserve other bits */
1240 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1241 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1242 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1243 }
1244
1245 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1246 * jumbo frames transmission.
1247 */
1248 if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1249 u32 phy_reg;
1250
1251 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1252 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1253 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1254 }
1255
1256 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1257 /* adjust output voltage */
1258 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1259 }
1260
1261 tg3_phy_toggle_automdix(tp, 1);
1262 tg3_phy_set_wirespeed(tp);
1263 return 0;
1264 }
1265
1266 static void tg3_frob_aux_power(struct tg3 *tp)
1267 {
1268 struct tg3 *tp_peer = tp;
1269
1270 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1271 return;
1272
1273 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1274 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1275 struct net_device *dev_peer;
1276
1277 dev_peer = pci_get_drvdata(tp->pdev_peer);
1278 /* remove_one() may have been run on the peer. */
1279 if (!dev_peer)
1280 tp_peer = tp;
1281 else
1282 tp_peer = netdev_priv(dev_peer);
1283 }
1284
1285 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1286 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1287 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1288 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1289 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1290 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1291 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1292 (GRC_LCLCTRL_GPIO_OE0 |
1293 GRC_LCLCTRL_GPIO_OE1 |
1294 GRC_LCLCTRL_GPIO_OE2 |
1295 GRC_LCLCTRL_GPIO_OUTPUT0 |
1296 GRC_LCLCTRL_GPIO_OUTPUT1),
1297 100);
1298 } else {
1299 u32 no_gpio2;
1300 u32 grc_local_ctrl = 0;
1301
1302 if (tp_peer != tp &&
1303 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1304 return;
1305
1306 /* Workaround to prevent overdrawing Amps. */
1307 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1308 ASIC_REV_5714) {
1309 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1310 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1311 grc_local_ctrl, 100);
1312 }
1313
1314 /* On 5753 and variants, GPIO2 cannot be used. */
1315 no_gpio2 = tp->nic_sram_data_cfg &
1316 NIC_SRAM_DATA_CFG_NO_GPIO2;
1317
1318 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1319 GRC_LCLCTRL_GPIO_OE1 |
1320 GRC_LCLCTRL_GPIO_OE2 |
1321 GRC_LCLCTRL_GPIO_OUTPUT1 |
1322 GRC_LCLCTRL_GPIO_OUTPUT2;
1323 if (no_gpio2) {
1324 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1325 GRC_LCLCTRL_GPIO_OUTPUT2);
1326 }
1327 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1328 grc_local_ctrl, 100);
1329
1330 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1331
1332 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1333 grc_local_ctrl, 100);
1334
1335 if (!no_gpio2) {
1336 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1337 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1338 grc_local_ctrl, 100);
1339 }
1340 }
1341 } else {
1342 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1343 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1344 if (tp_peer != tp &&
1345 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1346 return;
1347
1348 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1349 (GRC_LCLCTRL_GPIO_OE1 |
1350 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1351
1352 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1353 GRC_LCLCTRL_GPIO_OE1, 100);
1354
1355 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1356 (GRC_LCLCTRL_GPIO_OE1 |
1357 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1358 }
1359 }
1360 }
1361
1362 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
1363 {
1364 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
1365 return 1;
1366 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
1367 if (speed != SPEED_10)
1368 return 1;
1369 } else if (speed == SPEED_10)
1370 return 1;
1371
1372 return 0;
1373 }
1374
1375 static int tg3_setup_phy(struct tg3 *, int);
1376
1377 #define RESET_KIND_SHUTDOWN 0
1378 #define RESET_KIND_INIT 1
1379 #define RESET_KIND_SUSPEND 2
1380
1381 static void tg3_write_sig_post_reset(struct tg3 *, int);
1382 static int tg3_halt_cpu(struct tg3 *, u32);
1383 static int tg3_nvram_lock(struct tg3 *);
1384 static void tg3_nvram_unlock(struct tg3 *);
1385
1386 static void tg3_power_down_phy(struct tg3 *tp)
1387 {
1388 u32 val;
1389
1390 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1391 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1392 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
1393 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
1394
1395 sg_dig_ctrl |=
1396 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
1397 tw32(SG_DIG_CTRL, sg_dig_ctrl);
1398 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
1399 }
1400 return;
1401 }
1402
1403 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1404 tg3_bmcr_reset(tp);
1405 val = tr32(GRC_MISC_CFG);
1406 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
1407 udelay(40);
1408 return;
1409 } else {
1410 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1411 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1412 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1413 }
1414
1415 /* The PHY should not be powered down on some chips because
1416 * of bugs.
1417 */
1418 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1419 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1420 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1421 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1422 return;
1423
1424 if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) {
1425 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1426 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1427 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
1428 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1429 }
1430
1431 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1432 }
1433
1434 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1435 {
1436 u32 misc_host_ctrl;
1437 u16 power_control, power_caps;
1438 int pm = tp->pm_cap;
1439
1440 /* Make sure register accesses (indirect or otherwise)
1441 * will function correctly.
1442 */
1443 pci_write_config_dword(tp->pdev,
1444 TG3PCI_MISC_HOST_CTRL,
1445 tp->misc_host_ctrl);
1446
1447 pci_read_config_word(tp->pdev,
1448 pm + PCI_PM_CTRL,
1449 &power_control);
1450 power_control |= PCI_PM_CTRL_PME_STATUS;
1451 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1452 switch (state) {
1453 case PCI_D0:
1454 power_control |= 0;
1455 pci_write_config_word(tp->pdev,
1456 pm + PCI_PM_CTRL,
1457 power_control);
1458 udelay(100); /* Delay after power state change */
1459
1460 /* Switch out of Vaux if it is a NIC */
1461 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
1462 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1463
1464 return 0;
1465
1466 case PCI_D1:
1467 power_control |= 1;
1468 break;
1469
1470 case PCI_D2:
1471 power_control |= 2;
1472 break;
1473
1474 case PCI_D3hot:
1475 power_control |= 3;
1476 break;
1477
1478 default:
1479 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1480 "requested.\n",
1481 tp->dev->name, state);
1482 return -EINVAL;
1483 };
1484
1485 power_control |= PCI_PM_CTRL_PME_ENABLE;
1486
1487 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1488 tw32(TG3PCI_MISC_HOST_CTRL,
1489 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1490
1491 if (tp->link_config.phy_is_low_power == 0) {
1492 tp->link_config.phy_is_low_power = 1;
1493 tp->link_config.orig_speed = tp->link_config.speed;
1494 tp->link_config.orig_duplex = tp->link_config.duplex;
1495 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1496 }
1497
1498 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1499 tp->link_config.speed = SPEED_10;
1500 tp->link_config.duplex = DUPLEX_HALF;
1501 tp->link_config.autoneg = AUTONEG_ENABLE;
1502 tg3_setup_phy(tp, 0);
1503 }
1504
1505 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1506 u32 val;
1507
1508 val = tr32(GRC_VCPU_EXT_CTRL);
1509 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
1510 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1511 int i;
1512 u32 val;
1513
1514 for (i = 0; i < 200; i++) {
1515 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1516 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1517 break;
1518 msleep(1);
1519 }
1520 }
1521 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
1522 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1523 WOL_DRV_STATE_SHUTDOWN |
1524 WOL_DRV_WOL |
1525 WOL_SET_MAGIC_PKT);
1526
1527 pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1528
1529 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1530 u32 mac_mode;
1531
1532 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1533 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1534 udelay(40);
1535
1536 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
1537 mac_mode = MAC_MODE_PORT_MODE_GMII;
1538 else
1539 mac_mode = MAC_MODE_PORT_MODE_MII;
1540
1541 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
1542 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1543 ASIC_REV_5700) {
1544 u32 speed = (tp->tg3_flags &
1545 TG3_FLAG_WOL_SPEED_100MB) ?
1546 SPEED_100 : SPEED_10;
1547 if (tg3_5700_link_polarity(tp, speed))
1548 mac_mode |= MAC_MODE_LINK_POLARITY;
1549 else
1550 mac_mode &= ~MAC_MODE_LINK_POLARITY;
1551 }
1552 } else {
1553 mac_mode = MAC_MODE_PORT_MODE_TBI;
1554 }
1555
1556 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1557 tw32(MAC_LED_CTRL, tp->led_ctrl);
1558
1559 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1560 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1561 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1562
1563 tw32_f(MAC_MODE, mac_mode);
1564 udelay(100);
1565
1566 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1567 udelay(10);
1568 }
1569
1570 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1571 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1572 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1573 u32 base_val;
1574
1575 base_val = tp->pci_clock_ctrl;
1576 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1577 CLOCK_CTRL_TXCLK_DISABLE);
1578
1579 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1580 CLOCK_CTRL_PWRDOWN_PLL133, 40);
1581 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1582 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
1583 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
1584 /* do nothing */
1585 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1586 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1587 u32 newbits1, newbits2;
1588
1589 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1590 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1591 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1592 CLOCK_CTRL_TXCLK_DISABLE |
1593 CLOCK_CTRL_ALTCLK);
1594 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1595 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1596 newbits1 = CLOCK_CTRL_625_CORE;
1597 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1598 } else {
1599 newbits1 = CLOCK_CTRL_ALTCLK;
1600 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1601 }
1602
1603 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1604 40);
1605
1606 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1607 40);
1608
1609 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1610 u32 newbits3;
1611
1612 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1613 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1614 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1615 CLOCK_CTRL_TXCLK_DISABLE |
1616 CLOCK_CTRL_44MHZ_CORE);
1617 } else {
1618 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1619 }
1620
1621 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1622 tp->pci_clock_ctrl | newbits3, 40);
1623 }
1624 }
1625
1626 if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
1627 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
1628 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
1629 tg3_power_down_phy(tp);
1630
1631 tg3_frob_aux_power(tp);
1632
1633 /* Workaround for unstable PLL clock */
1634 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1635 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1636 u32 val = tr32(0x7d00);
1637
1638 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1639 tw32(0x7d00, val);
1640 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1641 int err;
1642
1643 err = tg3_nvram_lock(tp);
1644 tg3_halt_cpu(tp, RX_CPU_BASE);
1645 if (!err)
1646 tg3_nvram_unlock(tp);
1647 }
1648 }
1649
1650 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1651
1652 /* Finally, set the new power state. */
1653 pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1654 udelay(100); /* Delay after power state change */
1655
1656 return 0;
1657 }
1658
1659 static void tg3_link_report(struct tg3 *tp)
1660 {
1661 if (!netif_carrier_ok(tp->dev)) {
1662 if (netif_msg_link(tp))
1663 printk(KERN_INFO PFX "%s: Link is down.\n",
1664 tp->dev->name);
1665 } else if (netif_msg_link(tp)) {
1666 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1667 tp->dev->name,
1668 (tp->link_config.active_speed == SPEED_1000 ?
1669 1000 :
1670 (tp->link_config.active_speed == SPEED_100 ?
1671 100 : 10)),
1672 (tp->link_config.active_duplex == DUPLEX_FULL ?
1673 "full" : "half"));
1674
1675 printk(KERN_INFO PFX
1676 "%s: Flow control is %s for TX and %s for RX.\n",
1677 tp->dev->name,
1678 (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_TX) ?
1679 "on" : "off",
1680 (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_RX) ?
1681 "on" : "off");
1682 }
1683 }
1684
1685 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1686 {
1687 u16 miireg;
1688
1689 if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
1690 miireg = ADVERTISE_PAUSE_CAP;
1691 else if (flow_ctrl & TG3_FLOW_CTRL_TX)
1692 miireg = ADVERTISE_PAUSE_ASYM;
1693 else if (flow_ctrl & TG3_FLOW_CTRL_RX)
1694 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1695 else
1696 miireg = 0;
1697
1698 return miireg;
1699 }
1700
1701 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1702 {
1703 u16 miireg;
1704
1705 if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
1706 miireg = ADVERTISE_1000XPAUSE;
1707 else if (flow_ctrl & TG3_FLOW_CTRL_TX)
1708 miireg = ADVERTISE_1000XPSE_ASYM;
1709 else if (flow_ctrl & TG3_FLOW_CTRL_RX)
1710 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1711 else
1712 miireg = 0;
1713
1714 return miireg;
1715 }
1716
1717 static u8 tg3_resolve_flowctrl_1000T(u16 lcladv, u16 rmtadv)
1718 {
1719 u8 cap = 0;
1720
1721 if (lcladv & ADVERTISE_PAUSE_CAP) {
1722 if (lcladv & ADVERTISE_PAUSE_ASYM) {
1723 if (rmtadv & LPA_PAUSE_CAP)
1724 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1725 else if (rmtadv & LPA_PAUSE_ASYM)
1726 cap = TG3_FLOW_CTRL_RX;
1727 } else {
1728 if (rmtadv & LPA_PAUSE_CAP)
1729 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1730 }
1731 } else if (lcladv & ADVERTISE_PAUSE_ASYM) {
1732 if ((rmtadv & LPA_PAUSE_CAP) && (rmtadv & LPA_PAUSE_ASYM))
1733 cap = TG3_FLOW_CTRL_TX;
1734 }
1735
1736 return cap;
1737 }
1738
1739 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1740 {
1741 u8 cap = 0;
1742
1743 if (lcladv & ADVERTISE_1000XPAUSE) {
1744 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1745 if (rmtadv & LPA_1000XPAUSE)
1746 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1747 else if (rmtadv & LPA_1000XPAUSE_ASYM)
1748 cap = TG3_FLOW_CTRL_RX;
1749 } else {
1750 if (rmtadv & LPA_1000XPAUSE)
1751 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1752 }
1753 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1754 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1755 cap = TG3_FLOW_CTRL_TX;
1756 }
1757
1758 return cap;
1759 }
1760
1761 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1762 {
1763 u8 new_tg3_flags = 0;
1764 u32 old_rx_mode = tp->rx_mode;
1765 u32 old_tx_mode = tp->tx_mode;
1766
1767 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
1768 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1769 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1770 new_tg3_flags = tg3_resolve_flowctrl_1000X(local_adv,
1771 remote_adv);
1772 else
1773 new_tg3_flags = tg3_resolve_flowctrl_1000T(local_adv,
1774 remote_adv);
1775 } else {
1776 new_tg3_flags = tp->link_config.flowctrl;
1777 }
1778
1779 tp->link_config.active_flowctrl = new_tg3_flags;
1780
1781 if (new_tg3_flags & TG3_FLOW_CTRL_RX)
1782 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1783 else
1784 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1785
1786 if (old_rx_mode != tp->rx_mode) {
1787 tw32_f(MAC_RX_MODE, tp->rx_mode);
1788 }
1789
1790 if (new_tg3_flags & TG3_FLOW_CTRL_TX)
1791 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1792 else
1793 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1794
1795 if (old_tx_mode != tp->tx_mode) {
1796 tw32_f(MAC_TX_MODE, tp->tx_mode);
1797 }
1798 }
1799
1800 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1801 {
1802 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1803 case MII_TG3_AUX_STAT_10HALF:
1804 *speed = SPEED_10;
1805 *duplex = DUPLEX_HALF;
1806 break;
1807
1808 case MII_TG3_AUX_STAT_10FULL:
1809 *speed = SPEED_10;
1810 *duplex = DUPLEX_FULL;
1811 break;
1812
1813 case MII_TG3_AUX_STAT_100HALF:
1814 *speed = SPEED_100;
1815 *duplex = DUPLEX_HALF;
1816 break;
1817
1818 case MII_TG3_AUX_STAT_100FULL:
1819 *speed = SPEED_100;
1820 *duplex = DUPLEX_FULL;
1821 break;
1822
1823 case MII_TG3_AUX_STAT_1000HALF:
1824 *speed = SPEED_1000;
1825 *duplex = DUPLEX_HALF;
1826 break;
1827
1828 case MII_TG3_AUX_STAT_1000FULL:
1829 *speed = SPEED_1000;
1830 *duplex = DUPLEX_FULL;
1831 break;
1832
1833 default:
1834 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1835 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
1836 SPEED_10;
1837 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
1838 DUPLEX_HALF;
1839 break;
1840 }
1841 *speed = SPEED_INVALID;
1842 *duplex = DUPLEX_INVALID;
1843 break;
1844 };
1845 }
1846
1847 static void tg3_phy_copper_begin(struct tg3 *tp)
1848 {
1849 u32 new_adv;
1850 int i;
1851
1852 if (tp->link_config.phy_is_low_power) {
1853 /* Entering low power mode. Disable gigabit and
1854 * 100baseT advertisements.
1855 */
1856 tg3_writephy(tp, MII_TG3_CTRL, 0);
1857
1858 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1859 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1860 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1861 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1862
1863 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1864 } else if (tp->link_config.speed == SPEED_INVALID) {
1865 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1866 tp->link_config.advertising &=
1867 ~(ADVERTISED_1000baseT_Half |
1868 ADVERTISED_1000baseT_Full);
1869
1870 new_adv = ADVERTISE_CSMA;
1871 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1872 new_adv |= ADVERTISE_10HALF;
1873 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1874 new_adv |= ADVERTISE_10FULL;
1875 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1876 new_adv |= ADVERTISE_100HALF;
1877 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1878 new_adv |= ADVERTISE_100FULL;
1879
1880 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
1881
1882 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1883
1884 if (tp->link_config.advertising &
1885 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1886 new_adv = 0;
1887 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1888 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1889 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1890 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1891 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1892 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1893 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1894 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1895 MII_TG3_CTRL_ENABLE_AS_MASTER);
1896 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1897 } else {
1898 tg3_writephy(tp, MII_TG3_CTRL, 0);
1899 }
1900 } else {
1901 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
1902 new_adv |= ADVERTISE_CSMA;
1903
1904 /* Asking for a specific link mode. */
1905 if (tp->link_config.speed == SPEED_1000) {
1906 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1907
1908 if (tp->link_config.duplex == DUPLEX_FULL)
1909 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1910 else
1911 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1912 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1913 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1914 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1915 MII_TG3_CTRL_ENABLE_AS_MASTER);
1916 } else {
1917 if (tp->link_config.speed == SPEED_100) {
1918 if (tp->link_config.duplex == DUPLEX_FULL)
1919 new_adv |= ADVERTISE_100FULL;
1920 else
1921 new_adv |= ADVERTISE_100HALF;
1922 } else {
1923 if (tp->link_config.duplex == DUPLEX_FULL)
1924 new_adv |= ADVERTISE_10FULL;
1925 else
1926 new_adv |= ADVERTISE_10HALF;
1927 }
1928 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1929
1930 new_adv = 0;
1931 }
1932
1933 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1934 }
1935
1936 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1937 tp->link_config.speed != SPEED_INVALID) {
1938 u32 bmcr, orig_bmcr;
1939
1940 tp->link_config.active_speed = tp->link_config.speed;
1941 tp->link_config.active_duplex = tp->link_config.duplex;
1942
1943 bmcr = 0;
1944 switch (tp->link_config.speed) {
1945 default:
1946 case SPEED_10:
1947 break;
1948
1949 case SPEED_100:
1950 bmcr |= BMCR_SPEED100;
1951 break;
1952
1953 case SPEED_1000:
1954 bmcr |= TG3_BMCR_SPEED1000;
1955 break;
1956 };
1957
1958 if (tp->link_config.duplex == DUPLEX_FULL)
1959 bmcr |= BMCR_FULLDPLX;
1960
1961 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1962 (bmcr != orig_bmcr)) {
1963 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1964 for (i = 0; i < 1500; i++) {
1965 u32 tmp;
1966
1967 udelay(10);
1968 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1969 tg3_readphy(tp, MII_BMSR, &tmp))
1970 continue;
1971 if (!(tmp & BMSR_LSTATUS)) {
1972 udelay(40);
1973 break;
1974 }
1975 }
1976 tg3_writephy(tp, MII_BMCR, bmcr);
1977 udelay(40);
1978 }
1979 } else {
1980 tg3_writephy(tp, MII_BMCR,
1981 BMCR_ANENABLE | BMCR_ANRESTART);
1982 }
1983 }
1984
1985 static int tg3_init_5401phy_dsp(struct tg3 *tp)
1986 {
1987 int err;
1988
1989 /* Turn off tap power management. */
1990 /* Set Extended packet length bit */
1991 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1992
1993 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1994 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1995
1996 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1997 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1998
1999 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2000 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2001
2002 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2003 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2004
2005 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2006 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2007
2008 udelay(40);
2009
2010 return err;
2011 }
2012
2013 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2014 {
2015 u32 adv_reg, all_mask = 0;
2016
2017 if (mask & ADVERTISED_10baseT_Half)
2018 all_mask |= ADVERTISE_10HALF;
2019 if (mask & ADVERTISED_10baseT_Full)
2020 all_mask |= ADVERTISE_10FULL;
2021 if (mask & ADVERTISED_100baseT_Half)
2022 all_mask |= ADVERTISE_100HALF;
2023 if (mask & ADVERTISED_100baseT_Full)
2024 all_mask |= ADVERTISE_100FULL;
2025
2026 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2027 return 0;
2028
2029 if ((adv_reg & all_mask) != all_mask)
2030 return 0;
2031 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2032 u32 tg3_ctrl;
2033
2034 all_mask = 0;
2035 if (mask & ADVERTISED_1000baseT_Half)
2036 all_mask |= ADVERTISE_1000HALF;
2037 if (mask & ADVERTISED_1000baseT_Full)
2038 all_mask |= ADVERTISE_1000FULL;
2039
2040 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2041 return 0;
2042
2043 if ((tg3_ctrl & all_mask) != all_mask)
2044 return 0;
2045 }
2046 return 1;
2047 }
2048
2049 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2050 {
2051 u32 curadv, reqadv;
2052
2053 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2054 return 1;
2055
2056 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2057 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2058
2059 if (tp->link_config.active_duplex == DUPLEX_FULL) {
2060 if (curadv != reqadv)
2061 return 0;
2062
2063 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2064 tg3_readphy(tp, MII_LPA, rmtadv);
2065 } else {
2066 /* Reprogram the advertisement register, even if it
2067 * does not affect the current link. If the link
2068 * gets renegotiated in the future, we can save an
2069 * additional renegotiation cycle by advertising
2070 * it correctly in the first place.
2071 */
2072 if (curadv != reqadv) {
2073 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2074 ADVERTISE_PAUSE_ASYM);
2075 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2076 }
2077 }
2078
2079 return 1;
2080 }
2081
2082 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2083 {
2084 int current_link_up;
2085 u32 bmsr, dummy;
2086 u32 lcl_adv, rmt_adv;
2087 u16 current_speed;
2088 u8 current_duplex;
2089 int i, err;
2090
2091 tw32(MAC_EVENT, 0);
2092
2093 tw32_f(MAC_STATUS,
2094 (MAC_STATUS_SYNC_CHANGED |
2095 MAC_STATUS_CFG_CHANGED |
2096 MAC_STATUS_MI_COMPLETION |
2097 MAC_STATUS_LNKSTATE_CHANGED));
2098 udelay(40);
2099
2100 tp->mi_mode = MAC_MI_MODE_BASE;
2101 tw32_f(MAC_MI_MODE, tp->mi_mode);
2102 udelay(80);
2103
2104 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2105
2106 /* Some third-party PHYs need to be reset on link going
2107 * down.
2108 */
2109 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2110 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2111 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2112 netif_carrier_ok(tp->dev)) {
2113 tg3_readphy(tp, MII_BMSR, &bmsr);
2114 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2115 !(bmsr & BMSR_LSTATUS))
2116 force_reset = 1;
2117 }
2118 if (force_reset)
2119 tg3_phy_reset(tp);
2120
2121 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2122 tg3_readphy(tp, MII_BMSR, &bmsr);
2123 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2124 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2125 bmsr = 0;
2126
2127 if (!(bmsr & BMSR_LSTATUS)) {
2128 err = tg3_init_5401phy_dsp(tp);
2129 if (err)
2130 return err;
2131
2132 tg3_readphy(tp, MII_BMSR, &bmsr);
2133 for (i = 0; i < 1000; i++) {
2134 udelay(10);
2135 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2136 (bmsr & BMSR_LSTATUS)) {
2137 udelay(40);
2138 break;
2139 }
2140 }
2141
2142 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
2143 !(bmsr & BMSR_LSTATUS) &&
2144 tp->link_config.active_speed == SPEED_1000) {
2145 err = tg3_phy_reset(tp);
2146 if (!err)
2147 err = tg3_init_5401phy_dsp(tp);
2148 if (err)
2149 return err;
2150 }
2151 }
2152 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2153 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
2154 /* 5701 {A0,B0} CRC bug workaround */
2155 tg3_writephy(tp, 0x15, 0x0a75);
2156 tg3_writephy(tp, 0x1c, 0x8c68);
2157 tg3_writephy(tp, 0x1c, 0x8d68);
2158 tg3_writephy(tp, 0x1c, 0x8c68);
2159 }
2160
2161 /* Clear pending interrupts... */
2162 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2163 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2164
2165 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
2166 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
2167 else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
2168 tg3_writephy(tp, MII_TG3_IMASK, ~0);
2169
2170 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2171 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2172 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
2173 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2174 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
2175 else
2176 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
2177 }
2178
2179 current_link_up = 0;
2180 current_speed = SPEED_INVALID;
2181 current_duplex = DUPLEX_INVALID;
2182
2183 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
2184 u32 val;
2185
2186 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
2187 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
2188 if (!(val & (1 << 10))) {
2189 val |= (1 << 10);
2190 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2191 goto relink;
2192 }
2193 }
2194
2195 bmsr = 0;
2196 for (i = 0; i < 100; i++) {
2197 tg3_readphy(tp, MII_BMSR, &bmsr);
2198 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2199 (bmsr & BMSR_LSTATUS))
2200 break;
2201 udelay(40);
2202 }
2203
2204 if (bmsr & BMSR_LSTATUS) {
2205 u32 aux_stat, bmcr;
2206
2207 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
2208 for (i = 0; i < 2000; i++) {
2209 udelay(10);
2210 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
2211 aux_stat)
2212 break;
2213 }
2214
2215 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
2216 ¤t_speed,
2217 ¤t_duplex);
2218
2219 bmcr = 0;
2220 for (i = 0; i < 200; i++) {
2221 tg3_readphy(tp, MII_BMCR, &bmcr);
2222 if (tg3_readphy(tp, MII_BMCR, &bmcr))
2223 continue;
2224 if (bmcr && bmcr != 0x7fff)
2225 break;
2226 udelay(10);
2227 }
2228
2229 lcl_adv = 0;
2230 rmt_adv = 0;
2231
2232 tp->link_config.active_speed = current_speed;
2233 tp->link_config.active_duplex = current_duplex;
2234
2235 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2236 if ((bmcr & BMCR_ANENABLE) &&
2237 tg3_copper_is_advertising_all(tp,
2238 tp->link_config.advertising)) {
2239 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
2240 &rmt_adv))
2241 current_link_up = 1;
2242 }
2243 } else {
2244 if (!(bmcr & BMCR_ANENABLE) &&
2245 tp->link_config.speed == current_speed &&
2246 tp->link_config.duplex == current_duplex &&
2247 tp->link_config.flowctrl ==
2248 tp->link_config.active_flowctrl) {
2249 current_link_up = 1;
2250 }
2251 }
2252
2253 if (current_link_up == 1 &&
2254 tp->link_config.active_duplex == DUPLEX_FULL)
2255 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2256 }
2257
2258 relink:
2259 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
2260 u32 tmp;
2261
2262 tg3_phy_copper_begin(tp);
2263
2264 tg3_readphy(tp, MII_BMSR, &tmp);
2265 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
2266 (tmp & BMSR_LSTATUS))
2267 current_link_up = 1;
2268 }
2269
2270 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
2271 if (current_link_up == 1) {
2272 if (tp->link_config.active_speed == SPEED_100 ||
2273 tp->link_config.active_speed == SPEED_10)
2274 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
2275 else
2276 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2277 } else
2278 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2279
2280 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2281 if (tp->link_config.active_duplex == DUPLEX_HALF)
2282 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2283
2284 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
2285 if (current_link_up == 1 &&
2286 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
2287 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
2288 else
2289 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2290 }
2291
2292 /* ??? Without this setting Netgear GA302T PHY does not
2293 * ??? send/receive packets...
2294 */
2295 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
2296 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2297 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2298 tw32_f(MAC_MI_MODE, tp->mi_mode);
2299 udelay(80);
2300 }
2301
2302 tw32_f(MAC_MODE, tp->mac_mode);
2303 udelay(40);
2304
2305 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2306 /* Polled via timer. */
2307 tw32_f(MAC_EVENT, 0);
2308 } else {
2309 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2310 }
2311 udelay(40);
2312
2313 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2314 current_link_up == 1 &&
2315 tp->link_config.active_speed == SPEED_1000 &&
2316 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2317 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2318 udelay(120);
2319 tw32_f(MAC_STATUS,
2320 (MAC_STATUS_SYNC_CHANGED |
2321 MAC_STATUS_CFG_CHANGED));
2322 udelay(40);
2323 tg3_write_mem(tp,
2324 NIC_SRAM_FIRMWARE_MBOX,
2325 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2326 }
2327
2328 if (current_link_up != netif_carrier_ok(tp->dev)) {
2329 if (current_link_up)
2330 netif_carrier_on(tp->dev);
2331 else
2332 netif_carrier_off(tp->dev);
2333 tg3_link_report(tp);
2334 }
2335
2336 return 0;
2337 }
2338
2339 struct tg3_fiber_aneginfo {
2340 int state;
2341 #define ANEG_STATE_UNKNOWN 0
2342 #define ANEG_STATE_AN_ENABLE 1
2343 #define ANEG_STATE_RESTART_INIT 2
2344 #define ANEG_STATE_RESTART 3
2345 #define ANEG_STATE_DISABLE_LINK_OK 4
2346 #define ANEG_STATE_ABILITY_DETECT_INIT 5
2347 #define ANEG_STATE_ABILITY_DETECT 6
2348 #define ANEG_STATE_ACK_DETECT_INIT 7
2349 #define ANEG_STATE_ACK_DETECT 8
2350 #define ANEG_STATE_COMPLETE_ACK_INIT 9
2351 #define ANEG_STATE_COMPLETE_ACK 10
2352 #define ANEG_STATE_IDLE_DETECT_INIT 11
2353 #define ANEG_STATE_IDLE_DETECT 12
2354 #define ANEG_STATE_LINK_OK 13
2355 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
2356 #define ANEG_STATE_NEXT_PAGE_WAIT 15
2357
2358 u32 flags;
2359 #define MR_AN_ENABLE 0x00000001
2360 #define MR_RESTART_AN 0x00000002
2361 #define MR_AN_COMPLETE 0x00000004
2362 #define MR_PAGE_RX 0x00000008
2363 #define MR_NP_LOADED 0x00000010
2364 #define MR_TOGGLE_TX 0x00000020
2365 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
2366 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
2367 #define MR_LP_ADV_SYM_PAUSE 0x00000100
2368 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
2369 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2370 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2371 #define MR_LP_ADV_NEXT_PAGE 0x00001000
2372 #define MR_TOGGLE_RX 0x00002000
2373 #define MR_NP_RX 0x00004000
2374
2375 #define MR_LINK_OK 0x80000000
2376
2377 unsigned long link_time, cur_time;
2378
2379 u32 ability_match_cfg;
2380 int ability_match_count;
2381
2382 char ability_match, idle_match, ack_match;
2383
2384 u32 txconfig, rxconfig;
2385 #define ANEG_CFG_NP 0x00000080
2386 #define ANEG_CFG_ACK 0x00000040
2387 #define ANEG_CFG_RF2 0x00000020
2388 #define ANEG_CFG_RF1 0x00000010
2389 #define ANEG_CFG_PS2 0x00000001
2390 #define ANEG_CFG_PS1 0x00008000
2391 #define ANEG_CFG_HD 0x00004000
2392 #define ANEG_CFG_FD 0x00002000
2393 #define ANEG_CFG_INVAL 0x00001f06
2394
2395 };
2396 #define ANEG_OK 0
2397 #define ANEG_DONE 1
2398 #define ANEG_TIMER_ENAB 2
2399 #define ANEG_FAILED -1
2400
2401 #define ANEG_STATE_SETTLE_TIME 10000
2402
2403 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2404 struct tg3_fiber_aneginfo *ap)
2405 {
2406 u16 flowctrl;
2407 unsigned long delta;
2408 u32 rx_cfg_reg;
2409 int ret;
2410
2411 if (ap->state == ANEG_STATE_UNKNOWN) {
2412 ap->rxconfig = 0;
2413 ap->link_time = 0;
2414 ap->cur_time = 0;
2415 ap->ability_match_cfg = 0;
2416 ap->ability_match_count = 0;
2417 ap->ability_match = 0;
2418 ap->idle_match = 0;
2419 ap->ack_match = 0;
2420 }
2421 ap->cur_time++;
2422
2423 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2424 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2425
2426 if (rx_cfg_reg != ap->ability_match_cfg) {
2427 ap->ability_match_cfg = rx_cfg_reg;
2428 ap->ability_match = 0;
2429 ap->ability_match_count = 0;
2430 } else {
2431 if (++ap->ability_match_count > 1) {
2432 ap->ability_match = 1;
2433 ap->ability_match_cfg = rx_cfg_reg;
2434 }
2435 }
2436 if (rx_cfg_reg & ANEG_CFG_ACK)
2437 ap->ack_match = 1;
2438 else
2439 ap->ack_match = 0;
2440
2441 ap->idle_match = 0;
2442 } else {
2443 ap->idle_match = 1;
2444 ap->ability_match_cfg = 0;
2445 ap->ability_match_count = 0;
2446 ap->ability_match = 0;
2447 ap->ack_match = 0;
2448
2449 rx_cfg_reg = 0;
2450 }
2451
2452 ap->rxconfig = rx_cfg_reg;
2453 ret = ANEG_OK;
2454
2455 switch(ap->state) {
2456 case ANEG_STATE_UNKNOWN:
2457 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2458 ap->state = ANEG_STATE_AN_ENABLE;
2459
2460 /* fallthru */
2461 case ANEG_STATE_AN_ENABLE:
2462 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2463 if (ap->flags & MR_AN_ENABLE) {
2464 ap->link_time = 0;
2465 ap->cur_time = 0;
2466 ap->ability_match_cfg = 0;
2467 ap->ability_match_count = 0;
2468 ap->ability_match = 0;
2469 ap->idle_match = 0;
2470 ap->ack_match = 0;
2471
2472 ap->state = ANEG_STATE_RESTART_INIT;
2473 } else {
2474 ap->state = ANEG_STATE_DISABLE_LINK_OK;
2475 }
2476 break;
2477
2478 case ANEG_STATE_RESTART_INIT:
2479 ap->link_time = ap->cur_time;
2480 ap->flags &= ~(MR_NP_LOADED);
2481 ap->txconfig = 0;
2482 tw32(MAC_TX_AUTO_NEG, 0);
2483 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2484 tw32_f(MAC_MODE, tp->mac_mode);
2485 udelay(40);
2486
2487 ret = ANEG_TIMER_ENAB;
2488 ap->state = ANEG_STATE_RESTART;
2489
2490 /* fallthru */
2491 case ANEG_STATE_RESTART:
2492 delta = ap->cur_time - ap->link_time;
2493 if (delta > ANEG_STATE_SETTLE_TIME) {
2494 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2495 } else {
2496 ret = ANEG_TIMER_ENAB;
2497 }
2498 break;
2499
2500 case ANEG_STATE_DISABLE_LINK_OK:
2501 ret = ANEG_DONE;
2502 break;
2503
2504 case ANEG_STATE_ABILITY_DETECT_INIT:
2505 ap->flags &= ~(MR_TOGGLE_TX);
2506 ap->txconfig = ANEG_CFG_FD;
2507 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
2508 if (flowctrl & ADVERTISE_1000XPAUSE)
2509 ap->txconfig |= ANEG_CFG_PS1;
2510 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
2511 ap->txconfig |= ANEG_CFG_PS2;
2512 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2513 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2514 tw32_f(MAC_MODE, tp->mac_mode);
2515 udelay(40);
2516
2517 ap->state = ANEG_STATE_ABILITY_DETECT;
2518 break;
2519
2520 case ANEG_STATE_ABILITY_DETECT:
2521 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2522 ap->state = ANEG_STATE_ACK_DETECT_INIT;
2523 }
2524 break;
2525
2526 case ANEG_STATE_ACK_DETECT_INIT:
2527 ap->txconfig |= ANEG_CFG_ACK;
2528 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2529 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2530 tw32_f(MAC_MODE, tp->mac_mode);
2531 udelay(40);
2532
2533 ap->state = ANEG_STATE_ACK_DETECT;
2534
2535 /* fallthru */
2536 case ANEG_STATE_ACK_DETECT:
2537 if (ap->ack_match != 0) {
2538 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2539 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2540 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2541 } else {
2542 ap->state = ANEG_STATE_AN_ENABLE;
2543 }
2544 } else if (ap->ability_match != 0 &&
2545 ap->rxconfig == 0) {
2546 ap->state = ANEG_STATE_AN_ENABLE;
2547 }
2548 break;
2549
2550 case ANEG_STATE_COMPLETE_ACK_INIT:
2551 if (ap->rxconfig & ANEG_CFG_INVAL) {
2552 ret = ANEG_FAILED;
2553 break;
2554 }
2555 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2556 MR_LP_ADV_HALF_DUPLEX |
2557 MR_LP_ADV_SYM_PAUSE |
2558 MR_LP_ADV_ASYM_PAUSE |
2559 MR_LP_ADV_REMOTE_FAULT1 |
2560 MR_LP_ADV_REMOTE_FAULT2 |
2561 MR_LP_ADV_NEXT_PAGE |
2562 MR_TOGGLE_RX |
2563 MR_NP_RX);
2564 if (ap->rxconfig & ANEG_CFG_FD)
2565 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2566 if (ap->rxconfig & ANEG_CFG_HD)
2567 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2568 if (ap->rxconfig & ANEG_CFG_PS1)
2569 ap->flags |= MR_LP_ADV_SYM_PAUSE;
2570 if (ap->rxconfig & ANEG_CFG_PS2)
2571 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2572 if (ap->rxconfig & ANEG_CFG_RF1)
2573 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2574 if (ap->rxconfig & ANEG_CFG_RF2)
2575 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2576 if (ap->rxconfig & ANEG_CFG_NP)
2577 ap->flags |= MR_LP_ADV_NEXT_PAGE;
2578
2579 ap->link_time = ap->cur_time;
2580
2581 ap->flags ^= (MR_TOGGLE_TX);
2582 if (ap->rxconfig & 0x0008)
2583 ap->flags |= MR_TOGGLE_RX;
2584 if (ap->rxconfig & ANEG_CFG_NP)
2585 ap->flags |= MR_NP_RX;
2586 ap->flags |= MR_PAGE_RX;
2587
2588 ap->state = ANEG_STATE_COMPLETE_ACK;
2589 ret = ANEG_TIMER_ENAB;
2590 break;
2591
2592 case ANEG_STATE_COMPLETE_ACK:
2593 if (ap->ability_match != 0 &&
2594 ap->rxconfig == 0) {
2595 ap->state = ANEG_STATE_AN_ENABLE;
2596 break;
2597 }
2598 delta = ap->cur_time - ap->link_time;
2599 if (delta > ANEG_STATE_SETTLE_TIME) {
2600 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2601 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2602 } else {
2603 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2604 !(ap->flags & MR_NP_RX)) {
2605 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2606 } else {
2607 ret = ANEG_FAILED;
2608 }
2609 }
2610 }
2611 break;
2612
2613 case ANEG_STATE_IDLE_DETECT_INIT:
2614 ap->link_time = ap->cur_time;
2615 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2616 tw32_f(MAC_MODE, tp->mac_mode);
2617 udelay(40);
2618
2619 ap->state = ANEG_STATE_IDLE_DETECT;
2620 ret = ANEG_TIMER_ENAB;
2621 break;
2622
2623 case ANEG_STATE_IDLE_DETECT:
2624 if (ap->ability_match != 0 &&
2625 ap->rxconfig == 0) {
2626 ap->state = ANEG_STATE_AN_ENABLE;
2627 break;
2628 }
2629 delta = ap->cur_time - ap->link_time;
2630 if (delta > ANEG_STATE_SETTLE_TIME) {
2631 /* XXX another gem from the Broadcom driver :( */
2632 ap->state = ANEG_STATE_LINK_OK;
2633 }
2634 break;
2635
2636 case ANEG_STATE_LINK_OK:
2637 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2638 ret = ANEG_DONE;
2639 break;
2640
2641 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2642 /* ??? unimplemented */
2643 break;
2644
2645 case ANEG_STATE_NEXT_PAGE_WAIT:
2646 /* ??? unimplemented */
2647 break;
2648
2649 default:
2650 ret = ANEG_FAILED;
2651 break;
2652 };
2653
2654 return ret;
2655 }
2656
2657 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
2658 {
2659 int res = 0;
2660 struct tg3_fiber_aneginfo aninfo;
2661 int status = ANEG_FAILED;
2662 unsigned int tick;
2663 u32 tmp;
2664
2665 tw32_f(MAC_TX_AUTO_NEG, 0);
2666
2667 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2668 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2669 udelay(40);
2670
2671 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2672 udelay(40);
2673
2674 memset(&aninfo, 0, sizeof(aninfo));
2675 aninfo.flags |= MR_AN_ENABLE;
2676 aninfo.state = ANEG_STATE_UNKNOWN;
2677 aninfo.cur_time = 0;
2678 tick = 0;
2679 while (++tick < 195000) {
2680 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2681 if (status == ANEG_DONE || status == ANEG_FAILED)
2682 break;
2683
2684 udelay(1);
2685 }
2686
2687 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2688 tw32_f(MAC_MODE, tp->mac_mode);
2689 udelay(40);
2690
2691 *txflags = aninfo.txconfig;
2692 *rxflags = aninfo.flags;
2693
2694 if (status == ANEG_DONE &&
2695 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2696 MR_LP_ADV_FULL_DUPLEX)))
2697 res = 1;
2698
2699 return res;
2700 }
2701
2702 static void tg3_init_bcm8002(struct tg3 *tp)
2703 {
2704 u32 mac_status = tr32(MAC_STATUS);
2705 int i;
2706
2707 /* Reset when initting first time or we have a link. */
2708 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2709 !(mac_status & MAC_STATUS_PCS_SYNCED))
2710 return;
2711
2712 /* Set PLL lock range. */
2713 tg3_writephy(tp, 0x16, 0x8007);
2714
2715 /* SW reset */
2716 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2717
2718 /* Wait for reset to complete. */
2719 /* XXX schedule_timeout() ... */
2720 for (i = 0; i < 500; i++)
2721 udelay(10);
2722
2723 /* Config mode; select PMA/Ch 1 regs. */
2724 tg3_writephy(tp, 0x10, 0x8411);
2725
2726 /* Enable auto-lock and comdet, select txclk for tx. */
2727 tg3_writephy(tp, 0x11, 0x0a10);
2728
2729 tg3_writephy(tp, 0x18, 0x00a0);
2730 tg3_writephy(tp, 0x16, 0x41ff);
2731
2732 /* Assert and deassert POR. */
2733 tg3_writephy(tp, 0x13, 0x0400);
2734 udelay(40);
2735 tg3_writephy(tp, 0x13, 0x0000);
2736
2737 tg3_writephy(tp, 0x11, 0x0a50);
2738 udelay(40);
2739 tg3_writephy(tp, 0x11, 0x0a10);
2740
2741 /* Wait for signal to stabilize */
2742 /* XXX schedule_timeout() ... */
2743 for (i = 0; i < 15000; i++)
2744 udelay(10);
2745
2746 /* Deselect the channel register so we can read the PHYID
2747 * later.
2748 */
2749 tg3_writephy(tp, 0x10, 0x8011);
2750 }
2751
2752 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2753 {
2754 u16 flowctrl;
2755 u32 sg_dig_ctrl, sg_dig_status;
2756 u32 serdes_cfg, expected_sg_dig_ctrl;
2757 int workaround, port_a;
2758 int current_link_up;
2759
2760 serdes_cfg = 0;
2761 expected_sg_dig_ctrl = 0;
2762 workaround = 0;
2763 port_a = 1;
2764 current_link_up = 0;
2765
2766 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2767 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2768 workaround = 1;
2769 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2770 port_a = 0;
2771
2772 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2773 /* preserve bits 20-23 for voltage regulator */
2774 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2775 }
2776
2777 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2778
2779 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2780 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
2781 if (workaround) {
2782 u32 val = serdes_cfg;
2783
2784 if (port_a)
2785 val |= 0xc010000;
2786 else
2787 val |= 0x4010000;
2788 tw32_f(MAC_SERDES_CFG, val);
2789 }
2790
2791 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
2792 }
2793 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2794 tg3_setup_flow_control(tp, 0, 0);
2795 current_link_up = 1;
2796 }
2797 goto out;
2798 }
2799
2800 /* Want auto-negotiation. */
2801 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
2802
2803 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
2804 if (flowctrl & ADVERTISE_1000XPAUSE)
2805 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
2806 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
2807 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
2808
2809 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2810 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
2811 tp->serdes_counter &&
2812 ((mac_status & (MAC_STATUS_PCS_SYNCED |
2813 MAC_STATUS_RCVD_CFG)) ==
2814 MAC_STATUS_PCS_SYNCED)) {
2815 tp->serdes_counter--;
2816 current_link_up = 1;
2817 goto out;
2818 }
2819 restart_autoneg:
2820 if (workaround)
2821 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2822 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
2823 udelay(5);
2824 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2825
2826 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2827 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2828 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2829 MAC_STATUS_SIGNAL_DET)) {
2830 sg_dig_status = tr32(SG_DIG_STATUS);
2831 mac_status = tr32(MAC_STATUS);
2832
2833 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
2834 (mac_status & MAC_STATUS_PCS_SYNCED)) {
2835 u32 local_adv = 0, remote_adv = 0;
2836
2837 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
2838 local_adv |= ADVERTISE_1000XPAUSE;
2839 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
2840 local_adv |= ADVERTISE_1000XPSE_ASYM;
2841
2842 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
2843 remote_adv |= LPA_1000XPAUSE;
2844 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
2845 remote_adv |= LPA_1000XPAUSE_ASYM;
2846
2847 tg3_setup_flow_control(tp, local_adv, remote_adv);
2848 current_link_up = 1;
2849 tp->serdes_counter = 0;
2850 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2851 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
2852 if (tp->serdes_counter)
2853 tp->serdes_counter--;
2854 else {
2855 if (workaround) {
2856 u32 val = serdes_cfg;
2857
2858 if (port_a)
2859 val |= 0xc010000;
2860 else
2861 val |= 0x4010000;
2862
2863 tw32_f(MAC_SERDES_CFG, val);
2864 }
2865
2866 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
2867 udelay(40);
2868
2869 /* Link parallel detection - link is up */
2870 /* only if we have PCS_SYNC and not */
2871 /* receiving config code words */
2872 mac_status = tr32(MAC_STATUS);
2873 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2874 !(mac_status & MAC_STATUS_RCVD_CFG)) {
2875 tg3_setup_flow_control(tp, 0, 0);
2876 current_link_up = 1;
2877 tp->tg3_flags2 |=
2878 TG3_FLG2_PARALLEL_DETECT;
2879 tp->serdes_counter =
2880 SERDES_PARALLEL_DET_TIMEOUT;
2881 } else
2882 goto restart_autoneg;
2883 }
2884 }
2885 } else {
2886 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2887 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2888 }
2889
2890 out:
2891 return current_link_up;
2892 }
2893
2894 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2895 {
2896 int current_link_up = 0;
2897
2898 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
2899 goto out;
2900
2901 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2902 u32 txflags, rxflags;
2903 int i;
2904
2905 if (fiber_autoneg(tp, &txflags, &rxflags)) {
2906 u32 local_adv = 0, remote_adv = 0;
2907
2908 if (txflags & ANEG_CFG_PS1)
2909 local_adv |= ADVERTISE_1000XPAUSE;
2910 if (txflags & ANEG_CFG_PS2)
2911 local_adv |= ADVERTISE_1000XPSE_ASYM;
2912
2913 if (rxflags & MR_LP_ADV_SYM_PAUSE)
2914 remote_adv |= LPA_1000XPAUSE;
2915 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
2916 remote_adv |= LPA_1000XPAUSE_ASYM;
2917
2918 tg3_setup_flow_control(tp, local_adv, remote_adv);
2919
2920 current_link_up = 1;
2921 }
2922 for (i = 0; i < 30; i++) {
2923 udelay(20);
2924 tw32_f(MAC_STATUS,
2925 (MAC_STATUS_SYNC_CHANGED |
2926 MAC_STATUS_CFG_CHANGED));
2927 udelay(40);
2928 if ((tr32(MAC_STATUS) &
2929 (MAC_STATUS_SYNC_CHANGED |
2930 MAC_STATUS_CFG_CHANGED)) == 0)
2931 break;
2932 }
2933
2934 mac_status = tr32(MAC_STATUS);
2935 if (current_link_up == 0 &&
2936 (mac_status & MAC_STATUS_PCS_SYNCED) &&
2937 !(mac_status & MAC_STATUS_RCVD_CFG))
2938 current_link_up = 1;
2939 } else {
2940 tg3_setup_flow_control(tp, 0, 0);
2941
2942 /* Forcing 1000FD link up. */
2943 current_link_up = 1;
2944
2945 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2946 udelay(40);
2947
2948 tw32_f(MAC_MODE, tp->mac_mode);
2949 udelay(40);
2950 }
2951
2952 out:
2953 return current_link_up;
2954 }
2955
2956 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2957 {
2958 u32 orig_pause_cfg;
2959 u16 orig_active_speed;
2960 u8 orig_active_duplex;
2961 u32 mac_status;
2962 int current_link_up;
2963 int i;
2964
2965 orig_pause_cfg = tp->link_config.active_flowctrl;
2966 orig_active_speed = tp->link_config.active_speed;
2967 orig_active_duplex = tp->link_config.active_duplex;
2968
2969 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2970 netif_carrier_ok(tp->dev) &&
2971 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2972 mac_status = tr32(MAC_STATUS);
2973 mac_status &= (MAC_STATUS_PCS_SYNCED |
2974 MAC_STATUS_SIGNAL_DET |
2975 MAC_STATUS_CFG_CHANGED |
2976 MAC_STATUS_RCVD_CFG);
2977 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2978 MAC_STATUS_SIGNAL_DET)) {
2979 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2980 MAC_STATUS_CFG_CHANGED));
2981 return 0;
2982 }
2983 }
2984
2985 tw32_f(MAC_TX_AUTO_NEG, 0);
2986
2987 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2988 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2989 tw32_f(MAC_MODE, tp->mac_mode);
2990 udelay(40);
2991
2992 if (tp->phy_id == PHY_ID_BCM8002)
2993 tg3_init_bcm8002(tp);
2994
2995 /* Enable link change event even when serdes polling. */
2996 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2997 udelay(40);
2998
2999 current_link_up = 0;
3000 mac_status = tr32(MAC_STATUS);
3001
3002 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3003 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3004 else
3005 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3006
3007 tp->hw_status->status =
3008 (SD_STATUS_UPDATED |
3009 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
3010
3011 for (i = 0; i < 100; i++) {
3012 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3013 MAC_STATUS_CFG_CHANGED));
3014 udelay(5);
3015 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3016 MAC_STATUS_CFG_CHANGED |
3017 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3018 break;
3019 }
3020
3021 mac_status = tr32(MAC_STATUS);
3022 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3023 current_link_up = 0;
3024 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3025 tp->serdes_counter == 0) {
3026 tw32_f(MAC_MODE, (tp->mac_mode |
3027 MAC_MODE_SEND_CONFIGS));
3028 udelay(1);
3029 tw32_f(MAC_MODE, tp->mac_mode);
3030 }
3031 }
3032
3033 if (current_link_up == 1) {
3034 tp->link_config.active_speed = SPEED_1000;
3035 tp->link_config.active_duplex = DUPLEX_FULL;
3036 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3037 LED_CTRL_LNKLED_OVERRIDE |
3038 LED_CTRL_1000MBPS_ON));
3039 } else {
3040 tp->link_config.active_speed = SPEED_INVALID;
3041 tp->link_config.active_duplex = DUPLEX_INVALID;
3042 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3043 LED_CTRL_LNKLED_OVERRIDE |
3044 LED_CTRL_TRAFFIC_OVERRIDE));
3045 }
3046
3047 if (current_link_up != netif_carrier_ok(tp->dev)) {
3048 if (current_link_up)
3049 netif_carrier_on(tp->dev);
3050 else
3051 netif_carrier_off(tp->dev);
3052 tg3_link_report(tp);
3053 } else {
3054 u32 now_pause_cfg = tp->link_config.active_flowctrl;
3055 if (orig_pause_cfg != now_pause_cfg ||
3056 orig_active_speed != tp->link_config.active_speed ||
3057 orig_active_duplex != tp->link_config.active_duplex)
3058 tg3_link_report(tp);
3059 }
3060
3061 return 0;
3062 }
3063
3064 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3065 {
3066 int current_link_up, err = 0;
3067 u32 bmsr, bmcr;
3068 u16 current_speed;
3069 u8 current_duplex;
3070 u32 local_adv, remote_adv;
3071
3072 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3073 tw32_f(MAC_MODE, tp->mac_mode);
3074 udelay(40);
3075
3076 tw32(MAC_EVENT, 0);
3077
3078 tw32_f(MAC_STATUS,
3079 (MAC_STATUS_SYNC_CHANGED |
3080 MAC_STATUS_CFG_CHANGED |
3081 MAC_STATUS_MI_COMPLETION |
3082 MAC_STATUS_LNKSTATE_CHANGED));
3083 udelay(40);
3084
3085 if (force_reset)
3086 tg3_phy_reset(tp);
3087
3088 current_link_up = 0;
3089 current_speed = SPEED_INVALID;
3090 current_duplex = DUPLEX_INVALID;
3091
3092 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3093 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3094 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3095 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3096 bmsr |= BMSR_LSTATUS;
3097 else
3098 bmsr &= ~BMSR_LSTATUS;
3099 }
3100
3101 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
3102
3103 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
3104 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3105 tp->link_config.flowctrl == tp->link_config.active_flowctrl) {
3106 /* do nothing, just check for link up at the end */
3107 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3108 u32 adv, new_adv;
3109
3110 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3111 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
3112 ADVERTISE_1000XPAUSE |
3113 ADVERTISE_1000XPSE_ASYM |
3114 ADVERTISE_SLCT);
3115
3116 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3117
3118 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
3119 new_adv |= ADVERTISE_1000XHALF;
3120 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
3121 new_adv |= ADVERTISE_1000XFULL;
3122
3123 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
3124 tg3_writephy(tp, MII_ADVERTISE, new_adv);
3125 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
3126 tg3_writephy(tp, MII_BMCR, bmcr);
3127
3128 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3129 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
3130 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3131
3132 return err;
3133 }
3134 } else {
3135 u32 new_bmcr;
3136
3137 bmcr &= ~BMCR_SPEED1000;
3138 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
3139
3140 if (tp->link_config.duplex == DUPLEX_FULL)
3141 new_bmcr |= BMCR_FULLDPLX;
3142
3143 if (new_bmcr != bmcr) {
3144 /* BMCR_SPEED1000 is a reserved bit that needs
3145 * to be set on write.
3146 */
3147 new_bmcr |= BMCR_SPEED1000;
3148
3149 /* Force a linkdown */
3150 if (netif_carrier_ok(tp->dev)) {
3151 u32 adv;
3152
3153 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3154 adv &= ~(ADVERTISE_1000XFULL |
3155 ADVERTISE_1000XHALF |
3156 ADVERTISE_SLCT);
3157 tg3_writephy(tp, MII_ADVERTISE, adv);
3158 tg3_writephy(tp, MII_BMCR, bmcr |
3159 BMCR_ANRESTART |
3160 BMCR_ANENABLE);
3161 udelay(10);
3162 netif_carrier_off(tp->dev);
3163 }
3164 tg3_writephy(tp, MII_BMCR, new_bmcr);
3165 bmcr = new_bmcr;
3166 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3167 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3168 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
3169 ASIC_REV_5714) {
3170 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3171 bmsr |= BMSR_LSTATUS;
3172 else
3173 bmsr &= ~BMSR_LSTATUS;
3174 }
3175 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3176 }
3177 }
3178
3179 if (bmsr & BMSR_LSTATUS) {
3180 current_speed = SPEED_1000;
3181 current_link_up = 1;
3182 if (bmcr & BMCR_FULLDPLX)
3183 current_duplex = DUPLEX_FULL;
3184 else
3185 current_duplex = DUPLEX_HALF;
3186
3187 local_adv = 0;
3188 remote_adv = 0;
3189
3190 if (bmcr & BMCR_ANENABLE) {
3191 u32 common;
3192
3193 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
3194 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
3195 common = local_adv & remote_adv;
3196 if (common & (ADVERTISE_1000XHALF |
3197 ADVERTISE_1000XFULL)) {
3198 if (common & ADVERTISE_1000XFULL)
3199 current_duplex = DUPLEX_FULL;
3200 else
3201 current_duplex = DUPLEX_HALF;
3202 }
3203 else
3204 current_link_up = 0;
3205 }
3206 }
3207
3208 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
3209 tg3_setup_flow_control(tp, local_adv, remote_adv);
3210
3211 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3212 if (tp->link_config.active_duplex == DUPLEX_HALF)
3213 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3214
3215 tw32_f(MAC_MODE, tp->mac_mode);
3216 udelay(40);
3217
3218 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3219
3220 tp->link_config.active_speed = current_speed;
3221 tp->link_config.active_duplex = current_duplex;
3222
3223 if (current_link_up != netif_carrier_ok(tp->dev)) {
3224 if (current_link_up)
3225 netif_carrier_on(tp->dev);
3226 else {
3227 netif_carrier_off(tp->dev);
3228 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3229 }
3230 tg3_link_report(tp);
3231 }
3232 return err;
3233 }
3234
3235 static void tg3_serdes_parallel_detect(struct tg3 *tp)
3236 {
3237 if (tp->serdes_counter) {
3238 /* Give autoneg time to complete. */
3239 tp->serdes_counter--;
3240 return;
3241 }
3242 if (!netif_carrier_ok(tp->dev) &&
3243 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
3244 u32 bmcr;
3245
3246 tg3_readphy(tp, MII_BMCR, &bmcr);
3247 if (bmcr & BMCR_ANENABLE) {
3248 u32 phy1, phy2;
3249
3250 /* Select shadow register 0x1f */
3251 tg3_writephy(tp, 0x1c, 0x7c00);
3252 tg3_readphy(tp, 0x1c, &phy1);
3253
3254 /* Select expansion interrupt status register */
3255 tg3_writephy(tp, 0x17, 0x0f01);
3256 tg3_readphy(tp, 0x15, &phy2);
3257 tg3_readphy(tp, 0x15, &phy2);
3258
3259 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
3260 /* We have signal detect and not receiving
3261 * config code words, link is up by parallel
3262 * detection.
3263 */
3264
3265 bmcr &= ~BMCR_ANENABLE;
3266 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
3267 tg3_writephy(tp, MII_BMCR, bmcr);
3268 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
3269 }
3270 }
3271 }
3272 else if (netif_carrier_ok(tp->dev) &&
3273 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
3274 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3275 u32 phy2;
3276
3277 /* Select expansion interrupt status register */
3278 tg3_writephy(tp, 0x17, 0x0f01);
3279 tg3_readphy(tp, 0x15, &phy2);
3280 if (phy2 & 0x20) {
3281 u32 bmcr;
3282
3283 /* Config code words received, turn on autoneg. */
3284 tg3_readphy(tp, MII_BMCR, &bmcr);
3285 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
3286
3287 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3288
3289 }
3290 }
3291 }
3292
3293 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
3294 {
3295 int err;
3296
3297 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
3298 err = tg3_setup_fiber_phy(tp, force_reset);
3299 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
3300 err = tg3_setup_fiber_mii_phy(tp, force_reset);
3301 } else {
3302 err = tg3_setup_copper_phy(tp, force_reset);
3303 }
3304
3305 if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
3306 tp->pci_chip_rev_id == CHIPREV_ID_5784_A1) {
3307 u32 val, scale;
3308
3309 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
3310 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
3311 scale = 65;
3312 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
3313 scale = 6;
3314 else
3315 scale = 12;
3316
3317 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
3318 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
3319 tw32(GRC_MISC_CFG, val);
3320 }
3321
3322 if (tp->link_config.active_speed == SPEED_1000 &&
3323 tp->link_config.active_duplex == DUPLEX_HALF)
3324 tw32(MAC_TX_LENGTHS,
3325 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3326 (6 << TX_LENGTHS_IPG_SHIFT) |
3327 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
3328 else
3329 tw32(MAC_TX_LENGTHS,
3330 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3331 (6 << TX_LENGTHS_IPG_SHIFT) |
3332 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3333
3334 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3335 if (netif_carrier_ok(tp->dev)) {
3336 tw32(HOSTCC_STAT_COAL_TICKS,
3337 tp->coal.stats_block_coalesce_usecs);
3338 } else {
3339 tw32(HOSTCC_STAT_COAL_TICKS, 0);
3340 }
3341 }
3342
3343 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
3344 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
3345 if (!netif_carrier_ok(tp->dev))
3346 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
3347 tp->pwrmgmt_thresh;
3348 else
3349 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
3350 tw32(PCIE_PWR_MGMT_THRESH, val);
3351 }
3352
3353 return err;
3354 }
3355
3356 /* This is called whenever we suspect that the system chipset is re-
3357 * ordering the sequence of MMIO to the tx send mailbox. The symptom
3358 * is bogus tx completions. We try to recover by setting the
3359 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
3360 * in the workqueue.
3361 */
3362 static void tg3_tx_recover(struct tg3 *tp)
3363 {
3364 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3365 tp->write32_tx_mbox == tg3_write_indirect_mbox);
3366
3367 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3368 "mapped I/O cycles to the network device, attempting to "
3369 "recover. Please report the problem to the driver maintainer "
3370 "and include system chipset information.\n", tp->dev->name);
3371
3372 spin_lock(&tp->lock);
3373 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
3374 spin_unlock(&tp->lock);
3375 }
3376
3377 static inline u32 tg3_tx_avail(struct tg3 *tp)
3378 {
3379 smp_mb();
3380 return (tp->tx_pending -
3381 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3382 }
3383
3384 /* Tigon3 never reports partial packet sends. So we do not
3385 * need special logic to handle SKBs that have not had all
3386 * of their frags sent yet, like SunGEM does.
3387 */
3388 static void tg3_tx(struct tg3 *tp)
3389 {
3390 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3391 u32 sw_idx = tp->tx_cons;
3392
3393 while (sw_idx != hw_idx) {
3394 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3395 struct sk_buff *skb = ri->skb;
3396 int i, tx_bug = 0;
3397
3398 if (unlikely(skb == NULL)) {
3399 tg3_tx_recover(tp);
3400 return;
3401 }
3402
3403 pci_unmap_single(tp->pdev,
3404 pci_unmap_addr(ri, mapping),
3405 skb_headlen(skb),
3406 PCI_DMA_TODEVICE);
3407
3408 ri->skb = NULL;
3409
3410 sw_idx = NEXT_TX(sw_idx);
3411
3412 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3413 ri = &tp->tx_buffers[sw_idx];
3414 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3415 tx_bug = 1;
3416
3417 pci_unmap_page(tp->pdev,
3418 pci_unmap_addr(ri, mapping),
3419 skb_shinfo(skb)->frags[i].size,
3420 PCI_DMA_TODEVICE);
3421
3422 sw_idx = NEXT_TX(sw_idx);
3423 }
3424
3425 dev_kfree_skb(skb);
3426
3427 if (unlikely(tx_bug)) {
3428 tg3_tx_recover(tp);
3429 return;
3430 }
3431 }
3432
3433 tp->tx_cons = sw_idx;
3434
3435 /* Need to make the tx_cons update visible to tg3_start_xmit()
3436 * before checking for netif_queue_stopped(). Without the
3437 * memory barrier, there is a small possibility that tg3_start_xmit()
3438 * will miss it and cause the queue to be stopped forever.
3439 */
3440 smp_mb();
3441
3442 if (unlikely(netif_queue_stopped(tp->dev) &&
3443 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
3444 netif_tx_lock(tp->dev);
3445 if (netif_queue_stopped(tp->dev) &&
3446 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
3447 netif_wake_queue(tp->dev);
3448 netif_tx_unlock(tp->dev);
3449 }
3450 }
3451
3452 /* Returns size of skb allocated or < 0 on error.
3453 *
3454 * We only need to fill in the address because the other members
3455 * of the RX descriptor are invariant, see tg3_init_rings.
3456 *
3457 * Note the purposeful assymetry of cpu vs. chip accesses. For
3458 * posting buffers we only dirty the first cache line of the RX
3459 * descriptor (containing the address). Whereas for the RX status
3460 * buffers the cpu only reads the last cacheline of the RX descriptor
3461 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3462 */
3463 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3464 int src_idx, u32 dest_idx_unmasked)
3465 {
3466 struct tg3_rx_buffer_desc *desc;
3467 struct ring_info *map, *src_map;
3468 struct sk_buff *skb;
3469 dma_addr_t mapping;
3470 int skb_size, dest_idx;
3471
3472 src_map = NULL;
3473 switch (opaque_key) {
3474 case RXD_OPAQUE_RING_STD:
3475 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3476 desc = &tp->rx_std[dest_idx];
3477 map = &tp->rx_std_buffers[dest_idx];
3478 if (src_idx >= 0)
3479 src_map = &tp->rx_std_buffers[src_idx];
3480 skb_size = tp->rx_pkt_buf_sz;
3481 break;
3482
3483 case RXD_OPAQUE_RING_JUMBO:
3484 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3485 desc = &tp->rx_jumbo[dest_idx];
3486 map = &tp->rx_jumbo_buffers[dest_idx];
3487 if (src_idx >= 0)
3488 src_map = &tp->rx_jumbo_buffers[src_idx];
3489 skb_size = RX_JUMBO_PKT_BUF_SZ;
3490 break;
3491
3492 default:
3493 return -EINVAL;
3494 };
3495
3496 /* Do not overwrite any of the map or rp information
3497 * until we are sure we can commit to a new buffer.
3498 *
3499 * Callers depend upon this behavior and assume that
3500 * we leave everything unchanged if we fail.
3501 */
3502 skb = netdev_alloc_skb(tp->dev, skb_size);
3503 if (skb == NULL)
3504 return -ENOMEM;
3505
3506 skb_reserve(skb, tp->rx_offset);
3507
3508 mapping = pci_map_single(tp->pdev, skb->data,
3509 skb_size - tp->rx_offset,
3510 PCI_DMA_FROMDEVICE);
3511
3512 map->skb = skb;
3513 pci_unmap_addr_set(map, mapping, mapping);
3514
3515 if (src_map != NULL)
3516 src_map->skb = NULL;
3517
3518 desc->addr_hi = ((u64)mapping >> 32);
3519 desc->addr_lo = ((u64)mapping & 0xffffffff);
3520
3521 return skb_size;
3522 }
3523
3524 /* We only need to move over in the address because the other
3525 * members of the RX descriptor are invariant. See notes above
3526 * tg3_alloc_rx_skb for full details.
3527 */
3528 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3529 int src_idx, u32 dest_idx_unmasked)
3530 {
3531 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3532 struct ring_info *src_map, *dest_map;
3533 int dest_idx;
3534
3535 switch (opaque_key) {
3536 case RXD_OPAQUE_RING_STD:
3537 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3538 dest_desc = &tp->rx_std[dest_idx];
3539 dest_map = &tp->rx_std_buffers[dest_idx];
3540 src_desc = &tp->rx_std[src_idx];
3541 src_map = &tp->rx_std_buffers[src_idx];
3542 break;
3543
3544 case RXD_OPAQUE_RING_JUMBO:
3545 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3546 dest_desc = &tp->rx_jumbo[dest_idx];
3547 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3548 src_desc = &tp->rx_jumbo[src_idx];
3549 src_map = &tp->rx_jumbo_buffers[src_idx];
3550 break;
3551
3552 default:
3553 return;
3554 };
3555
3556 dest_map->skb = src_map->skb;
3557 pci_unmap_addr_set(dest_map, mapping,
3558 pci_unmap_addr(src_map, mapping));
3559 dest_desc->addr_hi = src_desc->addr_hi;
3560 dest_desc->addr_lo = src_desc->addr_lo;
3561
3562 src_map->skb = NULL;
3563 }
3564
3565 #if TG3_VLAN_TAG_USED
3566 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3567 {
3568 return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3569 }
3570 #endif
3571
3572 /* The RX ring scheme is composed of multiple rings which post fresh
3573 * buffers to the chip, and one special ring the chip uses to report
3574 * status back to the host.
3575 *
3576 * The special ring reports the status of received packets to the
3577 * host. The chip does not write into the original descriptor the
3578 * RX buffer was obtained from. The chip simply takes the original
3579 * descriptor as provided by the host, updates the status and length
3580 * field, then writes this into the next status ring entry.
3581 *
3582 * Each ring the host uses to post buffers to the chip is described
3583 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
3584 * it is first placed into the on-chip ram. When the packet's length
3585 * is known, it walks down the TG3_BDINFO entries to select the ring.
3586 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3587 * which is within the range of the new packet's length is chosen.
3588 *
3589 * The "separate ring for rx status" scheme may sound queer, but it makes
3590 * sense from a cache coherency perspective. If only the host writes
3591 * to the buffer post rings, and only the chip writes to the rx status
3592 * rings, then cache lines never move beyond shared-modified state.
3593 * If both the host and chip were to write into the same ring, cache line
3594 * eviction could occur since both entities want it in an exclusive state.
3595 */
3596 static int tg3_rx(struct tg3 *tp, int budget)
3597 {
3598 u32 work_mask, rx_std_posted = 0;
3599 u32 sw_idx = tp->rx_rcb_ptr;
3600 u16 hw_idx;
3601 int received;
3602
3603 hw_idx = tp->hw_status->idx[0].rx_producer;
3604 /*
3605 * We need to order the read of hw_idx and the read of
3606 * the opaque cookie.
3607 */
3608 rmb();
3609 work_mask = 0;
3610 received = 0;
3611 while (sw_idx != hw_idx && budget > 0) {
3612 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3613 unsigned int len;
3614 struct sk_buff *skb;
3615 dma_addr_t dma_addr;
3616 u32 opaque_key, desc_idx, *post_ptr;
3617
3618 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3619 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3620 if (opaque_key == RXD_OPAQUE_RING_STD) {
3621 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3622 mapping);
3623 skb = tp->rx_std_buffers[desc_idx].skb;
3624 post_ptr = &tp->rx_std_ptr;
3625 rx_std_posted++;
3626 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3627 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3628 mapping);
3629 skb = tp->rx_jumbo_buffers[desc_idx].skb;
3630 post_ptr = &tp->rx_jumbo_ptr;
3631 }
3632 else {
3633 goto next_pkt_nopost;
3634 }
3635
3636 work_mask |= opaque_key;
3637
3638 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3639 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3640 drop_it:
3641 tg3_recycle_rx(tp, opaque_key,
3642 desc_idx, *post_ptr);
3643 drop_it_no_recycle:
3644 /* Other statistics kept track of by card. */
3645 tp->net_stats.rx_dropped++;
3646 goto next_pkt;
3647 }
3648
3649 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3650
3651 if (len > RX_COPY_THRESHOLD
3652 && tp->rx_offset == 2
3653 /* rx_offset != 2 iff this is a 5701 card running
3654 * in PCI-X mode [see tg3_get_invariants()] */
3655 ) {
3656 int skb_size;
3657
3658 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3659 desc_idx, *post_ptr);
3660 if (skb_size < 0)
3661 goto drop_it;
3662
3663 pci_unmap_single(tp->pdev, dma_addr,
3664 skb_size - tp->rx_offset,
3665 PCI_DMA_FROMDEVICE);
3666
3667 skb_put(skb, len);
3668 } else {
3669 struct sk_buff *copy_skb;
3670
3671 tg3_recycle_rx(tp, opaque_key,
3672 desc_idx, *post_ptr);
3673
3674 copy_skb = netdev_alloc_skb(tp->dev, len + 2);
3675 if (copy_skb == NULL)
3676 goto drop_it_no_recycle;
3677
3678 skb_reserve(copy_skb, 2);
3679 skb_put(copy_skb, len);
3680 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3681 skb_copy_from_linear_data(skb, copy_skb->data, len);
3682 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3683
3684 /* We'll reuse the original ring buffer. */
3685 skb = copy_skb;
3686 }
3687
3688 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3689 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3690 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3691 >> RXD_TCPCSUM_SHIFT) == 0xffff))
3692 skb->ip_summed = CHECKSUM_UNNECESSARY;
3693 else
3694 skb->ip_summed = CHECKSUM_NONE;
3695
3696 skb->protocol = eth_type_trans(skb, tp->dev);
3697 #if TG3_VLAN_TAG_USED
3698 if (tp->vlgrp != NULL &&
3699 desc->type_flags & RXD_FLAG_VLAN) {
3700 tg3_vlan_rx(tp, skb,
3701 desc->err_vlan & RXD_VLAN_MASK);
3702 } else
3703 #endif
3704 netif_receive_skb(skb);
3705
3706 tp->dev->last_rx = jiffies;
3707 received++;
3708 budget--;
3709
3710 next_pkt:
3711 (*post_ptr)++;
3712
3713 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
3714 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
3715
3716 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
3717 TG3_64BIT_REG_LOW, idx);
3718 work_mask &= ~RXD_OPAQUE_RING_STD;
3719 rx_std_posted = 0;
3720 }
3721 next_pkt_nopost:
3722 sw_idx++;
3723 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
3724
3725 /* Refresh hw_idx to see if there is new work */
3726 if (sw_idx == hw_idx) {
3727 hw_idx = tp->hw_status->idx[0].rx_producer;
3728 rmb();
3729 }
3730 }
3731
3732 /* ACK the status ring. */
3733 tp->rx_rcb_ptr = sw_idx;
3734 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
3735
3736 /* Refill RX ring(s). */
3737 if (work_mask & RXD_OPAQUE_RING_STD) {
3738 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3739 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3740 sw_idx);
3741 }
3742 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3743 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3744 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3745 sw_idx);
3746 }
3747 mmiowb();
3748
3749 return received;
3750 }
3751
3752 static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
3753 {
3754 struct tg3_hw_status *sblk = tp->hw_status;
3755
3756 /* handle link change and other phy events */
3757 if (!(tp->tg3_flags &
3758 (TG3_FLAG_USE_LINKCHG_REG |
3759 TG3_FLAG_POLL_SERDES))) {
3760 if (sblk->status & SD_STATUS_LINK_CHG) {
3761 sblk->status = SD_STATUS_UPDATED |
3762 (sblk->status & ~SD_STATUS_LINK_CHG);
3763 spin_lock(&tp->lock);
3764 tg3_setup_phy(tp, 0);
3765 spin_unlock(&tp->lock);
3766 }
3767 }
3768
3769 /* run TX completion thread */
3770 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
3771 tg3_tx(tp);
3772 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
3773 return work_done;
3774 }
3775
3776 /* run RX thread, within the bounds set by NAPI.
3777 * All RX "locking" is done by ensuring outside
3778 * code synchronizes with tg3->napi.poll()
3779 */
3780 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
3781 work_done += tg3_rx(tp, budget - work_done);
3782
3783 return work_done;
3784 }
3785
3786 static int tg3_poll(struct napi_struct *napi, int budget)
3787 {
3788 struct tg3 *tp = container_of(napi, struct tg3, napi);
3789 int work_done = 0;
3790 struct tg3_hw_status *sblk = tp->hw_status;
3791
3792 while (1) {
3793 work_done = tg3_poll_work(tp, work_done, budget);
3794
3795 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
3796 goto tx_recovery;
3797
3798 if (unlikely(work_done >= budget))
3799 break;
3800
3801 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
3802 /* tp->last_tag is used in tg3_restart_ints() below
3803 * to tell the hw how much work has been processed,
3804 * so we must read it before checking for more work.
3805 */
3806 tp->last_tag = sblk->status_tag;
3807 rmb();
3808 } else
3809 sblk->status &= ~SD_STATUS_UPDATED;
3810
3811 if (likely(!tg3_has_work(tp))) {
3812 netif_rx_complete(tp->dev, napi);
3813 tg3_restart_ints(tp);
3814 break;
3815 }
3816 }
3817
3818 return work_done;
3819
3820 tx_recovery:
3821 /* work_done is guaranteed to be less than budget. */
3822 netif_rx_complete(tp->dev, napi);
3823 schedule_work(&tp->reset_task);
3824 return work_done;
3825 }
3826
3827 static void tg3_irq_quiesce(struct tg3 *tp)
3828 {
3829 BUG_ON(tp->irq_sync);
3830
3831 tp->irq_sync = 1;
3832 smp_mb();
3833
3834 synchronize_irq(tp->pdev->irq);
3835 }
3836
3837 static inline int tg3_irq_sync(struct tg3 *tp)
3838 {
3839 return tp->irq_sync;
3840 }
3841
3842 /* Fully shutdown all tg3 driver activity elsewhere in the system.
3843 * If irq_sync is non-zero, then the IRQ handler must be synchronized
3844 * with as well. Most of the time, this is not necessary except when
3845 * shutting down the device.
3846 */
3847 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3848 {
3849 spin_lock_bh(&tp->lock);
3850 if (irq_sync)
3851 tg3_irq_quiesce(tp);
3852 }
3853
3854 static inline void tg3_full_unlock(struct tg3 *tp)
3855 {
3856 spin_unlock_bh(&tp->lock);
3857 }
3858
3859 /* One-shot MSI handler - Chip automatically disables interrupt
3860 * after sending MSI so driver doesn't have to do it.
3861 */
3862 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
3863 {
3864 struct net_device *dev = dev_id;
3865 struct tg3 *tp = netdev_priv(dev);
3866
3867 prefetch(tp->hw_status);
3868 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3869
3870 if (likely(!tg3_irq_sync(tp)))
3871 netif_rx_schedule(dev, &tp->napi);
3872
3873 return IRQ_HANDLED;
3874 }
3875
3876 /* MSI ISR - No need to check for interrupt sharing and no need to
3877 * flush status block and interrupt mailbox. PCI ordering rules
3878 * guarantee that MSI will arrive after the status block.
3879 */
3880 static irqreturn_t tg3_msi(int irq, void *dev_id)
3881 {
3882 struct net_device *dev = dev_id;
3883 struct tg3 *tp = netdev_priv(dev);
3884
3885 prefetch(tp->hw_status);
3886 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3887 /*
3888 * Writing any value to intr-mbox-0 clears PCI INTA# and
3889 * chip-internal interrupt pending events.
3890 * Writing non-zero to intr-mbox-0 additional tells the
3891 * NIC to stop sending us irqs, engaging "in-intr-handler"
3892 * event coalescing.
3893 */
3894 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3895 if (likely(!tg3_irq_sync(tp)))
3896 netif_rx_schedule(dev, &tp->napi);
3897
3898 return IRQ_RETVAL(1);
3899 }
3900
3901 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
3902 {
3903 struct net_device *dev = dev_id;
3904 struct tg3 *tp = netdev_priv(dev);
3905 struct tg3_hw_status *sblk = tp->hw_status;
3906 unsigned int handled = 1;
3907
3908 /* In INTx mode, it is possible for the interrupt to arrive at
3909 * the CPU before the status block posted prior to the interrupt.
3910 * Reading the PCI State register will confirm whether the
3911 * interrupt is ours and will flush the status block.
3912 */
3913 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
3914 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3915 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3916 handled = 0;
3917 goto out;
3918 }
3919 }
3920
3921 /*
3922 * Writing any value to intr-mbox-0 clears PCI INTA# and
3923 * chip-internal interrupt pending events.
3924 * Writing non-zero to intr-mbox-0 additional tells the
3925 * NIC to stop sending us irqs, engaging "in-intr-handler"
3926 * event coalescing.
3927 *
3928 * Flush the mailbox to de-assert the IRQ immediately to prevent
3929 * spurious interrupts. The flush impacts performance but
3930 * excessive spurious interrupts can be worse in some cases.
3931 */
3932 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3933 if (tg3_irq_sync(tp))
3934 goto out;
3935 sblk->status &= ~SD_STATUS_UPDATED;
3936 if (likely(tg3_has_work(tp))) {
3937 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3938 netif_rx_schedule(dev, &tp->napi);
3939 } else {
3940 /* No work, shared interrupt perhaps? re-enable
3941 * interrupts, and flush that PCI write
3942 */
3943 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3944 0x00000000);
3945 }
3946 out:
3947 return IRQ_RETVAL(handled);
3948 }
3949
3950 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
3951 {
3952 struct net_device *dev = dev_id;
3953 struct tg3 *tp = netdev_priv(dev);
3954 struct tg3_hw_status *sblk = tp->hw_status;
3955 unsigned int handled = 1;
3956
3957 /* In INTx mode, it is possible for the interrupt to arrive at
3958 * the CPU before the status block posted prior to the interrupt.
3959 * Reading the PCI State register will confirm whether the
3960 * interrupt is ours and will flush the status block.
3961 */
3962 if (unlikely(sblk->status_tag == tp->last_tag)) {
3963 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3964 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3965 handled = 0;
3966 goto out;
3967 }
3968 }
3969
3970 /*
3971 * writing any value to intr-mbox-0 clears PCI INTA# and
3972 * chip-internal interrupt pending events.
3973 * writing non-zero to intr-mbox-0 additional tells the
3974 * NIC to stop sending us irqs, engaging "in-intr-handler"
3975 * event coalescing.
3976 *
3977 * Flush the mailbox to de-assert the IRQ immediately to prevent
3978 * spurious interrupts. The flush impacts performance but
3979 * excessive spurious interrupts can be worse in some cases.
3980 */
3981 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3982 if (tg3_irq_sync(tp))
3983 goto out;
3984 if (netif_rx_schedule_prep(dev, &tp->napi)) {
3985 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3986 /* Update last_tag to mark that this status has been
3987 * seen. Because interrupt may be shared, we may be
3988 * racing with tg3_poll(), so only update last_tag
3989 * if tg3_poll() is not scheduled.
3990 */
3991 tp->last_tag = sblk->status_tag;
3992 __netif_rx_schedule(dev, &tp->napi);
3993 }
3994 out:
3995 return IRQ_RETVAL(handled);
3996 }
3997
3998 /* ISR for interrupt test */
3999 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4000 {
4001 struct net_device *dev = dev_id;
4002 struct tg3 *tp = netdev_priv(dev);
4003 struct tg3_hw_status *sblk = tp->hw_status;
4004
4005 if ((sblk->status & SD_STATUS_UPDATED) ||
4006 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4007 tg3_disable_ints(tp);
4008 return IRQ_RETVAL(1);
4009 }
4010 return IRQ_RETVAL(0);
4011 }
4012
4013 static int tg3_init_hw(struct tg3 *, int);
4014 static int tg3_halt(struct tg3 *, int, int);
4015
4016 /* Restart hardware after configuration changes, self-test, etc.
4017 * Invoked with tp->lock held.
4018 */
4019 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
4020 {
4021 int err;
4022
4023 err = tg3_init_hw(tp, reset_phy);
4024 if (err) {
4025 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4026 "aborting.\n", tp->dev->name);
4027 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4028 tg3_full_unlock(tp);
4029 del_timer_sync(&tp->timer);
4030 tp->irq_sync = 0;
4031 napi_enable(&tp->napi);
4032 dev_close(tp->dev);
4033 tg3_full_lock(tp, 0);
4034 }
4035 return err;
4036 }
4037
4038 #ifdef CONFIG_NET_POLL_CONTROLLER
4039 static void tg3_poll_controller(struct net_device *dev)
4040 {
4041 struct tg3 *tp = netdev_priv(dev);
4042
4043 tg3_interrupt(tp->pdev->irq, dev);
4044 }
4045 #endif
4046
4047 static void tg3_reset_task(struct work_struct *work)
4048 {
4049 struct tg3 *tp = container_of(work, struct tg3, reset_task);
4050 unsigned int restart_timer;
4051
4052 tg3_full_lock(tp, 0);
4053
4054 if (!netif_running(tp->dev)) {
4055 tg3_full_unlock(tp);
4056 return;
4057 }
4058
4059 tg3_full_unlock(tp);
4060
4061 tg3_netif_stop(tp);
4062
4063 tg3_full_lock(tp, 1);
4064
4065 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4066 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4067
4068 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4069 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4070 tp->write32_rx_mbox = tg3_write_flush_reg32;
4071 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4072 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4073 }
4074
4075 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
4076 if (tg3_init_hw(tp, 1))
4077 goto out;
4078
4079 tg3_netif_start(tp);
4080
4081 if (restart_timer)
4082 mod_timer(&tp->timer, jiffies + 1);
4083
4084 out:
4085 tg3_full_unlock(tp);
4086 }
4087
4088 static void tg3_dump_short_state(struct tg3 *tp)
4089 {
4090 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
4091 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
4092 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
4093 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
4094 }
4095
4096 static void tg3_tx_timeout(struct net_device *dev)
4097 {
4098 struct tg3 *tp = netdev_priv(dev);
4099
4100 if (netif_msg_tx_err(tp)) {
4101 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
4102 dev->name);
4103 tg3_dump_short_state(tp);
4104 }
4105
4106 schedule_work(&tp->reset_task);
4107 }
4108
4109 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
4110 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
4111 {
4112 u32 base = (u32) mapping & 0xffffffff;
4113
4114 return ((base > 0xffffdcc0) &&
4115 (base + len + 8 < base));
4116 }
4117
4118 /* Test for DMA addresses > 40-bit */
4119 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
4120 int len)
4121 {
4122 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
4123 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
4124 return (((u64) mapping + len) > DMA_40BIT_MASK);
4125 return 0;
4126 #else
4127 return 0;
4128 #endif
4129 }
4130
4131 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
4132
4133 /* Workaround 4GB and 40-bit hardware DMA bugs. */
4134 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
4135 u32 last_plus_one, u32 *start,
4136 u32 base_flags, u32 mss)
4137 {
4138 struct sk_buff *new_skb;
4139 dma_addr_t new_addr = 0;
4140 u32 entry = *start;
4141 int i, ret = 0;
4142
4143 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
4144 new_skb = skb_copy(skb, GFP_ATOMIC);
4145 else {
4146 int more_headroom = 4 - ((unsigned long)skb->data & 3);
4147
4148 new_skb = skb_copy_expand(skb,
4149 skb_headroom(skb) + more_headroom,
4150 skb_tailroom(skb), GFP_ATOMIC);
4151 }
4152
4153 if (!new_skb) {
4154 ret = -1;
4155 } else {
4156 /* New SKB is guaranteed to be linear. */
4157 entry = *start;
4158 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
4159 PCI_DMA_TODEVICE);
4160 /* Make sure new skb does not cross any 4G boundaries.
4161 * Drop the packet if it does.
4162 */
4163 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
4164 ret = -1;
4165 dev_kfree_skb(new_skb);
4166 new_skb = NULL;
4167 } else {
4168 tg3_set_txd(tp, entry, new_addr, new_skb->len,
4169 base_flags, 1 | (mss << 1));
4170 *start = NEXT_TX(entry);
4171 }
4172 }
4173
4174 /* Now clean up the sw ring entries. */
4175 i = 0;
4176 while (entry != last_plus_one) {
4177 int len;
4178
4179 if (i == 0)
4180 len = skb_headlen(skb);
4181 else
4182 len = skb_shinfo(skb)->frags[i-1].size;
4183 pci_unmap_single(tp->pdev,
4184 pci_unmap_addr(&tp->tx_buffers[entry], mapping),
4185 len, PCI_DMA_TODEVICE);
4186 if (i == 0) {
4187 tp->tx_buffers[entry].skb = new_skb;
4188 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
4189 } else {
4190 tp->tx_buffers[entry].skb = NULL;
4191 }
4192 entry = NEXT_TX(entry);
4193 i++;
4194 }
4195
4196 dev_kfree_skb(skb);
4197
4198 return ret;
4199 }
4200
4201 static void tg3_set_txd(struct tg3 *tp, int entry,
4202 dma_addr_t mapping, int len, u32 flags,
4203 u32 mss_and_is_end)
4204 {
4205 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
4206 int is_end = (mss_and_is_end & 0x1);
4207 u32 mss = (mss_and_is_end >> 1);
4208 u32 vlan_tag = 0;
4209
4210 if (is_end)
4211 flags |= TXD_FLAG_END;
4212 if (flags & TXD_FLAG_VLAN) {
4213 vlan_tag = flags >> 16;
4214 flags &= 0xffff;
4215 }
4216 vlan_tag |= (mss << TXD_MSS_SHIFT);
4217
4218 txd->addr_hi = ((u64) mapping >> 32);
4219 txd->addr_lo = ((u64) mapping & 0xffffffff);
4220 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
4221 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
4222 }
4223
4224 /* hard_start_xmit for devices that don't have any bugs and
4225 * support TG3_FLG2_HW_TSO_2 only.
4226 */
4227 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
4228 {
4229 struct tg3 *tp = netdev_priv(dev);
4230 dma_addr_t mapping;
4231 u32 len, entry, base_flags, mss;
4232
4233 len = skb_headlen(skb);
4234
4235 /* We are running in BH disabled context with netif_tx_lock
4236 * and TX reclaim runs via tp->napi.poll inside of a software
4237 * interrupt. Furthermore, IRQ processing runs lockless so we have
4238 * no IRQ context deadlocks to worry about either. Rejoice!
4239 */
4240 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4241 if (!netif_queue_stopped(dev)) {
4242 netif_stop_queue(dev);
4243
4244 /* This is a hard error, log it. */
4245 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4246 "queue awake!\n", dev->name);
4247 }
4248 return NETDEV_TX_BUSY;
4249 }
4250
4251 entry = tp->tx_prod;
4252 base_flags = 0;
4253 mss = 0;
4254 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
4255 int tcp_opt_len, ip_tcp_len;
4256
4257 if (skb_header_cloned(skb) &&
4258 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4259 dev_kfree_skb(skb);
4260 goto out_unlock;
4261 }
4262
4263 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
4264 mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
4265 else {
4266 struct iphdr *iph = ip_hdr(skb);
4267
4268 tcp_opt_len = tcp_optlen(skb);
4269 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4270
4271 iph->check = 0;
4272 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
4273 mss |= (ip_tcp_len + tcp_opt_len) << 9;
4274 }
4275
4276 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4277 TXD_FLAG_CPU_POST_DMA);
4278
4279 tcp_hdr(skb)->check = 0;
4280
4281 }
4282 else if (skb->ip_summed == CHECKSUM_PARTIAL)
4283 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4284 #if TG3_VLAN_TAG_USED
4285 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4286 base_flags |= (TXD_FLAG_VLAN |
4287 (vlan_tx_tag_get(skb) << 16));
4288 #endif
4289
4290 /* Queue skb data, a.k.a. the main skb fragment. */
4291 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4292
4293 tp->tx_buffers[entry].skb = skb;
4294 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4295
4296 tg3_set_txd(tp, entry, mapping, len, base_flags,
4297 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4298
4299 entry = NEXT_TX(entry);
4300
4301 /* Now loop through additional data fragments, and queue them. */
4302 if (skb_shinfo(skb)->nr_frags > 0) {
4303 unsigned int i, last;
4304
4305 last = skb_shinfo(skb)->nr_frags - 1;
4306 for (i = 0; i <= last; i++) {
4307 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4308
4309 len = frag->size;
4310 mapping = pci_map_page(tp->pdev,
4311 frag->page,
4312 frag->page_offset,
4313 len, PCI_DMA_TODEVICE);
4314
4315 tp->tx_buffers[entry].skb = NULL;
4316 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4317
4318 tg3_set_txd(tp, entry, mapping, len,
4319 base_flags, (i == last) | (mss << 1));
4320
4321 entry = NEXT_TX(entry);
4322 }
4323 }
4324
4325 /* Packets are ready, update Tx producer idx local and on card. */
4326 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4327
4328 tp->tx_prod = entry;
4329 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4330 netif_stop_queue(dev);
4331 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4332 netif_wake_queue(tp->dev);
4333 }
4334
4335 out_unlock:
4336 mmiowb();
4337
4338 dev->trans_start = jiffies;
4339
4340 return NETDEV_TX_OK;
4341 }
4342
4343 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
4344
4345 /* Use GSO to workaround a rare TSO bug that may be triggered when the
4346 * TSO header is greater than 80 bytes.
4347 */
4348 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
4349 {
4350 struct sk_buff *segs, *nskb;
4351
4352 /* Estimate the number of fragments in the worst case */
4353 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
4354 netif_stop_queue(tp->dev);
4355 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
4356 return NETDEV_TX_BUSY;
4357
4358 netif_wake_queue(tp->dev);
4359 }
4360
4361 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
4362 if (unlikely(IS_ERR(segs)))
4363 goto tg3_tso_bug_end;
4364
4365 do {
4366 nskb = segs;
4367 segs = segs->next;
4368 nskb->next = NULL;
4369 tg3_start_xmit_dma_bug(nskb, tp->dev);
4370 } while (segs);
4371
4372 tg3_tso_bug_end:
4373 dev_kfree_skb(skb);
4374
4375 return NETDEV_TX_OK;
4376 }
4377
4378 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
4379 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
4380 */
4381 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
4382 {
4383 struct tg3 *tp = netdev_priv(dev);
4384 dma_addr_t mapping;
4385 u32 len, entry, base_flags, mss;
4386 int would_hit_hwbug;
4387
4388 len = skb_headlen(skb);
4389
4390 /* We are running in BH disabled context with netif_tx_lock
4391 * and TX reclaim runs via tp->napi.poll inside of a software
4392 * interrupt. Furthermore, IRQ processing runs lockless so we have
4393 * no IRQ context deadlocks to worry about either. Rejoice!
4394 */
4395 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4396 if (!netif_queue_stopped(dev)) {
4397 netif_stop_queue(dev);
4398
4399 /* This is a hard error, log it. */
4400 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4401 "queue awake!\n", dev->name);
4402 }
4403 return NETDEV_TX_BUSY;
4404 }
4405
4406 entry = tp->tx_prod;
4407 base_flags = 0;
4408 if (skb->ip_summed == CHECKSUM_PARTIAL)
4409 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4410 mss = 0;
4411 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
4412 struct iphdr *iph;
4413 int tcp_opt_len, ip_tcp_len, hdr_len;
4414
4415 if (skb_header_cloned(skb) &&
4416 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4417 dev_kfree_skb(skb);
4418 goto out_unlock;
4419 }
4420
4421 tcp_opt_len = tcp_optlen(skb);
4422 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4423
4424 hdr_len = ip_tcp_len + tcp_opt_len;
4425 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
4426 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
4427 return (tg3_tso_bug(tp, skb));
4428
4429 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4430 TXD_FLAG_CPU_POST_DMA);
4431
4432 iph = ip_hdr(skb);
4433 iph->check = 0;
4434 iph->tot_len = htons(mss + hdr_len);
4435 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
4436 tcp_hdr(skb)->check = 0;
4437 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
4438 } else
4439 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4440 iph->daddr, 0,
4441 IPPROTO_TCP,
4442 0);
4443
4444 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4445 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
4446 if (tcp_opt_len || iph->ihl > 5) {
4447 int tsflags;
4448
4449 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4450 mss |= (tsflags << 11);
4451 }
4452 } else {
4453 if (tcp_opt_len || iph->ihl > 5) {
4454 int tsflags;
4455
4456 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4457 base_flags |= tsflags << 12;
4458 }
4459 }
4460 }
4461 #if TG3_VLAN_TAG_USED
4462 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4463 base_flags |= (TXD_FLAG_VLAN |
4464 (vlan_tx_tag_get(skb) << 16));
4465 #endif
4466
4467 /* Queue skb data, a.k.a. the main skb fragment. */
4468 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4469
4470 tp->tx_buffers[entry].skb = skb;
4471 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4472
4473 would_hit_hwbug = 0;
4474
4475 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
4476 would_hit_hwbug = 1;
4477 else if (tg3_4g_overflow_test(mapping, len))
4478 would_hit_hwbug = 1;
4479
4480 tg3_set_txd(tp, entry, mapping, len, base_flags,
4481 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4482
4483 entry = NEXT_TX(entry);
4484
4485 /* Now loop through additional data fragments, and queue them. */
4486 if (skb_shinfo(skb)->nr_frags > 0) {
4487 unsigned int i, last;
4488
4489 last = skb_shinfo(skb)->nr_frags - 1;
4490 for (i = 0; i <= last; i++) {
4491 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4492
4493 len = frag->size;
4494 mapping = pci_map_page(tp->pdev,
4495 frag->page,
4496 frag->page_offset,
4497 len, PCI_DMA_TODEVICE);
4498
4499 tp->tx_buffers[entry].skb = NULL;
4500 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4501
4502 if (tg3_4g_overflow_test(mapping, len))
4503 would_hit_hwbug = 1;
4504
4505 if (tg3_40bit_overflow_test(tp, mapping, len))
4506 would_hit_hwbug = 1;
4507
4508 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4509 tg3_set_txd(tp, entry, mapping, len,
4510 base_flags, (i == last)|(mss << 1));
4511 else
4512 tg3_set_txd(tp, entry, mapping, len,
4513 base_flags, (i == last));
4514
4515 entry = NEXT_TX(entry);
4516 }
4517 }
4518
4519 if (would_hit_hwbug) {
4520 u32 last_plus_one = entry;
4521 u32 start;
4522
4523 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4524 start &= (TG3_TX_RING_SIZE - 1);
4525
4526 /* If the workaround fails due to memory/mapping
4527 * failure, silently drop this packet.
4528 */
4529 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
4530 &start, base_flags, mss))
4531 goto out_unlock;
4532
4533 entry = start;
4534 }
4535
4536 /* Packets are ready, update Tx producer idx local and on card. */
4537 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4538
4539 tp->tx_prod = entry;
4540 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4541 netif_stop_queue(dev);
4542 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4543 netif_wake_queue(tp->dev);
4544 }
4545
4546 out_unlock:
4547 mmiowb();
4548
4549 dev->trans_start = jiffies;
4550
4551 return NETDEV_TX_OK;
4552 }
4553
4554 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4555 int new_mtu)
4556 {
4557 dev->mtu = new_mtu;
4558
4559 if (new_mtu > ETH_DATA_LEN) {
4560 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4561 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4562 ethtool_op_set_tso(dev, 0);
4563 }
4564 else
4565 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4566 } else {
4567 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4568 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
4569 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
4570 }
4571 }
4572
4573 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4574 {
4575 struct tg3 *tp = netdev_priv(dev);
4576 int err;
4577
4578 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4579 return -EINVAL;
4580
4581 if (!netif_running(dev)) {
4582 /* We'll just catch it later when the
4583 * device is up'd.
4584 */
4585 tg3_set_mtu(dev, tp, new_mtu);
4586 return 0;
4587 }
4588
4589 tg3_netif_stop(tp);
4590
4591 tg3_full_lock(tp, 1);
4592
4593 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4594
4595 tg3_set_mtu(dev, tp, new_mtu);
4596
4597 err = tg3_restart_hw(tp, 0);
4598
4599 if (!err)
4600 tg3_netif_start(tp);
4601
4602 tg3_full_unlock(tp);
4603
4604 return err;
4605 }
4606
4607 /* Free up pending packets in all rx/tx rings.
4608 *
4609 * The chip has been shut down and the driver detached from
4610 * the networking, so no interrupts or new tx packets will
4611 * end up in the driver. tp->{tx,}lock is not held and we are not
4612 * in an interrupt context and thus may sleep.
4613 */
4614 static void tg3_free_rings(struct tg3 *tp)
4615 {
4616 struct ring_info *rxp;
4617 int i;
4618
4619 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4620 rxp = &tp->rx_std_buffers[i];
4621
4622 if (rxp->skb == NULL)
4623 continue;
4624 pci_unmap_single(tp->pdev,
4625 pci_unmap_addr(rxp, mapping),
4626 tp->rx_pkt_buf_sz - tp->rx_offset,
4627 PCI_DMA_FROMDEVICE);
4628 dev_kfree_skb_any(rxp->skb);
4629 rxp->skb = NULL;
4630 }
4631
4632 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4633 rxp = &tp->rx_jumbo_buffers[i];
4634
4635 if (rxp->skb == NULL)
4636 continue;
4637 pci_unmap_single(tp->pdev,
4638 pci_unmap_addr(rxp, mapping),
4639 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
4640 PCI_DMA_FROMDEVICE);
4641 dev_kfree_skb_any(rxp->skb);
4642 rxp->skb = NULL;
4643 }
4644
4645 for (i = 0; i < TG3_TX_RING_SIZE; ) {
4646 struct tx_ring_info *txp;
4647 struct sk_buff *skb;
4648 int j;
4649
4650 txp = &tp->tx_buffers[i];
4651 skb = txp->skb;
4652
4653 if (skb == NULL) {
4654 i++;
4655 continue;
4656 }
4657
4658 pci_unmap_single(tp->pdev,
4659 pci_unmap_addr(txp, mapping),
4660 skb_headlen(skb),
4661 PCI_DMA_TODEVICE);
4662 txp->skb = NULL;
4663
4664 i++;
4665
4666 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
4667 txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
4668 pci_unmap_page(tp->pdev,
4669 pci_unmap_addr(txp, mapping),
4670 skb_shinfo(skb)->frags[j].size,
4671 PCI_DMA_TODEVICE);
4672 i++;
4673 }
4674
4675 dev_kfree_skb_any(skb);
4676 }
4677 }
4678
4679 /* Initialize tx/rx rings for packet processing.
4680 *
4681 * The chip has been shut down and the driver detached from
4682 * the networking, so no interrupts or new tx packets will
4683 * end up in the driver. tp->{tx,}lock are held and thus
4684 * we may not sleep.
4685 */
4686 static int tg3_init_rings(struct tg3 *tp)
4687 {
4688 u32 i;
4689
4690 /* Free up all the SKBs. */
4691 tg3_free_rings(tp);
4692
4693 /* Zero out all descriptors. */
4694 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
4695 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
4696 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
4697 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
4698
4699 tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
4700 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
4701 (tp->dev->mtu > ETH_DATA_LEN))
4702 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
4703
4704 /* Initialize invariants of the rings, we only set this
4705 * stuff once. This works because the card does not
4706 * write into the rx buffer posting rings.
4707 */
4708 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4709 struct tg3_rx_buffer_desc *rxd;
4710
4711 rxd = &tp->rx_std[i];
4712 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
4713 << RXD_LEN_SHIFT;
4714 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
4715 rxd->opaque = (RXD_OPAQUE_RING_STD |
4716 (i << RXD_OPAQUE_INDEX_SHIFT));
4717 }
4718
4719 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4720 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4721 struct tg3_rx_buffer_desc *rxd;
4722
4723 rxd = &tp->rx_jumbo[i];
4724 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
4725 << RXD_LEN_SHIFT;
4726 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
4727 RXD_FLAG_JUMBO;
4728 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
4729 (i << RXD_OPAQUE_INDEX_SHIFT));
4730 }
4731 }
4732
4733 /* Now allocate fresh SKBs for each rx ring. */
4734 for (i = 0; i < tp->rx_pending; i++) {
4735 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
4736 printk(KERN_WARNING PFX
4737 "%s: Using a smaller RX standard ring, "
4738 "only %d out of %d buffers were allocated "
4739 "successfully.\n",
4740 tp->dev->name, i, tp->rx_pending);
4741 if (i == 0)
4742 return -ENOMEM;
4743 tp->rx_pending = i;
4744 break;
4745 }
4746 }
4747
4748 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4749 for (i = 0; i < tp->rx_jumbo_pending; i++) {
4750 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
4751 -1, i) < 0) {
4752 printk(KERN_WARNING PFX
4753 "%s: Using a smaller RX jumbo ring, "
4754 "only %d out of %d buffers were "
4755 "allocated successfully.\n",
4756 tp->dev->name, i, tp->rx_jumbo_pending);
4757 if (i == 0) {
4758 tg3_free_rings(tp);
4759 return -ENOMEM;
4760 }
4761 tp->rx_jumbo_pending = i;
4762 break;
4763 }
4764 }
4765 }
4766 return 0;
4767 }
4768
4769 /*
4770 * Must not be invoked with interrupt sources disabled and
4771 * the hardware shutdown down.
4772 */
4773 static void tg3_free_consistent(struct tg3 *tp)
4774 {
4775 kfree(tp->rx_std_buffers);
4776 tp->rx_std_buffers = NULL;
4777 if (tp->rx_std) {
4778 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
4779 tp->rx_std, tp->rx_std_mapping);
4780 tp->rx_std = NULL;
4781 }
4782 if (tp->rx_jumbo) {
4783 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4784 tp->rx_jumbo, tp->rx_jumbo_mapping);
4785 tp->rx_jumbo = NULL;
4786 }
4787 if (tp->rx_rcb) {
4788 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4789 tp->rx_rcb, tp->rx_rcb_mapping);
4790 tp->rx_rcb = NULL;
4791 }
4792 if (tp->tx_ring) {
4793 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
4794 tp->tx_ring, tp->tx_desc_mapping);
4795 tp->tx_ring = NULL;
4796 }
4797 if (tp->hw_status) {
4798 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
4799 tp->hw_status, tp->status_mapping);
4800 tp->hw_status = NULL;
4801 }
4802 if (tp->hw_stats) {
4803 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4804 tp->hw_stats, tp->stats_mapping);
4805 tp->hw_stats = NULL;
4806 }
4807 }
4808
4809 /*
4810 * Must not be invoked with interrupt sources disabled and
4811 * the hardware shutdown down. Can sleep.
4812 */
4813 static int tg3_alloc_consistent(struct tg3 *tp)
4814 {
4815 tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
4816 (TG3_RX_RING_SIZE +
4817 TG3_RX_JUMBO_RING_SIZE)) +
4818 (sizeof(struct tx_ring_info) *
4819 TG3_TX_RING_SIZE),
4820 GFP_KERNEL);
4821 if (!tp->rx_std_buffers)
4822 return -ENOMEM;
4823
4824 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4825 tp->tx_buffers = (struct tx_ring_info *)
4826 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4827
4828 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4829 &tp->rx_std_mapping);
4830 if (!tp->rx_std)
4831 goto err_out;
4832
4833 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4834 &tp->rx_jumbo_mapping);
4835
4836 if (!tp->rx_jumbo)
4837 goto err_out;
4838
4839 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4840 &tp->rx_rcb_mapping);
4841 if (!tp->rx_rcb)
4842 goto err_out;
4843
4844 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4845 &tp->tx_desc_mapping);
4846 if (!tp->tx_ring)
4847 goto err_out;
4848
4849 tp->hw_status = pci_alloc_consistent(tp->pdev,
4850 TG3_HW_STATUS_SIZE,
4851 &tp->status_mapping);
4852 if (!tp->hw_status)
4853 goto err_out;
4854
4855 tp->hw_stats = pci_alloc_consistent(tp->pdev,
4856 sizeof(struct tg3_hw_stats),
4857 &tp->stats_mapping);
4858 if (!tp->hw_stats)
4859 goto err_out;
4860
4861 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4862 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4863
4864 return 0;
4865
4866 err_out:
4867 tg3_free_consistent(tp);
4868 return -ENOMEM;
4869 }
4870
4871 #define MAX_WAIT_CNT 1000
4872
4873 /* To stop a block, clear the enable bit and poll till it
4874 * clears. tp->lock is held.
4875 */
4876 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
4877 {
4878 unsigned int i;
4879 u32 val;
4880
4881 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4882 switch (ofs) {
4883 case RCVLSC_MODE:
4884 case DMAC_MODE:
4885 case MBFREE_MODE:
4886 case BUFMGR_MODE:
4887 case MEMARB_MODE:
4888 /* We can't enable/disable these bits of the
4889 * 5705/5750, just say success.
4890 */
4891 return 0;
4892
4893 default:
4894 break;
4895 };
4896 }
4897
4898 val = tr32(ofs);
4899 val &= ~enable_bit;
4900 tw32_f(ofs, val);
4901
4902 for (i = 0; i < MAX_WAIT_CNT; i++) {
4903 udelay(100);
4904 val = tr32(ofs);
4905 if ((val & enable_bit) == 0)
4906 break;
4907 }
4908
4909 if (i == MAX_WAIT_CNT && !silent) {
4910 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4911 "ofs=%lx enable_bit=%x\n",
4912 ofs, enable_bit);
4913 return -ENODEV;
4914 }
4915
4916 return 0;
4917 }
4918
4919 /* tp->lock is held. */
4920 static int tg3_abort_hw(struct tg3 *tp, int silent)
4921 {
4922 int i, err;
4923
4924 tg3_disable_ints(tp);
4925
4926 tp->rx_mode &= ~RX_MODE_ENABLE;
4927 tw32_f(MAC_RX_MODE, tp->rx_mode);
4928 udelay(10);
4929
4930 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4931 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4932 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4933 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4934 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4935 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4936
4937 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4938 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4939 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4940 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4941 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4942 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4943 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
4944
4945 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4946 tw32_f(MAC_MODE, tp->mac_mode);
4947 udelay(40);
4948
4949 tp->tx_mode &= ~TX_MODE_ENABLE;
4950 tw32_f(MAC_TX_MODE, tp->tx_mode);
4951
4952 for (i = 0; i < MAX_WAIT_CNT; i++) {
4953 udelay(100);
4954 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4955 break;
4956 }
4957 if (i >= MAX_WAIT_CNT) {
4958 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4959 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4960 tp->dev->name, tr32(MAC_TX_MODE));
4961 err |= -ENODEV;
4962 }
4963
4964 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
4965 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4966 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
4967
4968 tw32(FTQ_RESET, 0xffffffff);
4969 tw32(FTQ_RESET, 0x00000000);
4970
4971 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4972 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
4973
4974 if (tp->hw_status)
4975 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4976 if (tp->hw_stats)
4977 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4978
4979 return err;
4980 }
4981
4982 /* tp->lock is held. */
4983 static int tg3_nvram_lock(struct tg3 *tp)
4984 {
4985 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4986 int i;
4987
4988 if (tp->nvram_lock_cnt == 0) {
4989 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4990 for (i = 0; i < 8000; i++) {
4991 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4992 break;
4993 udelay(20);
4994 }
4995 if (i == 8000) {
4996 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
4997 return -ENODEV;
4998 }
4999 }
5000 tp->nvram_lock_cnt++;
5001 }
5002 return 0;
5003 }
5004
5005 /* tp->lock is held. */
5006 static void tg3_nvram_unlock(struct tg3 *tp)
5007 {
5008 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
5009 if (tp->nvram_lock_cnt > 0)
5010 tp->nvram_lock_cnt--;
5011 if (tp->nvram_lock_cnt == 0)
5012 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
5013 }
5014 }
5015
5016 /* tp->lock is held. */
5017 static void tg3_enable_nvram_access(struct tg3 *tp)
5018 {
5019 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
5020 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
5021 u32 nvaccess = tr32(NVRAM_ACCESS);
5022
5023 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
5024 }
5025 }
5026
5027 /* tp->lock is held. */
5028 static void tg3_disable_nvram_access(struct tg3 *tp)
5029 {
5030 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
5031 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
5032 u32 nvaccess = tr32(NVRAM_ACCESS);
5033
5034 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
5035 }
5036 }
5037
5038 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5039 {
5040 int i;
5041 u32 apedata;
5042
5043 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5044 if (apedata != APE_SEG_SIG_MAGIC)
5045 return;
5046
5047 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
5048 if (apedata != APE_FW_STATUS_READY)
5049 return;
5050
5051 /* Wait for up to 1 millisecond for APE to service previous event. */
5052 for (i = 0; i < 10; i++) {
5053 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5054 return;
5055
5056 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5057
5058 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5059 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5060 event | APE_EVENT_STATUS_EVENT_PENDING);
5061
5062 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5063
5064 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5065 break;
5066
5067 udelay(100);
5068 }
5069
5070 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5071 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
5072 }
5073
5074 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
5075 {
5076 u32 event;
5077 u32 apedata;
5078
5079 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
5080 return;
5081
5082 switch (kind) {
5083 case RESET_KIND_INIT:
5084 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
5085 APE_HOST_SEG_SIG_MAGIC);
5086 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
5087 APE_HOST_SEG_LEN_MAGIC);
5088 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
5089 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
5090 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
5091 APE_HOST_DRIVER_ID_MAGIC);
5092 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
5093 APE_HOST_BEHAV_NO_PHYLOCK);
5094
5095 event = APE_EVENT_STATUS_STATE_START;
5096 break;
5097 case RESET_KIND_SHUTDOWN:
5098 event = APE_EVENT_STATUS_STATE_UNLOAD;
5099 break;
5100 case RESET_KIND_SUSPEND:
5101 event = APE_EVENT_STATUS_STATE_SUSPEND;
5102 break;
5103 default:
5104 return;
5105 }
5106
5107 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
5108
5109 tg3_ape_send_event(tp, event);
5110 }
5111
5112 /* tp->lock is held. */
5113 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
5114 {
5115 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
5116 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
5117
5118 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5119 switch (kind) {
5120 case RESET_KIND_INIT:
5121 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5122 DRV_STATE_START);
5123 break;
5124
5125 case RESET_KIND_SHUTDOWN:
5126 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5127 DRV_STATE_UNLOAD);
5128 break;
5129
5130 case RESET_KIND_SUSPEND:
5131 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5132 DRV_STATE_SUSPEND);
5133 break;
5134
5135 default:
5136 break;
5137 };
5138 }
5139
5140 if (kind == RESET_KIND_INIT ||
5141 kind == RESET_KIND_SUSPEND)
5142 tg3_ape_driver_state_change(tp, kind);
5143 }
5144
5145 /* tp->lock is held. */
5146 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
5147 {
5148 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5149 switch (kind) {
5150 case RESET_KIND_INIT:
5151 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5152 DRV_STATE_START_DONE);
5153 break;
5154
5155 case RESET_KIND_SHUTDOWN:
5156 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5157 DRV_STATE_UNLOAD_DONE);
5158 break;
5159
5160 default:
5161 break;
5162 };
5163 }
5164
5165 if (kind == RESET_KIND_SHUTDOWN)
5166 tg3_ape_driver_state_change(tp, kind);
5167 }
5168
5169 /* tp->lock is held. */
5170 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
5171 {
5172 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5173 switch (kind) {
5174 case RESET_KIND_INIT:
5175 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5176 DRV_STATE_START);
5177 break;
5178
5179 case RESET_KIND_SHUTDOWN:
5180 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5181 DRV_STATE_UNLOAD);
5182 break;
5183
5184 case RESET_KIND_SUSPEND:
5185 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5186 DRV_STATE_SUSPEND);
5187 break;
5188
5189 default:
5190 break;
5191 };
5192 }
5193 }
5194
5195 static int tg3_poll_fw(struct tg3 *tp)
5196 {
5197 int i;
5198 u32 val;
5199
5200 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5201 /* Wait up to 20ms for init done. */
5202 for (i = 0; i < 200; i++) {
5203 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
5204 return 0;
5205 udelay(100);
5206 }
5207 return -ENODEV;
5208 }
5209
5210 /* Wait for firmware initialization to complete. */
5211 for (i = 0; i < 100000; i++) {
5212 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
5213 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
5214 break;
5215 udelay(10);
5216 }
5217
5218 /* Chip might not be fitted with firmware. Some Sun onboard
5219 * parts are configured like that. So don't signal the timeout
5220 * of the above loop as an error, but do report the lack of
5221 * running firmware once.
5222 */
5223 if (i >= 100000 &&
5224 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
5225 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
5226
5227 printk(KERN_INFO PFX "%s: No firmware running.\n",
5228 tp->dev->name);
5229 }
5230
5231 return 0;
5232 }
5233
5234 /* Save PCI command register before chip reset */
5235 static void tg3_save_pci_state(struct tg3 *tp)
5236 {
5237 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
5238 }
5239
5240 /* Restore PCI state after chip reset */
5241 static void tg3_restore_pci_state(struct tg3 *tp)
5242 {
5243 u32 val;
5244
5245 /* Re-enable indirect register accesses. */
5246 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
5247 tp->misc_host_ctrl);
5248
5249 /* Set MAX PCI retry to zero. */
5250 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
5251 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
5252 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
5253 val |= PCISTATE_RETRY_SAME_DMA;
5254 /* Allow reads and writes to the APE register and memory space. */
5255 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
5256 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
5257 PCISTATE_ALLOW_APE_SHMEM_WR;
5258 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
5259
5260 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
5261
5262 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
5263 pcie_set_readrq(tp->pdev, 4096);
5264 else {
5265 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
5266 tp->pci_cacheline_sz);
5267 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
5268 tp->pci_lat_timer);
5269 }
5270
5271 /* Make sure PCI-X relaxed ordering bit is clear. */
5272 if (tp->pcix_cap) {
5273 u16 pcix_cmd;
5274
5275 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
5276 &pcix_cmd);
5277 pcix_cmd &= ~PCI_X_CMD_ERO;
5278 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
5279 pcix_cmd);
5280 }
5281
5282 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5283
5284 /* Chip reset on 5780 will reset MSI enable bit,
5285 * so need to restore it.
5286 */
5287 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
5288 u16 ctrl;
5289
5290 pci_read_config_word(tp->pdev,
5291 tp->msi_cap + PCI_MSI_FLAGS,
5292 &ctrl);
5293 pci_write_config_word(tp->pdev,
5294 tp->msi_cap + PCI_MSI_FLAGS,
5295 ctrl | PCI_MSI_FLAGS_ENABLE);
5296 val = tr32(MSGINT_MODE);
5297 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
5298 }
5299 }
5300 }
5301
5302 static void tg3_stop_fw(struct tg3 *);
5303
5304 /* tp->lock is held. */
5305 static int tg3_chip_reset(struct tg3 *tp)
5306 {
5307 u32 val;
5308 void (*write_op)(struct tg3 *, u32, u32);
5309 int err;
5310
5311 tg3_nvram_lock(tp);
5312
5313 /* No matching tg3_nvram_unlock() after this because
5314 * chip reset below will undo the nvram lock.
5315 */
5316 tp->nvram_lock_cnt = 0;
5317
5318 /* GRC_MISC_CFG core clock reset will clear the memory
5319 * enable bit in PCI register 4 and the MSI enable bit
5320 * on some chips, so we save relevant registers here.
5321 */
5322 tg3_save_pci_state(tp);
5323
5324 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
5325 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
5326 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
5327 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
5328 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
5329 tw32(GRC_FASTBOOT_PC, 0);
5330
5331 /*
5332 * We must avoid the readl() that normally takes place.
5333 * It locks machines, causes machine checks, and other
5334 * fun things. So, temporarily disable the 5701
5335 * hardware workaround, while we do the reset.
5336 */
5337 write_op = tp->write32;
5338 if (write_op == tg3_write_flush_reg32)
5339 tp->write32 = tg3_write32;
5340
5341 /* Prevent the irq handler from reading or writing PCI registers
5342 * during chip reset when the memory enable bit in the PCI command
5343 * register may be cleared. The chip does not generate interrupt
5344 * at this time, but the irq handler may still be called due to irq
5345 * sharing or irqpoll.
5346 */
5347 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
5348 if (tp->hw_status) {
5349 tp->hw_status->status = 0;
5350 tp->hw_status->status_tag = 0;
5351 }
5352 tp->last_tag = 0;
5353 smp_mb();
5354 synchronize_irq(tp->pdev->irq);
5355
5356 /* do the reset */
5357 val = GRC_MISC_CFG_CORECLK_RESET;
5358
5359 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
5360 if (tr32(0x7e2c) == 0x60) {
5361 tw32(0x7e2c, 0x20);
5362 }
5363 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
5364 tw32(GRC_MISC_CFG, (1 << 29));
5365 val |= (1 << 29);
5366 }
5367 }
5368
5369 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5370 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
5371 tw32(GRC_VCPU_EXT_CTRL,
5372 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
5373 }
5374
5375 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5376 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
5377 tw32(GRC_MISC_CFG, val);
5378
5379 /* restore 5701 hardware bug workaround write method */
5380 tp->write32 = write_op;
5381
5382 /* Unfortunately, we have to delay before the PCI read back.
5383 * Some 575X chips even will not respond to a PCI cfg access
5384 * when the reset command is given to the chip.
5385 *
5386 * How do these hardware designers expect things to work
5387 * properly if the PCI write is posted for a long period
5388 * of time? It is always necessary to have some method by
5389 * which a register read back can occur to push the write
5390 * out which does the reset.
5391 *
5392 * For most tg3 variants the trick below was working.
5393 * Ho hum...
5394 */
5395 udelay(120);
5396
5397 /* Flush PCI posted writes. The normal MMIO registers
5398 * are inaccessible at this time so this is the only
5399 * way to make this reliably (actually, this is no longer
5400 * the case, see above). I tried to use indirect
5401 * register read/write but this upset some 5701 variants.
5402 */
5403 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
5404
5405 udelay(120);
5406
5407 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
5408 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
5409 int i;
5410 u32 cfg_val;
5411
5412 /* Wait for link training to complete. */
5413 for (i = 0; i < 5000; i++)
5414 udelay(100);
5415
5416 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
5417 pci_write_config_dword(tp->pdev, 0xc4,
5418 cfg_val | (1 << 15));
5419 }
5420 /* Set PCIE max payload size and clear error status. */
5421 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
5422 }
5423
5424 tg3_restore_pci_state(tp);
5425
5426 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
5427
5428 val = 0;
5429 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5430 val = tr32(MEMARB_MODE);
5431 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
5432
5433 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
5434 tg3_stop_fw(tp);
5435 tw32(0x5000, 0x400);
5436 }
5437
5438 tw32(GRC_MODE, tp->grc_mode);
5439
5440 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
5441 val = tr32(0xc4);
5442
5443 tw32(0xc4, val | (1 << 15));
5444 }
5445
5446 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
5447 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5448 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
5449 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
5450 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
5451 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
5452 }
5453
5454 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5455 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
5456 tw32_f(MAC_MODE, tp->mac_mode);
5457 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
5458 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
5459 tw32_f(MAC_MODE, tp->mac_mode);
5460 } else
5461 tw32_f(MAC_MODE, 0);
5462 udelay(40);
5463
5464 err = tg3_poll_fw(tp);
5465 if (err)
5466 return err;
5467
5468 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
5469 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
5470 val = tr32(0x7c00);
5471
5472 tw32(0x7c00, val | (1 << 25));
5473 }
5474
5475 /* Reprobe ASF enable state. */
5476 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
5477 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
5478 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
5479 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
5480 u32 nic_cfg;
5481
5482 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
5483 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
5484 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
5485 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
5486 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
5487 }
5488 }
5489
5490 return 0;
5491 }
5492
5493 /* tp->lock is held. */
5494 static void tg3_stop_fw(struct tg3 *tp)
5495 {
5496 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
5497 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
5498 u32 val;
5499 int i;
5500
5501 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
5502 val = tr32(GRC_RX_CPU_EVENT);
5503 val |= (1 << 14);
5504 tw32(GRC_RX_CPU_EVENT, val);
5505
5506 /* Wait for RX cpu to ACK the event. */
5507 for (i = 0; i < 100; i++) {
5508 if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
5509 break;
5510 udelay(1);
5511 }
5512 }
5513 }
5514
5515 /* tp->lock is held. */
5516 static int tg3_halt(struct tg3 *tp, int kind, int silent)
5517 {
5518 int err;
5519
5520 tg3_stop_fw(tp);
5521
5522 tg3_write_sig_pre_reset(tp, kind);
5523
5524 tg3_abort_hw(tp, silent);
5525 err = tg3_chip_reset(tp);
5526
5527 tg3_write_sig_legacy(tp, kind);
5528 tg3_write_sig_post_reset(tp, kind);
5529
5530 if (err)
5531 return err;
5532
5533 return 0;
5534 }
5535
5536 #define TG3_FW_RELEASE_MAJOR 0x0
5537 #define TG3_FW_RELASE_MINOR 0x0
5538 #define TG3_FW_RELEASE_FIX 0x0
5539 #define TG3_FW_START_ADDR 0x08000000
5540 #define TG3_FW_TEXT_ADDR 0x08000000
5541 #define TG3_FW_TEXT_LEN 0x9c0
5542 #define TG3_FW_RODATA_ADDR 0x080009c0
5543 #define TG3_FW_RODATA_LEN 0x60
5544 #define TG3_FW_DATA_ADDR 0x08000a40
5545 #define TG3_FW_DATA_LEN 0x20
5546 #define TG3_FW_SBSS_ADDR 0x08000a60
5547 #define TG3_FW_SBSS_LEN 0xc
5548 #define TG3_FW_BSS_ADDR 0x08000a70
5549 #define TG3_FW_BSS_LEN 0x10
5550
5551 static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
5552 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
5553 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
5554 0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
5555 0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
5556 0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
5557 0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
5558 0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
5559 0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
5560 0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
5561 0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
5562 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
5563 0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
5564 0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
5565 0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
5566 0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
5567 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5568 0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
5569 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
5570 0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
5571 0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5572 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
5573 0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
5574 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5575 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5576 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5577 0, 0, 0, 0, 0, 0,
5578 0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
5579 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5580 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5581 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5582 0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
5583 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
5584 0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
5585 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
5586 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5587 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5588 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
5589 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5590 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5591 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5592 0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
5593 0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
5594 0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
5595 0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
5596 0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
5597 0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
5598 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
5599 0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
5600 0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
5601 0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
5602 0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
5603 0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
5604 0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
5605 0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
5606 0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
5607 0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
5608 0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
5609 0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
5610 0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
5611 0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
5612 0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
5613 0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
5614 0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
5615 0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
5616 0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
5617 0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
5618 0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
5619 0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
5620 0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
5621 0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
5622 0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
5623 0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
5624 0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
5625 0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
5626 0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
5627 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
5628 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
5629 0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
5630 0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
5631 0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
5632 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
5633 0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
5634 0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
5635 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
5636 0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
5637 0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
5638 0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
5639 0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
5640 0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
5641 0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
5642 0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
5643 };
5644
5645 static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
5646 0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
5647 0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
5648 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5649 0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
5650 0x00000000
5651 };
5652
5653 #if 0 /* All zeros, don't eat up space with it. */
5654 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
5655 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5656 0x00000000, 0x00000000, 0x00000000, 0x00000000
5657 };
5658 #endif
5659
5660 #define RX_CPU_SCRATCH_BASE 0x30000
5661 #define RX_CPU_SCRATCH_SIZE 0x04000
5662 #define TX_CPU_SCRATCH_BASE 0x34000
5663 #define TX_CPU_SCRATCH_SIZE 0x04000
5664
5665 /* tp->lock is held. */
5666 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
5667 {
5668 int i;
5669
5670 BUG_ON(offset == TX_CPU_BASE &&
5671 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
5672
5673 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5674 u32 val = tr32(GRC_VCPU_EXT_CTRL);
5675
5676 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
5677 return 0;
5678 }
5679 if (offset == RX_CPU_BASE) {
5680 for (i = 0; i < 10000; i++) {
5681 tw32(offset + CPU_STATE, 0xffffffff);
5682 tw32(offset + CPU_MODE, CPU_MODE_HALT);
5683 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5684 break;
5685 }
5686
5687 tw32(offset + CPU_STATE, 0xffffffff);
5688 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
5689 udelay(10);
5690 } else {
5691 for (i = 0; i < 10000; i++) {
5692 tw32(offset + CPU_STATE, 0xffffffff);
5693 tw32(offset + CPU_MODE, CPU_MODE_HALT);
5694 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5695 break;
5696 }
5697 }
5698
5699 if (i >= 10000) {
5700 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
5701 "and %s CPU\n",
5702 tp->dev->name,
5703 (offset == RX_CPU_BASE ? "RX" : "TX"));
5704 return -ENODEV;
5705 }
5706
5707 /* Clear firmware's nvram arbitration. */
5708 if (tp->tg3_flags & TG3_FLAG_NVRAM)
5709 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
5710 return 0;
5711 }
5712
5713 struct fw_info {
5714 unsigned int text_base;
5715 unsigned int text_len;
5716 const u32 *text_data;
5717 unsigned int rodata_base;
5718 unsigned int rodata_len;
5719 const u32 *rodata_data;
5720 unsigned int data_base;
5721 unsigned int data_len;
5722 const u32 *data_data;
5723 };
5724
5725 /* tp->lock is held. */
5726 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
5727 int cpu_scratch_size, struct fw_info *info)
5728 {
5729 int err, lock_err, i;
5730 void (*write_op)(struct tg3 *, u32, u32);
5731
5732 if (cpu_base == TX_CPU_BASE &&
5733 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5734 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
5735 "TX cpu firmware on %s which is 5705.\n",
5736 tp->dev->name);
5737 return -EINVAL;
5738 }
5739
5740 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5741 write_op = tg3_write_mem;
5742 else
5743 write_op = tg3_write_indirect_reg32;
5744
5745 /* It is possible that bootcode is still loading at this point.
5746 * Get the nvram lock first before halting the cpu.
5747 */
5748 lock_err = tg3_nvram_lock(tp);
5749 err = tg3_halt_cpu(tp, cpu_base);
5750 if (!lock_err)
5751 tg3_nvram_unlock(tp);
5752 if (err)
5753 goto out;
5754
5755 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
5756 write_op(tp, cpu_scratch_base + i, 0);
5757 tw32(cpu_base + CPU_STATE, 0xffffffff);
5758 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
5759 for (i = 0; i < (info->text_len / sizeof(u32)); i++)
5760 write_op(tp, (cpu_scratch_base +
5761 (info->text_base & 0xffff) +
5762 (i * sizeof(u32))),
5763 (info->text_data ?
5764 info->text_data[i] : 0));
5765 for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
5766 write_op(tp, (cpu_scratch_base +
5767 (info->rodata_base & 0xffff) +
5768 (i * sizeof(u32))),
5769 (info->rodata_data ?
5770 info->rodata_data[i] : 0));
5771 for (i = 0; i < (info->data_len / sizeof(u32)); i++)
5772 write_op(tp, (cpu_scratch_base +
5773 (info->data_base & 0xffff) +
5774 (i * sizeof(u32))),
5775 (info->data_data ?
5776 info->data_data[i] : 0));
5777
5778 err = 0;
5779
5780 out:
5781 return err;
5782 }
5783
5784 /* tp->lock is held. */
5785 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
5786 {
5787 struct fw_info info;
5788 int err, i;
5789
5790 info.text_base = TG3_FW_TEXT_ADDR;
5791 info.text_len = TG3_FW_TEXT_LEN;
5792 info.text_data = &tg3FwText[0];
5793 info.rodata_base = TG3_FW_RODATA_ADDR;
5794 info.rodata_len = TG3_FW_RODATA_LEN;
5795 info.rodata_data = &tg3FwRodata[0];
5796 info.data_base = TG3_FW_DATA_ADDR;
5797 info.data_len = TG3_FW_DATA_LEN;
5798 info.data_data = NULL;
5799
5800 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
5801 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
5802 &info);
5803 if (err)
5804 return err;
5805
5806 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
5807 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
5808 &info);
5809 if (err)
5810 return err;
5811
5812 /* Now startup only the RX cpu. */
5813 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5814 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
5815
5816 for (i = 0; i < 5; i++) {
5817 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
5818 break;
5819 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5820 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
5821 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
5822 udelay(1000);
5823 }
5824 if (i >= 5) {
5825 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
5826 "to set RX CPU PC, is %08x should be %08x\n",
5827 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
5828 TG3_FW_TEXT_ADDR);
5829 return -ENODEV;
5830 }
5831 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5832 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
5833
5834 return 0;
5835 }
5836
5837
5838 #define TG3_TSO_FW_RELEASE_MAJOR 0x1
5839 #define TG3_TSO_FW_RELASE_MINOR 0x6
5840 #define TG3_TSO_FW_RELEASE_FIX 0x0
5841 #define TG3_TSO_FW_START_ADDR 0x08000000
5842 #define TG3_TSO_FW_TEXT_ADDR 0x08000000
5843 #define TG3_TSO_FW_TEXT_LEN 0x1aa0
5844 #define TG3_TSO_FW_RODATA_ADDR 0x08001aa0
5845 #define TG3_TSO_FW_RODATA_LEN 0x60
5846 #define TG3_TSO_FW_DATA_ADDR 0x08001b20
5847 #define TG3_TSO_FW_DATA_LEN 0x30
5848 #define TG3_TSO_FW_SBSS_ADDR 0x08001b50
5849 #define TG3_TSO_FW_SBSS_LEN 0x2c
5850 #define TG3_TSO_FW_BSS_ADDR 0x08001b80
5851 #define TG3_TSO_FW_BSS_LEN 0x894
5852
5853 static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
5854 0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
5855 0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
5856 0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5857 0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
5858 0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
5859 0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
5860 0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
5861 0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
5862 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
5863 0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
5864 0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
5865 0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
5866 0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
5867 0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
5868 0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
5869 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
5870 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
5871 0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
5872 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5873 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
5874 0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
5875 0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
5876 0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
5877 0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
5878 0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
5879 0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
5880 0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
5881 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
5882 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
5883 0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5884 0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
5885 0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
5886 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
5887 0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
5888 0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
5889 0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
5890 0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
5891 0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
5892 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5893 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
5894 0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
5895 0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
5896 0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
5897 0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
5898 0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
5899 0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
5900 0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
5901 0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5902 0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
5903 0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5904 0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
5905 0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
5906 0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
5907 0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
5908 0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
5909 0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
5910 0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
5911 0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
5912 0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
5913 0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
5914 0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
5915 0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
5916 0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
5917 0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
5918 0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
5919 0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
5920 0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
5921 0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
5922 0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
5923 0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
5924 0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
5925 0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
5926 0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
5927 0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
5928 0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
5929 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
5930 0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
5931 0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
5932 0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
5933 0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
5934 0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
5935 0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
5936 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
5937 0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
5938 0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
5939 0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
5940 0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
5941 0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
5942 0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
5943 0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
5944 0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
5945 0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
5946 0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
5947 0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
5948 0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
5949 0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
5950 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
5951 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
5952 0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
5953 0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
5954 0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
5955 0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
5956 0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
5957 0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
5958 0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
5959 0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
5960 0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
5961 0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
5962 0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
5963 0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
5964 0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
5965 0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
5966 0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
5967 0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
5968 0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
5969 0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
5970 0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
5971 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
5972 0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
5973 0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
5974 0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
5975 0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
5976 0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
5977 0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
5978 0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
5979 0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
5980 0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
5981 0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
5982 0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
5983 0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
5984 0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
5985 0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
5986 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
5987 0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
5988 0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
5989 0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
5990 0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
5991 0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
5992 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5993 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
5994 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
5995 0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
5996 0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
5997 0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
5998 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
5999 0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
6000 0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
6001 0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
6002 0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
6003 0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
6004 0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
6005 0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
6006 0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
6007 0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
6008 0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
6009 0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
6010 0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
6011 0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
6012 0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
6013 0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
6014 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
6015 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
6016 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
6017 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
6018 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
6019 0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
6020 0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
6021 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
6022 0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
6023 0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
6024 0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
6025 0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
6026 0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
6027 0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
6028 0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
6029 0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
6030 0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
6031 0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
6032 0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
6033 0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
6034 0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
6035 0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
6036 0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
6037 0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
6038 0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
6039 0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
6040 0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
6041 0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
6042 0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
6043 0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
6044 0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
6045 0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
6046 0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
6047 0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
6048 0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
6049 0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
6050 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
6051 0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
6052 0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
6053 0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
6054 0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
6055 0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
6056 0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
6057 0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
6058 0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
6059 0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
6060 0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
6061 0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
6062 0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
6063 0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
6064 0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
6065 0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
6066 0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
6067 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
6068 0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
6069 0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
6070 0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
6071 0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
6072 0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
6073 0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
6074 0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
6075 0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
6076 0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
6077 0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
6078 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
6079 0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
6080 0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
6081 0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
6082 0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
6083 0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
6084 0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
6085 0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
6086 0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
6087 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
6088 0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
6089 0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
6090 0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
6091 0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
6092 0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
6093 0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
6094 0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
6095 0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
6096 0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
6097 0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
6098 0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
6099 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
6100 0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
6101 0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
6102 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
6103 0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
6104 0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
6105 0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
6106 0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
6107 0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
6108 0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
6109 0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
6110 0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
6111 0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
6112 0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
6113 0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
6114 0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
6115 0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
6116 0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
6117 0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
6118 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
6119 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
6120 0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
6121 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
6122 0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
6123 0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
6124 0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
6125 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
6126 0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
6127 0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
6128 0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
6129 0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
6130 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
6131 0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
6132 0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
6133 0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
6134 0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
6135 0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
6136 0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
6137 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
6138 };
6139
6140 static const u32 tg3TsoFwRodata[] = {
6141 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
6142 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
6143 0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
6144 0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
6145 0x00000000,
6146 };
6147
6148 static const u32 tg3TsoFwData[] = {
6149 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
6150 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
6151 0x00000000,
6152 };
6153
6154 /* 5705 needs a special version of the TSO firmware. */
6155 #define TG3_TSO5_FW_RELEASE_MAJOR 0x1
6156 #define TG3_TSO5_FW_RELASE_MINOR 0x2
6157 #define TG3_TSO5_FW_RELEASE_FIX 0x0
6158 #define TG3_TSO5_FW_START_ADDR 0x00010000
6159 #define TG3_TSO5_FW_TEXT_ADDR 0x00010000
6160 #define TG3_TSO5_FW_TEXT_LEN 0xe90
6161 #define TG3_TSO5_FW_RODATA_ADDR 0x00010e90
6162 #define TG3_TSO5_FW_RODATA_LEN 0x50
6163 #define TG3_TSO5_FW_DATA_ADDR 0x00010f00
6164 #define TG3_TSO5_FW_DATA_LEN 0x20
6165 #define TG3_TSO5_FW_SBSS_ADDR 0x00010f20
6166 #define TG3_TSO5_FW_SBSS_LEN 0x28
6167 #define TG3_TSO5_FW_BSS_ADDR 0x00010f50
6168 #define TG3_TSO5_FW_BSS_LEN 0x88
6169
6170 static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
6171 0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
6172 0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
6173 0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
6174 0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
6175 0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
6176 0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
6177 0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
6178 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
6179 0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
6180 0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
6181 0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
6182 0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
6183 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
6184 0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
6185 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
6186 0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
6187 0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
6188 0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
6189 0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
6190 0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
6191 0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
6192 0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
6193 0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
6194 0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
6195 0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
6196 0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
6197 0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
6198 0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
6199 0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
6200 0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
6201 0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
6202 0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
6203 0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
6204 0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
6205 0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
6206 0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
6207 0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
6208 0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
6209 0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
6210 0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
6211 0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
6212 0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
6213 0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
6214 0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
6215 0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
6216 0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
6217 0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
6218 0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
6219 0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
6220 0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
6221 0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
6222 0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
6223 0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
6224 0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
6225 0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
6226 0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
6227 0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
6228 0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
6229 0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
6230 0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
6231 0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
6232 0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
6233 0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
6234 0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
6235 0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
6236 0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
6237 0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
6238 0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
6239 0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
6240 0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
6241 0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
6242 0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
6243 0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
6244 0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
6245 0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
6246 0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
6247 0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
6248 0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
6249 0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
6250 0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
6251 0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
6252 0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
6253 0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
6254 0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
6255 0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
6256 0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
6257 0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
6258 0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
6259 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
6260 0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
6261 0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
6262 0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
6263 0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
6264 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
6265 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
6266 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
6267 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
6268 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
6269 0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
6270 0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
6271 0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
6272 0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
6273 0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
6274 0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
6275 0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
6276 0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
6277 0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
6278 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
6279 0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
6280 0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
6281 0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
6282 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
6283 0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
6284 0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
6285 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
6286 0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
6287 0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
6288 0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
6289 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
6290 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
6291 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
6292 0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
6293 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
6294 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
6295 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
6296 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
6297 0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
6298 0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
6299 0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
6300 0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
6301 0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
6302 0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
6303 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
6304 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
6305 0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
6306 0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
6307 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
6308 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
6309 0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
6310 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
6311 0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
6312 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
6313 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
6314 0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
6315 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
6316 0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
6317 0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
6318 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
6319 0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
6320 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
6321 0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
6322 0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
6323 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
6324 0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
6325 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
6326 0x00000000, 0x00000000, 0x00000000,
6327 };
6328
6329 static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
6330 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
6331 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
6332 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
6333 0x00000000, 0x00000000, 0x00000000,
6334 };
6335
6336 static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
6337 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
6338 0x00000000, 0x00000000, 0x00000000,
6339 };
6340
6341 /* tp->lock is held. */
6342 static int tg3_load_tso_firmware(struct tg3 *tp)
6343 {
6344 struct fw_info info;
6345 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6346 int err, i;
6347
6348 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6349 return 0;
6350
6351 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6352 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
6353 info.text_len = TG3_TSO5_FW_TEXT_LEN;
6354 info.text_data = &tg3Tso5FwText[0];
6355 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
6356 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
6357 info.rodata_data = &tg3Tso5FwRodata[0];
6358 info.data_base = TG3_TSO5_FW_DATA_ADDR;
6359 info.data_len = TG3_TSO5_FW_DATA_LEN;
6360 info.data_data = &tg3Tso5FwData[0];
6361 cpu_base = RX_CPU_BASE;
6362 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
6363 cpu_scratch_size = (info.text_len +
6364 info.rodata_len +
6365 info.data_len +
6366 TG3_TSO5_FW_SBSS_LEN +
6367 TG3_TSO5_FW_BSS_LEN);
6368 } else {
6369 info.text_base = TG3_TSO_FW_TEXT_ADDR;
6370 info.text_len = TG3_TSO_FW_TEXT_LEN;
6371 info.text_data = &tg3TsoFwText[0];
6372 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
6373 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
6374 info.rodata_data = &tg3TsoFwRodata[0];
6375 info.data_base = TG3_TSO_FW_DATA_ADDR;
6376 info.data_len = TG3_TSO_FW_DATA_LEN;
6377 info.data_data = &tg3TsoFwData[0];
6378 cpu_base = TX_CPU_BASE;
6379 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6380 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6381 }
6382
6383 err = tg3_load_firmware_cpu(tp, cpu_base,
6384 cpu_scratch_base, cpu_scratch_size,
6385 &info);
6386 if (err)
6387 return err;
6388
6389 /* Now startup the cpu. */
6390 tw32(cpu_base + CPU_STATE, 0xffffffff);
6391 tw32_f(cpu_base + CPU_PC, info.text_base);
6392
6393 for (i = 0; i < 5; i++) {
6394 if (tr32(cpu_base + CPU_PC) == info.text_base)
6395 break;
6396 tw32(cpu_base + CPU_STATE, 0xffffffff);
6397 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
6398 tw32_f(cpu_base + CPU_PC, info.text_base);
6399 udelay(1000);
6400 }
6401 if (i >= 5) {
6402 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6403 "to set CPU PC, is %08x should be %08x\n",
6404 tp->dev->name, tr32(cpu_base + CPU_PC),
6405 info.text_base);
6406 return -ENODEV;
6407 }
6408 tw32(cpu_base + CPU_STATE, 0xffffffff);
6409 tw32_f(cpu_base + CPU_MODE, 0x00000000);
6410 return 0;
6411 }
6412
6413
6414 /* tp->lock is held. */
6415 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
6416 {
6417 u32 addr_high, addr_low;
6418 int i;
6419
6420 addr_high = ((tp->dev->dev_addr[0] << 8) |
6421 tp->dev->dev_addr[1]);
6422 addr_low = ((tp->dev->dev_addr[2] << 24) |
6423 (tp->dev->dev_addr[3] << 16) |
6424 (tp->dev->dev_addr[4] << 8) |
6425 (tp->dev->dev_addr[5] << 0));
6426 for (i = 0; i < 4; i++) {
6427 if (i == 1 && skip_mac_1)
6428 continue;
6429 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
6430 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
6431 }
6432
6433 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
6434 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6435 for (i = 0; i < 12; i++) {
6436 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
6437 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
6438 }
6439 }
6440
6441 addr_high = (tp->dev->dev_addr[0] +
6442 tp->dev->dev_addr[1] +
6443 tp->dev->dev_addr[2] +
6444 tp->dev->dev_addr[3] +
6445 tp->dev->dev_addr[4] +
6446 tp->dev->dev_addr[5]) &
6447 TX_BACKOFF_SEED_MASK;
6448 tw32(MAC_TX_BACKOFF_SEED, addr_high);
6449 }
6450
6451 static int tg3_set_mac_addr(struct net_device *dev, void *p)
6452 {
6453 struct tg3 *tp = netdev_priv(dev);
6454 struct sockaddr *addr = p;
6455 int err = 0, skip_mac_1 = 0;
6456
6457 if (!is_valid_ether_addr(addr->sa_data))
6458 return -EINVAL;
6459
6460 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6461
6462 if (!netif_running(dev))
6463 return 0;
6464
6465 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6466 u32 addr0_high, addr0_low, addr1_high, addr1_low;
6467
6468 addr0_high = tr32(MAC_ADDR_0_HIGH);
6469 addr0_low = tr32(MAC_ADDR_0_LOW);
6470 addr1_high = tr32(MAC_ADDR_1_HIGH);
6471 addr1_low = tr32(MAC_ADDR_1_LOW);
6472
6473 /* Skip MAC addr 1 if ASF is using it. */
6474 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6475 !(addr1_high == 0 && addr1_low == 0))
6476 skip_mac_1 = 1;
6477 }
6478 spin_lock_bh(&tp->lock);
6479 __tg3_set_mac_addr(tp, skip_mac_1);
6480 spin_unlock_bh(&tp->lock);
6481
6482 return err;
6483 }
6484
6485 /* tp->lock is held. */
6486 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6487 dma_addr_t mapping, u32 maxlen_flags,
6488 u32 nic_addr)
6489 {
6490 tg3_write_mem(tp,
6491 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6492 ((u64) mapping >> 32));
6493 tg3_write_mem(tp,
6494 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6495 ((u64) mapping & 0xffffffff));
6496 tg3_write_mem(tp,
6497 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6498 maxlen_flags);
6499
6500 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6501 tg3_write_mem(tp,
6502 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6503 nic_addr);
6504 }
6505
6506 static void __tg3_set_rx_mode(struct net_device *);
6507 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6508 {
6509 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6510 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6511 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6512 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6513 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6514 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6515 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6516 }
6517 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6518 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6519 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6520 u32 val = ec->stats_block_coalesce_usecs;
6521
6522 if (!netif_carrier_ok(tp->dev))
6523 val = 0;
6524
6525 tw32(HOSTCC_STAT_COAL_TICKS, val);
6526 }
6527 }
6528
6529 /* tp->lock is held. */
6530 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6531 {
6532 u32 val, rdmac_mode;
6533 int i, err, limit;
6534
6535 tg3_disable_ints(tp);
6536
6537 tg3_stop_fw(tp);
6538
6539 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6540
6541 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
6542 tg3_abort_hw(tp, 1);
6543 }
6544
6545 if (reset_phy)
6546 tg3_phy_reset(tp);
6547
6548 err = tg3_chip_reset(tp);
6549 if (err)
6550 return err;
6551
6552 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6553
6554 if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
6555 tp->pci_chip_rev_id == CHIPREV_ID_5784_A1) {
6556 val = tr32(TG3_CPMU_CTRL);
6557 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
6558 tw32(TG3_CPMU_CTRL, val);
6559
6560 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
6561 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
6562 val |= CPMU_LSPD_10MB_MACCLK_6_25;
6563 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
6564
6565 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
6566 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
6567 val |= CPMU_LNK_AWARE_MACCLK_6_25;
6568 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
6569
6570 val = tr32(TG3_CPMU_HST_ACC);
6571 val &= ~CPMU_HST_ACC_MACCLK_MASK;
6572 val |= CPMU_HST_ACC_MACCLK_6_25;
6573 tw32(TG3_CPMU_HST_ACC, val);
6574 }
6575
6576 /* This works around an issue with Athlon chipsets on
6577 * B3 tigon3 silicon. This bit has no effect on any
6578 * other revision. But do not set this on PCI Express
6579 * chips and don't even touch the clocks if the CPMU is present.
6580 */
6581 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
6582 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6583 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6584 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6585 }
6586
6587 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6588 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6589 val = tr32(TG3PCI_PCISTATE);
6590 val |= PCISTATE_RETRY_SAME_DMA;
6591 tw32(TG3PCI_PCISTATE, val);
6592 }
6593
6594 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6595 /* Allow reads and writes to the
6596 * APE register and memory space.
6597 */
6598 val = tr32(TG3PCI_PCISTATE);
6599 val |=