1 /*------------------------------------------------------------------------
2 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
3 .
4 . Copyright (C) 1996 by Erik Stahlman
5 . Copyright (C) 2001 Standard Microsystems Corporation
6 . Developed by Simple Network Magic Corporation
7 . Copyright (C) 2003 Monta Vista Software, Inc.
8 . Unified SMC91x driver by Nicolas Pitre
9 .
10 . This program is free software; you can redistribute it and/or modify
11 . it under the terms of the GNU General Public License as published by
12 . the Free Software Foundation; either version 2 of the License, or
13 . (at your option) any later version.
14 .
15 . This program is distributed in the hope that it will be useful,
16 . but WITHOUT ANY WARRANTY; without even the implied warranty of
17 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 . GNU General Public License for more details.
19 .
20 . You should have received a copy of the GNU General Public License
21 . along with this program; if not, write to the Free Software
22 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 .
24 . Information contained in this file was obtained from the LAN91C111
25 . manual from SMC. To get a copy, if you really want one, you can find
26 . information under www.smsc.com.
27 .
28 . Authors
29 . Erik Stahlman <erik@vt.edu>
30 . Daris A Nevil <dnevil@snmc.com>
31 . Nicolas Pitre <nico@cam.org>
32 .
33 ---------------------------------------------------------------------------*/
34 #ifndef _SMC91X_H_
35 #define _SMC91X_H_
36
37
38 /*
39 * Define your architecture specific bus configuration parameters here.
40 */
41
42 #if defined(CONFIG_ARCH_LUBBOCK)
43
44 /* We can only do 16-bit reads and writes in the static memory space. */
45 #define SMC_CAN_USE_8BIT 0
46 #define SMC_CAN_USE_16BIT 1
47 #define SMC_CAN_USE_32BIT 0
48 #define SMC_NOWAIT 1
49
50 /* The first two address lines aren't connected... */
51 #define SMC_IO_SHIFT 2
52
53 #define SMC_inw(a, r) readw((a) + (r))
54 #define SMC_outw(v, a, r) writew(v, (a) + (r))
55 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
56 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
57
58 #elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6)
59
60 /* We can only do 16-bit reads and writes in the static memory space. */
61 #define SMC_CAN_USE_8BIT 0
62 #define SMC_CAN_USE_16BIT 1
63 #define SMC_CAN_USE_32BIT 0
64 #define SMC_NOWAIT 1
65
66 #define SMC_IO_SHIFT 0
67
68 #define SMC_inw(a, r) in_be16((volatile u16 *)((a) + (r)))
69 #define SMC_outw(v, a, r) out_be16((volatile u16 *)((a) + (r)), v)
70 #define SMC_insw(a, r, p, l) \
71 do { \
72 unsigned long __port = (a) + (r); \
73 u16 *__p = (u16 *)(p); \
74 int __l = (l); \
75 insw(__port, __p, __l); \
76 while (__l > 0) { \
77 *__p = swab16(*__p); \
78 __p++; \
79 __l--; \
80 } \
81 } while (0)
82 #define SMC_outsw(a, r, p, l) \
83 do { \
84 unsigned long __port = (a) + (r); \
85 u16 *__p = (u16 *)(p); \
86 int __l = (l); \
87 while (__l > 0) { \
88 /* Believe it or not, the swab isn't needed. */ \
89 outw( /* swab16 */ (*__p++), __port); \
90 __l--; \
91 } \
92 } while (0)
93 #define set_irq_type(irq, type)
94
95 #elif defined(CONFIG_SA1100_PLEB)
96 /* We can only do 16-bit reads and writes in the static memory space. */
97 #define SMC_CAN_USE_8BIT 1
98 #define SMC_CAN_USE_16BIT 1
99 #define SMC_CAN_USE_32BIT 0
100 #define SMC_IO_SHIFT 0
101 #define SMC_NOWAIT 1
102
103 #define SMC_inb(a, r) inb((a) + (r))
104 #define SMC_insb(a, r, p, l) insb((a) + (r), p, (l))
105 #define SMC_inw(a, r) inw((a) + (r))
106 #define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
107 #define SMC_outb(v, a, r) outb(v, (a) + (r))
108 #define SMC_outsb(a, r, p, l) outsb((a) + (r), p, (l))
109 #define SMC_outw(v, a, r) outw(v, (a) + (r))
110 #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
111
112 #define set_irq_type(irq, type) do {} while (0)
113
114 #elif defined(CONFIG_SA1100_ASSABET)
115
116 #include <asm/arch/neponset.h>
117
118 /* We can only do 8-bit reads and writes in the static memory space. */
119 #define SMC_CAN_USE_8BIT 1
120 #define SMC_CAN_USE_16BIT 0
121 #define SMC_CAN_USE_32BIT 0
122 #define SMC_NOWAIT 1
123
124 /* The first two address lines aren't connected... */
125 #define SMC_IO_SHIFT 2
126
127 #define SMC_inb(a, r) readb((a) + (r))
128 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
129 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
130 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
131
132 #elif defined(CONFIG_ARCH_INNOKOM) || \
133 defined(CONFIG_MACH_MAINSTONE) || \
134 defined(CONFIG_ARCH_PXA_IDP) || \
135 defined(CONFIG_ARCH_RAMSES)
136
137 #define SMC_CAN_USE_8BIT 1
138 #define SMC_CAN_USE_16BIT 1
139 #define SMC_CAN_USE_32BIT 1
140 #define SMC_IO_SHIFT 0
141 #define SMC_NOWAIT 1
142 #define SMC_USE_PXA_DMA 1
143
144 #define SMC_inb(a, r) readb((a) + (r))
145 #define SMC_inw(a, r) readw((a) + (r))
146 #define SMC_inl(a, r) readl((a) + (r))
147 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
148 #define SMC_outl(v, a, r) writel(v, (a) + (r))
149 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
150 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
151
152 /* We actually can't write halfwords properly if not word aligned */
153 static inline void
154 SMC_outw(u16 val, unsigned long ioaddr, int reg)
155 {
156 if (reg & 2) {
157 unsigned int v = val << 16;
158 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
159 writel(v, ioaddr + (reg & ~2));
160 } else {
161 writew(val, ioaddr + reg);
162 }
163 }
164
165 #elif defined(CONFIG_ISA)
166
167 #define SMC_CAN_USE_8BIT 1
168 #define SMC_CAN_USE_16BIT 1
169 #define SMC_CAN_USE_32BIT 0
170
171 #define SMC_inb(a, r) inb((a) + (r))
172 #define SMC_inw(a, r) inw((a) + (r))
173 #define SMC_outb(v, a, r) outb(v, (a) + (r))
174 #define SMC_outw(v, a, r) outw(v, (a) + (r))
175 #define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
176 #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
177
178 #elif defined(CONFIG_M32R)
179
180 #define SMC_CAN_USE_8BIT 0
181 #define SMC_CAN_USE_16BIT 1
182 #define SMC_CAN_USE_32BIT 0
183
184 #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000)
185 #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000)
186 #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000)
187 #define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000)
188 #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l)
189 #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l)
190
191 #define set_irq_type(irq, type) do {} while(0)
192
193 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
194 #define RPC_LSB_DEFAULT RPC_LED_100_10
195
196 #elif defined(CONFIG_MACH_LPD7A400) || defined(CONFIG_MACH_LPD7A404)
197
198 /* The LPD7A40X_IOBARRIER is necessary to overcome a mismatch between
199 * the way that the CPU handles chip selects and the way that the SMC
200 * chip expects the chip select to operate. Refer to
201 * Documentation/arm/Sharp-LH/IOBarrier for details. The read from
202 * IOBARRIER is a byte as a least-common denominator of possible
203 * regions to use as the barrier. It would be wasteful to read 32
204 * bits from a byte oriented region.
205 *
206 * There is no explicit protection against interrupts intervening
207 * between the writew and the IOBARRIER. In SMC ISR there is a
208 * preamble that performs an IOBARRIER in the extremely unlikely event
209 * that the driver interrupts itself between a writew to the chip an
210 * the IOBARRIER that follows *and* the cache is large enough that the
211 * first off-chip access while handing the interrupt is to the SMC
212 * chip. Other devices in the same address space as the SMC chip must
213 * be aware of the potential for trouble and perform a similar
214 * IOBARRIER on entry to their ISR.
215 */
216
217 #include <asm/arch/constants.h> /* IOBARRIER_VIRT */
218
219 #define SMC_CAN_USE_8BIT 0
220 #define SMC_CAN_USE_16BIT 1
221 #define SMC_CAN_USE_32BIT 0
222 #define SMC_NOWAIT 0
223 #define LPD7A40X_IOBARRIER readb (IOBARRIER_VIRT)
224
225 #define SMC_inw(a,r) readw ((void*) ((a) + (r)))
226 #define SMC_insw(a,r,p,l) readsw ((void*) ((a) + (r)), p, l)
227 #define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7A40X_IOBARRIER; })
228
229 static inline void SMC_outsw (unsigned long a, int r, unsigned char* p, int l)
230 {
231 unsigned short* ps = (unsigned short*) p;
232 while (l-- > 0) {
233 writew (*ps++, a + r);
234 LPD7A40X_IOBARRIER;
235 }
236 }
237
238 #define SMC_INTERRUPT_PREAMBLE LPD7A40X_IOBARRIER
239
240 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
241 #define RPC_LSB_DEFAULT RPC_LED_100_10
242
243 #else
244
245 #define SMC_CAN_USE_8BIT 1
246 #define SMC_CAN_USE_16BIT 1
247 #define SMC_CAN_USE_32BIT 1
248 #define SMC_NOWAIT 1
249
250 #define SMC_inb(a, r) readb((a) + (r))
251 #define SMC_inw(a, r) readw((a) + (r))
252 #define SMC_inl(a, r) readl((a) + (r))
253 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
254 #define SMC_outw(v, a, r) writew(v, (a) + (r))
255 #define SMC_outl(v, a, r) writel(v, (a) + (r))
256 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
257 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
258
259 #define RPC_LSA_DEFAULT RPC_LED_100_10
260 #define RPC_LSB_DEFAULT RPC_LED_TX_RX
261
262 #endif
263
264
265 #ifdef SMC_USE_PXA_DMA
266 /*
267 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
268 * always happening in irq context so no need to worry about races. TX is
269 * different and probably not worth it for that reason, and not as critical
270 * as RX which can overrun memory and lose packets.
271 */
272 #include <linux/dma-mapping.h>
273 #include <asm/dma.h>
274 #include <asm/arch/pxa-regs.h>
275
276 #ifdef SMC_insl
277 #undef SMC_insl
278 #define SMC_insl(a, r, p, l) \
279 smc_pxa_dma_insl(a, lp->physaddr, r, dev->dma, p, l)
280 static inline void
281 smc_pxa_dma_insl(u_long ioaddr, u_long physaddr, int reg, int dma,
282 u_char *buf, int len)
283 {
284 dma_addr_t dmabuf;
285
286 /* fallback if no DMA available */
287 if (dma == (unsigned char)-1) {
288 readsl(ioaddr + reg, buf, len);
289 return;
290 }
291
292 /* 64 bit alignment is required for memory to memory DMA */
293 if ((long)buf & 4) {
294 *((u32 *)buf) = SMC_inl(ioaddr, reg);
295 buf += 4;
296 len--;
297 }
298
299 len *= 4;
300 dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE);
301 DCSR(dma) = DCSR_NODESC;
302 DTADR(dma) = dmabuf;
303 DSADR(dma) = physaddr + reg;
304 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
305 DCMD_WIDTH4 | (DCMD_LENGTH & len));
306 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
307 while (!(DCSR(dma) & DCSR_STOPSTATE))
308 cpu_relax();
309 DCSR(dma) = 0;
310 dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE);
311 }
312 #endif
313
314 #ifdef SMC_insw
315 #undef SMC_insw
316 #define SMC_insw(a, r, p, l) \
317 smc_pxa_dma_insw(a, lp->physaddr, r, dev->dma, p, l)
318 static inline void
319 smc_pxa_dma_insw(u_long ioaddr, u_long physaddr, int reg, int dma,
320 u_char *buf, int len)
321 {
322 dma_addr_t dmabuf;
323
324 /* fallback if no DMA available */
325 if (dma == (unsigned char)-1) {
326 readsw(ioaddr + reg, buf, len);
327 return;
328 }
329
330 /* 64 bit alignment is required for memory to memory DMA */
331 while ((long)buf & 6) {
332 *((u16 *)buf) = SMC_inw(ioaddr, reg);
333 buf += 2;
334 len--;
335 }
336
337 len *= 2;
338 dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE);
339 DCSR(dma) = DCSR_NODESC;
340 DTADR(dma) = dmabuf;
341 DSADR(dma) = physaddr + reg;
342 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
343 DCMD_WIDTH2 | (DCMD_LENGTH & len));
344 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
345 while (!(DCSR(dma) & DCSR_STOPSTATE))
346 cpu_relax();
347 DCSR(dma) = 0;
348 dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE);
349 }
350 #endif
351
352 static void
353 smc_pxa_dma_irq(int dma, void *dummy, struct pt_regs *regs)
354 {
355 DCSR(dma) = 0;
356 }
357 #endif /* SMC_USE_PXA_DMA */
358
359
360 /* Because of bank switching, the LAN91x uses only 16 I/O ports */
361 #ifndef SMC_IO_SHIFT
362 #define SMC_IO_SHIFT 0
363 #endif
364 #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT)
365
366
367 /*
368 . Bank Select Register:
369 .
370 . yyyy yyyy 0000 00xx
371 . xx = bank number
372 . yyyy yyyy = 0x33, for identification purposes.
373 */
374 #define BANK_SELECT (14 << SMC_IO_SHIFT)
375
376
377 // Transmit Control Register
378 /* BANK 0 */
379 #define TCR_REG SMC_REG(0x0000, 0)
380 #define TCR_ENABLE 0x0001 // When 1 we can transmit
381 #define TCR_LOOP 0x0002 // Controls output pin LBK
382 #define TCR_FORCOL 0x0004 // When 1 will force a collision
383 #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
384 #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
385 #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
386 #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
387 #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
388 #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
389 #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
390
391 #define TCR_CLEAR 0 /* do NOTHING */
392 /* the default settings for the TCR register : */
393 #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN)
394
395
396 // EPH Status Register
397 /* BANK 0 */
398 #define EPH_STATUS_REG SMC_REG(0x0002, 0)
399 #define ES_TX_SUC 0x0001 // Last TX was successful
400 #define ES_SNGL_COL 0x0002 // Single collision detected for last tx
401 #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
402 #define ES_LTX_MULT 0x0008 // Last tx was a multicast
403 #define ES_16COL 0x0010 // 16 Collisions Reached
404 #define ES_SQET 0x0020 // Signal Quality Error Test
405 #define ES_LTXBRD 0x0040 // Last tx was a broadcast
406 #define ES_TXDEFR 0x0080 // Transmit Deferred
407 #define ES_LATCOL 0x0200 // Late collision detected on last tx
408 #define ES_LOSTCARR 0x0400 // Lost Carrier Sense
409 #define ES_EXC_DEF 0x0800 // Excessive Deferral
410 #define ES_CTR_ROL 0x1000 // Counter Roll Over indication
411 #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
412 #define ES_TXUNRN 0x8000 // Tx Underrun
413
414
415 // Receive Control Register
416 /* BANK 0 */
417 #define RCR_REG SMC_REG(0x0004, 0)
418 #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
419 #define RCR_PRMS 0x0002 // Enable promiscuous mode
420 #define RCR_ALMUL 0x0004 // When set accepts all multicast frames
421 #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
422 #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
423 #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
424 #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
425 #define RCR_SOFTRST 0x8000 // resets the chip
426
427 /* the normal settings for the RCR register : */
428 #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
429 #define RCR_CLEAR 0x0 // set it to a base state
430
431
432 // Counter Register
433 /* BANK 0 */
434 #define COUNTER_REG SMC_REG(0x0006, 0)
435
436
437 // Memory Information Register
438 /* BANK 0 */
439 #define MIR_REG SMC_REG(0x0008, 0)
440
441
442 // Receive/Phy Control Register
443 /* BANK 0 */
444 #define RPC_REG SMC_REG(0x000A, 0)
445 #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
446 #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
447 #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
448 #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
449 #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
450 #define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect
451 #define RPC_LED_RES (0x01) // LED = Reserved
452 #define RPC_LED_10 (0x02) // LED = 10Mbps link detect
453 #define RPC_LED_FD (0x03) // LED = Full Duplex Mode
454 #define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred
455 #define RPC_LED_100 (0x05) // LED = 100Mbps link dectect
456 #define RPC_LED_TX (0x06) // LED = TX packet occurred
457 #define RPC_LED_RX (0x07) // LED = RX packet occurred
458
459 #ifndef RPC_LSA_DEFAULT
460 #define RPC_LSA_DEFAULT RPC_LED_100
461 #endif
462 #ifndef RPC_LSB_DEFAULT
463 #define RPC_LSB_DEFAULT RPC_LED_FD
464 #endif
465
466 #define RPC_DEFAULT (RPC_ANEG | (RPC_LSA_DEFAULT << RPC_LSXA_SHFT) | (RPC_LSB_DEFAULT << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
467
468
469 /* Bank 0 0x0C is reserved */
470
471 // Bank Select Register
472 /* All Banks */
473 #define BSR_REG 0x000E
474
475
476 // Configuration Reg
477 /* BANK 1 */
478 #define CONFIG_REG SMC_REG(0x0000, 1)
479 #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
480 #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
481 #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
482 #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
483
484 // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
485 #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
486
487
488 // Base Address Register
489 /* BANK 1 */
490 #define BASE_REG SMC_REG(0x0002, 1)
491
492
493 // Individual Address Registers
494 /* BANK 1 */
495 #define ADDR0_REG SMC_REG(0x0004, 1)
496 #define ADDR1_REG SMC_REG(0x0006, 1)
497 #define ADDR2_REG SMC_REG(0x0008, 1)
498
499
500 // General Purpose Register
501 /* BANK 1 */
502 #define GP_REG SMC_REG(0x000A, 1)
503
504
505 // Control Register
506 /* BANK 1 */
507 #define CTL_REG SMC_REG(0x000C, 1)
508 #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
509 #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
510 #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
511 #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
512 #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
513 #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
514 #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
515 #define CTL_STORE 0x0001 // When set stores registers into EEPROM
516
517
518 // MMU Command Register
519 /* BANK 2 */
520 #define MMU_CMD_REG SMC_REG(0x0000, 2)
521 #define MC_BUSY 1 // When 1 the last release has not completed
522 #define MC_NOP (0<<5) // No Op
523 #define MC_ALLOC (1<<5) // OR with number of 256 byte packets
524 #define MC_RESET (2<<5) // Reset MMU to initial state
525 #define MC_REMOVE (3<<5) // Remove the current rx packet
526 #define MC_RELEASE (4<<5) // Remove and release the current rx packet
527 #define MC_FREEPKT (5<<5) // Release packet in PNR register
528 #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
529 #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
530
531
532 // Packet Number Register
533 /* BANK 2 */
534 #define PN_REG SMC_REG(0x0002, 2)
535
536
537 // Allocation Result Register
538 /* BANK 2 */
539 #define AR_REG SMC_REG(0x0003, 2)
540 #define AR_FAILED 0x80 // Alocation Failed
541
542
543 // TX FIFO Ports Register
544 /* BANK 2 */
545 #define TXFIFO_REG SMC_REG(0x0004, 2)
546 #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
547
548 // RX FIFO Ports Register
549 /* BANK 2 */
550 #define RXFIFO_REG SMC_REG(0x0005, 2)
551 #define RXFIFO_REMPTY 0x80 // RX FIFO Empty
552
553 #define FIFO_REG SMC_REG(0x0004, 2)
554
555 // Pointer Register
556 /* BANK 2 */
557 #define PTR_REG SMC_REG(0x0006, 2)
558 #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
559 #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
560 #define PTR_READ 0x2000 // When 1 the operation is a read
561
562
563 // Data Register
564 /* BANK 2 */
565 #define DATA_REG SMC_REG(0x0008, 2)
566
567
568 // Interrupt Status/Acknowledge Register
569 /* BANK 2 */
570 #define INT_REG SMC_REG(0x000C, 2)
571
572
573 // Interrupt Mask Register
574 /* BANK 2 */
575 #define IM_REG SMC_REG(0x000D, 2)
576 #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
577 #define IM_ERCV_INT 0x40 // Early Receive Interrupt
578 #define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
579 #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
580 #define IM_ALLOC_INT 0x08 // Set when allocation request is completed
581 #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
582 #define IM_TX_INT 0x02 // Transmit Interrupt
583 #define IM_RCV_INT 0x01 // Receive Interrupt
584
585
586 // Multicast Table Registers
587 /* BANK 3 */
588 #define MCAST_REG1 SMC_REG(0x0000, 3)
589 #define MCAST_REG2 SMC_REG(0x0002, 3)
590 #define MCAST_REG3 SMC_REG(0x0004, 3)
591 #define MCAST_REG4 SMC_REG(0x0006, 3)
592
593
594 // Management Interface Register (MII)
595 /* BANK 3 */
596 #define MII_REG SMC_REG(0x0008, 3)
597 #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
598 #define MII_MDOE 0x0008 // MII Output Enable
599 #define MII_MCLK 0x0004 // MII Clock, pin MDCLK
600 #define MII_MDI 0x0002 // MII Input, pin MDI
601 #define MII_MDO 0x0001 // MII Output, pin MDO
602
603
604 // Revision Register
605 /* BANK 3 */
606 /* ( hi: chip id low: rev # ) */
607 #define REV_REG SMC_REG(0x000A, 3)
608
609
610 // Early RCV Register
611 /* BANK 3 */
612 /* this is NOT on SMC9192 */
613 #define ERCV_REG SMC_REG(0x000C, 3)
614 #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
615 #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
616
617
618 // External Register
619 /* BANK 7 */
620 #define EXT_REG SMC_REG(0x0000, 7)
621
622
623 #define CHIP_9192 3
624 #define CHIP_9194 4
625 #define CHIP_9195 5
626 #define CHIP_9196 6
627 #define CHIP_91100 7
628 #define CHIP_91100FD 8
629 #define CHIP_91111FD 9
630
631 static const char * chip_ids[ 16 ] = {
632 NULL, NULL, NULL,
633 /* 3 */ "SMC91C90/91C92",
634 /* 4 */ "SMC91C94",
635 /* 5 */ "SMC91C95",
636 /* 6 */ "SMC91C96",
637 /* 7 */ "SMC91C100",
638 /* 8 */ "SMC91C100FD",
639 /* 9 */ "SMC91C11xFD",
640 NULL, NULL, NULL,
641 NULL, NULL, NULL};
642
643
644 /*
645 . Transmit status bits
646 */
647 #define TS_SUCCESS 0x0001
648 #define TS_LOSTCAR 0x0400
649 #define TS_LATCOL 0x0200
650 #define TS_16COL 0x0010
651
652 /*
653 . Receive status bits
654 */
655 #define RS_ALGNERR 0x8000
656 #define RS_BRODCAST 0x4000
657 #define RS_BADCRC 0x2000
658 #define RS_ODDFRAME 0x1000
659 #define RS_TOOLONG 0x0800
660 #define RS_TOOSHORT 0x0400
661 #define RS_MULTICAST 0x0001
662 #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
663
664
665 /*
666 * PHY IDs
667 * LAN83C183 == LAN91C111 Internal PHY
668 */
669 #define PHY_LAN83C183 0x0016f840
670 #define PHY_LAN83C180 0x02821c50
671
672 /*
673 * PHY Register Addresses (LAN91C111 Internal PHY)
674 *
675 * Generic PHY registers can be found in <linux/mii.h>
676 *
677 * These phy registers are specific to our on-board phy.
678 */
679
680 // PHY Configuration Register 1
681 #define PHY_CFG1_REG 0x10
682 #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
683 #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
684 #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
685 #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
686 #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
687 #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
688 #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
689 #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
690 #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
691 #define PHY_CFG1_TLVL_MASK 0x003C
692 #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
693
694
695 // PHY Configuration Register 2
696 #define PHY_CFG2_REG 0x11
697 #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
698 #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
699 #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
700 #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
701
702 // PHY Status Output (and Interrupt status) Register
703 #define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
704 #define PHY_INT_INT 0x8000 // 1=bits have changed since last read
705 #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
706 #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
707 #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
708 #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
709 #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
710 #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
711 #define PHY_INT_JAB 0x0100 // 1=Jabber detected
712 #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
713 #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
714
715 // PHY Interrupt/Status Mask Register
716 #define PHY_MASK_REG 0x13 // Interrupt Mask
717 // Uses the same bit definitions as PHY_INT_REG
718
719
720 /*
721 * SMC91C96 ethernet config and status registers.
722 * These are in the "attribute" space.
723 */
724 #define ECOR 0x8000
725 #define ECOR_RESET 0x80
726 #define ECOR_LEVEL_IRQ 0x40
727 #define ECOR_WR_ATTRIB 0x04
728 #define ECOR_ENABLE 0x01
729
730 #define ECSR 0x8002
731 #define ECSR_IOIS8 0x20
732 #define ECSR_PWRDWN 0x04
733 #define ECSR_INT 0x02
734
735 #define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT)
736
737
738 /*
739 * Macros to abstract register access according to the data bus
740 * capabilities. Please use those and not the in/out primitives.
741 * Note: the following macros do *not* select the bank -- this must
742 * be done separately as needed in the main code. The SMC_REG() macro
743 * only uses the bank argument for debugging purposes (when enabled).
744 */
745
746 #if SMC_DEBUG > 0
747 #define SMC_REG(reg, bank) \
748 ({ \
749 int __b = SMC_CURRENT_BANK(); \
750 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \
751 printk( "%s: bank reg screwed (0x%04x)\n", \
752 CARDNAME, __b ); \
753 BUG(); \
754 } \
755 reg<<SMC_IO_SHIFT; \
756 })
757 #else
758 #define SMC_REG(reg, bank) (reg<<SMC_IO_SHIFT)
759 #endif
760
761 #if SMC_CAN_USE_8BIT
762 #define SMC_GET_PN() SMC_inb( ioaddr, PN_REG )
763 #define SMC_SET_PN(x) SMC_outb( x, ioaddr, PN_REG )
764 #define SMC_GET_AR() SMC_inb( ioaddr, AR_REG )
765 #define SMC_GET_TXFIFO() SMC_inb( ioaddr, TXFIFO_REG )
766 #define SMC_GET_RXFIFO() SMC_inb( ioaddr, RXFIFO_REG )
767 #define SMC_GET_INT() SMC_inb( ioaddr, INT_REG )
768 #define SMC_ACK_INT(x) SMC_outb( x, ioaddr, INT_REG )
769 #define SMC_GET_INT_MASK() SMC_inb( ioaddr, IM_REG )
770 #define SMC_SET_INT_MASK(x) SMC_outb( x, ioaddr, IM_REG )
771 #else
772 #define SMC_GET_PN() (SMC_inw( ioaddr, PN_REG ) & 0xFF)
773 #define SMC_SET_PN(x) SMC_outw( x, ioaddr, PN_REG )
774 #define SMC_GET_AR() (SMC_inw( ioaddr, PN_REG ) >> 8)
775 #define SMC_GET_TXFIFO() (SMC_inw( ioaddr, TXFIFO_REG ) & 0xFF)
776 #define SMC_GET_RXFIFO() (SMC_inw( ioaddr, TXFIFO_REG ) >> 8)
777 #define SMC_GET_INT() (SMC_inw( ioaddr, INT_REG ) & 0xFF)
778 #define SMC_ACK_INT(x) \
779 do { \
780 unsigned long __flags; \
781 int __mask; \
782 local_irq_save(__flags); \
783 __mask = SMC_inw( ioaddr, INT_REG ) & ~0xff; \
784 SMC_outw( __mask | (x), ioaddr, INT_REG ); \
785 local_irq_restore(__flags); \
786 } while (0)
787 #define SMC_GET_INT_MASK() (SMC_inw( ioaddr, INT_REG ) >> 8)
788 #define SMC_SET_INT_MASK(x) SMC_outw( (x) << 8, ioaddr, INT_REG )
789 #endif
790
791 #define SMC_CURRENT_BANK() SMC_inw( ioaddr, BANK_SELECT )
792 #define SMC_SELECT_BANK(x) SMC_outw( x, ioaddr, BANK_SELECT )
793 #define SMC_GET_BASE() SMC_inw( ioaddr, BASE_REG )
794 #define SMC_SET_BASE(x) SMC_outw( x, ioaddr, BASE_REG )
795 #define SMC_GET_CONFIG() SMC_inw( ioaddr, CONFIG_REG )
796 #define SMC_SET_CONFIG(x) SMC_outw( x, ioaddr, CONFIG_REG )
797 #define SMC_GET_COUNTER() SMC_inw( ioaddr, COUNTER_REG )
798 #define SMC_GET_CTL() SMC_inw( ioaddr, CTL_REG )
799 #define SMC_SET_CTL(x) SMC_outw( x, ioaddr, CTL_REG )
800 #define SMC_GET_MII() SMC_inw( ioaddr, MII_REG )
801 #define SMC_SET_MII(x) SMC_outw( x, ioaddr, MII_REG )
802 #define SMC_GET_MIR() SMC_inw( ioaddr, MIR_REG )
803 #define SMC_SET_MIR(x) SMC_outw( x, ioaddr, MIR_REG )
804 #define SMC_GET_MMU_CMD() SMC_inw( ioaddr, MMU_CMD_REG )
805 #define SMC_SET_MMU_CMD(x) SMC_outw( x, ioaddr, MMU_CMD_REG )
806 #define SMC_GET_FIFO() SMC_inw( ioaddr, FIFO_REG )
807 #define SMC_GET_PTR() SMC_inw( ioaddr, PTR_REG )
808 #define SMC_SET_PTR(x) SMC_outw( x, ioaddr, PTR_REG )
809 #define SMC_GET_RCR() SMC_inw( ioaddr, RCR_REG )
810 #define SMC_SET_RCR(x) SMC_outw( x, ioaddr, RCR_REG )
811 #define SMC_GET_REV() SMC_inw( ioaddr, REV_REG )
812 #define SMC_GET_RPC() SMC_inw( ioaddr, RPC_REG )
813 #define SMC_SET_RPC(x) SMC_outw( x, ioaddr, RPC_REG )
814 #define SMC_GET_TCR() SMC_inw( ioaddr, TCR_REG )
815 #define SMC_SET_TCR(x) SMC_outw( x, ioaddr, TCR_REG )
816
817 #ifndef SMC_GET_MAC_ADDR
818 #define SMC_GET_MAC_ADDR(addr) \
819 do { \
820 unsigned int __v; \
821 __v = SMC_inw( ioaddr, ADDR0_REG ); \
822 addr[0] = __v; addr[1] = __v >> 8; \
823 __v = SMC_inw( ioaddr, ADDR1_REG ); \
824 addr[2] = __v; addr[3] = __v >> 8; \
825 __v = SMC_inw( ioaddr, ADDR2_REG ); \
826 addr[4] = __v; addr[5] = __v >> 8; \
827 } while (0)
828 #endif
829
830 #define SMC_SET_MAC_ADDR(addr) \
831 do { \
832 SMC_outw( addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG ); \
833 SMC_outw( addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG ); \
834 SMC_outw( addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG ); \
835 } while (0)
836
837 #define SMC_SET_MCAST(x) \
838 do { \
839 const unsigned char *mt = (x); \
840 SMC_outw( mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1 ); \
841 SMC_outw( mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2 ); \
842 SMC_outw( mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3 ); \
843 SMC_outw( mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4 ); \
844 } while (0)
845
846 #if SMC_CAN_USE_32BIT
847 /*
848 * Some setups just can't write 8 or 16 bits reliably when not aligned
849 * to a 32 bit boundary. I tell you that exists!
850 * We re-do the ones here that can be easily worked around if they can have
851 * their low parts written to 0 without adverse effects.
852 */
853 #undef SMC_SELECT_BANK
854 #define SMC_SELECT_BANK(x) SMC_outl( (x)<<16, ioaddr, 12<<SMC_IO_SHIFT )
855 #undef SMC_SET_RPC
856 #define SMC_SET_RPC(x) SMC_outl( (x)<<16, ioaddr, SMC_REG(8, 0) )
857 #undef SMC_SET_PN
858 #define SMC_SET_PN(x) SMC_outl( (x)<<16, ioaddr, SMC_REG(0, 2) )
859 #undef SMC_SET_PTR
860 #define SMC_SET_PTR(x) SMC_outl( (x)<<16, ioaddr, SMC_REG(4, 2) )
861 #endif
862
863 #if SMC_CAN_USE_32BIT
864 #define SMC_PUT_PKT_HDR(status, length) \
865 SMC_outl( (status) | (length) << 16, ioaddr, DATA_REG )
866 #define SMC_GET_PKT_HDR(status, length) \
867 do { \
868 unsigned int __val = SMC_inl( ioaddr, DATA_REG ); \
869 (status) = __val & 0xffff; \
870 (length) = __val >> 16; \
871 } while (0)
872 #else
873 #define SMC_PUT_PKT_HDR(status, length) \
874 do { \
875 SMC_outw( status, ioaddr, DATA_REG ); \
876 SMC_outw( length, ioaddr, DATA_REG ); \
877 } while (0)
878 #define SMC_GET_PKT_HDR(status, length) \
879 do { \
880 (status) = SMC_inw( ioaddr, DATA_REG ); \
881 (length) = SMC_inw( ioaddr, DATA_REG ); \
882 } while (0)
883 #endif
884
885 #if SMC_CAN_USE_32BIT
886 #define SMC_PUSH_DATA(p, l) \
887 do { \
888 char *__ptr = (p); \
889 int __len = (l); \
890 if (__len >= 2 && (unsigned long)__ptr & 2) { \
891 __len -= 2; \
892 SMC_outw( *(u16 *)__ptr, ioaddr, DATA_REG ); \
893 __ptr += 2; \
894 } \
895 SMC_outsl( ioaddr, DATA_REG, __ptr, __len >> 2); \
896 if (__len & 2) { \
897 __ptr += (__len & ~3); \
898 SMC_outw( *((u16 *)__ptr), ioaddr, DATA_REG ); \
899 } \
900 } while (0)
901 #define SMC_PULL_DATA(p, l) \
902 do { \
903 char *__ptr = (p); \
904 int __len = (l); \
905 if ((unsigned long)__ptr & 2) { \
906 /* \
907 * We want 32bit alignment here. \
908 * Since some buses perform a full 32bit \
909 * fetch even for 16bit data we can't use \
910 * SMC_inw() here. Back both source (on chip \
911 * and destination) pointers of 2 bytes. \
912 */ \
913 __ptr -= 2; \
914 __len += 2; \
915 SMC_SET_PTR( 2|PTR_READ|PTR_RCV|PTR_AUTOINC ); \
916 } \
917 __len += 2; \
918 SMC_insl( ioaddr, DATA_REG, __ptr, __len >> 2); \
919 } while (0)
920 #elif SMC_CAN_USE_16BIT
921 #define SMC_PUSH_DATA(p, l) SMC_outsw( ioaddr, DATA_REG, p, (l) >> 1 )
922 #define SMC_PULL_DATA(p, l) SMC_insw ( ioaddr, DATA_REG, p, (l) >> 1 )
923 #elif SMC_CAN_USE_8BIT
924 #define SMC_PUSH_DATA(p, l) SMC_outsb( ioaddr, DATA_REG, p, l )
925 #define SMC_PULL_DATA(p, l) SMC_insb ( ioaddr, DATA_REG, p, l )
926 #endif
927
928 #if ! SMC_CAN_USE_16BIT
929 #define SMC_outw(x, ioaddr, reg) \
930 do { \
931 unsigned int __val16 = (x); \
932 SMC_outb( __val16, ioaddr, reg ); \
933 SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\
934 } while (0)
935 #define SMC_inw(ioaddr, reg) \
936 ({ \
937 unsigned int __val16; \
938 __val16 = SMC_inb( ioaddr, reg ); \
939 __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \
940 __val16; \
941 })
942 #endif
943
944 #if !defined (SMC_INTERRUPT_PREAMBLE)
945 # define SMC_INTERRUPT_PREAMBLE
946 #endif
947
948 #endif /* _SMC91X_H_ */
949
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