1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/netdevice.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/etherdevice.h>
31 #include <linux/ethtool.h>
32 #include <linux/pci.h>
33 #include <linux/ip.h>
34 #include <net/ip.h>
35 #include <linux/tcp.h>
36 #include <linux/in.h>
37 #include <linux/delay.h>
38 #include <linux/workqueue.h>
39 #include <linux/if_vlan.h>
40 #include <linux/prefetch.h>
41 #include <linux/debugfs.h>
42 #include <linux/mii.h>
43
44 #include <asm/irq.h>
45
46 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47 #define SKY2_VLAN_TAG_USED 1
48 #endif
49
50 #include "sky2.h"
51
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.23"
54 #define PFX DRV_NAME " "
55
56 /*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
59 * similar to Tigon3.
60 */
61
62 #define RX_LE_SIZE 1024
63 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
64 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
65 #define RX_DEF_PENDING RX_MAX_PENDING
66
67 #define TX_RING_SIZE 512
68 #define TX_DEF_PENDING 128
69 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
70 #define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
71
72 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
73 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
74 #define TX_WATCHDOG (5 * HZ)
75 #define NAPI_WEIGHT 64
76 #define PHY_RETRIES 1000
77
78 #define SKY2_EEPROM_MAGIC 0x9955aabb
79
80
81 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
82
83 static const u32 default_msg =
84 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
85 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
86 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
87
88 static int debug = -1; /* defaults above */
89 module_param(debug, int, 0);
90 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
91
92 static int copybreak __read_mostly = 128;
93 module_param(copybreak, int, 0);
94 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
95
96 static int disable_msi = 0;
97 module_param(disable_msi, int, 0);
98 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
99
100 static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
101 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
103 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
140 { 0 }
141 };
142
143 MODULE_DEVICE_TABLE(pci, sky2_id_table);
144
145 /* Avoid conditionals by using array */
146 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
147 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
148 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
149
150 static void sky2_set_multicast(struct net_device *dev);
151
152 /* Access to PHY via serial interconnect */
153 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
154 {
155 int i;
156
157 gma_write16(hw, port, GM_SMI_DATA, val);
158 gma_write16(hw, port, GM_SMI_CTRL,
159 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
160
161 for (i = 0; i < PHY_RETRIES; i++) {
162 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
163 if (ctrl == 0xffff)
164 goto io_error;
165
166 if (!(ctrl & GM_SMI_CT_BUSY))
167 return 0;
168
169 udelay(10);
170 }
171
172 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
173 return -ETIMEDOUT;
174
175 io_error:
176 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
177 return -EIO;
178 }
179
180 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
181 {
182 int i;
183
184 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
185 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
186
187 for (i = 0; i < PHY_RETRIES; i++) {
188 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
189 if (ctrl == 0xffff)
190 goto io_error;
191
192 if (ctrl & GM_SMI_CT_RD_VAL) {
193 *val = gma_read16(hw, port, GM_SMI_DATA);
194 return 0;
195 }
196
197 udelay(10);
198 }
199
200 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
201 return -ETIMEDOUT;
202 io_error:
203 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
204 return -EIO;
205 }
206
207 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
208 {
209 u16 v;
210 __gm_phy_read(hw, port, reg, &v);
211 return v;
212 }
213
214
215 static void sky2_power_on(struct sky2_hw *hw)
216 {
217 /* switch power to VCC (WA for VAUX problem) */
218 sky2_write8(hw, B0_POWER_CTRL,
219 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
220
221 /* disable Core Clock Division, */
222 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
223
224 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
225 /* enable bits are inverted */
226 sky2_write8(hw, B2_Y2_CLK_GATE,
227 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
228 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
229 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
230 else
231 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
232
233 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
234 u32 reg;
235
236 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
237
238 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
239 /* set all bits to 0 except bits 15..12 and 8 */
240 reg &= P_ASPM_CONTROL_MSK;
241 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
242
243 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
244 /* set all bits to 0 except bits 28 & 27 */
245 reg &= P_CTL_TIM_VMAIN_AV_MSK;
246 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
247
248 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
249
250 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
251 reg = sky2_read32(hw, B2_GP_IO);
252 reg |= GLB_GPIO_STAT_RACE_DIS;
253 sky2_write32(hw, B2_GP_IO, reg);
254
255 sky2_read32(hw, B2_GP_IO);
256 }
257 }
258
259 static void sky2_power_aux(struct sky2_hw *hw)
260 {
261 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
262 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
263 else
264 /* enable bits are inverted */
265 sky2_write8(hw, B2_Y2_CLK_GATE,
266 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
267 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
268 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
269
270 /* switch power to VAUX */
271 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
272 sky2_write8(hw, B0_POWER_CTRL,
273 (PC_VAUX_ENA | PC_VCC_ENA |
274 PC_VAUX_ON | PC_VCC_OFF));
275 }
276
277 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
278 {
279 u16 reg;
280
281 /* disable all GMAC IRQ's */
282 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
283
284 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
285 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
286 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
287 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
288
289 reg = gma_read16(hw, port, GM_RX_CTRL);
290 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
291 gma_write16(hw, port, GM_RX_CTRL, reg);
292 }
293
294 /* flow control to advertise bits */
295 static const u16 copper_fc_adv[] = {
296 [FC_NONE] = 0,
297 [FC_TX] = PHY_M_AN_ASP,
298 [FC_RX] = PHY_M_AN_PC,
299 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
300 };
301
302 /* flow control to advertise bits when using 1000BaseX */
303 static const u16 fiber_fc_adv[] = {
304 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
305 [FC_TX] = PHY_M_P_ASYM_MD_X,
306 [FC_RX] = PHY_M_P_SYM_MD_X,
307 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
308 };
309
310 /* flow control to GMA disable bits */
311 static const u16 gm_fc_disable[] = {
312 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
313 [FC_TX] = GM_GPCR_FC_RX_DIS,
314 [FC_RX] = GM_GPCR_FC_TX_DIS,
315 [FC_BOTH] = 0,
316 };
317
318
319 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
320 {
321 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
322 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
323
324 if (sky2->autoneg == AUTONEG_ENABLE &&
325 !(hw->flags & SKY2_HW_NEWER_PHY)) {
326 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
327
328 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
329 PHY_M_EC_MAC_S_MSK);
330 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
331
332 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
333 if (hw->chip_id == CHIP_ID_YUKON_EC)
334 /* set downshift counter to 3x and enable downshift */
335 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
336 else
337 /* set master & slave downshift counter to 1x */
338 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
339
340 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
341 }
342
343 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
344 if (sky2_is_copper(hw)) {
345 if (!(hw->flags & SKY2_HW_GIGABIT)) {
346 /* enable automatic crossover */
347 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
348
349 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
350 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
351 u16 spec;
352
353 /* Enable Class A driver for FE+ A0 */
354 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
355 spec |= PHY_M_FESC_SEL_CL_A;
356 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
357 }
358 } else {
359 /* disable energy detect */
360 ctrl &= ~PHY_M_PC_EN_DET_MSK;
361
362 /* enable automatic crossover */
363 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
364
365 /* downshift on PHY 88E1112 and 88E1149 is changed */
366 if (sky2->autoneg == AUTONEG_ENABLE
367 && (hw->flags & SKY2_HW_NEWER_PHY)) {
368 /* set downshift counter to 3x and enable downshift */
369 ctrl &= ~PHY_M_PC_DSC_MSK;
370 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
371 }
372 }
373 } else {
374 /* workaround for deviation #4.88 (CRC errors) */
375 /* disable Automatic Crossover */
376
377 ctrl &= ~PHY_M_PC_MDIX_MSK;
378 }
379
380 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
381
382 /* special setup for PHY 88E1112 Fiber */
383 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
384 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
385
386 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
387 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
388 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
389 ctrl &= ~PHY_M_MAC_MD_MSK;
390 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
391 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
392
393 if (hw->pmd_type == 'P') {
394 /* select page 1 to access Fiber registers */
395 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
396
397 /* for SFP-module set SIGDET polarity to low */
398 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
399 ctrl |= PHY_M_FIB_SIGD_POL;
400 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
401 }
402
403 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
404 }
405
406 ctrl = PHY_CT_RESET;
407 ct1000 = 0;
408 adv = PHY_AN_CSMA;
409 reg = 0;
410
411 if (sky2->autoneg == AUTONEG_ENABLE) {
412 if (sky2_is_copper(hw)) {
413 if (sky2->advertising & ADVERTISED_1000baseT_Full)
414 ct1000 |= PHY_M_1000C_AFD;
415 if (sky2->advertising & ADVERTISED_1000baseT_Half)
416 ct1000 |= PHY_M_1000C_AHD;
417 if (sky2->advertising & ADVERTISED_100baseT_Full)
418 adv |= PHY_M_AN_100_FD;
419 if (sky2->advertising & ADVERTISED_100baseT_Half)
420 adv |= PHY_M_AN_100_HD;
421 if (sky2->advertising & ADVERTISED_10baseT_Full)
422 adv |= PHY_M_AN_10_FD;
423 if (sky2->advertising & ADVERTISED_10baseT_Half)
424 adv |= PHY_M_AN_10_HD;
425
426 adv |= copper_fc_adv[sky2->flow_mode];
427 } else { /* special defines for FIBER (88E1040S only) */
428 if (sky2->advertising & ADVERTISED_1000baseT_Full)
429 adv |= PHY_M_AN_1000X_AFD;
430 if (sky2->advertising & ADVERTISED_1000baseT_Half)
431 adv |= PHY_M_AN_1000X_AHD;
432
433 adv |= fiber_fc_adv[sky2->flow_mode];
434 }
435
436 /* Restart Auto-negotiation */
437 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
438 } else {
439 /* forced speed/duplex settings */
440 ct1000 = PHY_M_1000C_MSE;
441
442 /* Disable auto update for duplex flow control and speed */
443 reg |= GM_GPCR_AU_ALL_DIS;
444
445 switch (sky2->speed) {
446 case SPEED_1000:
447 ctrl |= PHY_CT_SP1000;
448 reg |= GM_GPCR_SPEED_1000;
449 break;
450 case SPEED_100:
451 ctrl |= PHY_CT_SP100;
452 reg |= GM_GPCR_SPEED_100;
453 break;
454 }
455
456 if (sky2->duplex == DUPLEX_FULL) {
457 reg |= GM_GPCR_DUP_FULL;
458 ctrl |= PHY_CT_DUP_MD;
459 } else if (sky2->speed < SPEED_1000)
460 sky2->flow_mode = FC_NONE;
461
462
463 reg |= gm_fc_disable[sky2->flow_mode];
464
465 /* Forward pause packets to GMAC? */
466 if (sky2->flow_mode & FC_RX)
467 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
468 else
469 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
470 }
471
472 gma_write16(hw, port, GM_GP_CTRL, reg);
473
474 if (hw->flags & SKY2_HW_GIGABIT)
475 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
476
477 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
478 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
479
480 /* Setup Phy LED's */
481 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
482 ledover = 0;
483
484 switch (hw->chip_id) {
485 case CHIP_ID_YUKON_FE:
486 /* on 88E3082 these bits are at 11..9 (shifted left) */
487 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
488
489 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
490
491 /* delete ACT LED control bits */
492 ctrl &= ~PHY_M_FELP_LED1_MSK;
493 /* change ACT LED control to blink mode */
494 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
495 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
496 break;
497
498 case CHIP_ID_YUKON_FE_P:
499 /* Enable Link Partner Next Page */
500 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
501 ctrl |= PHY_M_PC_ENA_LIP_NP;
502
503 /* disable Energy Detect and enable scrambler */
504 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
505 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
506
507 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
508 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
509 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
510 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
511
512 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
513 break;
514
515 case CHIP_ID_YUKON_XL:
516 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
517
518 /* select page 3 to access LED control register */
519 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
520
521 /* set LED Function Control register */
522 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
523 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
524 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
525 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
526 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
527
528 /* set Polarity Control register */
529 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
530 (PHY_M_POLC_LS1_P_MIX(4) |
531 PHY_M_POLC_IS0_P_MIX(4) |
532 PHY_M_POLC_LOS_CTRL(2) |
533 PHY_M_POLC_INIT_CTRL(2) |
534 PHY_M_POLC_STA1_CTRL(2) |
535 PHY_M_POLC_STA0_CTRL(2)));
536
537 /* restore page register */
538 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
539 break;
540
541 case CHIP_ID_YUKON_EC_U:
542 case CHIP_ID_YUKON_EX:
543 case CHIP_ID_YUKON_SUPR:
544 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
545
546 /* select page 3 to access LED control register */
547 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
548
549 /* set LED Function Control register */
550 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
551 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
552 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
553 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
554 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
555
556 /* set Blink Rate in LED Timer Control Register */
557 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
558 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
559 /* restore page register */
560 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
561 break;
562
563 default:
564 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
565 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
566
567 /* turn off the Rx LED (LED_RX) */
568 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
569 }
570
571 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
572 /* apply fixes in PHY AFE */
573 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
574
575 /* increase differential signal amplitude in 10BASE-T */
576 gm_phy_write(hw, port, 0x18, 0xaa99);
577 gm_phy_write(hw, port, 0x17, 0x2011);
578
579 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
580 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
581 gm_phy_write(hw, port, 0x18, 0xa204);
582 gm_phy_write(hw, port, 0x17, 0x2002);
583 }
584
585 /* set page register to 0 */
586 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
587 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
588 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
589 /* apply workaround for integrated resistors calibration */
590 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
591 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
592 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
593 hw->chip_id < CHIP_ID_YUKON_SUPR) {
594 /* no effect on Yukon-XL */
595 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
596
597 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
598 /* turn on 100 Mbps LED (LED_LINK100) */
599 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
600 }
601
602 if (ledover)
603 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
604
605 }
606
607 /* Enable phy interrupt on auto-negotiation complete (or link up) */
608 if (sky2->autoneg == AUTONEG_ENABLE)
609 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
610 else
611 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
612 }
613
614 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
615 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
616
617 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
618 {
619 u32 reg1;
620
621 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
622 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
623 reg1 &= ~phy_power[port];
624
625 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
626 reg1 |= coma_mode[port];
627
628 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
629 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
630 sky2_pci_read32(hw, PCI_DEV_REG1);
631
632 if (hw->chip_id == CHIP_ID_YUKON_FE)
633 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
634 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
635 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
636 }
637
638 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
639 {
640 u32 reg1;
641 u16 ctrl;
642
643 /* release GPHY Control reset */
644 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
645
646 /* release GMAC reset */
647 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
648
649 if (hw->flags & SKY2_HW_NEWER_PHY) {
650 /* select page 2 to access MAC control register */
651 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
652
653 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
654 /* allow GMII Power Down */
655 ctrl &= ~PHY_M_MAC_GMIF_PUP;
656 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
657
658 /* set page register back to 0 */
659 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
660 }
661
662 /* setup General Purpose Control Register */
663 gma_write16(hw, port, GM_GP_CTRL,
664 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 | GM_GPCR_AU_ALL_DIS);
665
666 if (hw->chip_id != CHIP_ID_YUKON_EC) {
667 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
668 /* select page 2 to access MAC control register */
669 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
670
671 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
672 /* enable Power Down */
673 ctrl |= PHY_M_PC_POW_D_ENA;
674 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
675
676 /* set page register back to 0 */
677 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
678 }
679
680 /* set IEEE compatible Power Down Mode (dev. #4.99) */
681 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
682 }
683
684 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
685 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
686 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
687 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
688 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
689 }
690
691 /* Force a renegotiation */
692 static void sky2_phy_reinit(struct sky2_port *sky2)
693 {
694 spin_lock_bh(&sky2->phy_lock);
695 sky2_phy_init(sky2->hw, sky2->port);
696 spin_unlock_bh(&sky2->phy_lock);
697 }
698
699 /* Put device in state to listen for Wake On Lan */
700 static void sky2_wol_init(struct sky2_port *sky2)
701 {
702 struct sky2_hw *hw = sky2->hw;
703 unsigned port = sky2->port;
704 enum flow_control save_mode;
705 u16 ctrl;
706 u32 reg1;
707
708 /* Bring hardware out of reset */
709 sky2_write16(hw, B0_CTST, CS_RST_CLR);
710 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
711
712 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
713 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
714
715 /* Force to 10/100
716 * sky2_reset will re-enable on resume
717 */
718 save_mode = sky2->flow_mode;
719 ctrl = sky2->advertising;
720
721 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
722 sky2->flow_mode = FC_NONE;
723
724 spin_lock_bh(&sky2->phy_lock);
725 sky2_phy_power_up(hw, port);
726 sky2_phy_init(hw, port);
727 spin_unlock_bh(&sky2->phy_lock);
728
729 sky2->flow_mode = save_mode;
730 sky2->advertising = ctrl;
731
732 /* Set GMAC to no flow control and auto update for speed/duplex */
733 gma_write16(hw, port, GM_GP_CTRL,
734 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
735 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
736
737 /* Set WOL address */
738 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
739 sky2->netdev->dev_addr, ETH_ALEN);
740
741 /* Turn on appropriate WOL control bits */
742 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
743 ctrl = 0;
744 if (sky2->wol & WAKE_PHY)
745 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
746 else
747 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
748
749 if (sky2->wol & WAKE_MAGIC)
750 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
751 else
752 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
753
754 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
755 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
756
757 /* Turn on legacy PCI-Express PME mode */
758 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
759 reg1 |= PCI_Y2_PME_LEGACY;
760 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
761
762 /* block receiver */
763 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
764
765 }
766
767 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
768 {
769 struct net_device *dev = hw->dev[port];
770
771 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
772 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
773 hw->chip_id == CHIP_ID_YUKON_FE_P ||
774 hw->chip_id == CHIP_ID_YUKON_SUPR) {
775 /* Yukon-Extreme B0 and further Extreme devices */
776 /* enable Store & Forward mode for TX */
777
778 if (dev->mtu <= ETH_DATA_LEN)
779 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
780 TX_JUMBO_DIS | TX_STFW_ENA);
781
782 else
783 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
784 TX_JUMBO_ENA| TX_STFW_ENA);
785 } else {
786 if (dev->mtu <= ETH_DATA_LEN)
787 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
788 else {
789 /* set Tx GMAC FIFO Almost Empty Threshold */
790 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
791 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
792
793 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
794
795 /* Can't do offload because of lack of store/forward */
796 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
797 }
798 }
799 }
800
801 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
802 {
803 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
804 u16 reg;
805 u32 rx_reg;
806 int i;
807 const u8 *addr = hw->dev[port]->dev_addr;
808
809 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
810 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
811
812 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
813
814 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
815 /* WA DEV_472 -- looks like crossed wires on port 2 */
816 /* clear GMAC 1 Control reset */
817 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
818 do {
819 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
820 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
821 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
822 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
823 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
824 }
825
826 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
827
828 /* Enable Transmit FIFO Underrun */
829 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
830
831 spin_lock_bh(&sky2->phy_lock);
832 sky2_phy_power_up(hw, port);
833 sky2_phy_init(hw, port);
834 spin_unlock_bh(&sky2->phy_lock);
835
836 /* MIB clear */
837 reg = gma_read16(hw, port, GM_PHY_ADDR);
838 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
839
840 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
841 gma_read16(hw, port, i);
842 gma_write16(hw, port, GM_PHY_ADDR, reg);
843
844 /* transmit control */
845 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
846
847 /* receive control reg: unicast + multicast + no FCS */
848 gma_write16(hw, port, GM_RX_CTRL,
849 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
850
851 /* transmit flow control */
852 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
853
854 /* transmit parameter */
855 gma_write16(hw, port, GM_TX_PARAM,
856 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
857 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
858 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
859 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
860
861 /* serial mode register */
862 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
863 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
864
865 if (hw->dev[port]->mtu > ETH_DATA_LEN)
866 reg |= GM_SMOD_JUMBO_ENA;
867
868 gma_write16(hw, port, GM_SERIAL_MODE, reg);
869
870 /* virtual address for data */
871 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
872
873 /* physical address: used for pause frames */
874 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
875
876 /* ignore counter overflows */
877 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
878 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
879 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
880
881 /* Configure Rx MAC FIFO */
882 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
883 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
884 if (hw->chip_id == CHIP_ID_YUKON_EX ||
885 hw->chip_id == CHIP_ID_YUKON_FE_P)
886 rx_reg |= GMF_RX_OVER_ON;
887
888 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
889
890 if (hw->chip_id == CHIP_ID_YUKON_XL) {
891 /* Hardware errata - clear flush mask */
892 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
893 } else {
894 /* Flush Rx MAC FIFO on any flow control or error */
895 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
896 }
897
898 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
899 reg = RX_GMF_FL_THR_DEF + 1;
900 /* Another magic mystery workaround from sk98lin */
901 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
902 hw->chip_rev == CHIP_REV_YU_FE2_A0)
903 reg = 0x178;
904 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
905
906 /* Configure Tx MAC FIFO */
907 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
908 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
909
910 /* On chips without ram buffer, pause is controled by MAC level */
911 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
912 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
913 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
914
915 sky2_set_tx_stfwd(hw, port);
916 }
917
918 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
919 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
920 /* disable dynamic watermark */
921 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
922 reg &= ~TX_DYN_WM_ENA;
923 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
924 }
925 }
926
927 /* Assign Ram Buffer allocation to queue */
928 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
929 {
930 u32 end;
931
932 /* convert from K bytes to qwords used for hw register */
933 start *= 1024/8;
934 space *= 1024/8;
935 end = start + space - 1;
936
937 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
938 sky2_write32(hw, RB_ADDR(q, RB_START), start);
939 sky2_write32(hw, RB_ADDR(q, RB_END), end);
940 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
941 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
942
943 if (q == Q_R1 || q == Q_R2) {
944 u32 tp = space - space/4;
945
946 /* On receive queue's set the thresholds
947 * give receiver priority when > 3/4 full
948 * send pause when down to 2K
949 */
950 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
951 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
952
953 tp = space - 2048/8;
954 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
955 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
956 } else {
957 /* Enable store & forward on Tx queue's because
958 * Tx FIFO is only 1K on Yukon
959 */
960 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
961 }
962
963 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
964 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
965 }
966
967 /* Setup Bus Memory Interface */
968 static void sky2_qset(struct sky2_hw *hw, u16 q)
969 {
970 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
971 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
972 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
973 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
974 }
975
976 /* Setup prefetch unit registers. This is the interface between
977 * hardware and driver list elements
978 */
979 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
980 u64 addr, u32 last)
981 {
982 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
983 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
984 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
985 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
986 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
987 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
988
989 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
990 }
991
992 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
993 {
994 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
995
996 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
997 le->ctrl = 0;
998 return le;
999 }
1000
1001 static void tx_init(struct sky2_port *sky2)
1002 {
1003 struct sky2_tx_le *le;
1004
1005 sky2->tx_prod = sky2->tx_cons = 0;
1006 sky2->tx_tcpsum = 0;
1007 sky2->tx_last_mss = 0;
1008
1009 le = get_tx_le(sky2);
1010 le->addr = 0;
1011 le->opcode = OP_ADDR64 | HW_OWNER;
1012 }
1013
1014 static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
1015 struct sky2_tx_le *le)
1016 {
1017 return sky2->tx_ring + (le - sky2->tx_le);
1018 }
1019
1020 /* Update chip's next pointer */
1021 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
1022 {
1023 /* Make sure write' to descriptors are complete before we tell hardware */
1024 wmb();
1025 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1026
1027 /* Synchronize I/O on since next processor may write to tail */
1028 mmiowb();
1029 }
1030
1031
1032 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1033 {
1034 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
1035 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
1036 le->ctrl = 0;
1037 return le;
1038 }
1039
1040 /* Build description to hardware for one receive segment */
1041 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1042 dma_addr_t map, unsigned len)
1043 {
1044 struct sky2_rx_le *le;
1045
1046 if (sizeof(dma_addr_t) > sizeof(u32)) {
1047 le = sky2_next_rx(sky2);
1048 le->addr = cpu_to_le32(upper_32_bits(map));
1049 le->opcode = OP_ADDR64 | HW_OWNER;
1050 }
1051
1052 le = sky2_next_rx(sky2);
1053 le->addr = cpu_to_le32((u32) map);
1054 le->length = cpu_to_le16(len);
1055 le->opcode = op | HW_OWNER;
1056 }
1057
1058 /* Build description to hardware for one possibly fragmented skb */
1059 static void sky2_rx_submit(struct sky2_port *sky2,
1060 const struct rx_ring_info *re)
1061 {
1062 int i;
1063
1064 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1065
1066 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1067 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1068 }
1069
1070
1071 static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1072 unsigned size)
1073 {
1074 struct sk_buff *skb = re->skb;
1075 int i;
1076
1077 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1078 if (unlikely(pci_dma_mapping_error(pdev, re->data_addr)))
1079 return -EIO;
1080
1081 pci_unmap_len_set(re, data_size, size);
1082
1083 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1084 re->frag_addr[i] = pci_map_page(pdev,
1085 skb_shinfo(skb)->frags[i].page,
1086 skb_shinfo(skb)->frags[i].page_offset,
1087 skb_shinfo(skb)->frags[i].size,
1088 PCI_DMA_FROMDEVICE);
1089 return 0;
1090 }
1091
1092 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1093 {
1094 struct sk_buff *skb = re->skb;
1095 int i;
1096
1097 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1098 PCI_DMA_FROMDEVICE);
1099
1100 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1101 pci_unmap_page(pdev, re->frag_addr[i],
1102 skb_shinfo(skb)->frags[i].size,
1103 PCI_DMA_FROMDEVICE);
1104 }
1105
1106 /* Tell chip where to start receive checksum.
1107 * Actually has two checksums, but set both same to avoid possible byte
1108 * order problems.
1109 */
1110 static void rx_set_checksum(struct sky2_port *sky2)
1111 {
1112 struct sky2_rx_le *le = sky2_next_rx(sky2);
1113
1114 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1115 le->ctrl = 0;
1116 le->opcode = OP_TCPSTART | HW_OWNER;
1117
1118 sky2_write32(sky2->hw,
1119 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1120 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1121 }
1122
1123 /*
1124 * The RX Stop command will not work for Yukon-2 if the BMU does not
1125 * reach the end of packet and since we can't make sure that we have
1126 * incoming data, we must reset the BMU while it is not doing a DMA
1127 * transfer. Since it is possible that the RX path is still active,
1128 * the RX RAM buffer will be stopped first, so any possible incoming
1129 * data will not trigger a DMA. After the RAM buffer is stopped, the
1130 * BMU is polled until any DMA in progress is ended and only then it
1131 * will be reset.
1132 */
1133 static void sky2_rx_stop(struct sky2_port *sky2)
1134 {
1135 struct sky2_hw *hw = sky2->hw;
1136 unsigned rxq = rxqaddr[sky2->port];
1137 int i;
1138
1139 /* disable the RAM Buffer receive queue */
1140 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1141
1142 for (i = 0; i < 0xffff; i++)
1143 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1144 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1145 goto stopped;
1146
1147 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1148 sky2->netdev->name);
1149 stopped:
1150 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1151
1152 /* reset the Rx prefetch unit */
1153 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1154 mmiowb();
1155 }
1156
1157 /* Clean out receive buffer area, assumes receiver hardware stopped */
1158 static void sky2_rx_clean(struct sky2_port *sky2)
1159 {
1160 unsigned i;
1161
1162 memset(sky2->rx_le, 0, RX_LE_BYTES);
1163 for (i = 0; i < sky2->rx_pending; i++) {
1164 struct rx_ring_info *re = sky2->rx_ring + i;
1165
1166 if (re->skb) {
1167 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1168 kfree_skb(re->skb);
1169 re->skb = NULL;
1170 }
1171 }
1172 skb_queue_purge(&sky2->rx_recycle);
1173 }
1174
1175 /* Basic MII support */
1176 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1177 {
1178 struct mii_ioctl_data *data = if_mii(ifr);
1179 struct sky2_port *sky2 = netdev_priv(dev);
1180 struct sky2_hw *hw = sky2->hw;
1181 int err = -EOPNOTSUPP;
1182
1183 if (!netif_running(dev))
1184 return -ENODEV; /* Phy still in reset */
1185
1186 switch (cmd) {
1187 case SIOCGMIIPHY:
1188 data->phy_id = PHY_ADDR_MARV;
1189
1190 /* fallthru */
1191 case SIOCGMIIREG: {
1192 u16 val = 0;
1193
1194 spin_lock_bh(&sky2->phy_lock);
1195 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1196 spin_unlock_bh(&sky2->phy_lock);
1197
1198 data->val_out = val;
1199 break;
1200 }
1201
1202 case SIOCSMIIREG:
1203 if (!capable(CAP_NET_ADMIN))
1204 return -EPERM;
1205
1206 spin_lock_bh(&sky2->phy_lock);
1207 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1208 data->val_in);
1209 spin_unlock_bh(&sky2->phy_lock);
1210 break;
1211 }
1212 return err;
1213 }
1214
1215 #ifdef SKY2_VLAN_TAG_USED
1216 static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
1217 {
1218 if (onoff) {
1219 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1220 RX_VLAN_STRIP_ON);
1221 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1222 TX_VLAN_TAG_ON);
1223 } else {
1224 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1225 RX_VLAN_STRIP_OFF);
1226 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1227 TX_VLAN_TAG_OFF);
1228 }
1229 }
1230
1231 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1232 {
1233 struct sky2_port *sky2 = netdev_priv(dev);
1234 struct sky2_hw *hw = sky2->hw;
1235 u16 port = sky2->port;
1236
1237 netif_tx_lock_bh(dev);
1238 napi_disable(&hw->napi);
1239
1240 sky2->vlgrp = grp;
1241 sky2_set_vlan_mode(hw, port, grp != NULL);
1242
1243 sky2_read32(hw, B0_Y2_SP_LISR);
1244 napi_enable(&hw->napi);
1245 netif_tx_unlock_bh(dev);
1246 }
1247 #endif
1248
1249 /* Amount of required worst case padding in rx buffer */
1250 static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1251 {
1252 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1253 }
1254
1255 /*
1256 * Allocate an skb for receiving. If the MTU is large enough
1257 * make the skb non-linear with a fragment list of pages.
1258 */
1259 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1260 {
1261 struct sk_buff *skb;
1262 int i;
1263
1264 skb = __skb_dequeue(&sky2->rx_recycle);
1265 if (!skb)
1266 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size
1267 + sky2_rx_pad(sky2->hw));
1268 if (!skb)
1269 goto nomem;
1270
1271 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
1272 unsigned char *start;
1273 /*
1274 * Workaround for a bug in FIFO that cause hang
1275 * if the FIFO if the receive buffer is not 64 byte aligned.
1276 * The buffer returned from netdev_alloc_skb is
1277 * aligned except if slab debugging is enabled.
1278 */
1279 start = PTR_ALIGN(skb->data, 8);
1280 skb_reserve(skb, start - skb->data);
1281 } else
1282 skb_reserve(skb, NET_IP_ALIGN);
1283
1284 for (i = 0; i < sky2->rx_nfrags; i++) {
1285 struct page *page = alloc_page(GFP_ATOMIC);
1286
1287 if (!page)
1288 goto free_partial;
1289 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1290 }
1291
1292 return skb;
1293 free_partial:
1294 kfree_skb(skb);
1295 nomem:
1296 return NULL;
1297 }
1298
1299 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1300 {
1301 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1302 }
1303
1304 /*
1305 * Allocate and setup receiver buffer pool.
1306 * Normal case this ends up creating one list element for skb
1307 * in the receive ring. Worst case if using large MTU and each
1308 * allocation falls on a different 64 bit region, that results
1309 * in 6 list elements per ring entry.
1310 * One element is used for checksum enable/disable, and one
1311 * extra to avoid wrap.
1312 */
1313 static int sky2_rx_start(struct sky2_port *sky2)
1314 {
1315 struct sky2_hw *hw = sky2->hw;
1316 struct rx_ring_info *re;
1317 unsigned rxq = rxqaddr[sky2->port];
1318 unsigned i, size, thresh;
1319
1320 sky2->rx_put = sky2->rx_next = 0;
1321 sky2_qset(hw, rxq);
1322
1323 /* On PCI express lowering the watermark gives better performance */
1324 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1325 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1326
1327 /* These chips have no ram buffer?
1328 * MAC Rx RAM Read is controlled by hardware */
1329 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1330 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1331 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1332 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1333
1334 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1335
1336 if (!(hw->flags & SKY2_HW_NEW_LE))
1337 rx_set_checksum(sky2);
1338
1339 /* Space needed for frame data + headers rounded up */
1340 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1341
1342 /* Stopping point for hardware truncation */
1343 thresh = (size - 8) / sizeof(u32);
1344
1345 sky2->rx_nfrags = size >> PAGE_SHIFT;
1346 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1347
1348 /* Compute residue after pages */
1349 size -= sky2->rx_nfrags << PAGE_SHIFT;
1350
1351 /* Optimize to handle small packets and headers */
1352 if (size < copybreak)
1353 size = copybreak;
1354 if (size < ETH_HLEN)
1355 size = ETH_HLEN;
1356
1357 sky2->rx_data_size = size;
1358
1359 skb_queue_head_init(&sky2->rx_recycle);
1360
1361 /* Fill Rx ring */
1362 for (i = 0; i < sky2->rx_pending; i++) {
1363 re = sky2->rx_ring + i;
1364
1365 re->skb = sky2_rx_alloc(sky2);
1366 if (!re->skb)
1367 goto nomem;
1368
1369 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1370 dev_kfree_skb(re->skb);
1371 re->skb = NULL;
1372 goto nomem;
1373 }
1374
1375 sky2_rx_submit(sky2, re);
1376 }
1377
1378 /*
1379 * The receiver hangs if it receives frames larger than the
1380 * packet buffer. As a workaround, truncate oversize frames, but
1381 * the register is limited to 9 bits, so if you do frames > 2052
1382 * you better get the MTU right!
1383 */
1384 if (thresh > 0x1ff)
1385 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1386 else {
1387 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1388 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1389 }
1390
1391 /* Tell chip about available buffers */
1392 sky2_rx_update(sky2, rxq);
1393 return 0;
1394 nomem:
1395 sky2_rx_clean(sky2);
1396 return -ENOMEM;
1397 }
1398
1399 /* Bring up network interface. */
1400 static int sky2_up(struct net_device *dev)
1401 {
1402 struct sky2_port *sky2 = netdev_priv(dev);
1403 struct sky2_hw *hw = sky2->hw;
1404 unsigned port = sky2->port;
1405 u32 imask, ramsize;
1406 int cap, err = -ENOMEM;
1407 struct net_device *otherdev = hw->dev[sky2->port^1];
1408
1409 /*
1410 * On dual port PCI-X card, there is an problem where status
1411 * can be received out of order due to split transactions
1412 */
1413 if (otherdev && netif_running(otherdev) &&
1414 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1415 u16 cmd;
1416
1417 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1418 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1419 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1420
1421 }
1422
1423 netif_carrier_off(dev);
1424
1425 /* must be power of 2 */
1426 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1427 TX_RING_SIZE *
1428 sizeof(struct sky2_tx_le),
1429 &sky2->tx_le_map);
1430 if (!sky2->tx_le)
1431 goto err_out;
1432
1433 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1434 GFP_KERNEL);
1435 if (!sky2->tx_ring)
1436 goto err_out;
1437
1438 tx_init(sky2);
1439
1440 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1441 &sky2->rx_le_map);
1442 if (!sky2->rx_le)
1443 goto err_out;
1444 memset(sky2->rx_le, 0, RX_LE_BYTES);
1445
1446 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1447 GFP_KERNEL);
1448 if (!sky2->rx_ring)
1449 goto err_out;
1450
1451 sky2_mac_init(hw, port);
1452
1453 /* Register is number of 4K blocks on internal RAM buffer. */
1454 ramsize = sky2_read8(hw, B2_E_0) * 4;
1455 if (ramsize > 0) {
1456 u32 rxspace;
1457
1458 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1459 if (ramsize < 16)
1460 rxspace = ramsize / 2;
1461 else
1462 rxspace = 8 + (2*(ramsize - 16))/3;
1463
1464 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1465 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1466
1467 /* Make sure SyncQ is disabled */
1468 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1469 RB_RST_SET);
1470 }
1471
1472 sky2_qset(hw, txqaddr[port]);
1473
1474 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1475 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1476 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1477
1478 /* Set almost empty threshold */
1479 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1480 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1481 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1482
1483 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1484 TX_RING_SIZE - 1);
1485
1486 #ifdef SKY2_VLAN_TAG_USED
1487 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1488 #endif
1489
1490 sky2->restarting = 0;
1491
1492 err = sky2_rx_start(sky2);
1493 if (err)
1494 goto err_out;
1495
1496 /* Enable interrupts from phy/mac for port */
1497 imask = sky2_read32(hw, B0_IMSK);
1498 imask |= portirq_msk[port];
1499 sky2_write32(hw, B0_IMSK, imask);
1500 sky2_read32(hw, B0_IMSK);
1501
1502 sky2_set_multicast(dev);
1503
1504 /* wake queue incase we are restarting */
1505 netif_wake_queue(dev);
1506
1507 if (netif_msg_ifup(sky2))
1508 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1509 return 0;
1510
1511 err_out:
1512 if (sky2->rx_le) {
1513 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1514 sky2->rx_le, sky2->rx_le_map);
1515 sky2->rx_le = NULL;
1516 }
1517 if (sky2->tx_le) {
1518 pci_free_consistent(hw->pdev,
1519 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1520 sky2->tx_le, sky2->tx_le_map);
1521 sky2->tx_le = NULL;
1522 }
1523 kfree(sky2->tx_ring);
1524 kfree(sky2->rx_ring);
1525
1526 sky2->tx_ring = NULL;
1527 sky2->rx_ring = NULL;
1528 return err;
1529 }
1530
1531 /* Modular subtraction in ring */
1532 static inline int tx_dist(unsigned tail, unsigned head)
1533 {
1534 return (head - tail) & (TX_RING_SIZE - 1);
1535 }
1536
1537 /* Number of list elements available for next tx */
1538 static inline int tx_avail(const struct sky2_port *sky2)
1539 {
1540 if (unlikely(sky2->restarting))
1541 return 0;
1542 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1543 }
1544
1545 /* Estimate of number of transmit list elements required */
1546 static unsigned tx_le_req(const struct sk_buff *skb)
1547 {
1548 unsigned count;
1549
1550 count = sizeof(dma_addr_t) / sizeof(u32);
1551 count += skb_shinfo(skb)->nr_frags * count;
1552
1553 if (skb_is_gso(skb))
1554 ++count;
1555
1556 if (skb->ip_summed == CHECKSUM_PARTIAL)
1557 ++count;
1558
1559 return count;
1560 }
1561
1562 /*
1563 * Put one packet in ring for transmit.
1564 * A single packet can generate multiple list elements, and
1565 * the number of ring elements will probably be less than the number
1566 * of list elements used.
1567 */
1568 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1569 {
1570 struct sky2_port *sky2 = netdev_priv(dev);
1571 struct sky2_hw *hw = sky2->hw;
1572 struct sky2_tx_le *le = NULL;
1573 struct tx_ring_info *re;
1574 unsigned i, len, first_slot;
1575 dma_addr_t mapping;
1576 u16 mss;
1577 u8 ctrl;
1578
1579 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1580 return NETDEV_TX_BUSY;
1581
1582 len = skb_headlen(skb);
1583 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1584
1585 if (pci_dma_mapping_error(hw->pdev, mapping))
1586 goto mapping_error;
1587
1588 first_slot = sky2->tx_prod;
1589 if (unlikely(netif_msg_tx_queued(sky2)))
1590 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1591 dev->name, first_slot, skb->len);
1592
1593 /* Send high bits if needed */
1594 if (sizeof(dma_addr_t) > sizeof(u32)) {
1595 le = get_tx_le(sky2);
1596 le->addr = cpu_to_le32(upper_32_bits(mapping));
1597 le->opcode = OP_ADDR64 | HW_OWNER;
1598 }
1599
1600 /* Check for TCP Segmentation Offload */
1601 mss = skb_shinfo(skb)->gso_size;
1602 if (mss != 0) {
1603
1604 if (!(hw->flags & SKY2_HW_NEW_LE))
1605 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1606
1607 if (mss != sky2->tx_last_mss) {
1608 le = get_tx_le(sky2);
1609 le->addr = cpu_to_le32(mss);
1610
1611 if (hw->flags & SKY2_HW_NEW_LE)
1612 le->opcode = OP_MSS | HW_OWNER;
1613 else
1614 le->opcode = OP_LRGLEN | HW_OWNER;
1615 sky2->tx_last_mss = mss;
1616 }
1617 }
1618
1619 ctrl = 0;
1620 #ifdef SKY2_VLAN_TAG_USED
1621 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1622 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1623 if (!le) {
1624 le = get_tx_le(sky2);
1625 le->addr = 0;
1626 le->opcode = OP_VLAN|HW_OWNER;
1627 } else
1628 le->opcode |= OP_VLAN;
1629 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1630 ctrl |= INS_VLAN;
1631 }
1632 #endif
1633
1634 /* Handle TCP checksum offload */
1635 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1636 /* On Yukon EX (some versions) encoding change. */
1637 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1638 ctrl |= CALSUM; /* auto checksum */
1639 else {
1640 const unsigned offset = skb_transport_offset(skb);
1641 u32 tcpsum;
1642
1643 tcpsum = offset << 16; /* sum start */
1644 tcpsum |= offset + skb->csum_offset; /* sum write */
1645
1646 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1647 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1648 ctrl |= UDPTCP;
1649
1650 if (tcpsum != sky2->tx_tcpsum) {
1651 sky2->tx_tcpsum = tcpsum;
1652
1653 le = get_tx_le(sky2);
1654 le->addr = cpu_to_le32(tcpsum);
1655 le->length = 0; /* initial checksum value */
1656 le->ctrl = 1; /* one packet */
1657 le->opcode = OP_TCPLISW | HW_OWNER;
1658 }
1659 }
1660 }
1661
1662 le = get_tx_le(sky2);
1663 le->addr = cpu_to_le32((u32) mapping);
1664 le->length = cpu_to_le16(len);
1665 le->ctrl = ctrl;
1666 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1667
1668 re = tx_le_re(sky2, le);
1669 re->skb = skb;
1670 pci_unmap_addr_set(re, mapaddr, mapping);
1671 pci_unmap_len_set(re, maplen, len);
1672
1673 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1674 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1675
1676 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1677 frag->size, PCI_DMA_TODEVICE);
1678
1679 if (pci_dma_mapping_error(hw->pdev, mapping))
1680 goto mapping_unwind;
1681
1682 if (sizeof(dma_addr_t) > sizeof(u32)) {
1683 le = get_tx_le(sky2);
1684 le->addr = cpu_to_le32(upper_32_bits(mapping));
1685 le->ctrl = 0;
1686 le->opcode = OP_ADDR64 | HW_OWNER;
1687 }
1688
1689 le = get_tx_le(sky2);
1690 le->addr = cpu_to_le32((u32) mapping);
1691 le->length = cpu_to_le16(frag->size);
1692 le->ctrl = ctrl;
1693 le->opcode = OP_BUFFER | HW_OWNER;
1694
1695 re = tx_le_re(sky2, le);
1696 re->skb = skb;
1697 pci_unmap_addr_set(re, mapaddr, mapping);
1698 pci_unmap_len_set(re, maplen, frag->size);
1699 }
1700
1701 le->ctrl |= EOP;
1702
1703 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1704 netif_stop_queue(dev);
1705
1706 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1707
1708 return NETDEV_TX_OK;
1709
1710 mapping_unwind:
1711 for (i = first_slot; i != sky2->tx_prod; i = RING_NEXT(i, TX_RING_SIZE)) {
1712 le = sky2->tx_le + i;
1713 re = sky2->tx_ring + i;
1714
1715 switch(le->opcode & ~HW_OWNER) {
1716 case OP_LARGESEND:
1717 case OP_PACKET:
1718 pci_unmap_single(hw->pdev,
1719 pci_unmap_addr(re, mapaddr),
1720 pci_unmap_len(re, maplen),
1721 PCI_DMA_TODEVICE);
1722 break;
1723 case OP_BUFFER:
1724 pci_unmap_page(hw->pdev, pci_unmap_addr(re, mapaddr),
1725 pci_unmap_len(re, maplen),
1726 PCI_DMA_TODEVICE);
1727 break;
1728 }
1729 }
1730
1731 sky2->tx_prod = first_slot;
1732 mapping_error:
1733 if (net_ratelimit())
1734 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1735 dev_kfree_skb(skb);
1736 return NETDEV_TX_OK;
1737 }
1738
1739 /*
1740 * Free ring elements from starting at tx_cons until "done"
1741 *
1742 * NB: the hardware will tell us about partial completion of multi-part
1743 * buffers so make sure not to free skb to early.
1744 */
1745 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1746 {
1747 struct net_device *dev = sky2->netdev;
1748 struct pci_dev *pdev = sky2->hw->pdev;
1749 unsigned idx;
1750
1751 BUG_ON(done >= TX_RING_SIZE);
1752
1753 for (idx = sky2->tx_cons; idx != done;
1754 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1755 struct sky2_tx_le *le = sky2->tx_le + idx;
1756 struct tx_ring_info *re = sky2->tx_ring + idx;
1757
1758 switch(le->opcode & ~HW_OWNER) {
1759 case OP_LARGESEND:
1760 case OP_PACKET:
1761 pci_unmap_single(pdev,
1762 pci_unmap_addr(re, mapaddr),
1763 pci_unmap_len(re, maplen),
1764 PCI_DMA_TODEVICE);
1765 break;
1766 case OP_BUFFER:
1767 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1768 pci_unmap_len(re, maplen),
1769 PCI_DMA_TODEVICE);
1770 break;
1771 }
1772
1773 if (le->ctrl & EOP) {
1774 struct sk_buff *skb = re->skb;
1775
1776 if (unlikely(netif_msg_tx_done(sky2)))
1777 printk(KERN_DEBUG "%s: tx done %u\n",
1778 dev->name, idx);
1779
1780 dev->stats.tx_packets++;
1781 dev->stats.tx_bytes += skb->len;
1782
1783 if (skb_queue_len(&sky2->rx_recycle) < sky2->rx_pending
1784 && skb_recycle_check(skb, sky2->rx_data_size
1785 + sky2_rx_pad(sky2->hw)))
1786 __skb_queue_head(&sky2->rx_recycle, skb);
1787 else
1788 dev_kfree_skb_any(skb);
1789
1790 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
1791 }
1792 }
1793
1794 sky2->tx_cons = idx;
1795 smp_mb();
1796
1797 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1798 netif_wake_queue(dev);
1799 }
1800
1801 /* Cleanup all untransmitted buffers, assume transmitter not running */
1802 static void sky2_tx_clean(struct net_device *dev)
1803 {
1804 struct sky2_port *sky2 = netdev_priv(dev);
1805
1806 netif_tx_lock_bh(dev);
1807 sky2_tx_complete(sky2, sky2->tx_prod);
1808 netif_tx_unlock_bh(dev);
1809 }
1810
1811 /* Network shutdown */
1812 static int sky2_down(struct net_device *dev)
1813 {
1814 struct sky2_port *sky2 = netdev_priv(dev);
1815 struct sky2_hw *hw = sky2->hw;
1816 unsigned port = sky2->port;
1817 u16 ctrl;
1818 u32 imask;
1819
1820 /* Never really got started! */
1821 if (!sky2->tx_le)
1822 return 0;
1823
1824 if (netif_msg_ifdown(sky2))
1825 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1826
1827 /* explicitly shut off tx incase we're restarting */
1828 sky2->restarting = 1;
1829 netif_tx_disable(dev);
1830
1831 /* Force flow control off */
1832 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1833
1834 /* Stop transmitter */
1835 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1836 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1837
1838 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1839 RB_RST_SET | RB_DIS_OP_MD);
1840
1841 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1842 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1843 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1844
1845 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1846
1847 /* Workaround shared GMAC reset */
1848 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1849 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1850 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1851
1852 /* Disable Force Sync bit and Enable Alloc bit */
1853 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1854 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1855
1856 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1857 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1858 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1859
1860 /* Reset the PCI FIFO of the async Tx queue */
1861 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1862 BMU_RST_SET | BMU_FIFO_RST);
1863
1864 /* Reset the Tx prefetch units */
1865 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1866 PREF_UNIT_RST_SET);
1867
1868 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1869
1870 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1871 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1872
1873 /* Force any delayed status interrrupt and NAPI */
1874 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1875 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1876 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1877 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1878
1879 sky2_rx_stop(sky2);
1880
1881 /* Disable port IRQ */
1882 imask = sky2_read32(hw, B0_IMSK);
1883 imask &= ~portirq_msk[port];
1884 sky2_write32(hw, B0_IMSK, imask);
1885 sky2_read32(hw, B0_IMSK);
1886
1887 synchronize_irq(hw->pdev->irq);
1888 napi_synchronize(&hw->napi);
1889
1890 sky2_phy_power_down(hw, port);
1891
1892 /* turn off LED's */
1893 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1894
1895 sky2_tx_clean(dev);
1896 sky2_rx_clean(sky2);
1897
1898 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1899 sky2->rx_le, sky2->rx_le_map);
1900 kfree(sky2->rx_ring);
1901
1902 pci_free_consistent(hw->pdev,
1903 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1904 sky2->tx_le, sky2->tx_le_map);
1905 kfree(sky2->tx_ring);
1906
1907 sky2->tx_le = NULL;
1908 sky2->rx_le = NULL;
1909
1910 sky2->rx_ring = NULL;
1911 sky2->tx_ring = NULL;
1912
1913 return 0;
1914 }
1915
1916 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1917 {
1918 if (hw->flags & SKY2_HW_FIBRE_PHY)
1919 return SPEED_1000;
1920
1921 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1922 if (aux & PHY_M_PS_SPEED_100)
1923 return SPEED_100;
1924 else
1925 return SPEED_10;
1926 }
1927
1928 switch (aux & PHY_M_PS_SPEED_MSK) {
1929 case PHY_M_PS_SPEED_1000:
1930 return SPEED_1000;
1931 case PHY_M_PS_SPEED_100:
1932 return SPEED_100;
1933 default:
1934 return SPEED_10;
1935 }
1936 }
1937
1938 static void sky2_link_up(struct sky2_port *sky2)
1939 {
1940 struct sky2_hw *hw = sky2->hw;
1941 unsigned port = sky2->port;
1942 u16 reg;
1943 static const char *fc_name[] = {
1944 [FC_NONE] = "none",
1945 [FC_TX] = "tx",
1946 [FC_RX] = "rx",
1947 [FC_BOTH] = "both",
1948 };
1949
1950 /* enable Rx/Tx */
1951 reg = gma_read16(hw, port, GM_GP_CTRL);
1952 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1953 gma_write16(hw, port, GM_GP_CTRL, reg);
1954
1955 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1956
1957 netif_carrier_on(sky2->netdev);
1958
1959 mod_timer(&hw->watchdog_timer, jiffies + 1);
1960
1961 /* Turn on link LED */
1962 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1963 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1964
1965 if (netif_msg_link(sky2))
1966 printk(KERN_INFO PFX
1967 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1968 sky2->netdev->name, sky2->speed,
1969 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1970 fc_name[sky2->flow_status]);
1971 }
1972
1973 static void sky2_link_down(struct sky2_port *sky2)
1974 {
1975 struct sky2_hw *hw = sky2->hw;
1976 unsigned port = sky2->port;
1977 u16 reg;
1978
1979 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1980
1981 reg = gma_read16(hw, port, GM_GP_CTRL);
1982 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1983 gma_write16(hw, port, GM_GP_CTRL, reg);
1984
1985 netif_carrier_off(sky2->netdev);
1986
1987 /* Turn on link LED */
1988 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1989
1990 if (netif_msg_link(sky2))
1991 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1992
1993 sky2_phy_init(hw, port);
1994 }
1995
1996 static enum flow_control sky2_flow(int rx, int tx)
1997 {
1998 if (rx)
1999 return tx ? FC_BOTH : FC_RX;
2000 else
2001 return tx ? FC_TX : FC_NONE;
2002 }
2003
2004 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2005 {
2006 struct sky2_hw *hw = sky2->hw;
2007 unsigned port = sky2->port;
2008 u16 advert, lpa;
2009
2010 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2011 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
2012 if (lpa & PHY_M_AN_RF) {
2013 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
2014 return -1;
2015 }
2016
2017 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2018 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
2019 sky2->netdev->name);
2020 return -1;
2021 }
2022
2023 sky2->speed = sky2_phy_speed(hw, aux);
2024 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2025
2026 /* Since the pause result bits seem to in different positions on
2027 * different chips. look at registers.
2028 */
2029 if (hw->flags & SKY2_HW_FIBRE_PHY) {
2030 /* Shift for bits in fiber PHY */
2031 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2032 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2033
2034 if (advert & ADVERTISE_1000XPAUSE)
2035 advert |= ADVERTISE_PAUSE_CAP;
2036 if (advert & ADVERTISE_1000XPSE_ASYM)
2037 advert |= ADVERTISE_PAUSE_ASYM;
2038 if (lpa & LPA_1000XPAUSE)
2039 lpa |= LPA_PAUSE_CAP;
2040 if (lpa & LPA_1000XPAUSE_ASYM)
2041 lpa |= LPA_PAUSE_ASYM;
2042 }
2043
2044 sky2->flow_status = FC_NONE;
2045 if (advert & ADVERTISE_PAUSE_CAP) {
2046 if (lpa & LPA_PAUSE_CAP)
2047 sky2->flow_status = FC_BOTH;
2048 else if (advert & ADVERTISE_PAUSE_ASYM)
2049 sky2->flow_status = FC_RX;
2050 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2051 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2052 sky2->flow_status = FC_TX;
2053 }
2054
2055 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
2056 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
2057 sky2->flow_status = FC_NONE;
2058
2059 if (sky2->flow_status & FC_TX)
2060 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2061 else
2062 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2063
2064 return 0;
2065 }
2066
2067 /* Interrupt from PHY */
2068 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2069 {
2070 struct net_device *dev = hw->dev[port];
2071 struct sky2_port *sky2 = netdev_priv(dev);
2072 u16 istatus, phystat;
2073
2074 if (!netif_running(dev))
2075 return;
2076
2077 spin_lock(&sky2->phy_lock);
2078 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2079 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2080
2081 if (netif_msg_intr(sky2))
2082 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2083 sky2->netdev->name, istatus, phystat);
2084
2085 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
2086 if (sky2_autoneg_done(sky2, phystat) == 0)
2087 sky2_link_up(sky2);
2088 goto out;
2089 }
2090
2091 if (istatus & PHY_M_IS_LSP_CHANGE)
2092 sky2->speed = sky2_phy_speed(hw, phystat);
2093
2094 if (istatus & PHY_M_IS_DUP_CHANGE)
2095 sky2->duplex =
2096 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2097
2098 if (istatus & PHY_M_IS_LST_CHANGE) {
2099 if (phystat & PHY_M_PS_LINK_UP)
2100 sky2_link_up(sky2);
2101 else
2102 sky2_link_down(sky2);
2103 }
2104 out:
2105 spin_unlock(&sky2->phy_lock);
2106 }
2107
2108 /* Transmit timeout is only called if we are running, carrier is up
2109 * and tx queue is full (stopped).
2110 */
2111 static void sky2_tx_timeout(struct net_device *dev)
2112 {
2113 struct sky2_port *sky2 = netdev_priv(dev);
2114 struct sky2_hw *hw = sky2->hw;
2115
2116 if (netif_msg_timer(sky2))
2117 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2118
2119 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
2120 dev->name, sky2->tx_cons, sky2->tx_prod,
2121 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2122 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
2123
2124 /* can't restart safely under softirq */
2125 schedule_work(&hw->restart_work);
2126 }
2127
2128 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2129 {
2130 struct sky2_port *sky2 = netdev_priv(dev);
2131 struct sky2_hw *hw = sky2->hw;
2132 unsigned port = sky2->port;
2133 int err;
2134 u16 ctl, mode;
2135 u32 imask;
2136
2137 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2138 return -EINVAL;
2139
2140 if (new_mtu > ETH_DATA_LEN &&
2141 (hw->chip_id == CHIP_ID_YUKON_FE ||
2142 hw->chip_id == CHIP_ID_YUKON_FE_P))
2143 return -EINVAL;
2144
2145 if (!netif_running(dev)) {
2146 dev->mtu = new_mtu;
2147 return 0;
2148 }
2149
2150 imask = sky2_read32(hw, B0_IMSK);
2151 sky2_write32(hw, B0_IMSK, 0);
2152
2153 dev->trans_start = jiffies; /* prevent tx timeout */
2154 netif_stop_queue(dev);
2155 napi_disable(&hw->napi);
2156
2157 synchronize_irq(hw->pdev->irq);
2158
2159 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
2160 sky2_set_tx_stfwd(hw, port);
2161
2162 ctl = gma_read16(hw, port, GM_GP_CTRL);
2163 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2164 sky2_rx_stop(sky2);
2165 sky2_rx_clean(sky2);
2166
2167 dev->mtu = new_mtu;
2168
2169 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2170 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2171
2172 if (dev->mtu > ETH_DATA_LEN)
2173 mode |= GM_SMOD_JUMBO_ENA;
2174
2175 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2176
2177 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2178
2179 err = sky2_rx_start(sky2);
2180 sky2_write32(hw, B0_IMSK, imask);
2181
2182 sky2_read32(hw, B0_Y2_SP_LISR);
2183 napi_enable(&hw->napi);
2184
2185 if (err)
2186 dev_close(dev);
2187 else {
2188 gma_write16(hw, port, GM_GP_CTRL, ctl);
2189
2190 netif_wake_queue(dev);
2191 }
2192
2193 return err;
2194 }
2195
2196 /* For small just reuse existing skb for next receive */
2197 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2198 const struct rx_ring_info *re,
2199 unsigned length)
2200 {
2201 struct sk_buff *skb;
2202
2203 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2204 if (likely(skb)) {
2205 skb_reserve(skb, 2);
2206 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2207 length, PCI_DMA_FROMDEVICE);
2208 skb_copy_from_linear_data(re->skb, skb->data, length);
2209 skb->ip_summed = re->skb->ip_summed;
2210 skb->csum = re->skb->csum;
2211 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2212 length, PCI_DMA_FROMDEVICE);
2213 re->skb->ip_summed = CHECKSUM_NONE;
2214 skb_put(skb, length);
2215 }
2216 return skb;
2217 }
2218
2219 /* Adjust length of skb with fragments to match received data */
2220 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2221 unsigned int length)
2222 {
2223 int i, num_frags;
2224 unsigned int size;
2225
2226 /* put header into skb */
2227 size = min(length, hdr_space);
2228 skb->tail += size;
2229 skb->len += size;
2230 length -= size;
2231
2232 num_frags = skb_shinfo(skb)->nr_frags;
2233 for (i = 0; i < num_frags; i++) {
2234 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2235
2236 if (length == 0) {
2237 /* don't need this page */
2238 __free_page(frag->page);
2239 --skb_shinfo(skb)->nr_frags;
2240 } else {
2241 size = min(length, (unsigned) PAGE_SIZE);
2242
2243 frag->size = size;
2244 skb->data_len += size;
2245 skb->truesize += size;
2246 skb->len += size;
2247 length -= size;
2248 }
2249 }
2250 }
2251
2252 /* Normal packet - take skb from ring element and put in a new one */
2253 static struct sk_buff *receive_new(struct sky2_port *sky2,
2254 struct rx_ring_info *re,
2255 unsigned int length)
2256 {
2257 struct sk_buff *skb, *nskb;
2258 unsigned hdr_space = sky2->rx_data_size;
2259
2260 /* Don't be tricky about reusing pages (yet) */
2261 nskb = sky2_rx_alloc(sky2);
2262 if (unlikely(!nskb))
2263 return NULL;
2264
2265 skb = re->skb;
2266 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2267
2268 prefetch(skb->data);
2269 re->skb = nskb;
2270 if (sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space)) {
2271 dev_kfree_skb(nskb);
2272 re->skb = skb;
2273 return NULL;
2274 }
2275
2276 if (skb_shinfo(skb)->nr_frags)
2277 skb_put_frags(skb, hdr_space, length);
2278 else
2279 skb_put(skb, length);
2280 return skb;
2281 }
2282
2283 /*
2284 * Receive one packet.
2285 * For larger packets, get new buffer.
2286 */
2287 static struct sk_buff *sky2_receive(struct net_device *dev,
2288 u16 length, u32 status)
2289 {
2290 struct sky2_port *sky2 = netdev_priv(dev);
2291 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2292 struct sk_buff *skb = NULL;
2293 u16 count = (status & GMR_FS_LEN) >> 16;
2294
2295 #ifdef SKY2_VLAN_TAG_USED
2296 /* Account for vlan tag */
2297 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2298 count -= VLAN_HLEN;
2299 #endif
2300
2301 if (unlikely(netif_msg_rx_status(sky2)))
2302 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2303 dev->name, sky2->rx_next, status, length);
2304
2305 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2306 prefetch(sky2->rx_ring + sky2->rx_next);
2307
2308 /* This chip has hardware problems that generates bogus status.
2309 * So do only marginal checking and expect higher level protocols
2310 * to handle crap frames.
2311 */
2312 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2313 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2314 length != count)
2315 goto okay;
2316
2317 if (status & GMR_FS_ANY_ERR)
2318 goto error;
2319
2320 if (!(status & GMR_FS_RX_OK))
2321 goto resubmit;
2322
2323 /* if length reported by DMA does not match PHY, packet was truncated */
2324 if (length != count)
2325 goto len_error;
2326
2327 okay:
2328 if (length < copybreak)
2329 skb = receive_copy(sky2, re, length);
2330 else
2331 skb = receive_new(sky2, re, length);
2332 resubmit:
2333 sky2_rx_submit(sky2, re);
2334
2335 return skb;
2336
2337 len_error:
2338 /* Truncation of overlength packets
2339 causes PHY length to not match MAC length */
2340 ++dev->stats.rx_length_errors;
2341 if (netif_msg_rx_err(sky2) && net_ratelimit())
2342 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2343 dev->name, status, length);
2344 goto resubmit;
2345
2346 error:
2347 ++dev->stats.rx_errors;
2348 if (status & GMR_FS_RX_FF_OV) {
2349 dev->stats.rx_over_errors++;
2350 goto resubmit;
2351 }
2352
2353 if (netif_msg_rx_err(sky2) && net_ratelimit())
2354 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2355 dev->name, status, length);
2356
2357 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2358 dev->stats.rx_length_errors++;
2359 if (status & GMR_FS_FRAGMENT)
2360 dev->stats.rx_frame_errors++;
2361 if (status & GMR_FS_CRC_ERR)
2362 dev->stats.rx_crc_errors++;
2363
2364 goto resubmit;
2365 }
2366
2367 /* Transmit complete */
2368 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2369 {
2370 struct sky2_port *sky2 = netdev_priv(dev);
2371
2372 if (likely(netif_running(dev) && !sky2->restarting)) {
2373 netif_tx_lock(dev);
2374 sky2_tx_complete(sky2, last);
2375 netif_tx_unlock(dev);
2376 }
2377 }
2378
2379 static inline void sky2_skb_rx(const struct sky2_port *sky2,
2380 u32 status, struct sk_buff *skb)
2381 {
2382 #ifdef SKY2_VLAN_TAG_USED
2383 u16 vlan_tag = be16_to_cpu(sky2->rx_tag);
2384 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2385 if (skb->ip_summed == CHECKSUM_NONE)
2386 vlan_hwaccel_receive_skb(skb, sky2->vlgrp, vlan_tag);
2387 else
2388 vlan_gro_receive(&sky2->hw->napi, sky2->vlgrp,
2389 vlan_tag, skb);
2390 return;
2391 }
2392 #endif
2393 if (skb->ip_summed == CHECKSUM_NONE)
2394 netif_receive_skb(skb);
2395 else
2396 napi_gro_receive(&sky2->hw->napi, skb);
2397 }
2398
2399 static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2400 unsigned packets, unsigned bytes)
2401 {
2402 if (packets) {
2403 struct net_device *dev = hw->dev[port];
2404
2405 dev->stats.rx_packets += packets;
2406 dev->stats.rx_bytes += bytes;
2407 dev->last_rx = jiffies;
2408 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2409 }
2410 }
2411
2412 /* Process status response ring */
2413 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2414 {
2415 int work_done = 0;
2416 unsigned int total_bytes[2] = { 0 };
2417 unsigned int total_packets[2] = { 0 };
2418
2419 rmb();
2420 do {
2421 struct sky2_port *sky2;
2422 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2423 unsigned port;
2424 struct net_device *dev;
2425 struct sk_buff *skb;
2426 u32 status;
2427 u16 length;
2428 u8 opcode = le->opcode;
2429
2430 if (!(opcode & HW_OWNER))
2431 break;
2432
2433 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2434
2435 port = le->css & CSS_LINK_BIT;
2436 dev = hw->dev[port];
2437 sky2 = netdev_priv(dev);
2438 length = le16_to_cpu(le->length);
2439 status = le32_to_cpu(le->status);
2440
2441 le->opcode = 0;
2442 switch (opcode & ~HW_OWNER) {
2443 case OP_RXSTAT:
2444 total_packets[port]++;
2445 total_bytes[port] += length;
2446 skb = sky2_receive(dev, length, status);
2447 if (unlikely(!skb)) {
2448 dev->stats.rx_dropped++;
2449 break;
2450 }
2451
2452 /* This chip reports checksum status differently */
2453 if (hw->flags & SKY2_HW_NEW_LE) {
2454 if (sky2->rx_csum &&
2455 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2456 (le->css & CSS_TCPUDPCSOK))
2457 skb->ip_summed = CHECKSUM_UNNECESSARY;
2458 else
2459 skb->ip_summed = CHECKSUM_NONE;
2460 }
2461
2462 skb->protocol = eth_type_trans(skb, dev);
2463
2464 sky2_skb_rx(sky2, status, skb);
2465
2466 /* Stop after net poll weight */
2467 if (++work_done >= to_do)
2468 goto exit_loop;
2469 break;
2470
2471 #ifdef SKY2_VLAN_TAG_USED
2472 case OP_RXVLAN:
2473 sky2->rx_tag = length;
2474 break;
2475
2476 case OP_RXCHKSVLAN:
2477 sky2->rx_tag = length;
2478 /* fall through */
2479 #endif
2480 case OP_RXCHKS:
2481 if (!sky2->rx_csum)
2482 break;
2483
2484 /* If this happens then driver assuming wrong format */
2485 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2486 if (net_ratelimit())
2487 printk(KERN_NOTICE "%s: unexpected"
2488 " checksum status\n",
2489 dev->name);
2490 break;
2491 }
2492
2493 /* Both checksum counters are programmed to start at
2494 * the same offset, so unless there is a problem they
2495 * should match. This failure is an early indication that
2496 * hardware receive checksumming won't work.
2497 */
2498 if (likely(status >> 16 == (status & 0xffff))) {
2499 skb = sky2->rx_ring[sky2->rx_next].skb;
2500 skb->ip_summed = CHECKSUM_COMPLETE;
2501 skb->csum = le16_to_cpu(status);
2502 } else {
2503 printk(KERN_NOTICE PFX "%s: hardware receive "
2504 "checksum problem (status = %#x)\n",
2505 dev->name, status);
2506 sky2->rx_csum = 0;
2507 sky2_write32(sky2->hw,
2508 Q_ADDR(rxqaddr[port], Q_CSR),
2509 BMU_DIS_RX_CHKSUM);
2510 }
2511 break;
2512
2513 case OP_TXINDEXLE:
2514 /* TX index reports status for both ports */
2515 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2516 sky2_tx_done(hw->dev[0], status & 0xfff);
2517 if (hw->dev[1])
2518 sky2_tx_done(hw->dev[1],
2519 ((status >> 24) & 0xff)
2520 | (u16)(length & 0xf) << 8);
2521 break;
2522
2523 default:
2524 if (net_ratelimit())
2525 printk(KERN_WARNING PFX
2526 "unknown status opcode 0x%x\n", opcode);
2527 }
2528 } while (hw->st_idx != idx);
2529
2530 /* Fully processed status ring so clear irq */
2531 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2532
2533 exit_loop:
2534 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2535 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
2536
2537 return work_done;
2538 }
2539
2540 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2541 {
2542 struct net_device *dev = hw->dev[port];
2543
2544 if (net_ratelimit())
2545 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2546 dev->name, status);
2547
2548 if (status & Y2_IS_PAR_RD1) {
2549 if (net_ratelimit())
2550 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2551 dev->name);
2552 /* Clear IRQ */
2553 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2554 }
2555
2556 if (status & Y2_IS_PAR_WR1) {
2557 if (net_ratelimit())
2558 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2559 dev->name);
2560
2561 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2562 }
2563
2564 if (status & Y2_IS_PAR_MAC1) {
2565 if (net_ratelimit())
2566 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2567 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2568 }
2569
2570 if (status & Y2_IS_PAR_RX1) {
2571 if (net_ratelimit())
2572 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2573 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2574 }
2575
2576 if (status & Y2_IS_TCP_TXA1) {
2577 if (net_ratelimit())
2578 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2579 dev->name);
2580 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2581 }
2582 }
2583
2584 static void sky2_hw_intr(struct sky2_hw *hw)
2585 {
2586 struct pci_dev *pdev = hw->pdev;
2587 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2588 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2589
2590 status &= hwmsk;
2591
2592 if (status & Y2_IS_TIST_OV)
2593 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2594
2595 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2596 u16 pci_err;
2597
2598 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2599 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2600 if (net_ratelimit())
2601 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2602 pci_err);
2603
2604 sky2_pci_write16(hw, PCI_STATUS,
2605 pci_err | PCI_STATUS_ERROR_BITS);
2606 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2607 }
2608
2609 if (status & Y2_IS_PCI_EXP) {
2610 /* PCI-Express uncorrectable Error occurred */
2611 u32 err;
2612
2613 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2614 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2615 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2616 0xfffffffful);
2617 if (net_ratelimit())
2618 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2619
2620 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2621 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2622 }
2623
2624 if (status & Y2_HWE_L1_MASK)
2625 sky2_hw_error(hw, 0, status);
2626 status >>= 8;
2627 if (status & Y2_HWE_L1_MASK)
2628 sky2_hw_error(hw, 1, status);
2629 }
2630
2631 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2632 {
2633 struct net_device *dev = hw->dev[port];
2634 struct sky2_port *sky2 = netdev_priv(dev);
2635 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2636
2637 if (netif_msg_intr(sky2))
2638 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2639 dev->name, status);
2640
2641 if (status & GM_IS_RX_CO_OV)
2642 gma_read16(hw, port, GM_RX_IRQ_SRC);
2643
2644 if (status & GM_IS_TX_CO_OV)
2645 gma_read16(hw, port, GM_TX_IRQ_SRC);
2646
2647 if (status & GM_IS_RX_FF_OR) {
2648 ++dev->stats.rx_fifo_errors;
2649 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2650 }
2651
2652 if (status & GM_IS_TX_FF_UR) {
2653 ++dev->stats.tx_fifo_errors;
2654 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2655 }
2656 }
2657
2658 /* This should never happen it is a bug. */
2659 static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2660 u16 q, unsigned ring_size)
2661 {
2662 struct net_device *dev = hw->dev[port];
2663 struct sky2_port *sky2 = netdev_priv(dev);
2664 unsigned idx;
2665 const u64 *le = (q == Q_R1 || q == Q_R2)
2666 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
2667
2668 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2669 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2670 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2671 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2672
2673 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2674 }
2675
2676 static int sky2_rx_hung(struct net_device *dev)
2677 {
2678 struct sky2_port *sky2 = netdev_priv(dev);
2679 struct sky2_hw *hw = sky2->hw;
2680 unsigned port = sky2->port;
2681 unsigned rxq = rxqaddr[port];
2682 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2683 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2684 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2685 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2686
2687 /* If idle and MAC or PCI is stuck */
2688 if (sky2->check.last == dev->last_rx &&
2689 ((mac_rp == sky2->check.mac_rp &&
2690 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2691 /* Check if the PCI RX hang */
2692 (fifo_rp == sky2->check.fifo_rp &&
2693 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2694 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2695 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2696 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2697 return 1;
2698 } else {
2699 sky2->check.last = dev->last_rx;
2700 sky2->check.mac_rp = mac_rp;
2701 sky2->check.mac_lev = mac_lev;
2702 sky2->check.fifo_rp = fifo_rp;
2703 sky2->check.fifo_lev = fifo_lev;
2704 return 0;
2705 }
2706 }
2707
2708 static void sky2_watchdog(unsigned long arg)
2709 {
2710 struct sky2_hw *hw = (struct sky2_hw *) arg;
2711
2712 /* Check for lost IRQ once a second */
2713 if (sky2_read32(hw, B0_ISRC)) {
2714 napi_schedule(&hw->napi);
2715 } else {
2716 int i, active = 0;
2717
2718 for (i = 0; i < hw->ports; i++) {
2719 struct net_device *dev = hw->dev[i];
2720 if (!netif_running(dev))
2721 continue;
2722 ++active;
2723
2724 /* For chips with Rx FIFO, check if stuck */
2725 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
2726 sky2_rx_hung(dev)) {
2727 pr_info(PFX "%s: receiver hang detected\n",
2728 dev->name);
2729 schedule_work(&hw->restart_work);
2730 return;
2731 }
2732 }
2733
2734 if (active == 0)
2735 return;
2736 }
2737
2738 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2739 }
2740
2741 /* Hardware/software error handling */
2742 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2743 {
2744 if (net_ratelimit())
2745 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2746
2747 if (status & Y2_IS_HW_ERR)
2748 sky2_hw_intr(hw);
2749
2750 if (status & Y2_IS_IRQ_MAC1)
2751 sky2_mac_intr(hw, 0);
2752
2753 if (status & Y2_IS_IRQ_MAC2)
2754 sky2_mac_intr(hw, 1);
2755
2756 if (status & Y2_IS_CHK_RX1)
2757 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
2758
2759 if (status & Y2_IS_CHK_RX2)
2760 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
2761
2762 if (status & Y2_IS_CHK_TXA1)
2763 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
2764
2765 if (status & Y2_IS_CHK_TXA2)
2766 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2767 }
2768
2769 static int sky2_poll(struct napi_struct *napi, int work_limit)
2770 {
2771 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
2772 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2773 int work_done = 0;
2774 u16 idx;
2775
2776 if (unlikely(status & Y2_IS_ERROR))
2777 sky2_err_intr(hw, status);
2778
2779 if (status & Y2_IS_IRQ_PHY1)
2780 sky2_phy_intr(hw, 0);
2781
2782 if (status & Y2_IS_IRQ_PHY2)
2783 sky2_phy_intr(hw, 1);
2784
2785 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2786 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
2787
2788 if (work_done >= work_limit)
2789 goto done;
2790 }
2791
2792 napi_complete(napi);
2793 sky2_read32(hw, B0_Y2_SP_LISR);
2794 done:
2795
2796 return work_done;
2797 }
2798
2799 static irqreturn_t sky2_intr(int irq, void *dev_id)
2800 {
2801 struct sky2_hw *hw = dev_id;
2802 u32 status;
2803
2804 /* Reading this mask interrupts as side effect */
2805 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2806 if (status == 0 || status == ~0)
2807 return IRQ_NONE;
2808
2809 prefetch(&hw->st_le[hw->st_idx]);
2810
2811 napi_schedule(&hw->napi);
2812
2813 return IRQ_HANDLED;
2814 }
2815
2816 #ifdef CONFIG_NET_POLL_CONTROLLER
2817 static void sky2_netpoll(struct net_device *dev)
2818 {
2819 struct sky2_port *sky2 = netdev_priv(dev);
2820
2821 napi_schedule(&sky2->hw->napi);
2822 }
2823 #endif
2824
2825 /* Chip internal frequency for clock calculations */
2826 static u32 sky2_mhz(const struct sky2_hw *hw)
2827 {
2828 switch (hw->chip_id) {
2829 case CHIP_ID_YUKON_EC:
2830 case CHIP_ID_YUKON_EC_U:
2831 case CHIP_ID_YUKON_EX:
2832 case CHIP_ID_YUKON_SUPR:
2833 case CHIP_ID_YUKON_UL_2:
2834 return 125;
2835
2836 case CHIP_ID_YUKON_FE:
2837 return 100;
2838
2839 case CHIP_ID_YUKON_FE_P:
2840 return 50;
2841
2842 case CHIP_ID_YUKON_XL:
2843 return 156;
2844
2845 default:
2846 BUG();
2847 }
2848 }
2849
2850 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2851 {
2852 return sky2_mhz(hw) * us;
2853 }
2854
2855 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2856 {
2857 return clk / sky2_mhz(hw);
2858 }
2859
2860
2861 static int __devinit sky2_init(struct sky2_hw *hw)
2862 {
2863 u8 t8;
2864
2865 /* Enable all clocks and check for bad PCI access */
2866 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2867
2868 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2869
2870 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2871 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2872
2873 switch(hw->chip_id) {
2874 case CHIP_ID_YUKON_XL:
2875 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
2876 break;
2877
2878 case CHIP_ID_YUKON_EC_U:
2879 hw->flags = SKY2_HW_GIGABIT
2880 | SKY2_HW_NEWER_PHY
2881 | SKY2_HW_ADV_POWER_CTL;
2882 break;
2883
2884 case CHIP_ID_YUKON_EX:
2885 hw->flags = SKY2_HW_GIGABIT
2886 | SKY2_HW_NEWER_PHY
2887 | SKY2_HW_NEW_LE
2888 | SKY2_HW_ADV_POWER_CTL;
2889
2890 /* New transmit checksum */
2891 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2892 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2893 break;
2894
2895 case CHIP_ID_YUKON_EC:
2896 /* This rev is really old, and requires untested workarounds */
2897 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2898 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2899 return -EOPNOTSUPP;
2900 }
2901 hw->flags = SKY2_HW_GIGABIT;
2902 break;
2903
2904 case CHIP_ID_YUKON_FE:
2905 break;
2906
2907 case CHIP_ID_YUKON_FE_P:
2908 hw->flags = SKY2_HW_NEWER_PHY
2909 | SKY2_HW_NEW_LE
2910 | SKY2_HW_AUTO_TX_SUM
2911 | SKY2_HW_ADV_POWER_CTL;
2912 break;
2913
2914 case CHIP_ID_YUKON_SUPR:
2915 hw->flags = SKY2_HW_GIGABIT
2916 | SKY2_HW_NEWER_PHY
2917 | SKY2_HW_NEW_LE
2918 | SKY2_HW_AUTO_TX_SUM
2919 | SKY2_HW_ADV_POWER_CTL;
2920 break;
2921
2922 case CHIP_ID_YUKON_UL_2:
2923 hw->flags = SKY2_HW_GIGABIT
2924 | SKY2_HW_ADV_POWER_CTL;
2925 break;
2926
2927 default:
2928 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2929 hw->chip_id);
2930 return -EOPNOTSUPP;
2931 }
2932
2933 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2934 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2935 hw->flags |= SKY2_HW_FIBRE_PHY;
2936
2937 hw->ports = 1;
2938 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2939 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2940 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2941 ++hw->ports;
2942 }
2943
2944 if (sky2_read8(hw, B2_E_0))
2945 hw->flags |= SKY2_HW_RAM_BUFFER;
2946
2947 return 0;
2948 }
2949
2950 static void sky2_reset(struct sky2_hw *hw)
2951 {
2952 struct pci_dev *pdev = hw->pdev;
2953 u16 status;
2954 int i, cap;
2955 u32 hwe_mask = Y2_HWE_ALL_MASK;
2956
2957 /* disable ASF */
2958 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2959 status = sky2_read16(hw, HCU_CCSR);
2960 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2961 HCU_CCSR_UC_STATE_MSK);
2962 sky2_write16(hw, HCU_CCSR, status);
2963 } else
2964 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2965 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2966
2967 /* do a SW reset */
2968 sky2_write8(hw, B0_CTST, CS_RST_SET);
2969 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2970
2971 /* allow writes to PCI config */
2972 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2973
2974 /* clear PCI errors, if any */
2975 status = sky2_pci_read16(hw, PCI_STATUS);
2976 status |= PCI_STATUS_ERROR_BITS;
2977 sky2_pci_write16(hw, PCI_STATUS, status);
2978
2979 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2980
2981 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2982 if (cap) {
2983 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2984 0xfffffffful);
2985
2986 /* If error bit is stuck on ignore it */
2987 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2988 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
2989 else
2990 hwe_mask |= Y2_IS_PCI_EXP;
2991 }
2992
2993 sky2_power_on(hw);
2994 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2995
2996 for (i = 0; i < hw->ports; i++) {
2997 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2998 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2999
3000 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3001 hw->chip_id == CHIP_ID_YUKON_SUPR)
3002 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3003 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3004 | GMC_BYP_RETR_ON);
3005 }
3006
3007 /* Clear I2C IRQ noise */
3008 sky2_write32(hw, B2_I2C_IRQ, 1);
3009
3010 /* turn off hardware timer (unused) */
3011 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3012 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3013
3014 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
3015
3016 /* Turn off descriptor polling */
3017 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
3018
3019 /* Turn off receive timestamp */
3020 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
3021 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3022
3023 /* enable the Tx Arbiters */
3024 for (i = 0; i < hw->ports; i++)
3025 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3026
3027 /* Initialize ram interface */
3028 for (i = 0; i < hw->ports; i++) {
3029 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
3030
3031 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3032 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3033 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3034 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3035 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3036 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3037 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3038 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3039 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3040 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3041 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3042 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3043 }
3044
3045 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
3046
3047 for (i = 0; i < hw->ports; i++)
3048 sky2_gmac_reset(hw, i);
3049
3050 memset(hw->st_le, 0, STATUS_LE_BYTES);
3051 hw->st_idx = 0;
3052
3053 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3054 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3055
3056 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
3057 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
3058
3059 /* Set the list last index */
3060 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
3061
3062 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3063 sky2_write8(hw, STAT_FIFO_WM, 16);
3064
3065 /* set Status-FIFO ISR watermark */
3066 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3067 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3068 else
3069 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
3070
3071 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
3072 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3073 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
3074
3075 /* enable status unit */
3076 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3077
3078 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3079 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3080 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3081 }
3082
3083 static void sky2_restart(struct work_struct *work)
3084 {
3085 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3086 struct net_device *dev;
3087 int i, err;
3088
3089 rtnl_lock();
3090 for (i = 0; i < hw->ports; i++) {
3091 dev = hw->dev[i];
3092 if (netif_running(dev))
3093 sky2_down(dev);
3094 }
3095
3096 napi_disable(&hw->napi);
3097 sky2_write32(hw, B0_IMSK, 0);
3098 sky2_reset(hw);
3099 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3100 napi_enable(&hw->napi);
3101
3102 for (i = 0; i < hw->ports; i++) {
3103 dev = hw->dev[i];
3104 if (netif_running(dev)) {
3105 err = sky2_up(dev);
3106 if (err) {
3107 printk(KERN_INFO PFX "%s: could not restart %d\n",
3108 dev->name, err);
3109 dev_close(dev);
3110 }
3111 }
3112 }
3113
3114 rtnl_unlock();
3115 }
3116
3117 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3118 {
3119 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3120 }
3121
3122 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3123 {
3124 const struct sky2_port *sky2 = netdev_priv(dev);
3125
3126 wol->supported = sky2_wol_supported(sky2->hw);
3127 wol->wolopts = sky2->wol;
3128 }
3129
3130 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3131 {
3132 struct sky2_port *sky2 = netdev_priv(dev);
3133 struct sky2_hw *hw = sky2->hw;
3134
3135 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw))
3136 || !device_can_wakeup(&hw->pdev->dev))
3137 return -EOPNOTSUPP;
3138
3139 sky2->wol = wol->wolopts;
3140
3141 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3142 hw->chip_id == CHIP_ID_YUKON_EX ||
3143 hw->chip_id == CHIP_ID_YUKON_FE_P)
3144 sky2_write32(hw, B0_CTST, sky2->wol
3145 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
3146
3147 device_set_wakeup_enable(&hw->pdev->dev, sky2->wol);
3148
3149 if (!netif_running(dev))
3150 sky2_wol_init(sky2);
3151 return 0;
3152 }
3153
3154 static u32 sky2_supported_modes(const struct sky2_hw *hw)
3155 {
3156 if (sky2_is_copper(hw)) {
3157 u32 modes = SUPPORTED_10baseT_Half
3158 | SUPPORTED_10baseT_Full
3159 | SUPPORTED_100baseT_Half
3160 | SUPPORTED_100baseT_Full
3161 | SUPPORTED_Autoneg | SUPPORTED_TP;
3162
3163 if (hw->flags & SKY2_HW_GIGABIT)
3164 modes |= SUPPORTED_1000baseT_Half
3165 | SUPPORTED_1000baseT_Full;
3166 return modes;
3167 } else
3168 return SUPPORTED_1000baseT_Half
3169 | SUPPORTED_1000baseT_Full
3170 | SUPPORTED_Autoneg
3171 | SUPPORTED_FIBRE;
3172 }
3173
3174 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3175 {
3176 struct sky2_port *sky2 = netdev_priv(dev);
3177 struct sky2_hw *hw = sky2->hw;
3178
3179 ecmd->transceiver = XCVR_INTERNAL;
3180 ecmd->supported = sky2_supported_modes(hw);
3181 ecmd->phy_address = PHY_ADDR_MARV;
3182 if (sky2_is_copper(hw)) {
3183 ecmd->port = PORT_TP;
3184 ecmd->speed = sky2->speed;
3185 } else {
3186 ecmd->speed = SPEED_1000;
3187 ecmd->port = PORT_FIBRE;
3188 }
3189
3190 ecmd->advertising = sky2->advertising;
3191 ecmd->autoneg = sky2->autoneg;
3192 ecmd->duplex = sky2->duplex;
3193 return 0;
3194 }
3195
3196 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3197 {
3198 struct sky2_port *sky2 = netdev_priv(dev);
3199 const struct sky2_hw *hw = sky2->hw;
3200 u32 supported = sky2_supported_modes(hw);
3201
3202 if (ecmd->autoneg == AUTONEG_ENABLE) {
3203 ecmd->advertising = supported;
3204 sky2->duplex = -1;
3205 sky2->speed = -1;
3206 } else {
3207 u32 setting;
3208
3209 switch (ecmd->speed) {
3210 case SPEED_1000:
3211 if (ecmd->duplex == DUPLEX_FULL)
3212 setting = SUPPORTED_1000baseT_Full;
3213 else if (ecmd->duplex == DUPLEX_HALF)
3214 setting = SUPPORTED_1000baseT_Half;
3215 else
3216 return -EINVAL;
3217 break;
3218 case SPEED_100:
3219 if (ecmd->duplex == DUPLEX_FULL)
3220 setting = SUPPORTED_100baseT_Full;
3221 else if (ecmd->duplex == DUPLEX_HALF)
3222 setting = SUPPORTED_100baseT_Half;
3223 else
3224 return -EINVAL;
3225 break;
3226
3227 case SPEED_10:
3228 if (ecmd->duplex == DUPLEX_FULL)
3229 setting = SUPPORTED_10baseT_Full;
3230 else if (ecmd->duplex == DUPLEX_HALF)
3231 setting = SUPPORTED_10baseT_Half;
3232 else
3233 return -EINVAL;
3234 break;
3235 default:
3236 return -EINVAL;
3237 }
3238
3239 if ((setting & supported) == 0)
3240 return -EINVAL;
3241
3242 sky2->speed = ecmd->speed;
3243 sky2->duplex = ecmd->duplex;
3244 }
3245
3246 sky2->autoneg = ecmd->autoneg;
3247 sky2->advertising = ecmd->advertising;
3248
3249 if (netif_running(dev)) {
3250 sky2_phy_reinit(sky2);
3251 sky2_set_multicast(dev);
3252 }
3253
3254 return 0;
3255 }
3256
3257 static void sky2_get_drvinfo(struct net_device *dev,
3258 struct ethtool_drvinfo *info)
3259 {
3260 struct sky2_port *sky2 = netdev_priv(dev);
3261
3262 strcpy(info->driver, DRV_NAME);
3263 strcpy(info->version, DRV_VERSION);
3264 strcpy(info->fw_version, "N/A");
3265 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3266 }
3267
3268 static const struct sky2_stat {
3269 char name[ETH_GSTRING_LEN];
3270 u16 offset;
3271 } sky2_stats[] = {
3272 { "tx_bytes", GM_TXO_OK_HI },
3273 { "rx_bytes", GM_RXO_OK_HI },
3274 { "tx_broadcast", GM_TXF_BC_OK },
3275 { "rx_broadcast", GM_RXF_BC_OK },
3276 { "tx_multicast", GM_TXF_MC_OK },
3277 { "rx_multicast", GM_RXF_MC_OK },
3278 { "tx_unicast", GM_TXF_UC_OK },
3279 { "rx_unicast", GM_RXF_UC_OK },
3280 { "tx_mac_pause", GM_TXF_MPAUSE },
3281 { "rx_mac_pause", GM_RXF_MPAUSE },
3282 { "collisions", GM_TXF_COL },
3283 { "late_collision",GM_TXF_LAT_COL },
3284 { "aborted", GM_TXF_ABO_COL },
3285 { "single_collisions", GM_TXF_SNG_COL },
3286 { "multi_collisions", GM_TXF_MUL_COL },
3287
3288 { "rx_short", GM_RXF_SHT },
3289 { "rx_runt", GM_RXE_FRAG },
3290 { "rx_64_byte_packets", GM_RXF_64B },
3291 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3292 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3293 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3294 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3295 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3296 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3297 { "rx_too_long", GM_RXF_LNG_ERR },
3298 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3299 { "rx_jabber", GM_RXF_JAB_PKT },
3300 { "rx_fcs_error", GM_RXF_FCS_ERR },
3301
3302 { "tx_64_byte_packets", GM_TXF_64B },
3303 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3304 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3305 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3306 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3307 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3308 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3309 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3310 };
3311
3312 static u32 sky2_get_rx_csum(struct net_device *dev)
3313 {
3314 struct sky2_port *sky2 = netdev_priv(dev);
3315
3316 return sky2->rx_csum;
3317 }
3318
3319 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3320 {
3321 struct sky2_port *sky2 = netdev_priv(dev);
3322
3323 sky2->rx_csum = data;
3324
3325 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3326 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3327
3328 return 0;
3329 }
3330
3331 static u32 sky2_get_msglevel(struct net_device *netdev)
3332 {
3333 struct sky2_port *sky2 = netdev_priv(netdev);
3334 return sky2->msg_enable;
3335 }
3336
3337 static int sky2_nway_reset(struct net_device *dev)
3338 {
3339 struct sky2_port *sky2 = netdev_priv(dev);
3340
3341 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
3342 return -EINVAL;
3343
3344 sky2_phy_reinit(sky2);
3345 sky2_set_multicast(dev);
3346
3347 return 0;
3348 }
3349
3350 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3351 {
3352 struct sky2_hw *hw = sky2->hw;
3353 unsigned port = sky2->port;
3354 int i;
3355
3356 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
3357 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
3358 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
3359 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
3360
3361 for (i = 2; i < count; i++)
3362 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3363 }
3364
3365 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3366 {
3367 struct sky2_port *sky2 = netdev_priv(netdev);
3368 sky2->msg_enable = value;
3369 }
3370
3371 static int sky2_get_sset_count(struct net_device *dev, int sset)
3372 {
3373 switch (sset) {
3374 case ETH_SS_STATS:
3375 return ARRAY_SIZE(sky2_stats);
3376 default:
3377 return -EOPNOTSUPP;
3378 }
3379 }
3380
3381 static void sky2_get_ethtool_stats(struct net_device *dev,
3382 struct ethtool_stats *stats, u64 * data)
3383 {
3384 struct sky2_port *sky2 = netdev_priv(dev);
3385
3386 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3387 }
3388
3389 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3390 {
3391 int i;
3392
3393 switch (stringset) {
3394 case ETH_SS_STATS:
3395 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3396 memcpy(data + i * ETH_GSTRING_LEN,
3397 sky2_stats[i].name, ETH_GSTRING_LEN);
3398 break;
3399 }
3400 }
3401
3402 static int sky2_set_mac_address(struct net_device *dev, void *p)
3403 {
3404 struct sky2_port *sky2 = netdev_priv(dev);
3405 struct sky2_hw *hw = sky2->hw;
3406 unsigned port = sky2->port;
3407 const struct sockaddr *addr = p;
3408
3409 if (!is_valid_ether_addr(addr->sa_data))
3410 return -EADDRNOTAVAIL;
3411
3412 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3413 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3414 dev->dev_addr, ETH_ALEN);
3415 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3416 dev->dev_addr, ETH_ALEN);
3417
3418 /* virtual address for data */
3419 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3420
3421 /* physical address: used for pause frames */
3422 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3423
3424 return 0;
3425 }
3426
3427 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3428 {
3429 u32 bit;
3430
3431 bit = ether_crc(ETH_ALEN, addr) & 63;
3432 filter[bit >> 3] |= 1 << (bit & 7);
3433 }
3434
3435 static void sky2_set_multicast(struct net_device *dev)
3436 {
3437 struct sky2_port *sky2 = netdev_priv(dev);
3438 struct sky2_hw *hw = sky2->hw;
3439 unsigned port = sky2->port;
3440 struct dev_mc_list *list = dev->mc_list;
3441 u16 reg;
3442 u8 filter[8];
3443 int rx_pause;
3444 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3445
3446 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3447 memset(filter, 0, sizeof(filter));
3448
3449 reg = gma_read16(hw, port, GM_RX_CTRL);
3450 reg |= GM_RXCR_UCF_ENA;
3451
3452 if (dev->flags & IFF_PROMISC) /* promiscuous */
3453 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3454 else if (dev->flags & IFF_ALLMULTI)
3455 memset(filter, 0xff, sizeof(filter));
3456 else if (dev->mc_count == 0 && !rx_pause)
3457 reg &= ~GM_RXCR_MCF_ENA;
3458 else {
3459 int i;
3460 reg |= GM_RXCR_MCF_ENA;
3461
3462 if (rx_pause)
3463 sky2_add_filter(filter, pause_mc_addr);
3464
3465 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3466 sky2_add_filter(filter, list->dmi_addr);
3467 }
3468
3469 gma_write16(hw, port, GM_MC_ADDR_H1,
3470 (u16) filter[0] | ((u16) filter[1] << 8));
3471 gma_write16(hw, port, GM_MC_ADDR_H2,
3472 (u16) filter[2] | ((u16) filter[3] << 8));
3473 gma_write16(hw, port, GM_MC_ADDR_H3,
3474 (u16) filter[4] | ((u16) filter[5] << 8));
3475 gma_write16(hw, port, GM_MC_ADDR_H4,
3476 (u16) filter[6] | ((u16) filter[7] << 8));
3477
3478 gma_write16(hw, port, GM_RX_CTRL, reg);
3479 }
3480
3481 /* Can have one global because blinking is controlled by
3482 * ethtool and that is always under RTNL mutex
3483 */
3484 static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
3485 {
3486 struct sky2_hw *hw = sky2->hw;
3487 unsigned port = sky2->port;
3488
3489 spin_lock_bh(&sky2->phy_lock);
3490 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3491 hw->chip_id == CHIP_ID_YUKON_EX ||
3492 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3493 u16 pg;
3494 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3495 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3496
3497 switch (mode) {
3498 case MO_LED_OFF:
3499 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3500 PHY_M_LEDC_LOS_CTRL(8) |
3501 PHY_M_LEDC_INIT_CTRL(8) |
3502 PHY_M_LEDC_STA1_CTRL(8) |
3503 PHY_M_LEDC_STA0_CTRL(8));
3504 break;
3505 case MO_LED_ON:
3506 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3507 PHY_M_LEDC_LOS_CTRL(9) |
3508 PHY_M_LEDC_INIT_CTRL(9) |
3509 PHY_M_LEDC_STA1_CTRL(9) |
3510 PHY_M_LEDC_STA0_CTRL(9));
3511 break;
3512 case MO_LED_BLINK:
3513 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3514 PHY_M_LEDC_LOS_CTRL(0xa) |
3515 PHY_M_LEDC_INIT_CTRL(0xa) |
3516 PHY_M_LEDC_STA1_CTRL(0xa) |
3517 PHY_M_LEDC_STA0_CTRL(0xa));
3518 break;
3519 case MO_LED_NORM:
3520 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3521 PHY_M_LEDC_LOS_CTRL(1) |
3522 PHY_M_LEDC_INIT_CTRL(8) |
3523 PHY_M_LEDC_STA1_CTRL(7) |
3524 PHY_M_LEDC_STA0_CTRL(7));
3525 }
3526
3527 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3528 } else
3529 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3530 PHY_M_LED_MO_DUP(mode) |
3531 PHY_M_LED_MO_10(mode) |
3532 PHY_M_LED_MO_100(mode) |
3533 PHY_M_LED_MO_1000(mode) |
3534 PHY_M_LED_MO_RX(mode) |
3535 PHY_M_LED_MO_TX(mode));
3536
3537 spin_unlock_bh(&sky2->phy_lock);
3538 }
3539
3540 /* blink LED's for finding board */
3541 static int sky2_phys_id(struct net_device *dev, u32 data)
3542 {
3543 struct sky2_port *sky2 = netdev_priv(dev);
3544 unsigned int i;
3545
3546 if (data == 0)
3547 data = UINT_MAX;
3548
3549 for (i = 0; i < data; i++) {
3550 sky2_led(sky2, MO_LED_ON);
3551 if (msleep_interruptible(500))
3552 break;
3553 sky2_led(sky2, MO_LED_OFF);
3554 if (msleep_interruptible(500))
3555 break;
3556 }
3557 sky2_led(sky2, MO_LED_NORM);
3558
3559 return 0;
3560 }
3561
3562 static void sky2_get_pauseparam(struct net_device *dev,
3563 struct ethtool_pauseparam *ecmd)
3564 {
3565 struct sky2_port *sky2 = netdev_priv(dev);
3566
3567 switch (sky2->flow_mode) {
3568 case FC_NONE:
3569 ecmd->tx_pause = ecmd->rx_pause = 0;
3570 break;
3571 case FC_TX:
3572 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3573 break;
3574 case FC_RX:
3575 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3576 break;
3577 case FC_BOTH:
3578 ecmd->tx_pause = ecmd->rx_pause = 1;
3579 }
3580
3581 ecmd->autoneg = sky2->autoneg;
3582 }
3583
3584 static int sky2_set_pauseparam(struct net_device *dev,
3585 struct ethtool_pauseparam *ecmd)
3586 {
3587 struct sky2_port *sky2 = netdev_priv(dev);
3588
3589 sky2->autoneg = ecmd->autoneg;
3590 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3591
3592 if (netif_running(dev))
3593 sky2_phy_reinit(sky2);
3594
3595 return 0;
3596 }
3597
3598 static int sky2_get_coalesce(struct net_device *dev,
3599 struct ethtool_coalesce *ecmd)
3600 {
3601 struct sky2_port *sky2 = netdev_priv(dev);
3602 struct sky2_hw *hw = sky2->hw;
3603
3604 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3605 ecmd->tx_coalesce_usecs = 0;
3606 else {
3607 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3608 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3609 }
3610 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3611
3612 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3613 ecmd->rx_coalesce_usecs = 0;
3614 else {
3615 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3616 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3617 }
3618 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3619
3620 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3621 ecmd->rx_coalesce_usecs_irq = 0;
3622 else {
3623 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3624 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3625 }
3626
3627 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3628
3629 return 0;
3630 }
3631
3632 /* Note: this affect both ports */
3633 static int sky2_set_coalesce(struct net_device *dev,
3634 struct ethtool_coalesce *ecmd)
3635 {
3636 struct sky2_port *sky2 = netdev_priv(dev);
3637 struct sky2_hw *hw = sky2->hw;
3638 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3639
3640 if (ecmd->tx_coalesce_usecs > tmax ||
3641 ecmd->rx_coalesce_usecs > tmax ||
3642 ecmd->rx_coalesce_usecs_irq > tmax)
3643 return -EINVAL;
3644
3645 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
3646 return -EINVAL;
3647 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3648 return -EINVAL;
3649 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3650 return -EINVAL;
3651
3652 if (ecmd->tx_coalesce_usecs == 0)
3653 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3654 else {
3655 sky2_write32(hw, STAT_TX_TIMER_INI,
3656 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3657 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3658 }
3659 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3660
3661 if (ecmd->rx_coalesce_usecs == 0)
3662 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3663 else {
3664 sky2_write32(hw, STAT_LEV_TIMER_INI,
3665 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3666 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3667 }
3668 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3669
3670 if (ecmd->rx_coalesce_usecs_irq == 0)
3671 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3672 else {
3673 sky2_write32(hw, STAT_ISR_TIMER_INI,
3674 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3675 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3676 }
3677 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3678 return 0;
3679 }
3680
3681 static void sky2_get_ringparam(struct net_device *dev,
3682 struct ethtool_ringparam *ering)
3683 {
3684 struct sky2_port *sky2 = netdev_priv(dev);
3685
3686 ering->rx_max_pending = RX_MAX_PENDING;
3687 ering->rx_mini_max_pending = 0;
3688 ering->rx_jumbo_max_pending = 0;
3689 ering->tx_max_pending = TX_RING_SIZE - 1;
3690
3691 ering->rx_pending = sky2->rx_pending;
3692 ering->rx_mini_pending = 0;
3693 ering->rx_jumbo_pending = 0;
3694 ering->tx_pending = sky2->tx_pending;
3695 }
3696
3697 static int sky2_set_ringparam(struct net_device *dev,
3698 struct ethtool_ringparam *ering)
3699 {
3700 struct sky2_port *sky2 = netdev_priv(dev);
3701 int err = 0;
3702
3703 if (ering->rx_pending > RX_MAX_PENDING ||
3704 ering->rx_pending < 8 ||
3705 ering->tx_pending < MAX_SKB_TX_LE ||
3706 ering->tx_pending > TX_RING_SIZE - 1)
3707 return -EINVAL;
3708
3709 if (netif_running(dev))
3710 sky2_down(dev);
3711
3712 sky2->rx_pending = ering->rx_pending;
3713 sky2->tx_pending = ering->tx_pending;
3714
3715 if (netif_running(dev)) {
3716 err = sky2_up(dev);
3717 if (err)
3718 dev_close(dev);
3719 }
3720
3721 return err;
3722 }
3723
3724 static int sky2_get_regs_len(struct net_device *dev)
3725 {
3726 return 0x4000;
3727 }
3728
3729 /*
3730 * Returns copy of control register region
3731 * Note: ethtool_get_regs always provides full size (16k) buffer
3732 */
3733 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3734 void *p)
3735 {
3736 const struct sky2_port *sky2 = netdev_priv(dev);
3737 const void __iomem *io = sky2->hw->regs;
3738 unsigned int b;
3739
3740 regs->version = 1;
3741
3742 for (b = 0; b < 128; b++) {
3743 /* This complicated switch statement is to make sure and
3744 * only access regions that are unreserved.
3745 * Some blocks are only valid on dual port cards.
3746 * and block 3 has some special diagnostic registers that
3747 * are poison.
3748 */
3749 switch (b) {
3750 case 3:
3751 /* skip diagnostic ram region */
3752 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3753 break;
3754
3755 /* dual port cards only */
3756 case 5: /* Tx Arbiter 2 */
3757 case 9: /* RX2 */
3758 case 14 ... 15: /* TX2 */
3759 case 17: case 19: /* Ram Buffer 2 */
3760 case 22 ... 23: /* Tx Ram Buffer 2 */
3761 case 25: /* Rx MAC Fifo 1 */
3762 case 27: /* Tx MAC Fifo 2 */
3763 case 31: /* GPHY 2 */
3764 case 40 ... 47: /* Pattern Ram 2 */
3765 case 52: case 54: /* TCP Segmentation 2 */
3766 case 112 ... 116: /* GMAC 2 */
3767 if (sky2->hw->ports == 1)
3768 goto reserved;
3769 /* fall through */
3770 case 0: /* Control */
3771 case 2: /* Mac address */
3772 case 4: /* Tx Arbiter 1 */
3773 case 7: /* PCI express reg */
3774 case 8: /* RX1 */
3775 case 12 ... 13: /* TX1 */
3776 case 16: case 18:/* Rx Ram Buffer 1 */
3777 case 20 ... 21: /* Tx Ram Buffer 1 */
3778 case 24: /* Rx MAC Fifo 1 */
3779 case 26: /* Tx MAC Fifo 1 */
3780 case 28 ... 29: /* Descriptor and status unit */
3781 case 30: /* GPHY 1*/
3782 case 32 ... 39: /* Pattern Ram 1 */
3783 case 48: case 50: /* TCP Segmentation 1 */
3784 case 56 ... 60: /* PCI space */
3785 case 80 ... 84: /* GMAC 1 */
3786 memcpy_fromio(p, io, 128);
3787 break;
3788 default:
3789 reserved:
3790 memset(p, 0, 128);
3791 }
3792
3793 p += 128;
3794 io += 128;
3795 }
3796 }
3797
3798 /* In order to do Jumbo packets on these chips, need to turn off the
3799 * transmit store/forward. Therefore checksum offload won't work.
3800 */
3801 static int no_tx_offload(struct net_device *dev)
3802 {
3803 const struct sky2_port *sky2 = netdev_priv(dev);
3804 const struct sky2_hw *hw = sky2->hw;
3805
3806 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
3807 }
3808
3809 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3810 {
3811 if (data && no_tx_offload(dev))
3812 return -EINVAL;
3813
3814 return ethtool_op_set_tx_csum(dev, data);
3815 }
3816
3817
3818 static int sky2_set_tso(struct net_device *dev, u32 data)
3819 {
3820 if (data && no_tx_offload(dev))
3821 return -EINVAL;
3822
3823 return ethtool_op_set_tso(dev, data);
3824 }
3825
3826 static int sky2_get_eeprom_len(struct net_device *dev)
3827 {
3828 struct sky2_port *sky2 = netdev_priv(dev);
3829 struct sky2_hw *hw = sky2->hw;
3830 u16 reg2;
3831
3832 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
3833 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3834 }
3835
3836 static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
3837 {
3838 unsigned long start = jiffies;
3839
3840 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
3841 /* Can take up to 10.6 ms for write */
3842 if (time_after(jiffies, start + HZ/4)) {
3843 dev_err(&hw->pdev->dev, PFX "VPD cycle timed out");
3844 return -ETIMEDOUT;
3845 }
3846 mdelay(1);
3847 }
3848
3849 return 0;
3850 }
3851
3852 static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
3853 u16 offset, size_t length)
3854 {
3855 int rc = 0;
3856
3857 while (length > 0) {
3858 u32 val;
3859
3860 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3861 rc = sky2_vpd_wait(hw, cap, 0);
3862 if (rc)
3863 break;
3864
3865 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3866
3867 memcpy(data, &val, min(sizeof(val), length));
3868 offset += sizeof(u32);
3869 data += sizeof(u32);
3870 length -= sizeof(u32);
3871 }
3872
3873 return rc;
3874 }
3875
3876 static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
3877 u16 offset, unsigned int length)
3878 {
3879 unsigned int i;
3880 int rc = 0;
3881
3882 for (i = 0; i < length; i += sizeof(u32)) {
3883 u32 val = *(u32 *)(data + i);
3884
3885 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
3886 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3887
3888 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
3889 if (rc)
3890 break;
3891 }
3892 return rc;
3893 }
3894
3895 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3896 u8 *data)
3897 {
3898 struct sky2_port *sky2 = netdev_priv(dev);
3899 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3900
3901 if (!cap)
3902 return -EINVAL;
3903
3904 eeprom->magic = SKY2_EEPROM_MAGIC;
3905
3906 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
3907 }
3908
3909 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3910 u8 *data)
3911 {
3912 struct sky2_port *sky2 = netdev_priv(dev);
3913 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3914
3915 if (!cap)
3916 return -EINVAL;
3917
3918 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3919 return -EINVAL;
3920
3921 /* Partial writes not supported */
3922 if ((eeprom->offset & 3) || (eeprom->len & 3))
3923 return -EINVAL;
3924
3925 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
3926 }
3927
3928
3929 static const struct ethtool_ops sky2_ethtool_ops = {
3930 .get_settings = sky2_get_settings,
3931 .set_settings = sky2_set_settings,
3932 .get_drvinfo = sky2_get_drvinfo,
3933 .get_wol = sky2_get_wol,
3934 .set_wol = sky2_set_wol,
3935 .get_msglevel = sky2_get_msglevel,
3936 .set_msglevel = sky2_set_msglevel,
3937 .nway_reset = sky2_nway_reset,
3938 .get_regs_len = sky2_get_regs_len,
3939 .get_regs = sky2_get_regs,
3940 .get_link = ethtool_op_get_link,
3941 .get_eeprom_len = sky2_get_eeprom_len,
3942 .get_eeprom = sky2_get_eeprom,
3943 .set_eeprom = sky2_set_eeprom,
3944 .set_sg = ethtool_op_set_sg,
3945 .set_tx_csum = sky2_set_tx_csum,
3946 .set_tso = sky2_set_tso,
3947 .get_rx_csum = sky2_get_rx_csum,
3948 .set_rx_csum = sky2_set_rx_csum,
3949 .get_strings = sky2_get_strings,
3950 .get_coalesce = sky2_get_coalesce,
3951 .set_coalesce = sky2_set_coalesce,
3952 .get_ringparam = sky2_get_ringparam,
3953 .set_ringparam = sky2_set_ringparam,
3954 .get_pauseparam = sky2_get_pauseparam,
3955 .set_pauseparam = sky2_set_pauseparam,
3956 .phys_id = sky2_phys_id,
3957 .get_sset_count = sky2_get_sset_count,
3958 .get_ethtool_stats = sky2_get_ethtool_stats,
3959 };
3960
3961 #ifdef CONFIG_SKY2_DEBUG
3962
3963 static struct dentry *sky2_debug;
3964
3965
3966 /*
3967 * Read and parse the first part of Vital Product Data
3968 */
3969 #define VPD_SIZE 128
3970 #define VPD_MAGIC 0x82
3971
3972 static const struct vpd_tag {
3973 char tag[2];
3974 char *label;
3975 } vpd_tags[] = {
3976 { "PN", "Part Number" },
3977 { "EC", "Engineering Level" },
3978 { "MN", "Manufacturer" },
3979 { "SN", "Serial Number" },
3980 { "YA", "Asset Tag" },
3981 { "VL", "First Error Log Message" },
3982 { "VF", "Second Error Log Message" },
3983 { "VB", "Boot Agent ROM Configuration" },
3984 { "VE", "EFI UNDI Configuration" },
3985 };
3986
3987 static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
3988 {
3989 size_t vpd_size;
3990 loff_t offs;
3991 u8 len;
3992 unsigned char *buf;
3993 u16 reg2;
3994
3995 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
3996 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3997
3998 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
3999 buf = kmalloc(vpd_size, GFP_KERNEL);
4000 if (!buf) {
4001 seq_puts(seq, "no memory!\n");
4002 return;
4003 }
4004
4005 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4006 seq_puts(seq, "VPD read failed\n");
4007 goto out;
4008 }
4009
4010 if (buf[0] != VPD_MAGIC) {
4011 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4012 goto out;
4013 }
4014 len = buf[1];
4015 if (len == 0 || len > vpd_size - 4) {
4016 seq_printf(seq, "Invalid id length: %d\n", len);
4017 goto out;
4018 }
4019
4020 seq_printf(seq, "%.*s\n", len, buf + 3);
4021 offs = len + 3;
4022
4023 while (offs < vpd_size - 4) {
4024 int i;
4025
4026 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4027 break;
4028 len = buf[offs + 2];
4029 if (offs + len + 3 >= vpd_size)
4030 break;
4031
4032 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4033 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4034 seq_printf(seq, " %s: %.*s\n",
4035 vpd_tags[i].label, len, buf + offs + 3);
4036 break;
4037 }
4038 }
4039 offs += len + 3;
4040 }
4041 out:
4042 kfree(buf);
4043 }
4044
4045 static int sky2_debug_show(struct seq_file *seq, void *v)
4046 {
4047 struct net_device *dev = seq->private;
4048 const struct sky2_port *sky2 = netdev_priv(dev);
4049 struct sky2_hw *hw = sky2->hw;
4050 unsigned port = sky2->port;
4051 unsigned idx, last;
4052 int sop;
4053
4054 sky2_show_vpd(seq, hw);
4055
4056 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
4057 sky2_read32(hw, B0_ISRC),
4058 sky2_read32(hw, B0_IMSK),
4059 sky2_read32(hw, B0_Y2_SP_ICR));
4060
4061 if (!netif_running(dev)) {
4062 seq_printf(seq, "network not running\n");
4063 return 0;
4064 }
4065
4066 napi_disable(&hw->napi);
4067 last = sky2_read16(hw, STAT_PUT_IDX);
4068
4069 if (hw->st_idx == last)
4070 seq_puts(seq, "Status ring (empty)\n");
4071 else {
4072 seq_puts(seq, "Status ring\n");
4073 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
4074 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
4075 const struct sky2_status_le *le = hw->st_le + idx;
4076 seq_printf(seq, "[%d] %#x %d %#x\n",
4077 idx, le->opcode, le->length, le->status);
4078 }
4079 seq_puts(seq, "\n");
4080 }
4081
4082 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4083 sky2->tx_cons, sky2->tx_prod,
4084 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4085 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4086
4087 /* Dump contents of tx ring */
4088 sop = 1;
4089 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
4090 idx = RING_NEXT(idx, TX_RING_SIZE)) {
4091 const struct sky2_tx_le *le = sky2->tx_le + idx;
4092 u32 a = le32_to_cpu(le->addr);
4093
4094 if (sop)
4095 seq_printf(seq, "%u:", idx);
4096 sop = 0;
4097
4098 switch(le->opcode & ~HW_OWNER) {
4099 case OP_ADDR64:
4100 seq_printf(seq, " %#x:", a);
4101 break;
4102 case OP_LRGLEN:
4103 seq_printf(seq, " mtu=%d", a);
4104 break;
4105 case OP_VLAN:
4106 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4107 break;
4108 case OP_TCPLISW:
4109 seq_printf(seq, " csum=%#x", a);
4110 break;
4111 case OP_LARGESEND:
4112 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4113 break;
4114 case OP_PACKET:
4115 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4116 break;
4117 case OP_BUFFER:
4118 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4119 break;
4120 default:
4121 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4122 a, le16_to_cpu(le->length));
4123 }
4124
4125 if (le->ctrl & EOP) {
4126 seq_putc(seq, '\n');
4127 sop = 1;
4128 }
4129 }
4130
4131 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4132 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4133 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4134 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4135
4136 sky2_read32(hw, B0_Y2_SP_LISR);
4137 napi_enable(&hw->napi);
4138 return 0;
4139 }
4140
4141 static int sky2_debug_open(struct inode *inode, struct file *file)
4142 {
4143 return single_open(file, sky2_debug_show, inode->i_private);
4144 }
4145
4146 static const struct file_operations sky2_debug_fops = {
4147 .owner = THIS_MODULE,
4148 .open = sky2_debug_open,
4149 .read = seq_read,
4150 .llseek = seq_lseek,
4151 .release = single_release,
4152 };
4153
4154 /*
4155 * Use network device events to create/remove/rename
4156 * debugfs file entries
4157 */
4158 static int sky2_device_event(struct notifier_block *unused,
4159 unsigned long event, void *ptr)
4160 {
4161 struct net_device *dev = ptr;
4162 struct sky2_port *sky2 = netdev_priv(dev);
4163
4164 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
4165 return NOTIFY_DONE;
4166
4167 switch(event) {
4168 case NETDEV_CHANGENAME:
4169 if (sky2->debugfs) {
4170 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4171 sky2_debug, dev->name);
4172 }
4173 break;
4174
4175 case NETDEV_GOING_DOWN:
4176 if (sky2->debugfs) {
4177 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
4178 dev->name);
4179 debugfs_remove(sky2->debugfs);
4180 sky2->debugfs = NULL;
4181 }
4182 break;
4183
4184 case NETDEV_UP:
4185 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4186 sky2_debug, dev,
4187 &sky2_debug_fops);
4188 if (IS_ERR(sky2->debugfs))
4189 sky2->debugfs = NULL;
4190 }
4191
4192 return NOTIFY_DONE;
4193 }
4194
4195 static struct notifier_block sky2_notifier = {
4196 .notifier_call = sky2_device_event,
4197 };
4198
4199
4200 static __init void sky2_debug_init(void)
4201 {
4202 struct dentry *ent;
4203
4204 ent = debugfs_create_dir("sky2", NULL);
4205 if (!ent || IS_ERR(ent))
4206 return;
4207
4208 sky2_debug = ent;
4209 register_netdevice_notifier(&sky2_notifier);
4210 }
4211
4212 static __exit void sky2_debug_cleanup(void)
4213 {
4214 if (sky2_debug) {
4215 unregister_netdevice_notifier(&sky2_notifier);
4216 debugfs_remove(sky2_debug);
4217 sky2_debug = NULL;
4218 }
4219 }
4220
4221 #else
4222 #define sky2_debug_init()
4223 #define sky2_debug_cleanup()
4224 #endif
4225
4226 /* Two copies of network device operations to handle special case of
4227 not allowing netpoll on second port */
4228 static const struct net_device_ops sky2_netdev_ops[2] = {
4229 {
4230 .ndo_open = sky2_up,
4231 .ndo_stop = sky2_down,
4232 .ndo_start_xmit = sky2_xmit_frame,
4233 .ndo_do_ioctl = sky2_ioctl,
4234 .ndo_validate_addr = eth_validate_addr,
4235 .ndo_set_mac_address = sky2_set_mac_address,
4236 .ndo_set_multicast_list = sky2_set_multicast,
4237 .ndo_change_mtu = sky2_change_mtu,
4238 .ndo_tx_timeout = sky2_tx_timeout,
4239 #ifdef SKY2_VLAN_TAG_USED
4240 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4241 #endif
4242 #ifdef CONFIG_NET_POLL_CONTROLLER
4243 .ndo_poll_controller = sky2_netpoll,
4244 #endif
4245 },
4246 {
4247 .ndo_open = sky2_up,
4248 .ndo_stop = sky2_down,
4249 .ndo_start_xmit = sky2_xmit_frame,
4250 .ndo_do_ioctl = sky2_ioctl,
4251 .ndo_validate_addr = eth_validate_addr,
4252 .ndo_set_mac_address = sky2_set_mac_address,
4253 .ndo_set_multicast_list = sky2_set_multicast,
4254 .ndo_change_mtu = sky2_change_mtu,
4255 .ndo_tx_timeout = sky2_tx_timeout,
4256 #ifdef SKY2_VLAN_TAG_USED
4257 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4258 #endif
4259 },
4260 };
4261
4262 /* Initialize network device */
4263 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
4264 unsigned port,
4265 int highmem, int wol)
4266 {
4267 struct sky2_port *sky2;
4268 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4269
4270 if (!dev) {
4271 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
4272 return NULL;
4273 }
4274
4275 SET_NETDEV_DEV(dev, &hw->pdev->dev);
4276 dev->irq = hw->pdev->irq;
4277 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
4278 dev->watchdog_timeo = TX_WATCHDOG;
4279 dev->netdev_ops = &sky2_netdev_ops[port];
4280
4281 sky2 = netdev_priv(dev);
4282 sky2->netdev = dev;
4283 sky2->hw = hw;
4284 sky2->msg_enable = netif_msg_init(debug, default_msg);
4285
4286 /* Auto speed and flow control */
4287 sky2->autoneg = AUTONEG_ENABLE;
4288 sky2->flow_mode = FC_BOTH;
4289
4290 sky2->duplex = -1;
4291 sky2->speed = -1;
4292 sky2->advertising = sky2_supported_modes(hw);
4293 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
4294 sky2->wol = wol;
4295
4296 spin_lock_init(&sky2->phy_lock);
4297 sky2->tx_pending = TX_DEF_PENDING;
4298 sky2->rx_pending = RX_DEF_PENDING;
4299 sky2->restarting = 0;
4300
4301 hw->dev[port] = dev;
4302
4303 sky2->port = port;
4304
4305 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
4306 if (highmem)
4307 dev->features |= NETIF_F_HIGHDMA;
4308
4309 #ifdef SKY2_VLAN_TAG_USED
4310 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4311 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4312 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4313 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4314 }
4315 #endif
4316
4317 /* read the mac address */
4318 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4319 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4320
4321 return dev;
4322 }
4323
4324 static void __devinit sky2_show_addr(struct net_device *dev)
4325 {
4326 const struct sky2_port *sky2 = netdev_priv(dev);
4327
4328 if (netif_msg_probe(sky2))
4329 printk(KERN_INFO PFX "%s: addr %pM\n",
4330 dev->name, dev->dev_addr);
4331 }
4332
4333 /* Handle software interrupt used during MSI test */
4334 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
4335 {
4336 struct sky2_hw *hw = dev_id;
4337 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4338
4339 if (status == 0)
4340 return IRQ_NONE;
4341
4342 if (status & Y2_IS_IRQ_SW) {
4343 hw->flags |= SKY2_HW_USE_MSI;
4344 wake_up(&hw->msi_wait);
4345 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4346 }
4347 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4348
4349 return IRQ_HANDLED;
4350 }
4351
4352 /* Test interrupt path by forcing a a software IRQ */
4353 static int __devinit sky2_test_msi(struct sky2_hw *hw)
4354 {
4355 struct pci_dev *pdev = hw->pdev;
4356 int err;
4357
4358 init_waitqueue_head (&hw->msi_wait);
4359
4360 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4361
4362 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4363 if (err) {
4364 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4365 return err;
4366 }
4367
4368 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4369 sky2_read8(hw, B0_CTST);
4370
4371 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4372
4373 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4374 /* MSI test failed, go back to INTx mode */
4375 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4376 "switching to INTx mode.\n");
4377
4378 err = -EOPNOTSUPP;
4379 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4380 }
4381
4382 sky2_write32(hw, B0_IMSK, 0);
4383 sky2_read32(hw, B0_IMSK);
4384
4385 free_irq(pdev->irq, hw);
4386
4387 return err;
4388 }
4389
4390 /* This driver supports yukon2 chipset only */
4391 static const char *sky2_name(u8 chipid, char *buf, int sz)
4392 {
4393 const char *name[] = {
4394 "XL", /* 0xb3 */
4395 "EC Ultra", /* 0xb4 */
4396 "Extreme", /* 0xb5 */
4397 "EC", /* 0xb6 */
4398 "FE", /* 0xb7 */
4399 "FE+", /* 0xb8 */
4400 "Supreme", /* 0xb9 */
4401 "UL 2", /* 0xba */
4402 };
4403
4404 if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_UL_2)
4405 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4406 else
4407 snprintf(buf, sz, "(chip %#x)", chipid);
4408 return buf;
4409 }
4410
4411 static int __devinit sky2_probe(struct pci_dev *pdev,
4412 const struct pci_device_id *ent)
4413 {
4414 struct net_device *dev;
4415 struct sky2_hw *hw;
4416 int err, using_dac = 0, wol_default;
4417 u32 reg;
4418 char buf1[16];
4419
4420 err = pci_enable_device(pdev);
4421 if (err) {
4422 dev_err(&pdev->dev, "cannot enable PCI device\n");
4423 goto err_out;
4424 }
4425
4426 /* Get configuration information
4427 * Note: only regular PCI config access once to test for HW issues
4428 * other PCI access through shared memory for speed and to
4429 * avoid MMCONFIG problems.
4430 */
4431 err = pci_read_config_dword(pdev, PCI_DEV_REG2, ®);
4432 if (err) {
4433 dev_err(&pdev->dev, "PCI read config failed\n");
4434 goto err_out;
4435 }
4436
4437 if (~reg == 0) {
4438 dev_err(&pdev->dev, "PCI configuration read error\n");
4439 goto err_out;
4440 }
4441
4442 err = pci_request_regions(pdev, DRV_NAME);
4443 if (err) {
4444 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4445 goto err_out_disable;
4446 }
4447
4448 pci_set_master(pdev);
4449
4450 if (sizeof(dma_addr_t) > sizeof(u32) &&
4451 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
4452 using_dac = 1;
4453 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4454 if (err < 0) {
4455 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4456 "for consistent allocations\n");
4457 goto err_out_free_regions;
4458 }
4459 } else {
4460 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4461 if (err) {
4462 dev_err(&pdev->dev, "no usable DMA configuration\n");
4463 goto err_out_free_regions;
4464 }
4465 }
4466
4467
4468 #ifdef __BIG_ENDIAN
4469 /* The sk98lin vendor driver uses hardware byte swapping but
4470 * this driver uses software swapping.
4471 */
4472 reg &= ~PCI_REV_DESC;
4473 err = pci_write_config_dword(pdev,PCI_DEV_REG2, reg);
4474 if (err) {
4475 dev_err(&pdev->dev, "PCI write config failed\n");
4476 goto err_out_free_regions;
4477 }
4478 #endif
4479
4480 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
4481
4482 err = -ENOMEM;
4483 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
4484 if (!hw) {
4485 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4486 goto err_out_free_regions;
4487 }
4488
4489 hw->pdev = pdev;
4490
4491 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4492 if (!hw->regs) {
4493 dev_err(&pdev->dev, "cannot map device registers\n");
4494 goto err_out_free_hw;
4495 }
4496
4497 /* ring for status responses */
4498 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
4499 if (!hw->st_le)
4500 goto err_out_iounmap;
4501
4502 err = sky2_init(hw);
4503 if (err)
4504 goto err_out_iounmap;
4505
4506 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4507 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
4508
4509 sky2_reset(hw);
4510
4511 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4512 if (!dev) {
4513 err = -ENOMEM;
4514 goto err_out_free_pci;
4515 }
4516
4517 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4518 err = sky2_test_msi(hw);
4519 if (err == -EOPNOTSUPP)
4520 pci_disable_msi(pdev);
4521 else if (err)
4522 goto err_out_free_netdev;
4523 }
4524
4525 err = register_netdev(dev);
4526 if (err) {
4527 dev_err(&pdev->dev, "cannot register net device\n");
4528 goto err_out_free_netdev;
4529 }
4530
4531 netif_carrier_off(dev);
4532
4533 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4534
4535 err = request_irq(pdev->irq, sky2_intr,
4536 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
4537 dev->name, hw);
4538 if (err) {
4539 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4540 goto err_out_unregister;
4541 }
4542 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4543 napi_enable(&hw->napi);
4544
4545 sky2_show_addr(dev);
4546
4547 if (hw->ports > 1) {
4548 struct net_device *dev1;
4549
4550 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4551 if (!dev1)
4552 dev_warn(&pdev->dev, "allocation for second device failed\n");
4553 else if ((err = register_netdev(dev1))) {
4554 dev_warn(&pdev->dev,
4555 "register of second port failed (%d)\n", err);
4556 hw->dev[1] = NULL;
4557 free_netdev(dev1);
4558 } else
4559 sky2_show_addr(dev1);
4560 }
4561
4562 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4563 INIT_WORK(&hw->restart_work, sky2_restart);
4564
4565 pci_set_drvdata(pdev, hw);
4566
4567 return 0;
4568
4569 err_out_unregister:
4570 if (hw->flags & SKY2_HW_USE_MSI)
4571 pci_disable_msi(pdev);
4572 unregister_netdev(dev);
4573 err_out_free_netdev:
4574 free_netdev(dev);
4575 err_out_free_pci:
4576 sky2_write8(hw, B0_CTST, CS_RST_SET);
4577 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4578 err_out_iounmap:
4579 iounmap(hw->regs);
4580 err_out_free_hw:
4581 kfree(hw);
4582 err_out_free_regions:
4583 pci_release_regions(pdev);
4584 err_out_disable:
4585 pci_disable_device(pdev);
4586 err_out:
4587 pci_set_drvdata(pdev, NULL);
4588 return err;
4589 }
4590
4591 static void __devexit sky2_remove(struct pci_dev *pdev)
4592 {
4593 struct sky2_hw *hw = pci_get_drvdata(pdev);
4594 int i;
4595
4596 if (!hw)
4597 return;
4598
4599 del_timer_sync(&hw->watchdog_timer);
4600 cancel_work_sync(&hw->restart_work);
4601
4602 for (i = hw->ports-1; i >= 0; --i)
4603 unregister_netdev(hw->dev[i]);
4604
4605 sky2_write32(hw, B0_IMSK, 0);
4606
4607 sky2_power_aux(hw);
4608
4609 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
4610 sky2_write8(hw, B0_CTST, CS_RST_SET);
4611 sky2_read8(hw, B0_CTST);
4612
4613 free_irq(pdev->irq, hw);
4614 if (hw->flags & SKY2_HW_USE_MSI)
4615 pci_disable_msi(pdev);
4616 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4617 pci_release_regions(pdev);
4618 pci_disable_device(pdev);
4619
4620 for (i = hw->ports-1; i >= 0; --i)
4621 free_netdev(hw->dev[i]);
4622
4623 iounmap(hw->regs);
4624 kfree(hw);
4625
4626 pci_set_drvdata(pdev, NULL);
4627 }
4628
4629 #ifdef CONFIG_PM
4630 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4631 {
4632 struct sky2_hw *hw = pci_get_drvdata(pdev);
4633 int i, wol = 0;
4634
4635 if (!hw)
4636 return 0;
4637
4638 del_timer_sync(&hw->watchdog_timer);
4639 cancel_work_sync(&hw->restart_work);
4640
4641 for (i = 0; i < hw->ports; i++) {
4642 struct net_device *dev = hw->dev[i];
4643 struct sky2_port *sky2 = netdev_priv(dev);
4644
4645 netif_device_detach(dev);
4646 if (netif_running(dev))
4647 sky2_down(dev);
4648
4649 if (sky2->wol)
4650 sky2_wol_init(sky2);
4651
4652 wol |= sky2->wol;
4653 }
4654
4655 sky2_write32(hw, B0_IMSK, 0);
4656 napi_disable(&hw->napi);
4657 sky2_power_aux(hw);
4658
4659 pci_save_state(pdev);
4660 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
4661 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4662
4663 return 0;
4664 }
4665
4666 static int sky2_resume(struct pci_dev *pdev)
4667 {
4668 struct sky2_hw *hw = pci_get_drvdata(pdev);
4669 int i, err;
4670
4671 if (!hw)
4672 return 0;
4673
4674 err = pci_set_power_state(pdev, PCI_D0);
4675 if (err)
4676 goto out;
4677
4678 err = pci_restore_state(pdev);
4679 if (err)
4680 goto out;
4681
4682 pci_enable_wake(pdev, PCI_D0, 0);
4683
4684 /* Re-enable all clocks */
4685 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4686 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4687 hw->chip_id == CHIP_ID_YUKON_FE_P)
4688 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
4689
4690 sky2_reset(hw);
4691 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4692 napi_enable(&hw->napi);
4693
4694 for (i = 0; i < hw->ports; i++) {
4695 struct net_device *dev = hw->dev[i];
4696
4697 netif_device_attach(dev);
4698 if (netif_running(dev)) {
4699 err = sky2_up(dev);
4700 if (err) {
4701 printk(KERN_ERR PFX "%s: could not up: %d\n",
4702 dev->name, err);
4703 rtnl_lock();
4704 dev_close(dev);
4705 rtnl_unlock();
4706 goto out;
4707 }
4708 }
4709 }
4710
4711 return 0;
4712 out:
4713 dev_err(&pdev->dev, "resume failed (%d)\n", err);
4714 pci_disable_device(pdev);
4715 return err;
4716 }
4717 #endif
4718
4719 static void sky2_shutdown(struct pci_dev *pdev)
4720 {
4721 struct sky2_hw *hw = pci_get_drvdata(pdev);
4722 int i, wol = 0;
4723
4724 if (!hw)
4725 return;
4726
4727 del_timer_sync(&hw->watchdog_timer);
4728
4729 for (i = 0; i < hw->ports; i++) {
4730 struct net_device *dev = hw->dev[i];
4731 struct sky2_port *sky2 = netdev_priv(dev);
4732
4733 if (sky2->wol) {
4734 wol = 1;
4735 sky2_wol_init(sky2);
4736 }
4737 }
4738
4739 if (wol)
4740 sky2_power_aux(hw);
4741
4742 pci_enable_wake(pdev, PCI_D3hot, wol);
4743 pci_enable_wake(pdev, PCI_D3cold, wol);
4744
4745 pci_disable_device(pdev);
4746 pci_set_power_state(pdev, PCI_D3hot);
4747 }
4748
4749 static struct pci_driver sky2_driver = {
4750 .name = DRV_NAME,
4751 .id_table = sky2_id_table,
4752 .probe = sky2_probe,
4753 .remove = __devexit_p(sky2_remove),
4754 #ifdef CONFIG_PM
4755 .suspend = sky2_suspend,
4756 .resume = sky2_resume,
4757 #endif
4758 .shutdown = sky2_shutdown,
4759 };
4760
4761 static int __init sky2_init_module(void)
4762 {
4763 pr_info(PFX "driver version " DRV_VERSION "\n");
4764
4765 sky2_debug_init();
4766 return pci_register_driver(&sky2_driver);
4767 }
4768
4769 static void __exit sky2_cleanup_module(void)
4770 {
4771 pci_unregister_driver(&sky2_driver);
4772 sky2_debug_cleanup();
4773 }
4774
4775 module_init(sky2_init_module);
4776 module_exit(sky2_cleanup_module);
4777
4778 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4779 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4780 MODULE_LICENSE("GPL");
4781 MODULE_VERSION(DRV_VERSION);
4782
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