1 /*-
2 *
3 * This software may be used and distributed according to the terms
4 * of the GNU General Public License, incorporated herein by reference.
5 *
6 * Module : sk_g16.h
7 * Version : $Revision$
8 *
9 * Author : M.Hipp (mhipp@student.uni-tuebingen.de)
10 * changes by : Patrick J.D. Weichmann
11 *
12 * Date Created : 94/05/25
13 *
14 * Description : In here are all necessary definitions of
15 * the am7990 (LANCE) chip used for writing a
16 * network device driver which uses this chip
17 *
18 * $Log$
19 -*/
20
21 #ifndef SK_G16_H
22
23 #define SK_G16_H
24
25
26 /*
27 * Control and Status Register 0 (CSR0) bit definitions
28 *
29 * (R=Readable) (W=Writeable) (S=Set on write) (C-Clear on write)
30 *
31 */
32
33 #define CSR0_ERR 0x8000 /* Error summary (R) */
34 #define CSR0_BABL 0x4000 /* Babble transmitter timeout error (RC) */
35 #define CSR0_CERR 0x2000 /* Collision Error (RC) */
36 #define CSR0_MISS 0x1000 /* Missed packet (RC) */
37 #define CSR0_MERR 0x0800 /* Memory Error (RC) */
38 #define CSR0_RINT 0x0400 /* Receiver Interrupt (RC) */
39 #define CSR0_TINT 0x0200 /* Transmit Interrupt (RC) */
40 #define CSR0_IDON 0x0100 /* Initialization Done (RC) */
41 #define CSR0_INTR 0x0080 /* Interrupt Flag (R) */
42 #define CSR0_INEA 0x0040 /* Interrupt Enable (RW) */
43 #define CSR0_RXON 0x0020 /* Receiver on (R) */
44 #define CSR0_TXON 0x0010 /* Transmitter on (R) */
45 #define CSR0_TDMD 0x0008 /* Transmit Demand (RS) */
46 #define CSR0_STOP 0x0004 /* Stop (RS) */
47 #define CSR0_STRT 0x0002 /* Start (RS) */
48 #define CSR0_INIT 0x0001 /* Initialize (RS) */
49
50 #define CSR0_CLRALL 0x7f00 /* mask for all clearable bits */
51
52 /*
53 * Control and Status Register 3 (CSR3) bit definitions
54 *
55 */
56
57 #define CSR3_BSWAP 0x0004 /* Byte Swap (RW) */
58 #define CSR3_ACON 0x0002 /* ALE Control (RW) */
59 #define CSR3_BCON 0x0001 /* Byte Control (RW) */
60
61 /*
62 * Initialization Block Mode operation Bit Definitions.
63 */
64
65 #define MODE_PROM 0x8000 /* Promiscuous Mode */
66 #define MODE_INTL 0x0040 /* Internal Loopback */
67 #define MODE_DRTY 0x0020 /* Disable Retry */
68 #define MODE_COLL 0x0010 /* Force Collision */
69 #define MODE_DTCR 0x0008 /* Disable Transmit CRC) */
70 #define MODE_LOOP 0x0004 /* Loopback */
71 #define MODE_DTX 0x0002 /* Disable the Transmitter */
72 #define MODE_DRX 0x0001 /* Disable the Receiver */
73
74 #define MODE_NORMAL 0x0000 /* Normal operation mode */
75
76 /*
77 * Receive message descriptor status bit definitions.
78 */
79
80 #define RX_OWN 0x80 /* Owner bit 0 = host, 1 = lance */
81 #define RX_ERR 0x40 /* Error Summary */
82 #define RX_FRAM 0x20 /* Framing Error */
83 #define RX_OFLO 0x10 /* Overflow Error */
84 #define RX_CRC 0x08 /* CRC Error */
85 #define RX_BUFF 0x04 /* Buffer Error */
86 #define RX_STP 0x02 /* Start of Packet */
87 #define RX_ENP 0x01 /* End of Packet */
88
89
90 /*
91 * Transmit message descriptor status bit definitions.
92 */
93
94 #define TX_OWN 0x80 /* Owner bit 0 = host, 1 = lance */
95 #define TX_ERR 0x40 /* Error Summary */
96 #define TX_MORE 0x10 /* More the 1 retry needed to Xmit */
97 #define TX_ONE 0x08 /* One retry needed to Xmit */
98 #define TX_DEF 0x04 /* Deferred */
99 #define TX_STP 0x02 /* Start of Packet */
100 #define TX_ENP 0x01 /* End of Packet */
101
102 /*
103 * Transmit status (2) (valid if TX_ERR == 1)
104 */
105
106 #define TX_BUFF 0x8000 /* Buffering error (no ENP) */
107 #define TX_UFLO 0x4000 /* Underflow (late memory) */
108 #define TX_LCOL 0x1000 /* Late collision */
109 #define TX_LCAR 0x0400 /* Loss of Carrier */
110 #define TX_RTRY 0x0200 /* Failed after 16 retransmissions */
111 #define TX_TDR 0x003f /* Time-domain-reflectometer-value */
112
113
114 /*
115 * Structures used for Communication with the LANCE
116 */
117
118 /* LANCE Initialize Block */
119
120 struct init_block
121 {
122 unsigned short mode; /* Mode Register */
123 unsigned char paddr[6]; /* Physical Address (MAC) */
124 unsigned char laddr[8]; /* Logical Filter Address (not used) */
125 unsigned int rdrp; /* Receive Descriptor Ring pointer */
126 unsigned int tdrp; /* Transmit Descriptor Ring pointer */
127 };
128
129
130 /* Receive Message Descriptor Entry */
131
132 struct rmd
133 {
134 union
135 {
136 unsigned long buffer; /* Address of buffer */
137 struct
138 {
139 unsigned char unused[3];
140 unsigned volatile char status; /* Status Bits */
141 } s;
142 } u;
143 volatile short blen; /* Buffer Length (two's complement) */
144 unsigned short mlen; /* Message Byte Count */
145 };
146
147
148 /* Transmit Message Descriptor Entry */
149
150 struct tmd
151 {
152 union
153 {
154 unsigned long buffer; /* Address of buffer */
155 struct
156 {
157 unsigned char unused[3];
158 unsigned volatile char status; /* Status Bits */
159 } s;
160 } u;
161 unsigned short blen; /* Buffer Length (two's complement) */
162 unsigned volatile short status2; /* Error Status Bits */
163 };
164
165 #endif /* End of SK_G16_H */
166
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