1 /************************************************************************
2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3 * Copyright(c) 2002-2007 Neterion Inc.
4
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 *
13 * Credits:
14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
21 * Francois Romieu : For pointing out all code part that were
22 * deprecated and also styling related comments.
23 * Grant Grundler : For helping me get rid of some Architecture
24 * dependent code.
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
26 *
27 * The module loadable parameters that are supported by the driver and a brief
28 * explaination of all the variables.
29 *
30 * rx_ring_num : This can be used to program the number of receive rings used
31 * in the driver.
32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
35 * values are 1, 2.
36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
38 * Tx descriptors that can be associated with each corresponding FIFO.
39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
40 * 2(MSI_X). Default value is '2(MSI_X)'
41 * lro_enable: Specifies whether to enable Large Receive Offload (LRO) or not.
42 * Possible values '1' for enable '' for disable. Default is ''
43 * lro_max_pkts: This parameter defines maximum number of packets can be
44 * aggregated as a single large packet
45 * napi: This parameter used to enable/disable NAPI (polling Rx)
46 * Possible values '1' for enable and '' for disable. Default is '1'
47 * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
48 * Possible values '1' for enable and '' for disable. Default is ''
49 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
50 * Possible values '1' for enable , '' for disable.
51 * Default is '2' - which means disable in promisc mode
52 * and enable in non-promiscuous mode.
53 * multiq: This parameter used to enable/disable MULTIQUEUE support.
54 * Possible values '1' for enable and '' for disable. Default is ''
55 ************************************************************************/
56
57 #include <linux/module.h>
58 #include <linux/types.h>
59 #include <linux/errno.h>
60 #include <linux/ioport.h>
61 #include <linux/pci.h>
62 #include <linux/dma-mapping.h>
63 #include <linux/kernel.h>
64 #include <linux/netdevice.h>
65 #include <linux/etherdevice.h>
66 #include <linux/mdio.h>
67 #include <linux/skbuff.h>
68 #include <linux/init.h>
69 #include <linux/delay.h>
70 #include <linux/stddef.h>
71 #include <linux/ioctl.h>
72 #include <linux/timex.h>
73 #include <linux/ethtool.h>
74 #include <linux/workqueue.h>
75 #include <linux/if_vlan.h>
76 #include <linux/ip.h>
77 #include <linux/tcp.h>
78 #include <net/tcp.h>
79
80 #include <asm/system.h>
81 #include <asm/uaccess.h>
82 #include <asm/io.h>
83 #include <asm/div64.h>
84 #include <asm/irq.h>
85
86 /* local include */
87 #include "s2io.h"
88 #include "s2io-regs.h"
89
90 #define DRV_VERSION "2.0.26.25"
91
92 /* S2io Driver name & version. */
93 static char s2io_driver_name[] = "Neterion";
94 static char s2io_driver_version[] = DRV_VERSION;
95
96 static int rxd_size[2] = {32,48};
97 static int rxd_count[2] = {127,85};
98
99 static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
100 {
101 int ret;
102
103 ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
104 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
105
106 return ret;
107 }
108
109 /*
110 * Cards with following subsystem_id have a link state indication
111 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
112 * macro below identifies these cards given the subsystem_id.
113 */
114 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
115 (dev_type == XFRAME_I_DEVICE) ? \
116 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
117 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
118
119 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
120 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
121
122 static inline int is_s2io_card_up(const struct s2io_nic * sp)
123 {
124 return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
125 }
126
127 /* Ethtool related variables and Macros. */
128 static char s2io_gstrings[][ETH_GSTRING_LEN] = {
129 "Register test\t(offline)",
130 "Eeprom test\t(offline)",
131 "Link test\t(online)",
132 "RLDRAM test\t(offline)",
133 "BIST Test\t(offline)"
134 };
135
136 static char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
137 {"tmac_frms"},
138 {"tmac_data_octets"},
139 {"tmac_drop_frms"},
140 {"tmac_mcst_frms"},
141 {"tmac_bcst_frms"},
142 {"tmac_pause_ctrl_frms"},
143 {"tmac_ttl_octets"},
144 {"tmac_ucst_frms"},
145 {"tmac_nucst_frms"},
146 {"tmac_any_err_frms"},
147 {"tmac_ttl_less_fb_octets"},
148 {"tmac_vld_ip_octets"},
149 {"tmac_vld_ip"},
150 {"tmac_drop_ip"},
151 {"tmac_icmp"},
152 {"tmac_rst_tcp"},
153 {"tmac_tcp"},
154 {"tmac_udp"},
155 {"rmac_vld_frms"},
156 {"rmac_data_octets"},
157 {"rmac_fcs_err_frms"},
158 {"rmac_drop_frms"},
159 {"rmac_vld_mcst_frms"},
160 {"rmac_vld_bcst_frms"},
161 {"rmac_in_rng_len_err_frms"},
162 {"rmac_out_rng_len_err_frms"},
163 {"rmac_long_frms"},
164 {"rmac_pause_ctrl_frms"},
165 {"rmac_unsup_ctrl_frms"},
166 {"rmac_ttl_octets"},
167 {"rmac_accepted_ucst_frms"},
168 {"rmac_accepted_nucst_frms"},
169 {"rmac_discarded_frms"},
170 {"rmac_drop_events"},
171 {"rmac_ttl_less_fb_octets"},
172 {"rmac_ttl_frms"},
173 {"rmac_usized_frms"},
174 {"rmac_osized_frms"},
175 {"rmac_frag_frms"},
176 {"rmac_jabber_frms"},
177 {"rmac_ttl_64_frms"},
178 {"rmac_ttl_65_127_frms"},
179 {"rmac_ttl_128_255_frms"},
180 {"rmac_ttl_256_511_frms"},
181 {"rmac_ttl_512_1023_frms"},
182 {"rmac_ttl_1024_1518_frms"},
183 {"rmac_ip"},
184 {"rmac_ip_octets"},
185 {"rmac_hdr_err_ip"},
186 {"rmac_drop_ip"},
187 {"rmac_icmp"},
188 {"rmac_tcp"},
189 {"rmac_udp"},
190 {"rmac_err_drp_udp"},
191 {"rmac_xgmii_err_sym"},
192 {"rmac_frms_q0"},
193 {"rmac_frms_q1"},
194 {"rmac_frms_q2"},
195 {"rmac_frms_q3"},
196 {"rmac_frms_q4"},
197 {"rmac_frms_q5"},
198 {"rmac_frms_q6"},
199 {"rmac_frms_q7"},
200 {"rmac_full_q0"},
201 {"rmac_full_q1"},
202 {"rmac_full_q2"},
203 {"rmac_full_q3"},
204 {"rmac_full_q4"},
205 {"rmac_full_q5"},
206 {"rmac_full_q6"},
207 {"rmac_full_q7"},
208 {"rmac_pause_cnt"},
209 {"rmac_xgmii_data_err_cnt"},
210 {"rmac_xgmii_ctrl_err_cnt"},
211 {"rmac_accepted_ip"},
212 {"rmac_err_tcp"},
213 {"rd_req_cnt"},
214 {"new_rd_req_cnt"},
215 {"new_rd_req_rtry_cnt"},
216 {"rd_rtry_cnt"},
217 {"wr_rtry_rd_ack_cnt"},
218 {"wr_req_cnt"},
219 {"new_wr_req_cnt"},
220 {"new_wr_req_rtry_cnt"},
221 {"wr_rtry_cnt"},
222 {"wr_disc_cnt"},
223 {"rd_rtry_wr_ack_cnt"},
224 {"txp_wr_cnt"},
225 {"txd_rd_cnt"},
226 {"txd_wr_cnt"},
227 {"rxd_rd_cnt"},
228 {"rxd_wr_cnt"},
229 {"txf_rd_cnt"},
230 {"rxf_wr_cnt"}
231 };
232
233 static char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
234 {"rmac_ttl_1519_4095_frms"},
235 {"rmac_ttl_4096_8191_frms"},
236 {"rmac_ttl_8192_max_frms"},
237 {"rmac_ttl_gt_max_frms"},
238 {"rmac_osized_alt_frms"},
239 {"rmac_jabber_alt_frms"},
240 {"rmac_gt_max_alt_frms"},
241 {"rmac_vlan_frms"},
242 {"rmac_len_discard"},
243 {"rmac_fcs_discard"},
244 {"rmac_pf_discard"},
245 {"rmac_da_discard"},
246 {"rmac_red_discard"},
247 {"rmac_rts_discard"},
248 {"rmac_ingm_full_discard"},
249 {"link_fault_cnt"}
250 };
251
252 static char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
253 {"\n DRIVER STATISTICS"},
254 {"single_bit_ecc_errs"},
255 {"double_bit_ecc_errs"},
256 {"parity_err_cnt"},
257 {"serious_err_cnt"},
258 {"soft_reset_cnt"},
259 {"fifo_full_cnt"},
260 {"ring_0_full_cnt"},
261 {"ring_1_full_cnt"},
262 {"ring_2_full_cnt"},
263 {"ring_3_full_cnt"},
264 {"ring_4_full_cnt"},
265 {"ring_5_full_cnt"},
266 {"ring_6_full_cnt"},
267 {"ring_7_full_cnt"},
268 {"alarm_transceiver_temp_high"},
269 {"alarm_transceiver_temp_low"},
270 {"alarm_laser_bias_current_high"},
271 {"alarm_laser_bias_current_low"},
272 {"alarm_laser_output_power_high"},
273 {"alarm_laser_output_power_low"},
274 {"warn_transceiver_temp_high"},
275 {"warn_transceiver_temp_low"},
276 {"warn_laser_bias_current_high"},
277 {"warn_laser_bias_current_low"},
278 {"warn_laser_output_power_high"},
279 {"warn_laser_output_power_low"},
280 {"lro_aggregated_pkts"},
281 {"lro_flush_both_count"},
282 {"lro_out_of_sequence_pkts"},
283 {"lro_flush_due_to_max_pkts"},
284 {"lro_avg_aggr_pkts"},
285 {"mem_alloc_fail_cnt"},
286 {"pci_map_fail_cnt"},
287 {"watchdog_timer_cnt"},
288 {"mem_allocated"},
289 {"mem_freed"},
290 {"link_up_cnt"},
291 {"link_down_cnt"},
292 {"link_up_time"},
293 {"link_down_time"},
294 {"tx_tcode_buf_abort_cnt"},
295 {"tx_tcode_desc_abort_cnt"},
296 {"tx_tcode_parity_err_cnt"},
297 {"tx_tcode_link_loss_cnt"},
298 {"tx_tcode_list_proc_err_cnt"},
299 {"rx_tcode_parity_err_cnt"},
300 {"rx_tcode_abort_cnt"},
301 {"rx_tcode_parity_abort_cnt"},
302 {"rx_tcode_rda_fail_cnt"},
303 {"rx_tcode_unkn_prot_cnt"},
304 {"rx_tcode_fcs_err_cnt"},
305 {"rx_tcode_buf_size_err_cnt"},
306 {"rx_tcode_rxd_corrupt_cnt"},
307 {"rx_tcode_unkn_err_cnt"},
308 {"tda_err_cnt"},
309 {"pfc_err_cnt"},
310 {"pcc_err_cnt"},
311 {"tti_err_cnt"},
312 {"tpa_err_cnt"},
313 {"sm_err_cnt"},
314 {"lso_err_cnt"},
315 {"mac_tmac_err_cnt"},
316 {"mac_rmac_err_cnt"},
317 {"xgxs_txgxs_err_cnt"},
318 {"xgxs_rxgxs_err_cnt"},
319 {"rc_err_cnt"},
320 {"prc_pcix_err_cnt"},
321 {"rpa_err_cnt"},
322 {"rda_err_cnt"},
323 {"rti_err_cnt"},
324 {"mc_err_cnt"}
325 };
326
327 #define S2IO_XENA_STAT_LEN ARRAY_SIZE(ethtool_xena_stats_keys)
328 #define S2IO_ENHANCED_STAT_LEN ARRAY_SIZE(ethtool_enhanced_stats_keys)
329 #define S2IO_DRIVER_STAT_LEN ARRAY_SIZE(ethtool_driver_stats_keys)
330
331 #define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN )
332 #define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN )
333
334 #define XFRAME_I_STAT_STRINGS_LEN ( XFRAME_I_STAT_LEN * ETH_GSTRING_LEN )
335 #define XFRAME_II_STAT_STRINGS_LEN ( XFRAME_II_STAT_LEN * ETH_GSTRING_LEN )
336
337 #define S2IO_TEST_LEN ARRAY_SIZE(s2io_gstrings)
338 #define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN
339
340 #define S2IO_TIMER_CONF(timer, handle, arg, exp) \
341 init_timer(&timer); \
342 timer.function = handle; \
343 timer.data = (unsigned long) arg; \
344 mod_timer(&timer, (jiffies + exp)) \
345
346 /* copy mac addr to def_mac_addr array */
347 static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
348 {
349 sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
350 sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
351 sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
352 sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
353 sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
354 sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
355 }
356
357 /* Add the vlan */
358 static void s2io_vlan_rx_register(struct net_device *dev,
359 struct vlan_group *grp)
360 {
361 int i;
362 struct s2io_nic *nic = netdev_priv(dev);
363 unsigned long flags[MAX_TX_FIFOS];
364 struct mac_info *mac_control = &nic->mac_control;
365 struct config_param *config = &nic->config;
366
367 for (i = 0; i < config->tx_fifo_num; i++)
368 spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags[i]);
369
370 nic->vlgrp = grp;
371 for (i = config->tx_fifo_num - 1; i >= 0; i--)
372 spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock,
373 flags[i]);
374 }
375
376 /* Unregister the vlan */
377 static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
378 {
379 int i;
380 struct s2io_nic *nic = netdev_priv(dev);
381 unsigned long flags[MAX_TX_FIFOS];
382 struct mac_info *mac_control = &nic->mac_control;
383 struct config_param *config = &nic->config;
384
385 for (i = 0; i < config->tx_fifo_num; i++)
386 spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags[i]);
387
388 if (nic->vlgrp)
389 vlan_group_set_device(nic->vlgrp, vid, NULL);
390
391 for (i = config->tx_fifo_num - 1; i >= 0; i--)
392 spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock,
393 flags[i]);
394 }
395
396 /*
397 * Constants to be programmed into the Xena's registers, to configure
398 * the XAUI.
399 */
400
401 #define END_SIGN 0x0
402 static const u64 herc_act_dtx_cfg[] = {
403 /* Set address */
404 0x8000051536750000ULL, 0x80000515367500E0ULL,
405 /* Write data */
406 0x8000051536750004ULL, 0x80000515367500E4ULL,
407 /* Set address */
408 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
409 /* Write data */
410 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
411 /* Set address */
412 0x801205150D440000ULL, 0x801205150D4400E0ULL,
413 /* Write data */
414 0x801205150D440004ULL, 0x801205150D4400E4ULL,
415 /* Set address */
416 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
417 /* Write data */
418 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
419 /* Done */
420 END_SIGN
421 };
422
423 static const u64 xena_dtx_cfg[] = {
424 /* Set address */
425 0x8000051500000000ULL, 0x80000515000000E0ULL,
426 /* Write data */
427 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
428 /* Set address */
429 0x8001051500000000ULL, 0x80010515000000E0ULL,
430 /* Write data */
431 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
432 /* Set address */
433 0x8002051500000000ULL, 0x80020515000000E0ULL,
434 /* Write data */
435 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
436 END_SIGN
437 };
438
439 /*
440 * Constants for Fixing the MacAddress problem seen mostly on
441 * Alpha machines.
442 */
443 static const u64 fix_mac[] = {
444 0x0060000000000000ULL, 0x0060600000000000ULL,
445 0x0040600000000000ULL, 0x0000600000000000ULL,
446 0x0020600000000000ULL, 0x0060600000000000ULL,
447 0x0020600000000000ULL, 0x0060600000000000ULL,
448 0x0020600000000000ULL, 0x0060600000000000ULL,
449 0x0020600000000000ULL, 0x0060600000000000ULL,
450 0x0020600000000000ULL, 0x0060600000000000ULL,
451 0x0020600000000000ULL, 0x0060600000000000ULL,
452 0x0020600000000000ULL, 0x0060600000000000ULL,
453 0x0020600000000000ULL, 0x0060600000000000ULL,
454 0x0020600000000000ULL, 0x0060600000000000ULL,
455 0x0020600000000000ULL, 0x0060600000000000ULL,
456 0x0020600000000000ULL, 0x0000600000000000ULL,
457 0x0040600000000000ULL, 0x0060600000000000ULL,
458 END_SIGN
459 };
460
461 MODULE_LICENSE("GPL");
462 MODULE_VERSION(DRV_VERSION);
463
464
465 /* Module Loadable parameters. */
466 S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM);
467 S2IO_PARM_INT(rx_ring_num, 1);
468 S2IO_PARM_INT(multiq, 0);
469 S2IO_PARM_INT(rx_ring_mode, 1);
470 S2IO_PARM_INT(use_continuous_tx_intrs, 1);
471 S2IO_PARM_INT(rmac_pause_time, 0x100);
472 S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
473 S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
474 S2IO_PARM_INT(shared_splits, 0);
475 S2IO_PARM_INT(tmac_util_period, 5);
476 S2IO_PARM_INT(rmac_util_period, 5);
477 S2IO_PARM_INT(l3l4hdr_size, 128);
478 /* 0 is no steering, 1 is Priority steering, 2 is Default steering */
479 S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING);
480 /* Frequency of Rx desc syncs expressed as power of 2 */
481 S2IO_PARM_INT(rxsync_frequency, 3);
482 /* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
483 S2IO_PARM_INT(intr_type, 2);
484 /* Large receive offload feature */
485 static unsigned int lro_enable;
486 module_param_named(lro, lro_enable, uint, 0);
487
488 /* Max pkts to be aggregated by LRO at one time. If not specified,
489 * aggregation happens until we hit max IP pkt size(64K)
490 */
491 S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
492 S2IO_PARM_INT(indicate_max_pkts, 0);
493
494 S2IO_PARM_INT(napi, 1);
495 S2IO_PARM_INT(ufo, 0);
496 S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
497
498 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
499 {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
500 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
501 {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
502 static unsigned int rts_frm_len[MAX_RX_RINGS] =
503 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
504
505 module_param_array(tx_fifo_len, uint, NULL, 0);
506 module_param_array(rx_ring_sz, uint, NULL, 0);
507 module_param_array(rts_frm_len, uint, NULL, 0);
508
509 /*
510 * S2IO device table.
511 * This table lists all the devices that this driver supports.
512 */
513 static struct pci_device_id s2io_tbl[] __devinitdata = {
514 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
515 PCI_ANY_ID, PCI_ANY_ID},
516 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
517 PCI_ANY_ID, PCI_ANY_ID},
518 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
519 PCI_ANY_ID, PCI_ANY_ID},
520 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
521 PCI_ANY_ID, PCI_ANY_ID},
522 {0,}
523 };
524
525 MODULE_DEVICE_TABLE(pci, s2io_tbl);
526
527 static struct pci_error_handlers s2io_err_handler = {
528 .error_detected = s2io_io_error_detected,
529 .slot_reset = s2io_io_slot_reset,
530 .resume = s2io_io_resume,
531 };
532
533 static struct pci_driver s2io_driver = {
534 .name = "S2IO",
535 .id_table = s2io_tbl,
536 .probe = s2io_init_nic,
537 .remove = __devexit_p(s2io_rem_nic),
538 .err_handler = &s2io_err_handler,
539 };
540
541 /* A simplifier macro used both by init and free shared_mem Fns(). */
542 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
543
544 /* netqueue manipulation helper functions */
545 static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp)
546 {
547 if (!sp->config.multiq) {
548 int i;
549
550 for (i = 0; i < sp->config.tx_fifo_num; i++)
551 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP;
552 }
553 netif_tx_stop_all_queues(sp->dev);
554 }
555
556 static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no)
557 {
558 if (!sp->config.multiq)
559 sp->mac_control.fifos[fifo_no].queue_state =
560 FIFO_QUEUE_STOP;
561
562 netif_tx_stop_all_queues(sp->dev);
563 }
564
565 static inline void s2io_start_all_tx_queue(struct s2io_nic *sp)
566 {
567 if (!sp->config.multiq) {
568 int i;
569
570 for (i = 0; i < sp->config.tx_fifo_num; i++)
571 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
572 }
573 netif_tx_start_all_queues(sp->dev);
574 }
575
576 static inline void s2io_start_tx_queue(struct s2io_nic *sp, int fifo_no)
577 {
578 if (!sp->config.multiq)
579 sp->mac_control.fifos[fifo_no].queue_state =
580 FIFO_QUEUE_START;
581
582 netif_tx_start_all_queues(sp->dev);
583 }
584
585 static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp)
586 {
587 if (!sp->config.multiq) {
588 int i;
589
590 for (i = 0; i < sp->config.tx_fifo_num; i++)
591 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
592 }
593 netif_tx_wake_all_queues(sp->dev);
594 }
595
596 static inline void s2io_wake_tx_queue(
597 struct fifo_info *fifo, int cnt, u8 multiq)
598 {
599
600 if (multiq) {
601 if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no))
602 netif_wake_subqueue(fifo->dev, fifo->fifo_no);
603 } else if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) {
604 if (netif_queue_stopped(fifo->dev)) {
605 fifo->queue_state = FIFO_QUEUE_START;
606 netif_wake_queue(fifo->dev);
607 }
608 }
609 }
610
611 /**
612 * init_shared_mem - Allocation and Initialization of Memory
613 * @nic: Device private variable.
614 * Description: The function allocates all the memory areas shared
615 * between the NIC and the driver. This includes Tx descriptors,
616 * Rx descriptors and the statistics block.
617 */
618
619 static int init_shared_mem(struct s2io_nic *nic)
620 {
621 u32 size;
622 void *tmp_v_addr, *tmp_v_addr_next;
623 dma_addr_t tmp_p_addr, tmp_p_addr_next;
624 struct RxD_block *pre_rxd_blk = NULL;
625 int i, j, blk_cnt;
626 int lst_size, lst_per_page;
627 struct net_device *dev = nic->dev;
628 unsigned long tmp;
629 struct buffAdd *ba;
630
631 struct mac_info *mac_control;
632 struct config_param *config;
633 unsigned long long mem_allocated = 0;
634
635 mac_control = &nic->mac_control;
636 config = &nic->config;
637
638
639 /* Allocation and initialization of TXDLs in FIOFs */
640 size = 0;
641 for (i = 0; i < config->tx_fifo_num; i++) {
642 size += config->tx_cfg[i].fifo_len;
643 }
644 if (size > MAX_AVAILABLE_TXDS) {
645 DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
646 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
647 return -EINVAL;
648 }
649
650 size = 0;
651 for (i = 0; i < config->tx_fifo_num; i++) {
652 size = config->tx_cfg[i].fifo_len;
653 /*
654 * Legal values are from 2 to 8192
655 */
656 if (size < 2) {
657 DBG_PRINT(ERR_DBG, "s2io: Invalid fifo len (%d)", size);
658 DBG_PRINT(ERR_DBG, "for fifo %d\n", i);
659 DBG_PRINT(ERR_DBG, "s2io: Legal values for fifo len"
660 "are 2 to 8192\n");
661 return -EINVAL;
662 }
663 }
664
665 lst_size = (sizeof(struct TxD) * config->max_txds);
666 lst_per_page = PAGE_SIZE / lst_size;
667
668 for (i = 0; i < config->tx_fifo_num; i++) {
669 int fifo_len = config->tx_cfg[i].fifo_len;
670 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
671 mac_control->fifos[i].list_info = kzalloc(list_holder_size,
672 GFP_KERNEL);
673 if (!mac_control->fifos[i].list_info) {
674 DBG_PRINT(INFO_DBG,
675 "Malloc failed for list_info\n");
676 return -ENOMEM;
677 }
678 mem_allocated += list_holder_size;
679 }
680 for (i = 0; i < config->tx_fifo_num; i++) {
681 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
682 lst_per_page);
683 mac_control->fifos[i].tx_curr_put_info.offset = 0;
684 mac_control->fifos[i].tx_curr_put_info.fifo_len =
685 config->tx_cfg[i].fifo_len - 1;
686 mac_control->fifos[i].tx_curr_get_info.offset = 0;
687 mac_control->fifos[i].tx_curr_get_info.fifo_len =
688 config->tx_cfg[i].fifo_len - 1;
689 mac_control->fifos[i].fifo_no = i;
690 mac_control->fifos[i].nic = nic;
691 mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
692 mac_control->fifos[i].dev = dev;
693
694 for (j = 0; j < page_num; j++) {
695 int k = 0;
696 dma_addr_t tmp_p;
697 void *tmp_v;
698 tmp_v = pci_alloc_consistent(nic->pdev,
699 PAGE_SIZE, &tmp_p);
700 if (!tmp_v) {
701 DBG_PRINT(INFO_DBG,
702 "pci_alloc_consistent ");
703 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
704 return -ENOMEM;
705 }
706 /* If we got a zero DMA address(can happen on
707 * certain platforms like PPC), reallocate.
708 * Store virtual address of page we don't want,
709 * to be freed later.
710 */
711 if (!tmp_p) {
712 mac_control->zerodma_virt_addr = tmp_v;
713 DBG_PRINT(INIT_DBG,
714 "%s: Zero DMA address for TxDL. ", dev->name);
715 DBG_PRINT(INIT_DBG,
716 "Virtual address %p\n", tmp_v);
717 tmp_v = pci_alloc_consistent(nic->pdev,
718 PAGE_SIZE, &tmp_p);
719 if (!tmp_v) {
720 DBG_PRINT(INFO_DBG,
721 "pci_alloc_consistent ");
722 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
723 return -ENOMEM;
724 }
725 mem_allocated += PAGE_SIZE;
726 }
727 while (k < lst_per_page) {
728 int l = (j * lst_per_page) + k;
729 if (l == config->tx_cfg[i].fifo_len)
730 break;
731 mac_control->fifos[i].list_info[l].list_virt_addr =
732 tmp_v + (k * lst_size);
733 mac_control->fifos[i].list_info[l].list_phy_addr =
734 tmp_p + (k * lst_size);
735 k++;
736 }
737 }
738 }
739
740 for (i = 0; i < config->tx_fifo_num; i++) {
741 size = config->tx_cfg[i].fifo_len;
742 mac_control->fifos[i].ufo_in_band_v
743 = kcalloc(size, sizeof(u64), GFP_KERNEL);
744 if (!mac_control->fifos[i].ufo_in_band_v)
745 return -ENOMEM;
746 mem_allocated += (size * sizeof(u64));
747 }
748
749 /* Allocation and initialization of RXDs in Rings */
750 size = 0;
751 for (i = 0; i < config->rx_ring_num; i++) {
752 if (config->rx_cfg[i].num_rxd %
753 (rxd_count[nic->rxd_mode] + 1)) {
754 DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
755 DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
756 i);
757 DBG_PRINT(ERR_DBG, "RxDs per Block");
758 return FAILURE;
759 }
760 size += config->rx_cfg[i].num_rxd;
761 mac_control->rings[i].block_count =
762 config->rx_cfg[i].num_rxd /
763 (rxd_count[nic->rxd_mode] + 1 );
764 mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
765 mac_control->rings[i].block_count;
766 }
767 if (nic->rxd_mode == RXD_MODE_1)
768 size = (size * (sizeof(struct RxD1)));
769 else
770 size = (size * (sizeof(struct RxD3)));
771
772 for (i = 0; i < config->rx_ring_num; i++) {
773 mac_control->rings[i].rx_curr_get_info.block_index = 0;
774 mac_control->rings[i].rx_curr_get_info.offset = 0;
775 mac_control->rings[i].rx_curr_get_info.ring_len =
776 config->rx_cfg[i].num_rxd - 1;
777 mac_control->rings[i].rx_curr_put_info.block_index = 0;
778 mac_control->rings[i].rx_curr_put_info.offset = 0;
779 mac_control->rings[i].rx_curr_put_info.ring_len =
780 config->rx_cfg[i].num_rxd - 1;
781 mac_control->rings[i].nic = nic;
782 mac_control->rings[i].ring_no = i;
783 mac_control->rings[i].lro = lro_enable;
784
785 blk_cnt = config->rx_cfg[i].num_rxd /
786 (rxd_count[nic->rxd_mode] + 1);
787 /* Allocating all the Rx blocks */
788 for (j = 0; j < blk_cnt; j++) {
789 struct rx_block_info *rx_blocks;
790 int l;
791
792 rx_blocks = &mac_control->rings[i].rx_blocks[j];
793 size = SIZE_OF_BLOCK; //size is always page size
794 tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
795 &tmp_p_addr);
796 if (tmp_v_addr == NULL) {
797 /*
798 * In case of failure, free_shared_mem()
799 * is called, which should free any
800 * memory that was alloced till the
801 * failure happened.
802 */
803 rx_blocks->block_virt_addr = tmp_v_addr;
804 return -ENOMEM;
805 }
806 mem_allocated += size;
807 memset(tmp_v_addr, 0, size);
808 rx_blocks->block_virt_addr = tmp_v_addr;
809 rx_blocks->block_dma_addr = tmp_p_addr;
810 rx_blocks->rxds = kmalloc(sizeof(struct rxd_info)*
811 rxd_count[nic->rxd_mode],
812 GFP_KERNEL);
813 if (!rx_blocks->rxds)
814 return -ENOMEM;
815 mem_allocated +=
816 (sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
817 for (l=0; l<rxd_count[nic->rxd_mode];l++) {
818 rx_blocks->rxds[l].virt_addr =
819 rx_blocks->block_virt_addr +
820 (rxd_size[nic->rxd_mode] * l);
821 rx_blocks->rxds[l].dma_addr =
822 rx_blocks->block_dma_addr +
823 (rxd_size[nic->rxd_mode] * l);
824 }
825 }
826 /* Interlinking all Rx Blocks */
827 for (j = 0; j < blk_cnt; j++) {
828 tmp_v_addr =
829 mac_control->rings[i].rx_blocks[j].block_virt_addr;
830 tmp_v_addr_next =
831 mac_control->rings[i].rx_blocks[(j + 1) %
832 blk_cnt].block_virt_addr;
833 tmp_p_addr =
834 mac_control->rings[i].rx_blocks[j].block_dma_addr;
835 tmp_p_addr_next =
836 mac_control->rings[i].rx_blocks[(j + 1) %
837 blk_cnt].block_dma_addr;
838
839 pre_rxd_blk = (struct RxD_block *) tmp_v_addr;
840 pre_rxd_blk->reserved_2_pNext_RxD_block =
841 (unsigned long) tmp_v_addr_next;
842 pre_rxd_blk->pNext_RxD_Blk_physical =
843 (u64) tmp_p_addr_next;
844 }
845 }
846 if (nic->rxd_mode == RXD_MODE_3B) {
847 /*
848 * Allocation of Storages for buffer addresses in 2BUFF mode
849 * and the buffers as well.
850 */
851 for (i = 0; i < config->rx_ring_num; i++) {
852 blk_cnt = config->rx_cfg[i].num_rxd /
853 (rxd_count[nic->rxd_mode]+ 1);
854 mac_control->rings[i].ba =
855 kmalloc((sizeof(struct buffAdd *) * blk_cnt),
856 GFP_KERNEL);
857 if (!mac_control->rings[i].ba)
858 return -ENOMEM;
859 mem_allocated +=(sizeof(struct buffAdd *) * blk_cnt);
860 for (j = 0; j < blk_cnt; j++) {
861 int k = 0;
862 mac_control->rings[i].ba[j] =
863 kmalloc((sizeof(struct buffAdd) *
864 (rxd_count[nic->rxd_mode] + 1)),
865 GFP_KERNEL);
866 if (!mac_control->rings[i].ba[j])
867 return -ENOMEM;
868 mem_allocated += (sizeof(struct buffAdd) * \
869 (rxd_count[nic->rxd_mode] + 1));
870 while (k != rxd_count[nic->rxd_mode]) {
871 ba = &mac_control->rings[i].ba[j][k];
872
873 ba->ba_0_org = (void *) kmalloc
874 (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
875 if (!ba->ba_0_org)
876 return -ENOMEM;
877 mem_allocated +=
878 (BUF0_LEN + ALIGN_SIZE);
879 tmp = (unsigned long)ba->ba_0_org;
880 tmp += ALIGN_SIZE;
881 tmp &= ~((unsigned long) ALIGN_SIZE);
882 ba->ba_0 = (void *) tmp;
883
884 ba->ba_1_org = (void *) kmalloc
885 (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
886 if (!ba->ba_1_org)
887 return -ENOMEM;
888 mem_allocated
889 += (BUF1_LEN + ALIGN_SIZE);
890 tmp = (unsigned long) ba->ba_1_org;
891 tmp += ALIGN_SIZE;
892 tmp &= ~((unsigned long) ALIGN_SIZE);
893 ba->ba_1 = (void *) tmp;
894 k++;
895 }
896 }
897 }
898 }
899
900 /* Allocation and initialization of Statistics block */
901 size = sizeof(struct stat_block);
902 mac_control->stats_mem = pci_alloc_consistent
903 (nic->pdev, size, &mac_control->stats_mem_phy);
904
905 if (!mac_control->stats_mem) {
906 /*
907 * In case of failure, free_shared_mem() is called, which
908 * should free any memory that was alloced till the
909 * failure happened.
910 */
911 return -ENOMEM;
912 }
913 mem_allocated += size;
914 mac_control->stats_mem_sz = size;
915
916 tmp_v_addr = mac_control->stats_mem;
917 mac_control->stats_info = (struct stat_block *) tmp_v_addr;
918 memset(tmp_v_addr, 0, size);
919 DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
920 (unsigned long long) tmp_p_addr);
921 mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
922 return SUCCESS;
923 }
924
925 /**
926 * free_shared_mem - Free the allocated Memory
927 * @nic: Device private variable.
928 * Description: This function is to free all memory locations allocated by
929 * the init_shared_mem() function and return it to the kernel.
930 */
931
932 static void free_shared_mem(struct s2io_nic *nic)
933 {
934 int i, j, blk_cnt, size;
935 void *tmp_v_addr;
936 dma_addr_t tmp_p_addr;
937 struct mac_info *mac_control;
938 struct config_param *config;
939 int lst_size, lst_per_page;
940 struct net_device *dev;
941 int page_num = 0;
942
943 if (!nic)
944 return;
945
946 dev = nic->dev;
947
948 mac_control = &nic->mac_control;
949 config = &nic->config;
950
951 lst_size = (sizeof(struct TxD) * config->max_txds);
952 lst_per_page = PAGE_SIZE / lst_size;
953
954 for (i = 0; i < config->tx_fifo_num; i++) {
955 page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
956 lst_per_page);
957 for (j = 0; j < page_num; j++) {
958 int mem_blks = (j * lst_per_page);
959 if (!mac_control->fifos[i].list_info)
960 return;
961 if (!mac_control->fifos[i].list_info[mem_blks].
962 list_virt_addr)
963 break;
964 pci_free_consistent(nic->pdev, PAGE_SIZE,
965 mac_control->fifos[i].
966 list_info[mem_blks].
967 list_virt_addr,
968 mac_control->fifos[i].
969 list_info[mem_blks].
970 list_phy_addr);
971 nic->mac_control.stats_info->sw_stat.mem_freed
972 += PAGE_SIZE;
973 }
974 /* If we got a zero DMA address during allocation,
975 * free the page now
976 */
977 if (mac_control->zerodma_virt_addr) {
978 pci_free_consistent(nic->pdev, PAGE_SIZE,
979 mac_control->zerodma_virt_addr,
980 (dma_addr_t)0);
981 DBG_PRINT(INIT_DBG,
982 "%s: Freeing TxDL with zero DMA addr. ",
983 dev->name);
984 DBG_PRINT(INIT_DBG, "Virtual address %p\n",
985 mac_control->zerodma_virt_addr);
986 nic->mac_control.stats_info->sw_stat.mem_freed
987 += PAGE_SIZE;
988 }
989 kfree(mac_control->fifos[i].list_info);
990 nic->mac_control.stats_info->sw_stat.mem_freed +=
991 (nic->config.tx_cfg[i].fifo_len *sizeof(struct list_info_hold));
992 }
993
994 size = SIZE_OF_BLOCK;
995 for (i = 0; i < config->rx_ring_num; i++) {
996 blk_cnt = mac_control->rings[i].block_count;
997 for (j = 0; j < blk_cnt; j++) {
998 tmp_v_addr = mac_control->rings[i].rx_blocks[j].
999 block_virt_addr;
1000 tmp_p_addr = mac_control->rings[i].rx_blocks[j].
1001 block_dma_addr;
1002 if (tmp_v_addr == NULL)
1003 break;
1004 pci_free_consistent(nic->pdev, size,
1005 tmp_v_addr, tmp_p_addr);
1006 nic->mac_control.stats_info->sw_stat.mem_freed += size;
1007 kfree(mac_control->rings[i].rx_blocks[j].rxds);
1008 nic->mac_control.stats_info->sw_stat.mem_freed +=
1009 ( sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
1010 }
1011 }
1012
1013 if (nic->rxd_mode == RXD_MODE_3B) {
1014 /* Freeing buffer storage addresses in 2BUFF mode. */
1015 for (i = 0; i < config->rx_ring_num; i++) {
1016 blk_cnt = config->rx_cfg[i].num_rxd /
1017 (rxd_count[nic->rxd_mode] + 1);
1018 for (j = 0; j < blk_cnt; j++) {
1019 int k = 0;
1020 if (!mac_control->rings[i].ba[j])
1021 continue;
1022 while (k != rxd_count[nic->rxd_mode]) {
1023 struct buffAdd *ba =
1024 &mac_control->rings[i].ba[j][k];
1025 kfree(ba->ba_0_org);
1026 nic->mac_control.stats_info->sw_stat.\
1027 mem_freed += (BUF0_LEN + ALIGN_SIZE);
1028 kfree(ba->ba_1_org);
1029 nic->mac_control.stats_info->sw_stat.\
1030 mem_freed += (BUF1_LEN + ALIGN_SIZE);
1031 k++;
1032 }
1033 kfree(mac_control->rings[i].ba[j]);
1034 nic->mac_control.stats_info->sw_stat.mem_freed +=
1035 (sizeof(struct buffAdd) *
1036 (rxd_count[nic->rxd_mode] + 1));
1037 }
1038 kfree(mac_control->rings[i].ba);
1039 nic->mac_control.stats_info->sw_stat.mem_freed +=
1040 (sizeof(struct buffAdd *) * blk_cnt);
1041 }
1042 }
1043
1044 for (i = 0; i < nic->config.tx_fifo_num; i++) {
1045 if (mac_control->fifos[i].ufo_in_band_v) {
1046 nic->mac_control.stats_info->sw_stat.mem_freed
1047 += (config->tx_cfg[i].fifo_len * sizeof(u64));
1048 kfree(mac_control->fifos[i].ufo_in_band_v);
1049 }
1050 }
1051
1052 if (mac_control->stats_mem) {
1053 nic->mac_control.stats_info->sw_stat.mem_freed +=
1054 mac_control->stats_mem_sz;
1055 pci_free_consistent(nic->pdev,
1056 mac_control->stats_mem_sz,
1057 mac_control->stats_mem,
1058 mac_control->stats_mem_phy);
1059 }
1060 }
1061
1062 /**
1063 * s2io_verify_pci_mode -
1064 */
1065
1066 static int s2io_verify_pci_mode(struct s2io_nic *nic)
1067 {
1068 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1069 register u64 val64 = 0;
1070 int mode;
1071
1072 val64 = readq(&bar0->pci_mode);
1073 mode = (u8)GET_PCI_MODE(val64);
1074
1075 if ( val64 & PCI_MODE_UNKNOWN_MODE)
1076 return -1; /* Unknown PCI mode */
1077 return mode;
1078 }
1079
1080 #define NEC_VENID 0x1033
1081 #define NEC_DEVID 0x0125
1082 static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
1083 {
1084 struct pci_dev *tdev = NULL;
1085 while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
1086 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
1087 if (tdev->bus == s2io_pdev->bus->parent) {
1088 pci_dev_put(tdev);
1089 return 1;
1090 }
1091 }
1092 }
1093 return 0;
1094 }
1095
1096 static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
1097 /**
1098 * s2io_print_pci_mode -
1099 */
1100 static int s2io_print_pci_mode(struct s2io_nic *nic)
1101 {
1102 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1103 register u64 val64 = 0;
1104 int mode;
1105 struct config_param *config = &nic->config;
1106
1107 val64 = readq(&bar0->pci_mode);
1108 mode = (u8)GET_PCI_MODE(val64);
1109
1110 if ( val64 & PCI_MODE_UNKNOWN_MODE)
1111 return -1; /* Unknown PCI mode */
1112
1113 config->bus_speed = bus_speed[mode];
1114
1115 if (s2io_on_nec_bridge(nic->pdev)) {
1116 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
1117 nic->dev->name);
1118 return mode;
1119 }
1120
1121 if (val64 & PCI_MODE_32_BITS) {
1122 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
1123 } else {
1124 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
1125 }
1126
1127 switch(mode) {
1128 case PCI_MODE_PCI_33:
1129 DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
1130 break;
1131 case PCI_MODE_PCI_66:
1132 DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
1133 break;
1134 case PCI_MODE_PCIX_M1_66:
1135 DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
1136 break;
1137 case PCI_MODE_PCIX_M1_100:
1138 DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
1139 break;
1140 case PCI_MODE_PCIX_M1_133:
1141 DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
1142 break;
1143 case PCI_MODE_PCIX_M2_66:
1144 DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
1145 break;
1146 case PCI_MODE_PCIX_M2_100:
1147 DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
1148 break;
1149 case PCI_MODE_PCIX_M2_133:
1150 DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
1151 break;
1152 default:
1153 return -1; /* Unsupported bus speed */
1154 }
1155
1156 return mode;
1157 }
1158
1159 /**
1160 * init_tti - Initialization transmit traffic interrupt scheme
1161 * @nic: device private variable
1162 * @link: link status (UP/DOWN) used to enable/disable continuous
1163 * transmit interrupts
1164 * Description: The function configures transmit traffic interrupts
1165 * Return Value: SUCCESS on success and
1166 * '-1' on failure
1167 */
1168
1169 static int init_tti(struct s2io_nic *nic, int link)
1170 {
1171 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1172 register u64 val64 = 0;
1173 int i;
1174 struct config_param *config;
1175
1176 config = &nic->config;
1177
1178 for (i = 0; i < config->tx_fifo_num; i++) {
1179 /*
1180 * TTI Initialization. Default Tx timer gets us about
1181 * 250 interrupts per sec. Continuous interrupts are enabled
1182 * by default.
1183 */
1184 if (nic->device_type == XFRAME_II_DEVICE) {
1185 int count = (nic->config.bus_speed * 125)/2;
1186 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1187 } else
1188 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1189
1190 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1191 TTI_DATA1_MEM_TX_URNG_B(0x10) |
1192 TTI_DATA1_MEM_TX_URNG_C(0x30) |
1193 TTI_DATA1_MEM_TX_TIMER_AC_EN;
1194 if (i == 0)
1195 if (use_continuous_tx_intrs && (link == LINK_UP))
1196 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1197 writeq(val64, &bar0->tti_data1_mem);
1198
1199 if (nic->config.intr_type == MSI_X) {
1200 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1201 TTI_DATA2_MEM_TX_UFC_B(0x100) |
1202 TTI_DATA2_MEM_TX_UFC_C(0x200) |
1203 TTI_DATA2_MEM_TX_UFC_D(0x300);
1204 } else {
1205 if ((nic->config.tx_steering_type ==
1206 TX_DEFAULT_STEERING) &&
1207 (config->tx_fifo_num > 1) &&
1208 (i >= nic->udp_fifo_idx) &&
1209 (i < (nic->udp_fifo_idx +
1210 nic->total_udp_fifos)))
1211 val64 = TTI_DATA2_MEM_TX_UFC_A(0x50) |
1212 TTI_DATA2_MEM_TX_UFC_B(0x80) |
1213 TTI_DATA2_MEM_TX_UFC_C(0x100) |
1214 TTI_DATA2_MEM_TX_UFC_D(0x120);
1215 else
1216 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1217 TTI_DATA2_MEM_TX_UFC_B(0x20) |
1218 TTI_DATA2_MEM_TX_UFC_C(0x40) |
1219 TTI_DATA2_MEM_TX_UFC_D(0x80);
1220 }
1221
1222 writeq(val64, &bar0->tti_data2_mem);
1223
1224 val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD |
1225 TTI_CMD_MEM_OFFSET(i);
1226 writeq(val64, &bar0->tti_command_mem);
1227
1228 if (wait_for_cmd_complete(&bar0->tti_command_mem,
1229 TTI_CMD_MEM_STROBE_NEW_CMD, S2IO_BIT_RESET) != SUCCESS)
1230 return FAILURE;
1231 }
1232
1233 return SUCCESS;
1234 }
1235
1236 /**
1237 * init_nic - Initialization of hardware
1238 * @nic: device private variable
1239 * Description: The function sequentially configures every block
1240 * of the H/W from their reset values.
1241 * Return Value: SUCCESS on success and
1242 * '-1' on failure (endian settings incorrect).
1243 */
1244
1245 static int init_nic(struct s2io_nic *nic)
1246 {
1247 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1248 struct net_device *dev = nic->dev;
1249 register u64 val64 = 0;
1250 void __iomem *add;
1251 u32 time;
1252 int i, j;
1253 struct mac_info *mac_control;
1254 struct config_param *config;
1255 int dtx_cnt = 0;
1256 unsigned long long mem_share;
1257 int mem_size;
1258
1259 mac_control = &nic->mac_control;
1260 config = &nic->config;
1261
1262 /* to set the swapper controle on the card */
1263 if(s2io_set_swapper(nic)) {
1264 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
1265 return -EIO;
1266 }
1267
1268 /*
1269 * Herc requires EOI to be removed from reset before XGXS, so..
1270 */
1271 if (nic->device_type & XFRAME_II_DEVICE) {
1272 val64 = 0xA500000000ULL;
1273 writeq(val64, &bar0->sw_reset);
1274 msleep(500);
1275 val64 = readq(&bar0->sw_reset);
1276 }
1277
1278 /* Remove XGXS from reset state */
1279 val64 = 0;
1280 writeq(val64, &bar0->sw_reset);
1281 msleep(500);
1282 val64 = readq(&bar0->sw_reset);
1283
1284 /* Ensure that it's safe to access registers by checking
1285 * RIC_RUNNING bit is reset. Check is valid only for XframeII.
1286 */
1287 if (nic->device_type == XFRAME_II_DEVICE) {
1288 for (i = 0; i < 50; i++) {
1289 val64 = readq(&bar0->adapter_status);
1290 if (!(val64 & ADAPTER_STATUS_RIC_RUNNING))
1291 break;
1292 msleep(10);
1293 }
1294 if (i == 50)
1295 return -ENODEV;
1296 }
1297
1298 /* Enable Receiving broadcasts */
1299 add = &bar0->mac_cfg;
1300 val64 = readq(&bar0->mac_cfg);
1301 val64 |= MAC_RMAC_BCAST_ENABLE;
1302 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1303 writel((u32) val64, add);
1304 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1305 writel((u32) (val64 >> 32), (add + 4));
1306
1307 /* Read registers in all blocks */
1308 val64 = readq(&bar0->mac_int_mask);
1309 val64 = readq(&bar0->mc_int_mask);
1310 val64 = readq(&bar0->xgxs_int_mask);
1311
1312 /* Set MTU */
1313 val64 = dev->mtu;
1314 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1315
1316 if (nic->device_type & XFRAME_II_DEVICE) {
1317 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
1318 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1319 &bar0->dtx_control, UF);
1320 if (dtx_cnt & 0x1)
1321 msleep(1); /* Necessary!! */
1322 dtx_cnt++;
1323 }
1324 } else {
1325 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1326 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1327 &bar0->dtx_control, UF);
1328 val64 = readq(&bar0->dtx_control);
1329 dtx_cnt++;
1330 }
1331 }
1332
1333 /* Tx DMA Initialization */
1334 val64 = 0;
1335 writeq(val64, &bar0->tx_fifo_partition_0);
1336 writeq(val64, &bar0->tx_fifo_partition_1);
1337 writeq(val64, &bar0->tx_fifo_partition_2);
1338 writeq(val64, &bar0->tx_fifo_partition_3);
1339
1340
1341 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1342 val64 |=
1343 vBIT(config->tx_cfg[i].fifo_len - 1, ((j * 32) + 19),
1344 13) | vBIT(config->tx_cfg[i].fifo_priority,
1345 ((j * 32) + 5), 3);
1346
1347 if (i == (config->tx_fifo_num - 1)) {
1348 if (i % 2 == 0)
1349 i++;
1350 }
1351
1352 switch (i) {
1353 case 1:
1354 writeq(val64, &bar0->tx_fifo_partition_0);
1355 val64 = 0;
1356 j = 0;
1357 break;
1358 case 3:
1359 writeq(val64, &bar0->tx_fifo_partition_1);
1360 val64 = 0;
1361 j = 0;
1362 break;
1363 case 5:
1364 writeq(val64, &bar0->tx_fifo_partition_2);
1365 val64 = 0;
1366 j = 0;
1367 break;
1368 case 7:
1369 writeq(val64, &bar0->tx_fifo_partition_3);
1370 val64 = 0;
1371 j = 0;
1372 break;
1373 default:
1374 j++;
1375 break;
1376 }
1377 }
1378
1379 /*
1380 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1381 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1382 */
1383 if ((nic->device_type == XFRAME_I_DEVICE) &&
1384 (nic->pdev->revision < 4))
1385 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1386
1387 val64 = readq(&bar0->tx_fifo_partition_0);
1388 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1389 &bar0->tx_fifo_partition_0, (unsigned long long) val64);
1390
1391 /*
1392 * Initialization of Tx_PA_CONFIG register to ignore packet
1393 * integrity checking.
1394 */
1395 val64 = readq(&bar0->tx_pa_cfg);
1396 val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
1397 TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
1398 writeq(val64, &bar0->tx_pa_cfg);
1399
1400 /* Rx DMA intialization. */
1401 val64 = 0;
1402 for (i = 0; i < config->rx_ring_num; i++) {
1403 val64 |=
1404 vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
1405 3);
1406 }
1407 writeq(val64, &bar0->rx_queue_priority);
1408
1409 /*
1410 * Allocating equal share of memory to all the
1411 * configured Rings.
1412 */
1413 val64 = 0;
1414 if (nic->device_type & XFRAME_II_DEVICE)
1415 mem_size = 32;
1416 else
1417 mem_size = 64;
1418
1419 for (i = 0; i < config->rx_ring_num; i++) {
1420 switch (i) {
1421 case 0:
1422 mem_share = (mem_size / config->rx_ring_num +
1423 mem_size % config->rx_ring_num);
1424 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1425 continue;
1426 case 1:
1427 mem_share = (mem_size / config->rx_ring_num);
1428 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1429 continue;
1430 case 2:
1431 mem_share = (mem_size / config->rx_ring_num);
1432 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1433 continue;
1434 case 3:
1435 mem_share = (mem_size / config->rx_ring_num);
1436 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1437 continue;
1438 case 4:
1439 mem_share = (mem_size / config->rx_ring_num);
1440 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1441 continue;
1442 case 5:
1443 mem_share = (mem_size / config->rx_ring_num);
1444 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1445 continue;
1446 case 6:
1447 mem_share = (mem_size / config->rx_ring_num);
1448 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1449 continue;
1450 case 7:
1451 mem_share = (mem_size / config->rx_ring_num);
1452 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1453 continue;
1454 }
1455 }
1456 writeq(val64, &bar0->rx_queue_cfg);
1457
1458 /*
1459 * Filling Tx round robin registers
1460 * as per the number of FIFOs for equal scheduling priority
1461 */
1462 switch (config->tx_fifo_num) {
1463 case 1:
1464 val64 = 0x0;
1465 writeq(val64, &bar0->tx_w_round_robin_0);
1466 writeq(val64, &bar0->tx_w_round_robin_1);
1467 writeq(val64, &bar0->tx_w_round_robin_2);
1468 writeq(val64, &bar0->tx_w_round_robin_3);
1469 writeq(val64, &bar0->tx_w_round_robin_4);
1470 break;
1471 case 2:
1472 val64 = 0x0001000100010001ULL;
1473 writeq(val64, &bar0->tx_w_round_robin_0);
1474 writeq(val64, &bar0->tx_w_round_robin_1);
1475 writeq(val64, &bar0->tx_w_round_robin_2);
1476 writeq(val64, &bar0->tx_w_round_robin_3);
1477 val64 = 0x0001000100000000ULL;
1478 writeq(val64, &bar0->tx_w_round_robin_4);
1479 break;
1480 case 3:
1481 val64 = 0x0001020001020001ULL;
1482 writeq(val64, &bar0->tx_w_round_robin_0);
1483 val64 = 0x0200010200010200ULL;
1484 writeq(val64, &bar0->tx_w_round_robin_1);
1485 val64 = 0x0102000102000102ULL;
1486 writeq(val64, &bar0->tx_w_round_robin_2);
1487 val64 = 0x0001020001020001ULL;
1488 writeq(val64, &bar0->tx_w_round_robin_3);
1489 val64 = 0x0200010200000000ULL;
1490 writeq(val64, &bar0->tx_w_round_robin_4);
1491 break;
1492 case 4:
1493 val64 = 0x0001020300010203ULL;
1494 writeq(val64, &bar0->tx_w_round_robin_0);
1495 writeq(val64, &bar0->tx_w_round_robin_1);
1496 writeq(val64, &bar0->tx_w_round_robin_2);
1497 writeq(val64, &bar0->tx_w_round_robin_3);
1498 val64 = 0x0001020300000000ULL;
1499 writeq(val64, &bar0->tx_w_round_robin_4);
1500 break;
1501 case 5:
1502 val64 = 0x0001020304000102ULL;
1503 writeq(val64, &bar0->tx_w_round_robin_0);
1504 val64 = 0x0304000102030400ULL;
1505 writeq(val64, &bar0->tx_w_round_robin_1);
1506 val64 = 0x0102030400010203ULL;
1507 writeq(val64, &bar0->tx_w_round_robin_2);
1508 val64 = 0x0400010203040001ULL;
1509 writeq(val64, &bar0->tx_w_round_robin_3);
1510 val64 = 0x0203040000000000ULL;
1511 writeq(val64, &bar0->tx_w_round_robin_4);
1512 break;
1513 case 6:
1514 val64 = 0x0001020304050001ULL;
1515 writeq(val64, &bar0->tx_w_round_robin_0);
1516 val64 = 0x0203040500010203ULL;
1517 writeq(val64, &bar0->tx_w_round_robin_1);
1518 val64 = 0x0405000102030405ULL;
1519 writeq(val64, &bar0->tx_w_round_robin_2);
1520 val64 = 0x0001020304050001ULL;
1521 writeq(val64, &bar0->tx_w_round_robin_3);
1522 val64 = 0x0203040500000000ULL;
1523 writeq(val64, &bar0->tx_w_round_robin_4);
1524 break;
1525 case 7:
1526 val64 = 0x0001020304050600ULL;
1527 writeq(val64, &bar0->tx_w_round_robin_0);
1528 val64 = 0x0102030405060001ULL;
1529 writeq(val64, &bar0->tx_w_round_robin_1);
1530 val64 = 0x0203040506000102ULL;
1531 writeq(val64, &bar0->tx_w_round_robin_2);
1532 val64 = 0x0304050600010203ULL;
1533 writeq(val64, &bar0->tx_w_round_robin_3);
1534 val64 = 0x0405060000000000ULL;
1535 writeq(val64, &bar0->tx_w_round_robin_4);
1536 break;
1537 case 8:
1538 val64 = 0x0001020304050607ULL;
1539 writeq(val64, &bar0->tx_w_round_robin_0);
1540 writeq(val64, &bar0->tx_w_round_robin_1);
1541 writeq(val64, &bar0->tx_w_round_robin_2);
1542 writeq(val64, &bar0->tx_w_round_robin_3);
1543 val64 = 0x0001020300000000ULL;
1544 writeq(val64, &bar0->tx_w_round_robin_4);
1545 break;
1546 }
1547
1548 /* Enable all configured Tx FIFO partitions */
1549 val64 = readq(&bar0->tx_fifo_partition_0);
1550 val64 |= (TX_FIFO_PARTITION_EN);
1551 writeq(val64, &bar0->tx_fifo_partition_0);
1552
1553 /* Filling the Rx round robin registers as per the
1554 * number of Rings and steering based on QoS with
1555 * equal priority.
1556 */
1557 switch (config->rx_ring_num) {
1558 case 1:
1559 val64 = 0x0;
1560 writeq(val64, &bar0->rx_w_round_robin_0);
1561 writeq(val64, &bar0->rx_w_round_robin_1);
1562 writeq(val64, &bar0->rx_w_round_robin_2);
1563 writeq(val64, &bar0->rx_w_round_robin_3);
1564 writeq(val64, &bar0->rx_w_round_robin_4);
1565
1566 val64 = 0x8080808080808080ULL;
1567 writeq(val64, &bar0->rts_qos_steering);
1568 break;
1569 case 2:
1570 val64 = 0x0001000100010001ULL;
1571 writeq(val64, &bar0->rx_w_round_robin_0);
1572 writeq(val64, &bar0->rx_w_round_robin_1);
1573 writeq(val64, &bar0->rx_w_round_robin_2);
1574 writeq(val64, &bar0->rx_w_round_robin_3);
1575 val64 = 0x0001000100000000ULL;
1576 writeq(val64, &bar0->rx_w_round_robin_4);
1577
1578 val64 = 0x8080808040404040ULL;
1579 writeq(val64, &bar0->rts_qos_steering);
1580 break;
1581 case 3:
1582 val64 = 0x0001020001020001ULL;
1583 writeq(val64, &bar0->rx_w_round_robin_0);
1584 val64 = 0x0200010200010200ULL;
1585 writeq(val64, &bar0->rx_w_round_robin_1);
1586 val64 = 0x0102000102000102ULL;
1587 writeq(val64, &bar0->rx_w_round_robin_2);
1588 val64 = 0x0001020001020001ULL;
1589 writeq(val64, &bar0->rx_w_round_robin_3);
1590 val64 = 0x0200010200000000ULL;
1591 writeq(val64, &bar0->rx_w_round_robin_4);
1592
1593 val64 = 0x8080804040402020ULL;
1594 writeq(val64, &bar0->rts_qos_steering);
1595 break;
1596 case 4:
1597 val64 = 0x0001020300010203ULL;
1598 writeq(val64, &bar0->rx_w_round_robin_0);
1599 writeq(val64, &bar0->rx_w_round_robin_1);
1600 writeq(val64, &bar0->rx_w_round_robin_2);
1601 writeq(val64, &bar0->rx_w_round_robin_3);
1602 val64 = 0x0001020300000000ULL;
1603 writeq(val64, &bar0->rx_w_round_robin_4);
1604
1605 val64 = 0x8080404020201010ULL;
1606 writeq(val64, &bar0->rts_qos_steering);
1607 break;
1608 case 5:
1609 val64 = 0x0001020304000102ULL;
1610 writeq(val64, &bar0->rx_w_round_robin_0);
1611 val64 = 0x0304000102030400ULL;
1612 writeq(val64, &bar0->rx_w_round_robin_1);
1613 val64 = 0x0102030400010203ULL;
1614 writeq(val64, &bar0->rx_w_round_robin_2);
1615 val64 = 0x0400010203040001ULL;
1616 writeq(val64, &bar0->rx_w_round_robin_3);
1617 val64 = 0x0203040000000000ULL;
1618 writeq(val64, &bar0->rx_w_round_robin_4);
1619
1620 val64 = 0x8080404020201008ULL;
1621 writeq(val64, &bar0->rts_qos_steering);
1622 break;
1623 case 6:
1624 val64 = 0x0001020304050001ULL;
1625 writeq(val64, &bar0->rx_w_round_robin_0);
1626 val64 = 0x0203040500010203ULL;
1627 writeq(val64, &bar0->rx_w_round_robin_1);
1628 val64 = 0x0405000102030405ULL;
1629 writeq(val64, &bar0->rx_w_round_robin_2);
1630 val64 = 0x0001020304050001ULL;
1631 writeq(val64, &bar0->rx_w_round_robin_3);
1632 val64 = 0x0203040500000000ULL;
1633 writeq(val64, &bar0->rx_w_round_robin_4);
1634
1635 val64 = 0x8080404020100804ULL;
1636 writeq(val64, &bar0->rts_qos_steering);
1637 break;
1638 case 7:
1639 val64 = 0x0001020304050600ULL;
1640 writeq(val64, &bar0->rx_w_round_robin_0);
1641 val64 = 0x0102030405060001ULL;
1642 writeq(val64, &bar0->rx_w_round_robin_1);
1643 val64 = 0x0203040506000102ULL;
1644 writeq(val64, &bar0->rx_w_round_robin_2);
1645 val64 = 0x0304050600010203ULL;
1646 writeq(val64, &bar0->rx_w_round_robin_3);
1647 val64 = 0x0405060000000000ULL;
1648 writeq(val64, &bar0->rx_w_round_robin_4);
1649
1650 val64 = 0x8080402010080402ULL;
1651 writeq(val64, &bar0->rts_qos_steering);
1652 break;
1653 case 8:
1654 val64 = 0x0001020304050607ULL;
1655 writeq(val64, &bar0->rx_w_round_robin_0);
1656 writeq(val64, &bar0->rx_w_round_robin_1);
1657 writeq(val64, &bar0->rx_w_round_robin_2);
1658 writeq(val64, &bar0->rx_w_round_robin_3);
1659 val64 = 0x0001020300000000ULL;
1660 writeq(val64, &bar0->rx_w_round_robin_4);
1661
1662 val64 = 0x8040201008040201ULL;
1663 writeq(val64, &bar0->rts_qos_steering);
1664 break;
1665 }
1666
1667 /* UDP Fix */
1668 val64 = 0;
1669 for (i = 0; i < 8; i++)
1670 writeq(val64, &bar0->rts_frm_len_n[i]);
1671
1672 /* Set the default rts frame length for the rings configured */
1673 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1674 for (i = 0 ; i < config->rx_ring_num ; i++)
1675 writeq(val64, &bar0->rts_frm_len_n[i]);
1676
1677 /* Set the frame length for the configured rings
1678 * desired by the user
1679 */
1680 for (i = 0; i < config->rx_ring_num; i++) {
1681 /* If rts_frm_len[i] == 0 then it is assumed that user not
1682 * specified frame length steering.
1683 * If the user provides the frame length then program
1684 * the rts_frm_len register for those values or else
1685 * leave it as it is.
1686 */
1687 if (rts_frm_len[i] != 0) {
1688 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1689 &bar0->rts_frm_len_n[i]);
1690 }
1691 }
1692
1693 /* Disable differentiated services steering logic */
1694 for (i = 0; i < 64; i++) {
1695 if (rts_ds_steer(nic, i, 0) == FAILURE) {
1696 DBG_PRINT(ERR_DBG, "%s: failed rts ds steering",
1697 dev->name);
1698 DBG_PRINT(ERR_DBG, "set on codepoint %d\n", i);
1699 return -ENODEV;
1700 }
1701 }
1702
1703 /* Program statistics memory */
1704 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1705
1706 if (nic->device_type == XFRAME_II_DEVICE) {
1707 val64 = STAT_BC(0x320);
1708 writeq(val64, &bar0->stat_byte_cnt);
1709 }
1710
1711 /*
1712 * Initializing the sampling rate for the device to calculate the
1713 * bandwidth utilization.
1714 */
1715 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1716 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1717 writeq(val64, &bar0->mac_link_util);
1718
1719 /*
1720 * Initializing the Transmit and Receive Traffic Interrupt
1721 * Scheme.
1722 */
1723
1724 /* Initialize TTI */
1725 if (SUCCESS != init_tti(nic, nic->last_link_state))
1726 return -ENODEV;
1727
1728 /* RTI Initialization */
1729 if (nic->device_type == XFRAME_II_DEVICE) {
1730 /*
1731 * Programmed to generate Apprx 500 Intrs per
1732 * second
1733 */
1734 int count = (nic->config.bus_speed * 125)/4;
1735 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1736 } else
1737 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1738 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1739 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1740 RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
1741
1742 writeq(val64, &bar0->rti_data1_mem);
1743
1744 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1745 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1746 if (nic->config.intr_type == MSI_X)
1747 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1748 RTI_DATA2_MEM_RX_UFC_D(0x40));
1749 else
1750 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1751 RTI_DATA2_MEM_RX_UFC_D(0x80));
1752 writeq(val64, &bar0->rti_data2_mem);
1753
1754 for (i = 0; i < config->rx_ring_num; i++) {
1755 val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
1756 | RTI_CMD_MEM_OFFSET(i);
1757 writeq(val64, &bar0->rti_command_mem);
1758
1759 /*
1760 * Once the operation completes, the Strobe bit of the
1761 * command register will be reset. We poll for this
1762 * particular condition. We wait for a maximum of 500ms
1763 * for the operation to complete, if it's not complete
1764 * by then we return error.
1765 */
1766 time = 0;
1767 while (true) {
1768 val64 = readq(&bar0->rti_command_mem);
1769 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1770 break;
1771
1772 if (time > 10) {
1773 DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1774 dev->name);
1775 return -ENODEV;
1776 }
1777 time++;
1778 msleep(50);
1779 }
1780 }
1781
1782 /*
1783 * Initializing proper values as Pause threshold into all
1784 * the 8 Queues on Rx side.
1785 */
1786 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1787 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1788
1789 /* Disable RMAC PAD STRIPPING */
1790 add = &bar0->mac_cfg;
1791 val64 = readq(&bar0->mac_cfg);
1792 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1793 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1794 writel((u32) (val64), add);
1795 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1796 writel((u32) (val64 >> 32), (add + 4));
1797 val64 = readq(&bar0->mac_cfg);
1798
1799 /* Enable FCS stripping by adapter */
1800 add = &bar0->mac_cfg;
1801 val64 = readq(&bar0->mac_cfg);
1802 val64 |= MAC_CFG_RMAC_STRIP_FCS;
1803 if (nic->device_type == XFRAME_II_DEVICE)
1804 writeq(val64, &bar0->mac_cfg);
1805 else {
1806 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1807 writel((u32) (val64), add);
1808 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1809 writel((u32) (val64 >> 32), (add + 4));
1810 }
1811
1812 /*
1813 * Set the time value to be inserted in the pause frame
1814 * generated by xena.
1815 */
1816 val64 = readq(&bar0->rmac_pause_cfg);
1817 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1818 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1819 writeq(val64, &bar0->rmac_pause_cfg);
1820
1821 /*
1822 * Set the Threshold Limit for Generating the pause frame
1823 * If the amount of data in any Queue exceeds ratio of
1824 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1825 * pause frame is generated
1826 */
1827 val64 = 0;
1828 for (i = 0; i < 4; i++) {
1829 val64 |=
1830 (((u64) 0xFF00 | nic->mac_control.
1831 mc_pause_threshold_q0q3)
1832 << (i * 2 * 8));
1833 }
1834 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1835
1836 val64 = 0;
1837 for (i = 0; i < 4; i++) {
1838 val64 |=
1839 (((u64) 0xFF00 | nic->mac_control.
1840 mc_pause_threshold_q4q7)
1841 << (i * 2 * 8));
1842 }
1843 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1844
1845 /*
1846 * TxDMA will stop Read request if the number of read split has
1847 * exceeded the limit pointed by shared_splits
1848 */
1849 val64 = readq(&bar0->pic_control);
1850 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1851 writeq(val64, &bar0->pic_control);
1852
1853 if (nic->config.bus_speed == 266) {
1854 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1855 writeq(0x0, &bar0->read_retry_delay);
1856 writeq(0x0, &bar0->write_retry_delay);
1857 }
1858
1859 /*
1860 * Programming the Herc to split every write transaction
1861 * that does not start on an ADB to reduce disconnects.
1862 */
1863 if (nic->device_type == XFRAME_II_DEVICE) {
1864 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1865 MISC_LINK_STABILITY_PRD(3);
1866 writeq(val64, &bar0->misc_control);
1867 val64 = readq(&bar0->pic_control2);
1868 val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
1869 writeq(val64, &bar0->pic_control2);
1870 }
1871 if (strstr(nic->product_name, "CX4")) {
1872 val64 = TMAC_AVG_IPG(0x17);
1873 writeq(val64, &bar0->tmac_avg_ipg);
1874 }
1875
1876 return SUCCESS;
1877 }
1878 #define LINK_UP_DOWN_INTERRUPT 1
1879 #define MAC_RMAC_ERR_TIMER 2
1880
1881 static int s2io_link_fault_indication(struct s2io_nic *nic)
1882 {
1883 if (nic->device_type == XFRAME_II_DEVICE)
1884 return LINK_UP_DOWN_INTERRUPT;
1885 else
1886 return MAC_RMAC_ERR_TIMER;
1887 }
1888
1889 /**
1890 * do_s2io_write_bits - update alarm bits in alarm register
1891 * @value: alarm bits
1892 * @flag: interrupt status
1893 * @addr: address value
1894 * Description: update alarm bits in alarm register
1895 * Return Value:
1896 * NONE.
1897 */
1898 static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1899 {
1900 u64 temp64;
1901
1902 temp64 = readq(addr);
1903
1904 if(flag == ENABLE_INTRS)
1905 temp64 &= ~((u64) value);
1906 else
1907 temp64 |= ((u64) value);
1908 writeq(temp64, addr);
1909 }
1910
1911 static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
1912 {
1913 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1914 register u64 gen_int_mask = 0;
1915 u64 interruptible;
1916
1917 writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask);
1918 if (mask & TX_DMA_INTR) {
1919
1920 gen_int_mask |= TXDMA_INT_M;
1921
1922 do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
1923 TXDMA_PCC_INT | TXDMA_TTI_INT |
1924 TXDMA_LSO_INT | TXDMA_TPA_INT |
1925 TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
1926
1927 do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
1928 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1929 PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1930 &bar0->pfc_err_mask);
1931
1932 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
1933 TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1934 TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
1935
1936 do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
1937 PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1938 PCC_N_SERR | PCC_6_COF_OV_ERR |
1939 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1940 PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1941 PCC_TXB_ECC_SG_ERR, flag, &bar0->pcc_err_mask);
1942
1943 do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
1944 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
1945
1946 do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
1947 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1948 LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1949 flag, &bar0->lso_err_mask);
1950
1951 do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
1952 flag, &bar0->tpa_err_mask);
1953
1954 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
1955
1956 }
1957
1958 if (mask & TX_MAC_INTR) {
1959 gen_int_mask |= TXMAC_INT_M;
1960 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
1961 &bar0->mac_int_mask);
1962 do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
1963 TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1964 TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1965 flag, &bar0->mac_tmac_err_mask);
1966 }
1967
1968 if (mask & TX_XGXS_INTR) {
1969 gen_int_mask |= TXXGXS_INT_M;
1970 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
1971 &bar0->xgxs_int_mask);
1972 do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
1973 TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1974 flag, &bar0->xgxs_txgxs_err_mask);
1975 }
1976
1977 if (mask & RX_DMA_INTR) {
1978 gen_int_mask |= RXDMA_INT_M;
1979 do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
1980 RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
1981 flag, &bar0->rxdma_int_mask);
1982 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
1983 RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
1984 RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
1985 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
1986 do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
1987 PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
1988 PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
1989 &bar0->prc_pcix_err_mask);
1990 do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
1991 RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
1992 &bar0->rpa_err_mask);
1993 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
1994 RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
1995 RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
1996 RDA_FRM_ECC_SG_ERR | RDA_MISC_ERR|RDA_PCIX_ERR,
1997 flag, &bar0->rda_err_mask);
1998 do_s2io_write_bits(RTI_SM_ERR_ALARM |
1999 RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
2000 flag, &bar0->rti_err_mask);
2001 }
2002
2003 if (mask & RX_MAC_INTR) {
2004 gen_int_mask |= RXMAC_INT_M;
2005 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
2006 &bar0->mac_int_mask);
2007 interruptible = RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
2008 RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
2009 RMAC_DOUBLE_ECC_ERR;
2010 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER)
2011 interruptible |= RMAC_LINK_STATE_CHANGE_INT;
2012 do_s2io_write_bits(interruptible,
2013 flag, &bar0->mac_rmac_err_mask);
2014 }
2015
2016 if (mask & RX_XGXS_INTR)
2017 {
2018 gen_int_mask |= RXXGXS_INT_M;
2019 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
2020 &bar0->xgxs_int_mask);
2021 do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
2022 &bar0->xgxs_rxgxs_err_mask);
2023 }
2024
2025 if (mask & MC_INTR) {
2026 gen_int_mask |= MC_INT_M;
2027 do_s2io_write_bits(MC_INT_MASK_MC_INT, flag, &bar0->mc_int_mask);
2028 do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
2029 MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
2030 &bar0->mc_err_mask);
2031 }
2032 nic->general_int_mask = gen_int_mask;
2033
2034 /* Remove this line when alarm interrupts are enabled */
2035 nic->general_int_mask = 0;
2036 }
2037 /**
2038 * en_dis_able_nic_intrs - Enable or Disable the interrupts
2039 * @nic: device private variable,
2040 * @mask: A mask indicating which Intr block must be modified and,
2041 * @flag: A flag indicating whether to enable or disable the Intrs.
2042 * Description: This function will either disable or enable the interrupts
2043 * depending on the flag argument. The mask argument can be used to
2044 * enable/disable any Intr block.
2045 * Return Value: NONE.
2046 */
2047
2048 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
2049 {
2050 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2051 register u64 temp64 = 0, intr_mask = 0;
2052
2053 intr_mask = nic->general_int_mask;
2054
2055 /* Top level interrupt classification */
2056 /* PIC Interrupts */
2057 if (mask & TX_PIC_INTR) {
2058 /* Enable PIC Intrs in the general intr mask register */
2059 intr_mask |= TXPIC_INT_M;
2060 if (flag == ENABLE_INTRS) {
2061 /*
2062 * If Hercules adapter enable GPIO otherwise
2063 * disable all PCIX, Flash, MDIO, IIC and GPIO
2064 * interrupts for now.
2065 * TODO
2066 */
2067 if (s2io_link_fault_indication(nic) ==
2068 LINK_UP_DOWN_INTERRUPT ) {
2069 do_s2io_write_bits(PIC_INT_GPIO, flag,
2070 &bar0->pic_int_mask);
2071 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
2072 &bar0->gpio_int_mask);
2073 } else
2074 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2075 } else if (flag == DISABLE_INTRS) {
2076 /*
2077 * Disable PIC Intrs in the general
2078 * intr mask register
2079 */
2080 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2081 }
2082 }
2083
2084 /* Tx traffic interrupts */
2085 if (mask & TX_TRAFFIC_INTR) {
2086 intr_mask |= TXTRAFFIC_INT_M;
2087 if (flag == ENABLE_INTRS) {
2088 /*
2089 * Enable all the Tx side interrupts
2090 * writing 0 Enables all 64 TX interrupt levels
2091 */
2092 writeq(0x0, &bar0->tx_traffic_mask);
2093 } else if (flag == DISABLE_INTRS) {
2094 /*
2095 * Disable Tx Traffic Intrs in the general intr mask
2096 * register.
2097 */
2098 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
2099 }
2100 }
2101
2102 /* Rx traffic interrupts */
2103 if (mask & RX_TRAFFIC_INTR) {
2104 intr_mask |= RXTRAFFIC_INT_M;
2105 if (flag == ENABLE_INTRS) {
2106 /* writing 0 Enables all 8 RX interrupt levels */
2107 writeq(0x0, &bar0->rx_traffic_mask);
2108 } else if (flag == DISABLE_INTRS) {
2109 /*
2110 * Disable Rx Traffic Intrs in the general intr mask
2111 * register.
2112 */
2113 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
2114 }
2115 }
2116
2117 temp64 = readq(&bar0->general_int_mask);
2118 if (flag == ENABLE_INTRS)
2119 temp64 &= ~((u64) intr_mask);
2120 else
2121 temp64 = DISABLE_ALL_INTRS;
2122 writeq(temp64, &bar0->general_int_mask);
2123
2124 nic->general_int_mask = readq(&bar0->general_int_mask);
2125 }
2126
2127 /**
2128 * verify_pcc_quiescent- Checks for PCC quiescent state
2129 * Return: 1 If PCC is quiescence
2130 * 0 If PCC is not quiescence
2131 */
2132 static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
2133 {
2134 int ret = 0, herc;
2135 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2136 u64 val64 = readq(&bar0->adapter_status);
2137
2138 herc = (sp->device_type == XFRAME_II_DEVICE);
2139
2140 if (flag == false) {
2141 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2142 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
2143 ret = 1;
2144 } else {
2145 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2146 ret = 1;
2147 }
2148 } else {
2149 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2150 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
2151 ADAPTER_STATUS_RMAC_PCC_IDLE))
2152 ret = 1;
2153 } else {
2154 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
2155 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2156 ret = 1;
2157 }
2158 }
2159
2160 return ret;
2161 }
2162 /**
2163 * verify_xena_quiescence - Checks whether the H/W is ready
2164 * Description: Returns whether the H/W is ready to go or not. Depending
2165 * on whether adapter enable bit was written or not the comparison
2166 * differs and the calling function passes the input argument flag to
2167 * indicate this.
2168 * Return: 1 If xena is quiescence
2169 * 0 If Xena is not quiescence
2170 */
2171
2172 static int verify_xena_quiescence(struct s2io_nic *sp)
2173 {
2174 int mode;
2175 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2176 u64 val64 = readq(&bar0->adapter_status);
2177 mode = s2io_verify_pci_mode(sp);
2178
2179 if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
2180 DBG_PRINT(ERR_DBG, "%s", "TDMA is not ready!");
2181 return 0;
2182 }
2183 if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
2184 DBG_PRINT(ERR_DBG, "%s", "RDMA is not ready!");
2185 return 0;
2186 }
2187 if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
2188 DBG_PRINT(ERR_DBG, "%s", "PFC is not ready!");
2189 return 0;
2190 }
2191 if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
2192 DBG_PRINT(ERR_DBG, "%s", "TMAC BUF is not empty!");
2193 return 0;
2194 }
2195 if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
2196 DBG_PRINT(ERR_DBG, "%s", "PIC is not QUIESCENT!");
2197 return 0;
2198 }
2199 if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
2200 DBG_PRINT(ERR_DBG, "%s", "MC_DRAM is not ready!");
2201 return 0;
2202 }
2203 if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
2204 DBG_PRINT(ERR_DBG, "%s", "MC_QUEUES is not ready!");
2205 return 0;
2206 }
2207 if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
2208 DBG_PRINT(ERR_DBG, "%s", "M_PLL is not locked!");
2209 return 0;
2210 }
2211
2212 /*
2213 * In PCI 33 mode, the P_PLL is not used, and therefore,
2214 * the the P_PLL_LOCK bit in the adapter_status register will
2215 * not be asserted.
2216 */
2217 if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
2218 sp->device_type == XFRAME_II_DEVICE && mode !=
2219 PCI_MODE_PCI_33) {
2220 DBG_PRINT(ERR_DBG, "%s", "P_PLL is not locked!");
2221 return 0;
2222 }
2223 if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
2224 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
2225 DBG_PRINT(ERR_DBG, "%s", "RC_PRC is not QUIESCENT!");
2226 return 0;
2227 }
2228 return 1;
2229 }
2230
2231 /**
2232 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
2233 * @sp: Pointer to device specifc structure
2234 * Description :
2235 * New procedure to clear mac address reading problems on Alpha platforms
2236 *
2237 */
2238
2239 static void fix_mac_address(struct s2io_nic * sp)
2240 {
2241 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2242 u64 val64;
2243 int i = 0;
2244
2245 while (fix_mac[i] != END_SIGN) {
2246 writeq(fix_mac[i++], &bar0->gpio_control);
2247 udelay(10);
2248 val64 = readq(&bar0->gpio_control);
2249 }
2250 }
2251
2252 /**
2253 * start_nic - Turns the device on
2254 * @nic : device private variable.
2255 * Description:
2256 * This function actually turns the device on. Before this function is
2257 * called,all Registers are configured from their reset states
2258 * and shared memory is allocated but the NIC is still quiescent. On
2259 * calling this function, the device interrupts are cleared and the NIC is
2260 * literally switched on by writing into the adapter control register.
2261 * Return Value:
2262 * SUCCESS on success and -1 on failure.
2263 */
2264
2265 static int start_nic(struct s2io_nic *nic)
2266 {
2267 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2268 struct net_device *dev = nic->dev;
2269 register u64 val64 = 0;
2270 u16 subid, i;
2271 struct mac_info *mac_control;
2272 struct config_param *config;
2273
2274 mac_control = &nic->mac_control;
2275 config = &nic->config;
2276
2277 /* PRC Initialization and configuration */
2278 for (i = 0; i < config->rx_ring_num; i++) {
2279 writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
2280 &bar0->prc_rxd0_n[i]);
2281
2282 val64 = readq(&bar0->prc_ctrl_n[i]);
2283 if (nic->rxd_mode == RXD_MODE_1)
2284 val64 |= PRC_CTRL_RC_ENABLED;
2285 else
2286 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
2287 if (nic->device_type == XFRAME_II_DEVICE)
2288 val64 |= PRC_CTRL_GROUP_READS;
2289 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2290 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2291 writeq(val64, &bar0->prc_ctrl_n[i]);
2292 }
2293
2294 if (nic->rxd_mode == RXD_MODE_3B) {
2295 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2296 val64 = readq(&bar0->rx_pa_cfg);
2297 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2298 writeq(val64, &bar0->rx_pa_cfg);
2299 }
2300
2301 if (vlan_tag_strip == 0) {
2302 val64 = readq(&bar0->rx_pa_cfg);
2303 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2304 writeq(val64, &bar0->rx_pa_cfg);
2305 nic->vlan_strip_flag = 0;
2306 }
2307
2308 /*
2309 * Enabling MC-RLDRAM. After enabling the device, we timeout
2310 * for around 100ms, which is approximately the time required
2311 * for the device to be ready for operation.
2312 */
2313 val64 = readq(&bar0->mc_rldram_mrs);
2314 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2315 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2316 val64 = readq(&bar0->mc_rldram_mrs);
2317
2318 msleep(100); /* Delay by around 100 ms. */
2319
2320 /* Enabling ECC Protection. */
2321 val64 = readq(&bar0->adapter_control);
2322 val64 &= ~ADAPTER_ECC_EN;
2323 writeq(val64, &bar0->adapter_control);
2324
2325 /*
2326 * Verify if the device is ready to be enabled, if so enable
2327 * it.
2328 */
2329 val64 = readq(&bar0->adapter_status);
2330 if (!verify_xena_quiescence(nic)) {
2331 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
2332 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
2333 (unsigned long long) val64);
2334 return FAILURE;
2335 }
2336
2337 /*
2338 * With some switches, link might be already up at this point.
2339 * Because of this weird behavior, when we enable laser,
2340 * we may not get link. We need to handle this. We cannot
2341 * figure out which switch is misbehaving. So we are forced to
2342 * make a global change.
2343 */
2344
2345 /* Enabling Laser. */
2346 val64 = readq(&bar0->adapter_control);
2347 val64 |= ADAPTER_EOI_TX_ON;
2348 writeq(val64, &bar0->adapter_control);
2349
2350 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2351 /*
2352 * Dont see link state interrupts initally on some switches,
2353 * so directly scheduling the link state task here.
2354 */
2355 schedule_work(&nic->set_link_task);
2356 }
2357 /* SXE-002: Initialize link and activity LED */
2358 subid = nic->pdev->subsystem_device;
2359 if (((subid & 0xFF) >= 0x07) &&
2360 (nic->device_type == XFRAME_I_DEVICE)) {
2361 val64 = readq(&bar0->gpio_control);
2362 val64 |= 0x0000800000000000ULL;
2363 writeq(val64, &bar0->gpio_control);
2364 val64 = 0x0411040400000000ULL;
2365 writeq(val64, (void __iomem *)bar0 + 0x2700);
2366 }
2367
2368 return SUCCESS;
2369 }
2370 /**
2371 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2372 */
2373 static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data, struct \
2374 TxD *txdlp, int get_off)
2375 {
2376 struct s2io_nic *nic = fifo_data->nic;
2377 struct sk_buff *skb;
2378 struct TxD *txds;
2379 u16 j, frg_cnt;
2380
2381 txds = txdlp;
2382 if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) {
2383 pci_unmap_single(nic->pdev, (dma_addr_t)
2384 txds->Buffer_Pointer, sizeof(u64),
2385 PCI_DMA_TODEVICE);
2386 txds++;
2387 }
2388
2389 skb = (struct sk_buff *) ((unsigned long)
2390 txds->Host_Control);
2391 if (!skb) {
2392 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2393 return NULL;
2394 }
2395 pci_unmap_single(nic->pdev, (dma_addr_t)
2396 txds->Buffer_Pointer,
2397 skb->len - skb->data_len,
2398 PCI_DMA_TODEVICE);
2399 frg_cnt = skb_shinfo(skb)->nr_frags;
2400 if (frg_cnt) {
2401 txds++;
2402 for (j = 0; j < frg_cnt; j++, txds++) {
2403 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2404 if (!txds->Buffer_Pointer)
2405 break;
2406 pci_unmap_page(nic->pdev, (dma_addr_t)
2407 txds->Buffer_Pointer,
2408 frag->size, PCI_DMA_TODEVICE);
2409 }
2410 }
2411 memset(txdlp,0, (sizeof(struct TxD) * fifo_data->max_txds));
2412 return(skb);
2413 }
2414
2415 /**
2416 * free_tx_buffers - Free all queued Tx buffers
2417 * @nic : device private variable.
2418 * Description:
2419 * Free all queued Tx buffers.
2420 * Return Value: void
2421 */
2422
2423 static void free_tx_buffers(struct s2io_nic *nic)
2424 {
2425 struct net_device *dev = nic->dev;
2426 struct sk_buff *skb;
2427 struct TxD *txdp;
2428 int i, j;
2429 struct mac_info *mac_control;
2430 struct config_param *config;
2431 int cnt = 0;
2432
2433 mac_control = &nic->mac_control;
2434 config = &nic->config;
2435
2436 for (i = 0; i < config->tx_fifo_num; i++) {
2437 unsigned long flags;
2438 spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags);
2439 for (j = 0; j < config->tx_cfg[i].fifo_len; j++) {
2440 txdp = (struct TxD *) \
2441 mac_control->fifos[i].list_info[j].list_virt_addr;
2442 skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2443 if (skb) {
2444 nic->mac_control.stats_info->sw_stat.mem_freed
2445 += skb->truesize;
2446 dev_kfree_skb(skb);
2447 cnt++;
2448 }
2449 }
2450 DBG_PRINT(INTR_DBG,
2451 "%s:forcibly freeing %d skbs on FIFO%d\n",
2452 dev->name, cnt, i);
2453 mac_control->fifos[i].tx_curr_get_info.offset = 0;
2454 mac_control->fifos[i].tx_curr_put_info.offset = 0;
2455 spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock, flags);
2456 }
2457 }
2458
2459 /**
2460 * stop_nic - To stop the nic
2461 * @nic ; device private variable.
2462 * Description:
2463 * This function does exactly the opposite of what the start_nic()
2464 * function does. This function is called to stop the device.
2465 * Return Value:
2466 * void.
2467 */
2468
2469 static void stop_nic(struct s2io_nic *nic)
2470 {
2471 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2472 register u64 val64 = 0;
2473 u16 interruptible;
2474 struct mac_info *mac_control;
2475 struct config_param *config;
2476
2477 mac_control = &nic->mac_control;
2478 config = &nic->config;
2479
2480 /* Disable all interrupts */
2481 en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
2482 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2483 interruptible |= TX_PIC_INTR;
2484 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2485
2486 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2487 val64 = readq(&bar0->adapter_control);
2488 val64 &= ~(ADAPTER_CNTL_EN);
2489 writeq(val64, &bar0->adapter_control);
2490 }
2491
2492 /**
2493 * fill_rx_buffers - Allocates the Rx side skbs
2494 * @ring_info: per ring structure
2495 * @from_card_up: If this is true, we will map the buffer to get
2496 * the dma address for buf0 and buf1 to give it to the card.
2497 * Else we will sync the already mapped buffer to give it to the card.
2498 * Description:
2499 * The function allocates Rx side skbs and puts the physical
2500 * address of these buffers into the RxD buffer pointers, so that the NIC
2501 * can DMA the received frame into these locations.
2502 * The NIC supports 3 receive modes, viz
2503 * 1. single buffer,
2504 * 2. three buffer and
2505 * 3. Five buffer modes.
2506 * Each mode defines how many fragments the received frame will be split
2507 * up into by the NIC. The frame is split into L3 header, L4 Header,
2508 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2509 * is split into 3 fragments. As of now only single buffer mode is
2510 * supported.
2511 * Return Value:
2512 * SUCCESS on success or an appropriate -ve value on failure.
2513 */
2514 static int fill_rx_buffers(struct s2io_nic *nic, struct ring_info *ring,
2515 int from_card_up)
2516 {
2517 struct sk_buff *skb;
2518 struct RxD_t *rxdp;
2519 int off, size, block_no, block_no1;
2520 u32 alloc_tab = 0;
2521 u32 alloc_cnt;
2522 u64 tmp;
2523 struct buffAdd *ba;
2524 struct RxD_t *first_rxdp = NULL;
2525 u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
2526 int rxd_index = 0;
2527 struct RxD1 *rxdp1;
2528 struct RxD3 *rxdp3;
2529 struct swStat *stats = &ring->nic->mac_control.stats_info->sw_stat;
2530
2531 alloc_cnt = ring->pkt_cnt - ring->rx_bufs_left;
2532
2533 block_no1 = ring->rx_curr_get_info.block_index;
2534 while (alloc_tab < alloc_cnt) {
2535 block_no = ring->rx_curr_put_info.block_index;
2536
2537 off = ring->rx_curr_put_info.offset;
2538
2539 rxdp = ring->rx_blocks[block_no].rxds[off].virt_addr;
2540
2541 rxd_index = off + 1;
2542 if (block_no)
2543 rxd_index += (block_no * ring->rxd_count);
2544
2545 if ((block_no == block_no1) &&
2546 (off == ring->rx_curr_get_info.offset) &&
2547 (rxdp->Host_Control)) {
2548 DBG_PRINT(INTR_DBG, "%s: Get and Put",
2549 ring->dev->name);
2550 DBG_PRINT(INTR_DBG, " info equated\n");
2551 goto end;
2552 }
2553 if (off && (off == ring->rxd_count)) {
2554 ring->rx_curr_put_info.block_index++;
2555 if (ring->rx_curr_put_info.block_index ==
2556 ring->block_count)
2557 ring->rx_curr_put_info.block_index = 0;
2558 block_no = ring->rx_curr_put_info.block_index;
2559 off = 0;
2560 ring->rx_curr_put_info.offset = off;
2561 rxdp = ring->rx_blocks[block_no].block_virt_addr;
2562 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2563 ring->dev->name, rxdp);
2564
2565 }
2566
2567 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2568 ((ring->rxd_mode == RXD_MODE_3B) &&
2569 (rxdp->Control_2 & s2BIT(0)))) {
2570 ring->rx_curr_put_info.offset = off;
2571 goto end;
2572 }
2573 /* calculate size of skb based on ring mode */
2574 size = ring->mtu + HEADER_ETHERNET_II_802_3_SIZE +
2575 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2576 if (ring->rxd_mode == RXD_MODE_1)
2577 size += NET_IP_ALIGN;
2578 else
2579 size = ring->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2580
2581 /* allocate skb */
2582 skb = dev_alloc_skb(size);
2583 if(!skb) {
2584 DBG_PRINT(INFO_DBG, "%s: Out of ", ring->dev->name);
2585 DBG_PRINT(INFO_DBG, "memory to allocate SKBs\n");
2586 if (first_rxdp) {
2587 wmb();
2588 first_rxdp->Control_1 |= RXD_OWN_XENA;
2589 }
2590 stats->mem_alloc_fail_cnt++;
2591
2592 return -ENOMEM ;
2593 }
2594 stats->mem_allocated += skb->truesize;
2595
2596 if (ring->rxd_mode == RXD_MODE_1) {
2597 /* 1 buffer mode - normal operation mode */
2598 rxdp1 = (struct RxD1*)rxdp;
2599 memset(rxdp, 0, sizeof(struct RxD1));
2600 skb_reserve(skb, NET_IP_ALIGN);
2601 rxdp1->Buffer0_ptr = pci_map_single
2602 (ring->pdev, skb->data, size - NET_IP_ALIGN,
2603 PCI_DMA_FROMDEVICE);
2604 if (pci_dma_mapping_error(nic->pdev,
2605 rxdp1->Buffer0_ptr))
2606 goto pci_map_failed;
2607
2608 rxdp->Control_2 =
2609 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
2610 rxdp->Host_Control = (unsigned long) (skb);
2611 } else if (ring->rxd_mode == RXD_MODE_3B) {
2612 /*
2613 * 2 buffer mode -
2614 * 2 buffer mode provides 128
2615 * byte aligned receive buffers.
2616 */
2617
2618 rxdp3 = (struct RxD3*)rxdp;
2619 /* save buffer pointers to avoid frequent dma mapping */
2620 Buffer0_ptr = rxdp3->Buffer0_ptr;
2621 Buffer1_ptr = rxdp3->Buffer1_ptr;
2622 memset(rxdp, 0, sizeof(struct RxD3));
2623 /* restore the buffer pointers for dma sync*/
2624 rxdp3->Buffer0_ptr = Buffer0_ptr;
2625 rxdp3->Buffer1_ptr = Buffer1_ptr;
2626
2627 ba = &ring->ba[block_no][off];
2628 skb_reserve(skb, BUF0_LEN);
2629 tmp = (u64)(unsigned long) skb->data;
2630 tmp += ALIGN_SIZE;
2631 tmp &= ~ALIGN_SIZE;
2632 skb->data = (void *) (unsigned long)tmp;
2633 skb_reset_tail_pointer(skb);
2634
2635 if (from_card_up) {
2636 rxdp3->Buffer0_ptr =
2637 pci_map_single(ring->pdev, ba->ba_0,
2638 BUF0_LEN, PCI_DMA_FROMDEVICE);
2639 if (pci_dma_mapping_error(nic->pdev,
2640 rxdp3->Buffer0_ptr))
2641 goto pci_map_failed;
2642 } else
2643 pci_dma_sync_single_for_device(ring->pdev,
2644 (dma_addr_t) rxdp3->Buffer0_ptr,
2645 BUF0_LEN, PCI_DMA_FROMDEVICE);
2646
2647 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2648 if (ring->rxd_mode == RXD_MODE_3B) {
2649 /* Two buffer mode */
2650
2651 /*
2652 * Buffer2 will have L3/L4 header plus
2653 * L4 payload
2654 */
2655 rxdp3->Buffer2_ptr = pci_map_single
2656 (ring->pdev, skb->data, ring->mtu + 4,
2657 PCI_DMA_FROMDEVICE);
2658
2659 if (pci_dma_mapping_error(nic->pdev,
2660 rxdp3->Buffer2_ptr))
2661 goto pci_map_failed;
2662
2663 if (from_card_up) {
2664 rxdp3->Buffer1_ptr =
2665 pci_map_single(ring->pdev,
2666 ba->ba_1, BUF1_LEN,
2667 PCI_DMA_FROMDEVICE);
2668
2669 if (pci_dma_mapping_error(nic->pdev,
2670 rxdp3->Buffer1_ptr)) {
2671 pci_unmap_single
2672 (ring->pdev,
2673 (dma_addr_t)(unsigned long)
2674 skb->data,
2675 ring->mtu + 4,
2676 PCI_DMA_FROMDEVICE);
2677 goto pci_map_failed;
2678 }
2679 }
2680 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2681 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2682 (ring->mtu + 4);
2683 }
2684 rxdp->Control_2 |= s2BIT(0);
2685 rxdp->Host_Control = (unsigned long) (skb);
2686 }
2687 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2688 rxdp->Control_1 |= RXD_OWN_XENA;
2689 off++;
2690 if (off == (ring->rxd_count + 1))
2691 off = 0;
2692 ring->rx_curr_put_info.offset = off;
2693
2694 rxdp->Control_2 |= SET_RXD_MARKER;
2695 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2696 if (first_rxdp) {
2697 wmb();
2698 first_rxdp->Control_1 |= RXD_OWN_XENA;
2699 }
2700 first_rxdp = rxdp;
2701 }
2702 ring->rx_bufs_left += 1;
2703 alloc_tab++;
2704 }
2705
2706 end:
2707 /* Transfer ownership of first descriptor to adapter just before
2708 * exiting. Before that, use memory barrier so that ownership
2709 * and other fields are seen by adapter correctly.
2710 */
2711 if (first_rxdp) {
2712 wmb();
2713 first_rxdp->Control_1 |= RXD_OWN_XENA;
2714 }
2715
2716 return SUCCESS;
2717 pci_map_failed:
2718 stats->pci_map_fail_cnt++;
2719 stats->mem_freed += skb->truesize;
2720 dev_kfree_skb_irq(skb);
2721 return -ENOMEM;
2722 }
2723
2724 static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2725 {
2726 struct net_device *dev = sp->dev;
2727 int j;
2728 struct sk_buff *skb;
2729 struct RxD_t *rxdp;
2730 struct mac_info *mac_control;
2731 struct buffAdd *ba;
2732 struct RxD1 *rxdp1;
2733 struct RxD3 *rxdp3;
2734
2735 mac_control = &sp->mac_control;
2736 for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2737 rxdp = mac_control->rings[ring_no].
2738 rx_blocks[blk].rxds[j].virt_addr;
2739 skb = (struct sk_buff *)
2740 ((unsigned long) rxdp->Host_Control);
2741 if (!skb) {
2742 continue;
2743 }
2744 if (sp->rxd_mode == RXD_MODE_1) {
2745 rxdp1 = (struct RxD1*)rxdp;
2746 pci_unmap_single(sp->pdev, (dma_addr_t)
2747 rxdp1->Buffer0_ptr,
2748 dev->mtu +
2749 HEADER_ETHERNET_II_802_3_SIZE
2750 + HEADER_802_2_SIZE +
2751 HEADER_SNAP_SIZE,
2752 PCI_DMA_FROMDEVICE);
2753 memset(rxdp, 0, sizeof(struct RxD1));
2754 } else if(sp->rxd_mode == RXD_MODE_3B) {
2755 rxdp3 = (struct RxD3*)rxdp;
2756 ba = &mac_control->rings[ring_no].
2757 ba[blk][j];
2758 pci_unmap_single(sp->pdev, (dma_addr_t)
2759 rxdp3->Buffer0_ptr,
2760 BUF0_LEN,
2761 PCI_DMA_FROMDEVICE);
2762 pci_unmap_single(sp->pdev, (dma_addr_t)
2763 rxdp3->Buffer1_ptr,
2764 BUF1_LEN,
2765 PCI_DMA_FROMDEVICE);
2766 pci_unmap_single(sp->pdev, (dma_addr_t)
2767 rxdp3->Buffer2_ptr,
2768 dev->mtu + 4,
2769 PCI_DMA_FROMDEVICE);
2770 memset(rxdp, 0, sizeof(struct RxD3));
2771 }
2772 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
2773 dev_kfree_skb(skb);
2774 mac_control->rings[ring_no].rx_bufs_left -= 1;
2775 }
2776 }
2777
2778 /**
2779 * free_rx_buffers - Frees all Rx buffers
2780 * @sp: device private variable.
2781 * Description:
2782 * This function will free all Rx buffers allocated by host.
2783 * Return Value:
2784 * NONE.
2785 */
2786
2787 static void free_rx_buffers(struct s2io_nic *sp)
2788 {
2789 struct net_device *dev = sp->dev;
2790 int i, blk = 0, buf_cnt = 0;
2791 struct mac_info *mac_control;
2792 struct config_param *config;
2793
2794 mac_control = &sp->mac_control;
2795 config = &sp->config;
2796
2797 for (i = 0; i < config->rx_ring_num; i++) {
2798 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2799 free_rxd_blk(sp,i,blk);
2800
2801 mac_control->rings[i].rx_curr_put_info.block_index = 0;
2802 mac_control->rings[i].rx_curr_get_info.block_index = 0;
2803 mac_control->rings[i].rx_curr_put_info.offset = 0;
2804 mac_control->rings[i].rx_curr_get_info.offset = 0;
2805 mac_control->rings[i].rx_bufs_left = 0;
2806 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2807 dev->name, buf_cnt, i);
2808 }
2809 }
2810
2811 static int s2io_chk_rx_buffers(struct s2io_nic *nic, struct ring_info *ring)
2812 {
2813 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
2814 DBG_PRINT(INFO_DBG, "%s:Out of memory", ring->dev->name);
2815 DBG_PRINT(INFO_DBG, " in Rx Intr!!\n");
2816 }
2817 return 0;
2818 }
2819
2820 /**
2821 * s2io_poll - Rx interrupt handler for NAPI support
2822 * @napi : pointer to the napi structure.
2823 * @budget : The number of packets that were budgeted to be processed
2824 * during one pass through the 'Poll" function.
2825 * Description:
2826 * Comes into picture only if NAPI support has been incorporated. It does
2827 * the same thing that rx_intr_handler does, but not in a interrupt context
2828 * also It will process only a given number of packets.
2829 * Return value:
2830 * 0 on success and 1 if there are No Rx packets to be processed.
2831 */
2832
2833 static int s2io_poll_msix(struct napi_struct *napi, int budget)
2834 {
2835 struct ring_info *ring = container_of(napi, struct ring_info, napi);
2836 struct net_device *dev = ring->dev;
2837 struct config_param *config;
2838 struct mac_info *mac_control;
2839 int pkts_processed = 0;
2840 u8 __iomem *addr = NULL;
2841 u8 val8 = 0;
2842 struct s2io_nic *nic = netdev_priv(dev);
2843 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2844 int budget_org = budget;
2845
2846 config = &nic->config;
2847 mac_control = &nic->mac_control;
2848
2849 if (unlikely(!is_s2io_card_up(nic)))
2850 return 0;
2851
2852 pkts_processed = rx_intr_handler(ring, budget);
2853 s2io_chk_rx_buffers(nic, ring);
2854
2855 if (pkts_processed < budget_org) {
2856 napi_complete(napi);
2857 /*Re Enable MSI-Rx Vector*/
2858 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
2859 addr += 7 - ring->ring_no;
2860 val8 = (ring->ring_no == 0) ? 0x3f : 0xbf;
2861 writeb(val8, addr);
2862 val8 = readb(addr);
2863 }
2864 return pkts_processed;
2865 }
2866 static int s2io_poll_inta(struct napi_struct *napi, int budget)
2867 {
2868 struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
2869 struct ring_info *ring;
2870 struct config_param *config;
2871 struct mac_info *mac_control;
2872 int pkts_processed = 0;
2873 int ring_pkts_processed, i;
2874 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2875 int budget_org = budget;
2876
2877 config = &nic->config;
2878 mac_control = &nic->mac_control;
2879
2880 if (unlikely(!is_s2io_card_up(nic)))
2881 return 0;
2882
2883 for (i = 0; i < config->rx_ring_num; i++) {
2884 ring = &mac_control->rings[i];
2885 ring_pkts_processed = rx_intr_handler(ring, budget);
2886 s2io_chk_rx_buffers(nic, ring);
2887 pkts_processed += ring_pkts_processed;
2888 budget -= ring_pkts_processed;
2889 if (budget <= 0)
2890 break;
2891 }
2892 if (pkts_processed < budget_org) {
2893 napi_complete(napi);
2894 /* Re enable the Rx interrupts for the ring */
2895 writeq(0, &bar0->rx_traffic_mask);
2896 readl(&bar0->rx_traffic_mask);
2897 }
2898 return pkts_processed;
2899 }
2900
2901 #ifdef CONFIG_NET_POLL_CONTROLLER
2902 /**
2903 * s2io_netpoll - netpoll event handler entry point
2904 * @dev : pointer to the device structure.
2905 * Description:
2906 * This function will be called by upper layer to check for events on the
2907 * interface in situations where interrupts are disabled. It is used for
2908 * specific in-kernel networking tasks, such as remote consoles and kernel
2909 * debugging over the network (example netdump in RedHat).
2910 */
2911 static void s2io_netpoll(struct net_device *dev)
2912 {
2913 struct s2io_nic *nic = netdev_priv(dev);
2914 struct mac_info *mac_control;
2915 struct config_param *config;
2916 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2917 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2918 int i;
2919
2920 if (pci_channel_offline(nic->pdev))
2921 return;
2922
2923 disable_irq(dev->irq);
2924
2925 mac_control = &nic->mac_control;
2926 config = &nic->config;
2927
2928 writeq(val64, &bar0->rx_traffic_int);
2929 writeq(val64, &bar0->tx_traffic_int);
2930
2931 /* we need to free up the transmitted skbufs or else netpoll will
2932 * run out of skbs and will fail and eventually netpoll application such
2933 * as netdump will fail.
2934 */
2935 for (i = 0; i < config->tx_fifo_num; i++)
2936 tx_intr_handler(&mac_control->fifos[i]);
2937
2938 /* check for received packet and indicate up to network */
2939 for (i = 0; i < config->rx_ring_num; i++)
2940 rx_intr_handler(&mac_control->rings[i], 0);
2941
2942 for (i = 0; i < config->rx_ring_num; i++) {
2943 if (fill_rx_buffers(nic, &mac_control->rings[i], 0) ==
2944 -ENOMEM) {
2945 DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2946 DBG_PRINT(INFO_DBG, " in Rx Netpoll!!\n");
2947 break;
2948 }
2949 }
2950 enable_irq(dev->irq);
2951 return;
2952 }
2953 #endif
2954
2955 /**
2956 * rx_intr_handler - Rx interrupt handler
2957 * @ring_info: per ring structure.
2958 * @budget: budget for napi processing.
2959 * Description:
2960 * If the interrupt is because of a received frame or if the
2961 * receive ring contains fresh as yet un-processed frames,this function is
2962 * called. It picks out the RxD at which place the last Rx processing had
2963 * stopped and sends the skb to the OSM's Rx handler and then increments
2964 * the offset.
2965 * Return Value:
2966 * No. of napi packets processed.
2967 */
2968 static int rx_intr_handler(struct ring_info *ring_data, int budget)
2969 {
2970 int get_block, put_block;
2971 struct rx_curr_get_info get_info, put_info;
2972 struct RxD_t *rxdp;
2973 struct sk_buff *skb;
2974 int pkt_cnt = 0, napi_pkts = 0;
2975 int i;
2976 struct RxD1* rxdp1;
2977 struct RxD3* rxdp3;
2978
2979 get_info = ring_data->rx_curr_get_info;
2980 get_block = get_info.block_index;
2981 memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
2982 put_block = put_info.block_index;
2983 rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2984
2985 while (RXD_IS_UP2DT(rxdp)) {
2986 /*
2987 * If your are next to put index then it's
2988 * FIFO full condition
2989 */
2990 if ((get_block == put_block) &&
2991 (get_info.offset + 1) == put_info.offset) {
2992 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",
2993 ring_data->dev->name);
2994 break;
2995 }
2996 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
2997 if (skb == NULL) {
2998 DBG_PRINT(ERR_DBG, "%s: The skb is ",
2999 ring_data->dev->name);
3000 DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
3001 return 0;
3002 }
3003 if (ring_data->rxd_mode == RXD_MODE_1) {
3004 rxdp1 = (struct RxD1*)rxdp;
3005 pci_unmap_single(ring_data->pdev, (dma_addr_t)
3006 rxdp1->Buffer0_ptr,
3007 ring_data->mtu +
3008 HEADER_ETHERNET_II_802_3_SIZE +
3009 HEADER_802_2_SIZE +
3010 HEADER_SNAP_SIZE,
3011 PCI_DMA_FROMDEVICE);
3012 } else if (ring_data->rxd_mode == RXD_MODE_3B) {
3013 rxdp3 = (struct RxD3*)rxdp;
3014 pci_dma_sync_single_for_cpu(ring_data->pdev, (dma_addr_t)
3015 rxdp3->Buffer0_ptr,
3016 BUF0_LEN, PCI_DMA_FROMDEVICE);
3017 pci_unmap_single(ring_data->pdev, (dma_addr_t)
3018 rxdp3->Buffer2_ptr,
3019 ring_data->mtu + 4,
3020 PCI_DMA_FROMDEVICE);
3021 }
3022 prefetch(skb->data);
3023 rx_osm_handler(ring_data, rxdp);
3024 get_info.offset++;
3025 ring_data->rx_curr_get_info.offset = get_info.offset;
3026 rxdp = ring_data->rx_blocks[get_block].
3027 rxds[get_info.offset].virt_addr;
3028 if (get_info.offset == rxd_count[ring_data->rxd_mode]) {
3029 get_info.offset = 0;
3030 ring_data->rx_curr_get_info.offset = get_info.offset;
3031 get_block++;
3032 if (get_block == ring_data->block_count)
3033 get_block = 0;
3034 ring_data->rx_curr_get_info.block_index = get_block;
3035 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
3036 }
3037
3038 if (ring_data->nic->config.napi) {
3039 budget--;
3040 napi_pkts++;
3041 if (!budget)
3042 break;
3043 }
3044 pkt_cnt++;
3045 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
3046 break;
3047 }
3048 if (ring_data->lro) {
3049 /* Clear all LRO sessions before exiting */
3050 for (i=0; i<MAX_LRO_SESSIONS; i++) {
3051 struct lro *lro = &ring_data->lro0_n[i];
3052 if (lro->in_use) {
3053 update_L3L4_header(ring_data->nic, lro);
3054 queue_rx_frame(lro->parent, lro->vlan_tag);
3055 clear_lro_session(lro);
3056 }
3057 }
3058 }
3059 return(napi_pkts);
3060 }
3061
3062 /**
3063 * tx_intr_handler - Transmit interrupt handler
3064 * @nic : device private variable
3065 * Description:
3066 * If an interrupt was raised to indicate DMA complete of the
3067 * Tx packet, this function is called. It identifies the last TxD
3068 * whose buffer was freed and frees all skbs whose data have already
3069 * DMA'ed into the NICs internal memory.
3070 * Return Value:
3071 * NONE
3072 */
3073
3074 static void tx_intr_handler(struct fifo_info *fifo_data)
3075 {
3076 struct s2io_nic *nic = fifo_data->nic;
3077 struct tx_curr_get_info get_info, put_info;
3078 struct sk_buff *skb = NULL;
3079 struct TxD *txdlp;
3080 int pkt_cnt = 0;
3081 unsigned long flags = 0;
3082 u8 err_mask;
3083
3084 if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags))
3085 return;
3086
3087 get_info = fifo_data->tx_curr_get_info;
3088 memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
3089 txdlp = (struct TxD *) fifo_data->list_info[get_info.offset].
3090 list_virt_addr;
3091 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
3092 (get_info.offset != put_info.offset) &&
3093 (txdlp->Host_Control)) {
3094 /* Check for TxD errors */
3095 if (txdlp->Control_1 & TXD_T_CODE) {
3096 unsigned long long err;
3097 err = txdlp->Control_1 & TXD_T_CODE;
3098 if (err & 0x1) {
3099 nic->mac_control.stats_info->sw_stat.
3100 parity_err_cnt++;
3101 }
3102
3103 /* update t_code statistics */
3104 err_mask = err >> 48;
3105 switch(err_mask) {
3106 case 2:
3107 nic->mac_control.stats_info->sw_stat.
3108 tx_buf_abort_cnt++;
3109 break;
3110
3111 case 3:
3112 nic->mac_control.stats_info->sw_stat.
3113 tx_desc_abort_cnt++;
3114 break;
3115
3116 case 7:
3117 nic->mac_control.stats_info->sw_stat.
3118 tx_parity_err_cnt++;
3119 break;
3120
3121 case 10:
3122 nic->mac_control.stats_info->sw_stat.
3123 tx_link_loss_cnt++;
3124 break;
3125
3126 case 15:
3127 nic->mac_control.stats_info->sw_stat.
3128 tx_list_proc_err_cnt++;
3129 break;
3130 }
3131 }
3132
3133 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
3134 if (skb == NULL) {
3135 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3136 DBG_PRINT(ERR_DBG, "%s: Null skb ",
3137 __func__);
3138 DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
3139 return;
3140 }
3141 pkt_cnt++;
3142
3143 /* Updating the statistics block */
3144 nic->dev->stats.tx_bytes += skb->len;
3145 nic->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
3146 dev_kfree_skb_irq(skb);
3147
3148 get_info.offset++;
3149 if (get_info.offset == get_info.fifo_len + 1)
3150 get_info.offset = 0;
3151 txdlp = (struct TxD *) fifo_data->list_info
3152 [get_info.offset].list_virt_addr;
3153 fifo_data->tx_curr_get_info.offset =
3154 get_info.offset;
3155 }
3156
3157 s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq);
3158
3159 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3160 }
3161
3162 /**
3163 * s2io_mdio_write - Function to write in to MDIO registers
3164 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3165 * @addr : address value
3166 * @value : data value
3167 * @dev : pointer to net_device structure
3168 * Description:
3169 * This function is used to write values to the MDIO registers
3170 * NONE
3171 */
3172 static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev)
3173 {
3174 u64 val64 = 0x0;
3175 struct s2io_nic *sp = netdev_priv(dev);
3176 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3177
3178 //address transaction
3179 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3180 | MDIO_MMD_DEV_ADDR(mmd_type)
3181 | MDIO_MMS_PRT_ADDR(0x0);
3182 writeq(val64, &bar0->mdio_control);
3183 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3184 writeq(val64, &bar0->mdio_control);
3185 udelay(100);
3186
3187 //Data transaction
3188 val64 = 0x0;
3189 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3190 | MDIO_MMD_DEV_ADDR(mmd_type)
3191 | MDIO_MMS_PRT_ADDR(0x0)
3192 | MDIO_MDIO_DATA(value)
3193 | MDIO_OP(MDIO_OP_WRITE_TRANS);
3194 writeq(val64, &bar0->mdio_control);
3195 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3196 writeq(val64, &bar0->mdio_control);
3197 udelay(100);
3198
3199 val64 = 0x0;
3200 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3201 | MDIO_MMD_DEV_ADDR(mmd_type)
3202 | MDIO_MMS_PRT_ADDR(0x0)
3203 | MDIO_OP(MDIO_OP_READ_TRANS);
3204 writeq(val64, &bar0->mdio_control);
3205 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3206 writeq(val64, &bar0->mdio_control);
3207 udelay(100);
3208
3209 }
3210
3211 /**
3212 * s2io_mdio_read - Function to write in to MDIO registers
3213 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3214 * @addr : address value
3215 * @dev : pointer to net_device structure
3216 * Description:
3217 * This function is used to read values to the MDIO registers
3218 * NONE
3219 */
3220 static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3221 {
3222 u64 val64 = 0x0;
3223 u64 rval64 = 0x0;
3224 struct s2io_nic *sp = netdev_priv(dev);
3225 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3226
3227 /* address transaction */
3228 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3229 | MDIO_MMD_DEV_ADDR(mmd_type)
3230 | MDIO_MMS_PRT_ADDR(0x0);
3231 writeq(val64, &bar0->mdio_control);
3232 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3233 writeq(val64, &bar0->mdio_control);
3234 udelay(100);
3235
3236 /* Data transaction */
3237 val64 = 0x0;
3238 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3239 | MDIO_MMD_DEV_ADDR(mmd_type)
3240 | MDIO_MMS_PRT_ADDR(0x0)
3241 | MDIO_OP(MDIO_OP_READ_TRANS);
3242 writeq(val64, &bar0->mdio_control);
3243 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3244 writeq(val64, &bar0->mdio_control);
3245 udelay(100);
3246
3247 /* Read the value from regs */
3248 rval64 = readq(&bar0->mdio_control);
3249 rval64 = rval64 & 0xFFFF0000;
3250 rval64 = rval64 >> 16;
3251 return rval64;
3252 }
3253 /**
3254 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
3255 * @counter : couter value to be updated
3256 * @flag : flag to indicate the status
3257 * @type : counter type
3258 * Description:
3259 * This function is to check the status of the xpak counters value
3260 * NONE
3261 */
3262
3263 static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index, u16 flag, u16 type)
3264 {
3265 u64 mask = 0x3;
3266 u64 val64;
3267 int i;
3268 for(i = 0; i <index; i++)
3269 mask = mask << 0x2;
3270
3271 if(flag > 0)
3272 {
3273 *counter = *counter + 1;
3274 val64 = *regs_stat & mask;
3275 val64 = val64 >> (index * 0x2);
3276 val64 = val64 + 1;
3277 if(val64 == 3)
3278 {
3279 switch(type)
3280 {
3281 case 1:
3282 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3283 "service. Excessive temperatures may "
3284 "result in premature transceiver "
3285 "failure \n");
3286 break;
3287 case 2:
3288 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3289 "service Excessive bias currents may "
3290 "indicate imminent laser diode "
3291 "failure \n");
3292 break;
3293 case 3:
3294 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3295 "service Excessive laser output "
3296 "power may saturate far-end "
3297 "receiver\n");
3298 break;
3299 default:
3300 DBG_PRINT(ERR_DBG, "Incorrect XPAK Alarm "
3301 "type \n");
3302 }
3303 val64 = 0x0;
3304 }
3305 val64 = val64 << (index * 0x2);
3306 *regs_stat = (*regs_stat & (~mask)) | (val64);
3307
3308 } else {
3309 *regs_stat = *regs_stat & (~mask);
3310 }
3311 }
3312
3313 /**
3314 * s2io_updt_xpak_counter - Function to update the xpak counters
3315 * @dev : pointer to net_device struct
3316 * Description:
3317 * This function is to upate the status of the xpak counters value
3318 * NONE
3319 */
3320 static void s2io_updt_xpak_counter(struct net_device *dev)
3321 {
3322 u16 flag = 0x0;
3323 u16 type = 0x0;
3324 u16 val16 = 0x0;
3325 u64 val64 = 0x0;
3326 u64 addr = 0x0;
3327
3328 struct s2io_nic *sp = netdev_priv(dev);
3329 struct stat_block *stat_info = sp->mac_control.stats_info;
3330
3331 /* Check the communication with the MDIO slave */
3332 addr = MDIO_CTRL1;
3333 val64 = 0x0;
3334 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3335 if((val64 == 0xFFFF) || (val64 == 0x0000))
3336 {
3337 DBG_PRINT(ERR_DBG, "ERR: MDIO slave access failed - "
3338 "Returned %llx\n", (unsigned long long)val64);
3339 return;
3340 }
3341
3342 /* Check for the expected value of control reg 1 */
3343 if(val64 != MDIO_CTRL1_SPEED10G)
3344 {
3345 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - ");
3346 DBG_PRINT(ERR_DBG, "Returned: %llx- Expected: 0x%x\n",
3347 (unsigned long long)val64, MDIO_CTRL1_SPEED10G);
3348 return;
3349 }
3350
3351 /* Loading the DOM register to MDIO register */
3352 addr = 0xA100;
3353 s2io_mdio_write(MDIO_MMD_PMAPMD, addr, val16, dev);
3354 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3355
3356 /* Reading the Alarm flags */
3357 addr = 0xA070;
3358 val64 = 0x0;
3359 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3360
3361 flag = CHECKBIT(val64, 0x7);
3362 type = 1;
3363 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_transceiver_temp_high,
3364 &stat_info->xpak_stat.xpak_regs_stat,
3365 0x0, flag, type);
3366
3367 if(CHECKBIT(val64, 0x6))
3368 stat_info->xpak_stat.alarm_transceiver_temp_low++;
3369
3370 flag = CHECKBIT(val64, 0x3);
3371 type = 2;
3372 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_bias_current_high,
3373 &stat_info->xpak_stat.xpak_regs_stat,
3374 0x2, flag, type);
3375
3376 if(CHECKBIT(val64, 0x2))
3377 stat_info->xpak_stat.alarm_laser_bias_current_low++;
3378
3379 flag = CHECKBIT(val64, 0x1);
3380 type = 3;
3381 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_output_power_high,
3382 &stat_info->xpak_stat.xpak_regs_stat,
3383 0x4, flag, type);
3384
3385 if(CHECKBIT(val64, 0x0))
3386 stat_info->xpak_stat.alarm_laser_output_power_low++;
3387
3388 /* Reading the Warning flags */
3389 addr = 0xA074;
3390 val64 = 0x0;
3391 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3392
3393 if(CHECKBIT(val64, 0x7))
3394 stat_info->xpak_stat.warn_transceiver_temp_high++;
3395
3396 if(CHECKBIT(val64, 0x6))
3397 stat_info->xpak_stat.warn_transceiver_temp_low++;
3398
3399 if(CHECKBIT(val64, 0x3))
3400 stat_info->xpak_stat.warn_laser_bias_current_high++;
3401
3402 if(CHECKBIT(val64, 0x2))
3403 stat_info->xpak_stat.warn_laser_bias_current_low++;
3404
3405 if(CHECKBIT(val64, 0x1))
3406 stat_info->xpak_stat.warn_laser_output_power_high++;
3407
3408 if(CHECKBIT(val64, 0x0))
3409 stat_info->xpak_stat.warn_laser_output_power_low++;
3410 }
3411
3412 /**
3413 * wait_for_cmd_complete - waits for a command to complete.
3414 * @sp : private member of the device structure, which is a pointer to the
3415 * s2io_nic structure.
3416 * Description: Function that waits for a command to Write into RMAC
3417 * ADDR DATA registers to be completed and returns either success or
3418 * error depending on whether the command was complete or not.
3419 * Return value:
3420 * SUCCESS on success and FAILURE on failure.
3421 */
3422
3423 static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
3424 int bit_state)
3425 {
3426 int ret = FAILURE, cnt = 0, delay = 1;
3427 u64 val64;
3428
3429 if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3430 return FAILURE;
3431
3432 do {
3433 val64 = readq(addr);
3434 if (bit_state == S2IO_BIT_RESET) {
3435 if (!(val64 & busy_bit)) {
3436 ret = SUCCESS;
3437 break;
3438 }
3439 } else {
3440 if (!(val64 & busy_bit)) {
3441 ret = SUCCESS;
3442 break;
3443 }
3444 }
3445
3446 if(in_interrupt())
3447 mdelay(delay);
3448 else
3449 msleep(delay);
3450
3451 if (++cnt >= 10)
3452 delay = 50;
3453 } while (cnt < 20);
3454 return ret;
3455 }
3456 /*
3457 * check_pci_device_id - Checks if the device id is supported
3458 * @id : device id
3459 * Description: Function to check if the pci device id is supported by driver.
3460 * Return value: Actual device id if supported else PCI_ANY_ID
3461 */
3462 static u16 check_pci_device_id(u16 id)
3463 {
3464 switch (id) {
3465 case PCI_DEVICE_ID_HERC_WIN:
3466 case PCI_DEVICE_ID_HERC_UNI:
3467 return XFRAME_II_DEVICE;
3468 case PCI_DEVICE_ID_S2IO_UNI:
3469 case PCI_DEVICE_ID_S2IO_WIN:
3470 return XFRAME_I_DEVICE;
3471 default:
3472 return PCI_ANY_ID;
3473 }
3474 }
3475
3476 /**
3477 * s2io_reset - Resets the card.
3478 * @sp : private member of the device structure.
3479 * Description: Function to Reset the card. This function then also
3480 * restores the previously saved PCI configuration space registers as
3481 * the card reset also resets the configuration space.
3482 * Return value:
3483 * void.
3484 */
3485
3486 static void s2io_reset(struct s2io_nic * sp)
3487 {
3488 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3489 u64 val64;
3490 u16 subid, pci_cmd;
3491 int i;
3492 u16 val16;
3493 unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3494 unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
3495
3496 DBG_PRINT(INIT_DBG,"%s - Resetting XFrame card %s\n",
3497 __func__, sp->dev->name);
3498
3499 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3500 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
3501
3502 val64 = SW_RESET_ALL;
3503 writeq(val64, &bar0->sw_reset);
3504 if (strstr(sp->product_name, "CX4")) {
3505 msleep(750);
3506 }
3507 msleep(250);
3508 for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
3509
3510 /* Restore the PCI state saved during initialization. */
3511 pci_restore_state(sp->pdev);
3512 pci_read_config_word(sp->pdev, 0x2, &val16);
3513 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3514 break;
3515 msleep(200);
3516 }
3517
3518 if (check_pci_device_id(val16) == (u16)PCI_ANY_ID) {
3519 DBG_PRINT(ERR_DBG,"%s SW_Reset failed!\n", __func__);
3520 }
3521
3522 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3523
3524 s2io_init_pci(sp);
3525
3526 /* Set swapper to enable I/O register access */
3527 s2io_set_swapper(sp);
3528
3529 /* restore mac_addr entries */
3530 do_s2io_restore_unicast_mc(sp);
3531
3532 /* Restore the MSIX table entries from local variables */
3533 restore_xmsi_data(sp);
3534
3535 /* Clear certain PCI/PCI-X fields after reset */
3536 if (sp->device_type == XFRAME_II_DEVICE) {
3537 /* Clear "detected parity error" bit */
3538 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
3539
3540 /* Clearing PCIX Ecc status register */
3541 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
3542
3543 /* Clearing PCI_STATUS error reflected here */
3544 writeq(s2BIT(62), &bar0->txpic_int_reg);
3545 }
3546
3547 /* Reset device statistics maintained by OS */
3548 memset(&sp->stats, 0, sizeof (struct net_device_stats));
3549
3550 up_cnt = sp->mac_control.stats_info->sw_stat.link_up_cnt;
3551 down_cnt = sp->mac_control.stats_info->sw_stat.link_down_cnt;
3552 up_time = sp->mac_control.stats_info->sw_stat.link_up_time;
3553 down_time = sp->mac_control.stats_info->sw_stat.link_down_time;
3554 reset_cnt = sp->mac_control.stats_info->sw_stat.soft_reset_cnt;
3555 mem_alloc_cnt = sp->mac_control.stats_info->sw_stat.mem_allocated;
3556 mem_free_cnt = sp->mac_control.stats_info->sw_stat.mem_freed;
3557 watchdog_cnt = sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt;
3558 /* save link up/down time/cnt, reset/memory/watchdog cnt */
3559 memset(sp->mac_control.stats_info, 0, sizeof(struct stat_block));
3560 /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3561 sp->mac_control.stats_info->sw_stat.link_up_cnt = up_cnt;
3562 sp->mac_control.stats_info->sw_stat.link_down_cnt = down_cnt;
3563 sp->mac_control.stats_info->sw_stat.link_up_time = up_time;
3564 sp->mac_control.stats_info->sw_stat.link_down_time = down_time;
3565 sp->mac_control.stats_info->sw_stat.soft_reset_cnt = reset_cnt;
3566 sp->mac_control.stats_info->sw_stat.mem_allocated = mem_alloc_cnt;
3567 sp->mac_control.stats_info->sw_stat.mem_freed = mem_free_cnt;
3568 sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt = watchdog_cnt;
3569
3570 /* SXE-002: Configure link and activity LED to turn it off */
3571 subid = sp->pdev->subsystem_device;
3572 if (((subid & 0xFF) >= 0x07) &&
3573 (sp->device_type == XFRAME_I_DEVICE)) {
3574 val64 = readq(&bar0->gpio_control);
3575 val64 |= 0x0000800000000000ULL;
3576 writeq(val64, &bar0->gpio_control);
3577 val64 = 0x0411040400000000ULL;
3578 writeq(val64, (void __iomem *)bar0 + 0x2700);
3579 }
3580
3581 /*
3582 * Clear spurious ECC interrupts that would have occured on
3583 * XFRAME II cards after reset.
3584 */
3585 if (sp->device_type == XFRAME_II_DEVICE) {
3586 val64 = readq(&bar0->pcc_err_reg);
3587 writeq(val64, &bar0->pcc_err_reg);
3588 }
3589
3590 sp->device_enabled_once = false;
3591 }
3592
3593 /**
3594 * s2io_set_swapper - to set the swapper controle on the card
3595 * @sp : private member of the device structure,
3596 * pointer to the s2io_nic structure.
3597 * Description: Function to set the swapper control on the card
3598 * correctly depending on the 'endianness' of the system.
3599 * Return value:
3600 * SUCCESS on success and FAILURE on failure.
3601 */
3602
3603 static int s2io_set_swapper(struct s2io_nic * sp)
3604 {
3605 struct net_device *dev = sp->dev;
3606 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3607 u64 val64, valt, valr;
3608
3609 /*
3610 * Set proper endian settings and verify the same by reading
3611 * the PIF Feed-back register.
3612 */
3613
3614 val64 = readq(&bar0->pif_rd_swapper_fb);
3615 if (val64 != 0x0123456789ABCDEFULL) {
3616 int i = 0;
3617 u64 value[] = { 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
3618 0x8100008181000081ULL, /* FE=1, SE=0 */
3619 0x4200004242000042ULL, /* FE=0, SE=1 */
3620 0}; /* FE=0, SE=0 */
3621
3622 while(i<4) {
3623 writeq(value[i], &bar0->swapper_ctrl);
3624 val64 = readq(&bar0->pif_rd_swapper_fb);
3625 if (val64 == 0x0123456789ABCDEFULL)
3626 break;
3627 i++;
3628 }
3629 if (i == 4) {
3630 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3631 dev->name);
3632 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3633 (unsigned long long) val64);
3634 return FAILURE;
3635 }
3636 valr = value[i];
3637 } else {
3638 valr = readq(&bar0->swapper_ctrl);
3639 }
3640
3641 valt = 0x0123456789ABCDEFULL;
3642 writeq(valt, &bar0->xmsi_address);
3643 val64 = readq(&bar0->xmsi_address);
3644
3645 if(val64 != valt) {
3646 int i = 0;
3647 u64 value[] = { 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
3648 0x0081810000818100ULL, /* FE=1, SE=0 */
3649 0x0042420000424200ULL, /* FE=0, SE=1 */
3650 0}; /* FE=0, SE=0 */
3651
3652 while(i<4) {
3653 writeq((value[i] | valr), &bar0->swapper_ctrl);
3654 writeq(valt, &bar0->xmsi_address);
3655 val64 = readq(&bar0->xmsi_address);
3656 if(val64 == valt)
3657 break;
3658 i++;
3659 }
3660 if(i == 4) {
3661 unsigned long long x = val64;
3662 DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
3663 DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
3664 return FAILURE;
3665 }
3666 }
3667 val64 = readq(&bar0->swapper_ctrl);
3668 val64 &= 0xFFFF000000000000ULL;
3669
3670 #ifdef __BIG_ENDIAN
3671 /*
3672 * The device by default set to a big endian format, so a
3673 * big endian driver need not set anything.
3674 */
3675 val64 |= (SWAPPER_CTRL_TXP_FE |
3676 SWAPPER_CTRL_TXP_SE |
3677 SWAPPER_CTRL_TXD_R_FE |
3678 SWAPPER_CTRL_TXD_W_FE |
3679 SWAPPER_CTRL_TXF_R_FE |
3680 SWAPPER_CTRL_RXD_R_FE |
3681 SWAPPER_CTRL_RXD_W_FE |
3682 SWAPPER_CTRL_RXF_W_FE |
3683 SWAPPER_CTRL_XMSI_FE |
3684 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3685 if (sp->config.intr_type == INTA)
3686 val64 |= SWAPPER_CTRL_XMSI_SE;
3687 writeq(val64, &bar0->swapper_ctrl);
3688 #else
3689 /*
3690 * Initially we enable all bits to make it accessible by the
3691 * driver, then we selectively enable only those bits that
3692 * we want to set.
3693 */
3694 val64 |= (SWAPPER_CTRL_TXP_FE |
3695 SWAPPER_CTRL_TXP_SE |
3696 SWAPPER_CTRL_TXD_R_FE |
3697 SWAPPER_CTRL_TXD_R_SE |
3698 SWAPPER_CTRL_TXD_W_FE |
3699 SWAPPER_CTRL_TXD_W_SE |
3700 SWAPPER_CTRL_TXF_R_FE |
3701 SWAPPER_CTRL_RXD_R_FE |
3702 SWAPPER_CTRL_RXD_R_SE |
3703 SWAPPER_CTRL_RXD_W_FE |
3704 SWAPPER_CTRL_RXD_W_SE |
3705 SWAPPER_CTRL_RXF_W_FE |
3706 SWAPPER_CTRL_XMSI_FE |
3707 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3708 if (sp->config.intr_type == INTA)
3709 val64 |= SWAPPER_CTRL_XMSI_SE;
3710 writeq(val64, &bar0->swapper_ctrl);
3711 #endif
3712 val64 = readq(&bar0->swapper_ctrl);
3713
3714 /*
3715 * Verifying if endian settings are accurate by reading a
3716 * feedback register.
3717 */
3718 val64 = readq(&bar0->pif_rd_swapper_fb);
3719 if (val64 != 0x0123456789ABCDEFULL) {
3720 /* Endian settings are incorrect, calls for another dekko. */
3721 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3722 dev->name);
3723 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3724 (unsigned long long) val64);
3725 return FAILURE;
3726 }
3727
3728 return SUCCESS;
3729 }
3730
3731 static int wait_for_msix_trans(struct s2io_nic *nic, int i)
3732 {
3733 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3734 u64 val64;
3735 int ret = 0, cnt = 0;
3736
3737 do {
3738 val64 = readq(&bar0->xmsi_access);
3739 if (!(val64 & s2BIT(15)))
3740 break;
3741 mdelay(1);
3742 cnt++;
3743 } while(cnt < 5);
3744 if (cnt == 5) {
3745 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3746 ret = 1;
3747 }
3748
3749 return ret;
3750 }
3751
3752 static void restore_xmsi_data(struct s2io_nic *nic)
3753 {
3754 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3755 u64 val64;
3756 int i, msix_index;
3757
3758
3759 if (nic->device_type == XFRAME_I_DEVICE)
3760 return;
3761
3762 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
3763 msix_index = (i) ? ((i-1) * 8 + 1): 0;
3764 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3765 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3766 val64 = (s2BIT(7) | s2BIT(15) | vBIT(msix_index, 26, 6));
3767 writeq(val64, &bar0->xmsi_access);
3768 if (wait_for_msix_trans(nic, msix_index)) {
3769 DBG_PRINT(ERR_DBG, "failed in %s\n", __func__);
3770 continue;
3771 }
3772 }
3773 }
3774
3775 static void store_xmsi_data(struct s2io_nic *nic)
3776 {