1 /* niu.c: Neptune ethernet driver.
2 *
3 * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
4 */
5
6 #include <linux/module.h>
7 #include <linux/init.h>
8 #include <linux/pci.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/netdevice.h>
11 #include <linux/ethtool.h>
12 #include <linux/etherdevice.h>
13 #include <linux/platform_device.h>
14 #include <linux/delay.h>
15 #include <linux/bitops.h>
16 #include <linux/mii.h>
17 #include <linux/if_ether.h>
18 #include <linux/if_vlan.h>
19 #include <linux/ip.h>
20 #include <linux/in.h>
21 #include <linux/ipv6.h>
22 #include <linux/log2.h>
23 #include <linux/jiffies.h>
24 #include <linux/crc32.h>
25 #include <linux/list.h>
26
27 #include <linux/io.h>
28
29 #ifdef CONFIG_SPARC64
30 #include <linux/of_device.h>
31 #endif
32
33 #include "niu.h"
34
35 #define DRV_MODULE_NAME "niu"
36 #define PFX DRV_MODULE_NAME ": "
37 #define DRV_MODULE_VERSION "1.0"
38 #define DRV_MODULE_RELDATE "Nov 14, 2008"
39
40 static char version[] __devinitdata =
41 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
42
43 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
44 MODULE_DESCRIPTION("NIU ethernet driver");
45 MODULE_LICENSE("GPL");
46 MODULE_VERSION(DRV_MODULE_VERSION);
47
48 #ifndef DMA_44BIT_MASK
49 #define DMA_44BIT_MASK 0x00000fffffffffffULL
50 #endif
51
52 #ifndef readq
53 static u64 readq(void __iomem *reg)
54 {
55 return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32);
56 }
57
58 static void writeq(u64 val, void __iomem *reg)
59 {
60 writel(val & 0xffffffff, reg);
61 writel(val >> 32, reg + 0x4UL);
62 }
63 #endif
64
65 static struct pci_device_id niu_pci_tbl[] = {
66 {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)},
67 {}
68 };
69
70 MODULE_DEVICE_TABLE(pci, niu_pci_tbl);
71
72 #define NIU_TX_TIMEOUT (5 * HZ)
73
74 #define nr64(reg) readq(np->regs + (reg))
75 #define nw64(reg, val) writeq((val), np->regs + (reg))
76
77 #define nr64_mac(reg) readq(np->mac_regs + (reg))
78 #define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg))
79
80 #define nr64_ipp(reg) readq(np->regs + np->ipp_off + (reg))
81 #define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg))
82
83 #define nr64_pcs(reg) readq(np->regs + np->pcs_off + (reg))
84 #define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg))
85
86 #define nr64_xpcs(reg) readq(np->regs + np->xpcs_off + (reg))
87 #define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg))
88
89 #define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
90
91 static int niu_debug;
92 static int debug = -1;
93 module_param(debug, int, 0);
94 MODULE_PARM_DESC(debug, "NIU debug level");
95
96 #define niudbg(TYPE, f, a...) \
97 do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
98 printk(KERN_DEBUG PFX f, ## a); \
99 } while (0)
100
101 #define niuinfo(TYPE, f, a...) \
102 do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
103 printk(KERN_INFO PFX f, ## a); \
104 } while (0)
105
106 #define niuwarn(TYPE, f, a...) \
107 do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
108 printk(KERN_WARNING PFX f, ## a); \
109 } while (0)
110
111 #define niu_lock_parent(np, flags) \
112 spin_lock_irqsave(&np->parent->lock, flags)
113 #define niu_unlock_parent(np, flags) \
114 spin_unlock_irqrestore(&np->parent->lock, flags)
115
116 static int serdes_init_10g_serdes(struct niu *np);
117
118 static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg,
119 u64 bits, int limit, int delay)
120 {
121 while (--limit >= 0) {
122 u64 val = nr64_mac(reg);
123
124 if (!(val & bits))
125 break;
126 udelay(delay);
127 }
128 if (limit < 0)
129 return -ENODEV;
130 return 0;
131 }
132
133 static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg,
134 u64 bits, int limit, int delay,
135 const char *reg_name)
136 {
137 int err;
138
139 nw64_mac(reg, bits);
140 err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
141 if (err)
142 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
143 "would not clear, val[%llx]\n",
144 np->dev->name, (unsigned long long) bits, reg_name,
145 (unsigned long long) nr64_mac(reg));
146 return err;
147 }
148
149 #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
150 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
151 __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
152 })
153
154 static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg,
155 u64 bits, int limit, int delay)
156 {
157 while (--limit >= 0) {
158 u64 val = nr64_ipp(reg);
159
160 if (!(val & bits))
161 break;
162 udelay(delay);
163 }
164 if (limit < 0)
165 return -ENODEV;
166 return 0;
167 }
168
169 static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg,
170 u64 bits, int limit, int delay,
171 const char *reg_name)
172 {
173 int err;
174 u64 val;
175
176 val = nr64_ipp(reg);
177 val |= bits;
178 nw64_ipp(reg, val);
179
180 err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
181 if (err)
182 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
183 "would not clear, val[%llx]\n",
184 np->dev->name, (unsigned long long) bits, reg_name,
185 (unsigned long long) nr64_ipp(reg));
186 return err;
187 }
188
189 #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
190 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
191 __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
192 })
193
194 static int __niu_wait_bits_clear(struct niu *np, unsigned long reg,
195 u64 bits, int limit, int delay)
196 {
197 while (--limit >= 0) {
198 u64 val = nr64(reg);
199
200 if (!(val & bits))
201 break;
202 udelay(delay);
203 }
204 if (limit < 0)
205 return -ENODEV;
206 return 0;
207 }
208
209 #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
210 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
211 __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
212 })
213
214 static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg,
215 u64 bits, int limit, int delay,
216 const char *reg_name)
217 {
218 int err;
219
220 nw64(reg, bits);
221 err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
222 if (err)
223 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
224 "would not clear, val[%llx]\n",
225 np->dev->name, (unsigned long long) bits, reg_name,
226 (unsigned long long) nr64(reg));
227 return err;
228 }
229
230 #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
231 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
232 __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
233 })
234
235 static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on)
236 {
237 u64 val = (u64) lp->timer;
238
239 if (on)
240 val |= LDG_IMGMT_ARM;
241
242 nw64(LDG_IMGMT(lp->ldg_num), val);
243 }
244
245 static int niu_ldn_irq_enable(struct niu *np, int ldn, int on)
246 {
247 unsigned long mask_reg, bits;
248 u64 val;
249
250 if (ldn < 0 || ldn > LDN_MAX)
251 return -EINVAL;
252
253 if (ldn < 64) {
254 mask_reg = LD_IM0(ldn);
255 bits = LD_IM0_MASK;
256 } else {
257 mask_reg = LD_IM1(ldn - 64);
258 bits = LD_IM1_MASK;
259 }
260
261 val = nr64(mask_reg);
262 if (on)
263 val &= ~bits;
264 else
265 val |= bits;
266 nw64(mask_reg, val);
267
268 return 0;
269 }
270
271 static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on)
272 {
273 struct niu_parent *parent = np->parent;
274 int i;
275
276 for (i = 0; i <= LDN_MAX; i++) {
277 int err;
278
279 if (parent->ldg_map[i] != lp->ldg_num)
280 continue;
281
282 err = niu_ldn_irq_enable(np, i, on);
283 if (err)
284 return err;
285 }
286 return 0;
287 }
288
289 static int niu_enable_interrupts(struct niu *np, int on)
290 {
291 int i;
292
293 for (i = 0; i < np->num_ldg; i++) {
294 struct niu_ldg *lp = &np->ldg[i];
295 int err;
296
297 err = niu_enable_ldn_in_ldg(np, lp, on);
298 if (err)
299 return err;
300 }
301 for (i = 0; i < np->num_ldg; i++)
302 niu_ldg_rearm(np, &np->ldg[i], on);
303
304 return 0;
305 }
306
307 static u32 phy_encode(u32 type, int port)
308 {
309 return (type << (port * 2));
310 }
311
312 static u32 phy_decode(u32 val, int port)
313 {
314 return (val >> (port * 2)) & PORT_TYPE_MASK;
315 }
316
317 static int mdio_wait(struct niu *np)
318 {
319 int limit = 1000;
320 u64 val;
321
322 while (--limit > 0) {
323 val = nr64(MIF_FRAME_OUTPUT);
324 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
325 return val & MIF_FRAME_OUTPUT_DATA;
326
327 udelay(10);
328 }
329
330 return -ENODEV;
331 }
332
333 static int mdio_read(struct niu *np, int port, int dev, int reg)
334 {
335 int err;
336
337 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
338 err = mdio_wait(np);
339 if (err < 0)
340 return err;
341
342 nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
343 return mdio_wait(np);
344 }
345
346 static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
347 {
348 int err;
349
350 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
351 err = mdio_wait(np);
352 if (err < 0)
353 return err;
354
355 nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
356 err = mdio_wait(np);
357 if (err < 0)
358 return err;
359
360 return 0;
361 }
362
363 static int mii_read(struct niu *np, int port, int reg)
364 {
365 nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
366 return mdio_wait(np);
367 }
368
369 static int mii_write(struct niu *np, int port, int reg, int data)
370 {
371 int err;
372
373 nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
374 err = mdio_wait(np);
375 if (err < 0)
376 return err;
377
378 return 0;
379 }
380
381 static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
382 {
383 int err;
384
385 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
386 ESR2_TI_PLL_TX_CFG_L(channel),
387 val & 0xffff);
388 if (!err)
389 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
390 ESR2_TI_PLL_TX_CFG_H(channel),
391 val >> 16);
392 return err;
393 }
394
395 static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
396 {
397 int err;
398
399 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
400 ESR2_TI_PLL_RX_CFG_L(channel),
401 val & 0xffff);
402 if (!err)
403 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
404 ESR2_TI_PLL_RX_CFG_H(channel),
405 val >> 16);
406 return err;
407 }
408
409 /* Mode is always 10G fiber. */
410 static int serdes_init_niu_10g_fiber(struct niu *np)
411 {
412 struct niu_link_config *lp = &np->link_config;
413 u32 tx_cfg, rx_cfg;
414 unsigned long i;
415
416 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
417 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
418 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
419 PLL_RX_CFG_EQ_LP_ADAPTIVE);
420
421 if (lp->loopback_mode == LOOPBACK_PHY) {
422 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
423
424 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
425 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
426
427 tx_cfg |= PLL_TX_CFG_ENTEST;
428 rx_cfg |= PLL_RX_CFG_ENTEST;
429 }
430
431 /* Initialize all 4 lanes of the SERDES. */
432 for (i = 0; i < 4; i++) {
433 int err = esr2_set_tx_cfg(np, i, tx_cfg);
434 if (err)
435 return err;
436 }
437
438 for (i = 0; i < 4; i++) {
439 int err = esr2_set_rx_cfg(np, i, rx_cfg);
440 if (err)
441 return err;
442 }
443
444 return 0;
445 }
446
447 static int serdes_init_niu_1g_serdes(struct niu *np)
448 {
449 struct niu_link_config *lp = &np->link_config;
450 u16 pll_cfg, pll_sts;
451 int max_retry = 100;
452 u64 uninitialized_var(sig), mask, val;
453 u32 tx_cfg, rx_cfg;
454 unsigned long i;
455 int err;
456
457 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV |
458 PLL_TX_CFG_RATE_HALF);
459 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
460 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
461 PLL_RX_CFG_RATE_HALF);
462
463 if (np->port == 0)
464 rx_cfg |= PLL_RX_CFG_EQ_LP_ADAPTIVE;
465
466 if (lp->loopback_mode == LOOPBACK_PHY) {
467 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
468
469 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
470 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
471
472 tx_cfg |= PLL_TX_CFG_ENTEST;
473 rx_cfg |= PLL_RX_CFG_ENTEST;
474 }
475
476 /* Initialize PLL for 1G */
477 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_8X);
478
479 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
480 ESR2_TI_PLL_CFG_L, pll_cfg);
481 if (err) {
482 dev_err(np->device, PFX "NIU Port %d "
483 "serdes_init_niu_1g_serdes: "
484 "mdio write to ESR2_TI_PLL_CFG_L failed", np->port);
485 return err;
486 }
487
488 pll_sts = PLL_CFG_ENPLL;
489
490 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
491 ESR2_TI_PLL_STS_L, pll_sts);
492 if (err) {
493 dev_err(np->device, PFX "NIU Port %d "
494 "serdes_init_niu_1g_serdes: "
495 "mdio write to ESR2_TI_PLL_STS_L failed", np->port);
496 return err;
497 }
498
499 udelay(200);
500
501 /* Initialize all 4 lanes of the SERDES. */
502 for (i = 0; i < 4; i++) {
503 err = esr2_set_tx_cfg(np, i, tx_cfg);
504 if (err)
505 return err;
506 }
507
508 for (i = 0; i < 4; i++) {
509 err = esr2_set_rx_cfg(np, i, rx_cfg);
510 if (err)
511 return err;
512 }
513
514 switch (np->port) {
515 case 0:
516 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
517 mask = val;
518 break;
519
520 case 1:
521 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
522 mask = val;
523 break;
524
525 default:
526 return -EINVAL;
527 }
528
529 while (max_retry--) {
530 sig = nr64(ESR_INT_SIGNALS);
531 if ((sig & mask) == val)
532 break;
533
534 mdelay(500);
535 }
536
537 if ((sig & mask) != val) {
538 dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
539 "[%08x]\n", np->port, (int) (sig & mask), (int) val);
540 return -ENODEV;
541 }
542
543 return 0;
544 }
545
546 static int serdes_init_niu_10g_serdes(struct niu *np)
547 {
548 struct niu_link_config *lp = &np->link_config;
549 u32 tx_cfg, rx_cfg, pll_cfg, pll_sts;
550 int max_retry = 100;
551 u64 uninitialized_var(sig), mask, val;
552 unsigned long i;
553 int err;
554
555 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
556 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
557 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
558 PLL_RX_CFG_EQ_LP_ADAPTIVE);
559
560 if (lp->loopback_mode == LOOPBACK_PHY) {
561 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
562
563 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
564 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
565
566 tx_cfg |= PLL_TX_CFG_ENTEST;
567 rx_cfg |= PLL_RX_CFG_ENTEST;
568 }
569
570 /* Initialize PLL for 10G */
571 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_10X);
572
573 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
574 ESR2_TI_PLL_CFG_L, pll_cfg & 0xffff);
575 if (err) {
576 dev_err(np->device, PFX "NIU Port %d "
577 "serdes_init_niu_10g_serdes: "
578 "mdio write to ESR2_TI_PLL_CFG_L failed", np->port);
579 return err;
580 }
581
582 pll_sts = PLL_CFG_ENPLL;
583
584 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
585 ESR2_TI_PLL_STS_L, pll_sts & 0xffff);
586 if (err) {
587 dev_err(np->device, PFX "NIU Port %d "
588 "serdes_init_niu_10g_serdes: "
589 "mdio write to ESR2_TI_PLL_STS_L failed", np->port);
590 return err;
591 }
592
593 udelay(200);
594
595 /* Initialize all 4 lanes of the SERDES. */
596 for (i = 0; i < 4; i++) {
597 err = esr2_set_tx_cfg(np, i, tx_cfg);
598 if (err)
599 return err;
600 }
601
602 for (i = 0; i < 4; i++) {
603 err = esr2_set_rx_cfg(np, i, rx_cfg);
604 if (err)
605 return err;
606 }
607
608 /* check if serdes is ready */
609
610 switch (np->port) {
611 case 0:
612 mask = ESR_INT_SIGNALS_P0_BITS;
613 val = (ESR_INT_SRDY0_P0 |
614 ESR_INT_DET0_P0 |
615 ESR_INT_XSRDY_P0 |
616 ESR_INT_XDP_P0_CH3 |
617 ESR_INT_XDP_P0_CH2 |
618 ESR_INT_XDP_P0_CH1 |
619 ESR_INT_XDP_P0_CH0);
620 break;
621
622 case 1:
623 mask = ESR_INT_SIGNALS_P1_BITS;
624 val = (ESR_INT_SRDY0_P1 |
625 ESR_INT_DET0_P1 |
626 ESR_INT_XSRDY_P1 |
627 ESR_INT_XDP_P1_CH3 |
628 ESR_INT_XDP_P1_CH2 |
629 ESR_INT_XDP_P1_CH1 |
630 ESR_INT_XDP_P1_CH0);
631 break;
632
633 default:
634 return -EINVAL;
635 }
636
637 while (max_retry--) {
638 sig = nr64(ESR_INT_SIGNALS);
639 if ((sig & mask) == val)
640 break;
641
642 mdelay(500);
643 }
644
645 if ((sig & mask) != val) {
646 pr_info(PFX "NIU Port %u signal bits [%08x] are not "
647 "[%08x] for 10G...trying 1G\n",
648 np->port, (int) (sig & mask), (int) val);
649
650 /* 10G failed, try initializing at 1G */
651 err = serdes_init_niu_1g_serdes(np);
652 if (!err) {
653 np->flags &= ~NIU_FLAGS_10G;
654 np->mac_xcvr = MAC_XCVR_PCS;
655 } else {
656 dev_err(np->device, PFX "Port %u 10G/1G SERDES "
657 "Link Failed \n", np->port);
658 return -ENODEV;
659 }
660 }
661 return 0;
662 }
663
664 static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
665 {
666 int err;
667
668 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
669 if (err >= 0) {
670 *val = (err & 0xffff);
671 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
672 ESR_RXTX_CTRL_H(chan));
673 if (err >= 0)
674 *val |= ((err & 0xffff) << 16);
675 err = 0;
676 }
677 return err;
678 }
679
680 static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
681 {
682 int err;
683
684 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
685 ESR_GLUE_CTRL0_L(chan));
686 if (err >= 0) {
687 *val = (err & 0xffff);
688 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
689 ESR_GLUE_CTRL0_H(chan));
690 if (err >= 0) {
691 *val |= ((err & 0xffff) << 16);
692 err = 0;
693 }
694 }
695 return err;
696 }
697
698 static int esr_read_reset(struct niu *np, u32 *val)
699 {
700 int err;
701
702 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
703 ESR_RXTX_RESET_CTRL_L);
704 if (err >= 0) {
705 *val = (err & 0xffff);
706 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
707 ESR_RXTX_RESET_CTRL_H);
708 if (err >= 0) {
709 *val |= ((err & 0xffff) << 16);
710 err = 0;
711 }
712 }
713 return err;
714 }
715
716 static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
717 {
718 int err;
719
720 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
721 ESR_RXTX_CTRL_L(chan), val & 0xffff);
722 if (!err)
723 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
724 ESR_RXTX_CTRL_H(chan), (val >> 16));
725 return err;
726 }
727
728 static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
729 {
730 int err;
731
732 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
733 ESR_GLUE_CTRL0_L(chan), val & 0xffff);
734 if (!err)
735 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
736 ESR_GLUE_CTRL0_H(chan), (val >> 16));
737 return err;
738 }
739
740 static int esr_reset(struct niu *np)
741 {
742 u32 uninitialized_var(reset);
743 int err;
744
745 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
746 ESR_RXTX_RESET_CTRL_L, 0x0000);
747 if (err)
748 return err;
749 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
750 ESR_RXTX_RESET_CTRL_H, 0xffff);
751 if (err)
752 return err;
753 udelay(200);
754
755 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
756 ESR_RXTX_RESET_CTRL_L, 0xffff);
757 if (err)
758 return err;
759 udelay(200);
760
761 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
762 ESR_RXTX_RESET_CTRL_H, 0x0000);
763 if (err)
764 return err;
765 udelay(200);
766
767 err = esr_read_reset(np, &reset);
768 if (err)
769 return err;
770 if (reset != 0) {
771 dev_err(np->device, PFX "Port %u ESR_RESET "
772 "did not clear [%08x]\n",
773 np->port, reset);
774 return -ENODEV;
775 }
776
777 return 0;
778 }
779
780 static int serdes_init_10g(struct niu *np)
781 {
782 struct niu_link_config *lp = &np->link_config;
783 unsigned long ctrl_reg, test_cfg_reg, i;
784 u64 ctrl_val, test_cfg_val, sig, mask, val;
785 int err;
786
787 switch (np->port) {
788 case 0:
789 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
790 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
791 break;
792 case 1:
793 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
794 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
795 break;
796
797 default:
798 return -EINVAL;
799 }
800 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
801 ENET_SERDES_CTRL_SDET_1 |
802 ENET_SERDES_CTRL_SDET_2 |
803 ENET_SERDES_CTRL_SDET_3 |
804 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
805 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
806 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
807 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
808 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
809 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
810 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
811 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
812 test_cfg_val = 0;
813
814 if (lp->loopback_mode == LOOPBACK_PHY) {
815 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
816 ENET_SERDES_TEST_MD_0_SHIFT) |
817 (ENET_TEST_MD_PAD_LOOPBACK <<
818 ENET_SERDES_TEST_MD_1_SHIFT) |
819 (ENET_TEST_MD_PAD_LOOPBACK <<
820 ENET_SERDES_TEST_MD_2_SHIFT) |
821 (ENET_TEST_MD_PAD_LOOPBACK <<
822 ENET_SERDES_TEST_MD_3_SHIFT));
823 }
824
825 nw64(ctrl_reg, ctrl_val);
826 nw64(test_cfg_reg, test_cfg_val);
827
828 /* Initialize all 4 lanes of the SERDES. */
829 for (i = 0; i < 4; i++) {
830 u32 rxtx_ctrl, glue0;
831
832 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
833 if (err)
834 return err;
835 err = esr_read_glue0(np, i, &glue0);
836 if (err)
837 return err;
838
839 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
840 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
841 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
842
843 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
844 ESR_GLUE_CTRL0_THCNT |
845 ESR_GLUE_CTRL0_BLTIME);
846 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
847 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
848 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
849 (BLTIME_300_CYCLES <<
850 ESR_GLUE_CTRL0_BLTIME_SHIFT));
851
852 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
853 if (err)
854 return err;
855 err = esr_write_glue0(np, i, glue0);
856 if (err)
857 return err;
858 }
859
860 err = esr_reset(np);
861 if (err)
862 return err;
863
864 sig = nr64(ESR_INT_SIGNALS);
865 switch (np->port) {
866 case 0:
867 mask = ESR_INT_SIGNALS_P0_BITS;
868 val = (ESR_INT_SRDY0_P0 |
869 ESR_INT_DET0_P0 |
870 ESR_INT_XSRDY_P0 |
871 ESR_INT_XDP_P0_CH3 |
872 ESR_INT_XDP_P0_CH2 |
873 ESR_INT_XDP_P0_CH1 |
874 ESR_INT_XDP_P0_CH0);
875 break;
876
877 case 1:
878 mask = ESR_INT_SIGNALS_P1_BITS;
879 val = (ESR_INT_SRDY0_P1 |
880 ESR_INT_DET0_P1 |
881 ESR_INT_XSRDY_P1 |
882 ESR_INT_XDP_P1_CH3 |
883 ESR_INT_XDP_P1_CH2 |
884 ESR_INT_XDP_P1_CH1 |
885 ESR_INT_XDP_P1_CH0);
886 break;
887
888 default:
889 return -EINVAL;
890 }
891
892 if ((sig & mask) != val) {
893 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
894 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
895 return 0;
896 }
897 dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
898 "[%08x]\n", np->port, (int) (sig & mask), (int) val);
899 return -ENODEV;
900 }
901 if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
902 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
903 return 0;
904 }
905
906 static int serdes_init_1g(struct niu *np)
907 {
908 u64 val;
909
910 val = nr64(ENET_SERDES_1_PLL_CFG);
911 val &= ~ENET_SERDES_PLL_FBDIV2;
912 switch (np->port) {
913 case 0:
914 val |= ENET_SERDES_PLL_HRATE0;
915 break;
916 case 1:
917 val |= ENET_SERDES_PLL_HRATE1;
918 break;
919 case 2:
920 val |= ENET_SERDES_PLL_HRATE2;
921 break;
922 case 3:
923 val |= ENET_SERDES_PLL_HRATE3;
924 break;
925 default:
926 return -EINVAL;
927 }
928 nw64(ENET_SERDES_1_PLL_CFG, val);
929
930 return 0;
931 }
932
933 static int serdes_init_1g_serdes(struct niu *np)
934 {
935 struct niu_link_config *lp = &np->link_config;
936 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
937 u64 ctrl_val, test_cfg_val, sig, mask, val;
938 int err;
939 u64 reset_val, val_rd;
940
941 val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 |
942 ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 |
943 ENET_SERDES_PLL_FBDIV0;
944 switch (np->port) {
945 case 0:
946 reset_val = ENET_SERDES_RESET_0;
947 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
948 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
949 pll_cfg = ENET_SERDES_0_PLL_CFG;
950 break;
951 case 1:
952 reset_val = ENET_SERDES_RESET_1;
953 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
954 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
955 pll_cfg = ENET_SERDES_1_PLL_CFG;
956 break;
957
958 default:
959 return -EINVAL;
960 }
961 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
962 ENET_SERDES_CTRL_SDET_1 |
963 ENET_SERDES_CTRL_SDET_2 |
964 ENET_SERDES_CTRL_SDET_3 |
965 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
966 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
967 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
968 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
969 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
970 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
971 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
972 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
973 test_cfg_val = 0;
974
975 if (lp->loopback_mode == LOOPBACK_PHY) {
976 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
977 ENET_SERDES_TEST_MD_0_SHIFT) |
978 (ENET_TEST_MD_PAD_LOOPBACK <<
979 ENET_SERDES_TEST_MD_1_SHIFT) |
980 (ENET_TEST_MD_PAD_LOOPBACK <<
981 ENET_SERDES_TEST_MD_2_SHIFT) |
982 (ENET_TEST_MD_PAD_LOOPBACK <<
983 ENET_SERDES_TEST_MD_3_SHIFT));
984 }
985
986 nw64(ENET_SERDES_RESET, reset_val);
987 mdelay(20);
988 val_rd = nr64(ENET_SERDES_RESET);
989 val_rd &= ~reset_val;
990 nw64(pll_cfg, val);
991 nw64(ctrl_reg, ctrl_val);
992 nw64(test_cfg_reg, test_cfg_val);
993 nw64(ENET_SERDES_RESET, val_rd);
994 mdelay(2000);
995
996 /* Initialize all 4 lanes of the SERDES. */
997 for (i = 0; i < 4; i++) {
998 u32 rxtx_ctrl, glue0;
999
1000 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
1001 if (err)
1002 return err;
1003 err = esr_read_glue0(np, i, &glue0);
1004 if (err)
1005 return err;
1006
1007 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
1008 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
1009 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
1010
1011 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
1012 ESR_GLUE_CTRL0_THCNT |
1013 ESR_GLUE_CTRL0_BLTIME);
1014 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
1015 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
1016 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
1017 (BLTIME_300_CYCLES <<
1018 ESR_GLUE_CTRL0_BLTIME_SHIFT));
1019
1020 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
1021 if (err)
1022 return err;
1023 err = esr_write_glue0(np, i, glue0);
1024 if (err)
1025 return err;
1026 }
1027
1028
1029 sig = nr64(ESR_INT_SIGNALS);
1030 switch (np->port) {
1031 case 0:
1032 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
1033 mask = val;
1034 break;
1035
1036 case 1:
1037 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
1038 mask = val;
1039 break;
1040
1041 default:
1042 return -EINVAL;
1043 }
1044
1045 if ((sig & mask) != val) {
1046 dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
1047 "[%08x]\n", np->port, (int) (sig & mask), (int) val);
1048 return -ENODEV;
1049 }
1050
1051 return 0;
1052 }
1053
1054 static int link_status_1g_serdes(struct niu *np, int *link_up_p)
1055 {
1056 struct niu_link_config *lp = &np->link_config;
1057 int link_up;
1058 u64 val;
1059 u16 current_speed;
1060 unsigned long flags;
1061 u8 current_duplex;
1062
1063 link_up = 0;
1064 current_speed = SPEED_INVALID;
1065 current_duplex = DUPLEX_INVALID;
1066
1067 spin_lock_irqsave(&np->lock, flags);
1068
1069 val = nr64_pcs(PCS_MII_STAT);
1070
1071 if (val & PCS_MII_STAT_LINK_STATUS) {
1072 link_up = 1;
1073 current_speed = SPEED_1000;
1074 current_duplex = DUPLEX_FULL;
1075 }
1076
1077 lp->active_speed = current_speed;
1078 lp->active_duplex = current_duplex;
1079 spin_unlock_irqrestore(&np->lock, flags);
1080
1081 *link_up_p = link_up;
1082 return 0;
1083 }
1084
1085 static int link_status_10g_serdes(struct niu *np, int *link_up_p)
1086 {
1087 unsigned long flags;
1088 struct niu_link_config *lp = &np->link_config;
1089 int link_up = 0;
1090 int link_ok = 1;
1091 u64 val, val2;
1092 u16 current_speed;
1093 u8 current_duplex;
1094
1095 if (!(np->flags & NIU_FLAGS_10G))
1096 return link_status_1g_serdes(np, link_up_p);
1097
1098 current_speed = SPEED_INVALID;
1099 current_duplex = DUPLEX_INVALID;
1100 spin_lock_irqsave(&np->lock, flags);
1101
1102 val = nr64_xpcs(XPCS_STATUS(0));
1103 val2 = nr64_mac(XMAC_INTER2);
1104 if (val2 & 0x01000000)
1105 link_ok = 0;
1106
1107 if ((val & 0x1000ULL) && link_ok) {
1108 link_up = 1;
1109 current_speed = SPEED_10000;
1110 current_duplex = DUPLEX_FULL;
1111 }
1112 lp->active_speed = current_speed;
1113 lp->active_duplex = current_duplex;
1114 spin_unlock_irqrestore(&np->lock, flags);
1115 *link_up_p = link_up;
1116 return 0;
1117 }
1118
1119 static int link_status_mii(struct niu *np, int *link_up_p)
1120 {
1121 struct niu_link_config *lp = &np->link_config;
1122 int err;
1123 int bmsr, advert, ctrl1000, stat1000, lpa, bmcr, estatus;
1124 int supported, advertising, active_speed, active_duplex;
1125
1126 err = mii_read(np, np->phy_addr, MII_BMCR);
1127 if (unlikely(err < 0))
1128 return err;
1129 bmcr = err;
1130
1131 err = mii_read(np, np->phy_addr, MII_BMSR);
1132 if (unlikely(err < 0))
1133 return err;
1134 bmsr = err;
1135
1136 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1137 if (unlikely(err < 0))
1138 return err;
1139 advert = err;
1140
1141 err = mii_read(np, np->phy_addr, MII_LPA);
1142 if (unlikely(err < 0))
1143 return err;
1144 lpa = err;
1145
1146 if (likely(bmsr & BMSR_ESTATEN)) {
1147 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1148 if (unlikely(err < 0))
1149 return err;
1150 estatus = err;
1151
1152 err = mii_read(np, np->phy_addr, MII_CTRL1000);
1153 if (unlikely(err < 0))
1154 return err;
1155 ctrl1000 = err;
1156
1157 err = mii_read(np, np->phy_addr, MII_STAT1000);
1158 if (unlikely(err < 0))
1159 return err;
1160 stat1000 = err;
1161 } else
1162 estatus = ctrl1000 = stat1000 = 0;
1163
1164 supported = 0;
1165 if (bmsr & BMSR_ANEGCAPABLE)
1166 supported |= SUPPORTED_Autoneg;
1167 if (bmsr & BMSR_10HALF)
1168 supported |= SUPPORTED_10baseT_Half;
1169 if (bmsr & BMSR_10FULL)
1170 supported |= SUPPORTED_10baseT_Full;
1171 if (bmsr & BMSR_100HALF)
1172 supported |= SUPPORTED_100baseT_Half;
1173 if (bmsr & BMSR_100FULL)
1174 supported |= SUPPORTED_100baseT_Full;
1175 if (estatus & ESTATUS_1000_THALF)
1176 supported |= SUPPORTED_1000baseT_Half;
1177 if (estatus & ESTATUS_1000_TFULL)
1178 supported |= SUPPORTED_1000baseT_Full;
1179 lp->supported = supported;
1180
1181 advertising = 0;
1182 if (advert & ADVERTISE_10HALF)
1183 advertising |= ADVERTISED_10baseT_Half;
1184 if (advert & ADVERTISE_10FULL)
1185 advertising |= ADVERTISED_10baseT_Full;
1186 if (advert & ADVERTISE_100HALF)
1187 advertising |= ADVERTISED_100baseT_Half;
1188 if (advert & ADVERTISE_100FULL)
1189 advertising |= ADVERTISED_100baseT_Full;
1190 if (ctrl1000 & ADVERTISE_1000HALF)
1191 advertising |= ADVERTISED_1000baseT_Half;
1192 if (ctrl1000 & ADVERTISE_1000FULL)
1193 advertising |= ADVERTISED_1000baseT_Full;
1194
1195 if (bmcr & BMCR_ANENABLE) {
1196 int neg, neg1000;
1197
1198 lp->active_autoneg = 1;
1199 advertising |= ADVERTISED_Autoneg;
1200
1201 neg = advert & lpa;
1202 neg1000 = (ctrl1000 << 2) & stat1000;
1203
1204 if (neg1000 & (LPA_1000FULL | LPA_1000HALF))
1205 active_speed = SPEED_1000;
1206 else if (neg & LPA_100)
1207 active_speed = SPEED_100;
1208 else if (neg & (LPA_10HALF | LPA_10FULL))
1209 active_speed = SPEED_10;
1210 else
1211 active_speed = SPEED_INVALID;
1212
1213 if ((neg1000 & LPA_1000FULL) || (neg & LPA_DUPLEX))
1214 active_duplex = DUPLEX_FULL;
1215 else if (active_speed != SPEED_INVALID)
1216 active_duplex = DUPLEX_HALF;
1217 else
1218 active_duplex = DUPLEX_INVALID;
1219 } else {
1220 lp->active_autoneg = 0;
1221
1222 if ((bmcr & BMCR_SPEED1000) && !(bmcr & BMCR_SPEED100))
1223 active_speed = SPEED_1000;
1224 else if (bmcr & BMCR_SPEED100)
1225 active_speed = SPEED_100;
1226 else
1227 active_speed = SPEED_10;
1228
1229 if (bmcr & BMCR_FULLDPLX)
1230 active_duplex = DUPLEX_FULL;
1231 else
1232 active_duplex = DUPLEX_HALF;
1233 }
1234
1235 lp->active_advertising = advertising;
1236 lp->active_speed = active_speed;
1237 lp->active_duplex = active_duplex;
1238 *link_up_p = !!(bmsr & BMSR_LSTATUS);
1239
1240 return 0;
1241 }
1242
1243 static int link_status_1g_rgmii(struct niu *np, int *link_up_p)
1244 {
1245 struct niu_link_config *lp = &np->link_config;
1246 u16 current_speed, bmsr;
1247 unsigned long flags;
1248 u8 current_duplex;
1249 int err, link_up;
1250
1251 link_up = 0;
1252 current_speed = SPEED_INVALID;
1253 current_duplex = DUPLEX_INVALID;
1254
1255 spin_lock_irqsave(&np->lock, flags);
1256
1257 err = -EINVAL;
1258
1259 err = mii_read(np, np->phy_addr, MII_BMSR);
1260 if (err < 0)
1261 goto out;
1262
1263 bmsr = err;
1264 if (bmsr & BMSR_LSTATUS) {
1265 u16 adv, lpa, common, estat;
1266
1267 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1268 if (err < 0)
1269 goto out;
1270 adv = err;
1271
1272 err = mii_read(np, np->phy_addr, MII_LPA);
1273 if (err < 0)
1274 goto out;
1275 lpa = err;
1276
1277 common = adv & lpa;
1278
1279 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1280 if (err < 0)
1281 goto out;
1282 estat = err;
1283 link_up = 1;
1284 current_speed = SPEED_1000;
1285 current_duplex = DUPLEX_FULL;
1286
1287 }
1288 lp->active_speed = current_speed;
1289 lp->active_duplex = current_duplex;
1290 err = 0;
1291
1292 out:
1293 spin_unlock_irqrestore(&np->lock, flags);
1294
1295 *link_up_p = link_up;
1296 return err;
1297 }
1298
1299 static int link_status_1g(struct niu *np, int *link_up_p)
1300 {
1301 struct niu_link_config *lp = &np->link_config;
1302 unsigned long flags;
1303 int err;
1304
1305 spin_lock_irqsave(&np->lock, flags);
1306
1307 err = link_status_mii(np, link_up_p);
1308 lp->supported |= SUPPORTED_TP;
1309 lp->active_advertising |= ADVERTISED_TP;
1310
1311 spin_unlock_irqrestore(&np->lock, flags);
1312 return err;
1313 }
1314
1315 static int bcm8704_reset(struct niu *np)
1316 {
1317 int err, limit;
1318
1319 err = mdio_read(np, np->phy_addr,
1320 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1321 if (err < 0 || err == 0xffff)
1322 return err;
1323 err |= BMCR_RESET;
1324 err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1325 MII_BMCR, err);
1326 if (err)
1327 return err;
1328
1329 limit = 1000;
1330 while (--limit >= 0) {
1331 err = mdio_read(np, np->phy_addr,
1332 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1333 if (err < 0)
1334 return err;
1335 if (!(err & BMCR_RESET))
1336 break;
1337 }
1338 if (limit < 0) {
1339 dev_err(np->device, PFX "Port %u PHY will not reset "
1340 "(bmcr=%04x)\n", np->port, (err & 0xffff));
1341 return -ENODEV;
1342 }
1343 return 0;
1344 }
1345
1346 /* When written, certain PHY registers need to be read back twice
1347 * in order for the bits to settle properly.
1348 */
1349 static int bcm8704_user_dev3_readback(struct niu *np, int reg)
1350 {
1351 int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1352 if (err < 0)
1353 return err;
1354 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1355 if (err < 0)
1356 return err;
1357 return 0;
1358 }
1359
1360 static int bcm8706_init_user_dev3(struct niu *np)
1361 {
1362 int err;
1363
1364
1365 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1366 BCM8704_USER_OPT_DIGITAL_CTRL);
1367 if (err < 0)
1368 return err;
1369 err &= ~USER_ODIG_CTRL_GPIOS;
1370 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1371 err |= USER_ODIG_CTRL_RESV2;
1372 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1373 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1374 if (err)
1375 return err;
1376
1377 mdelay(1000);
1378
1379 return 0;
1380 }
1381
1382 static int bcm8704_init_user_dev3(struct niu *np)
1383 {
1384 int err;
1385
1386 err = mdio_write(np, np->phy_addr,
1387 BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL,
1388 (USER_CONTROL_OPTXRST_LVL |
1389 USER_CONTROL_OPBIASFLT_LVL |
1390 USER_CONTROL_OBTMPFLT_LVL |
1391 USER_CONTROL_OPPRFLT_LVL |
1392 USER_CONTROL_OPTXFLT_LVL |
1393 USER_CONTROL_OPRXLOS_LVL |
1394 USER_CONTROL_OPRXFLT_LVL |
1395 USER_CONTROL_OPTXON_LVL |
1396 (0x3f << USER_CONTROL_RES1_SHIFT)));
1397 if (err)
1398 return err;
1399
1400 err = mdio_write(np, np->phy_addr,
1401 BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL,
1402 (USER_PMD_TX_CTL_XFP_CLKEN |
1403 (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) |
1404 (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) |
1405 USER_PMD_TX_CTL_TSCK_LPWREN));
1406 if (err)
1407 return err;
1408
1409 err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
1410 if (err)
1411 return err;
1412 err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
1413 if (err)
1414 return err;
1415
1416 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1417 BCM8704_USER_OPT_DIGITAL_CTRL);
1418 if (err < 0)
1419 return err;
1420 err &= ~USER_ODIG_CTRL_GPIOS;
1421 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1422 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1423 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1424 if (err)
1425 return err;
1426
1427 mdelay(1000);
1428
1429 return 0;
1430 }
1431
1432 static int mrvl88x2011_act_led(struct niu *np, int val)
1433 {
1434 int err;
1435
1436 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1437 MRVL88X2011_LED_8_TO_11_CTL);
1438 if (err < 0)
1439 return err;
1440
1441 err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK);
1442 err |= MRVL88X2011_LED(MRVL88X2011_LED_ACT,val);
1443
1444 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1445 MRVL88X2011_LED_8_TO_11_CTL, err);
1446 }
1447
1448 static int mrvl88x2011_led_blink_rate(struct niu *np, int rate)
1449 {
1450 int err;
1451
1452 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1453 MRVL88X2011_LED_BLINK_CTL);
1454 if (err >= 0) {
1455 err &= ~MRVL88X2011_LED_BLKRATE_MASK;
1456 err |= (rate << 4);
1457
1458 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1459 MRVL88X2011_LED_BLINK_CTL, err);
1460 }
1461
1462 return err;
1463 }
1464
1465 static int xcvr_init_10g_mrvl88x2011(struct niu *np)
1466 {
1467 int err;
1468
1469 /* Set LED functions */
1470 err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS);
1471 if (err)
1472 return err;
1473
1474 /* led activity */
1475 err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF);
1476 if (err)
1477 return err;
1478
1479 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1480 MRVL88X2011_GENERAL_CTL);
1481 if (err < 0)
1482 return err;
1483
1484 err |= MRVL88X2011_ENA_XFPREFCLK;
1485
1486 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1487 MRVL88X2011_GENERAL_CTL, err);
1488 if (err < 0)
1489 return err;
1490
1491 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1492 MRVL88X2011_PMA_PMD_CTL_1);
1493 if (err < 0)
1494 return err;
1495
1496 if (np->link_config.loopback_mode == LOOPBACK_MAC)
1497 err |= MRVL88X2011_LOOPBACK;
1498 else
1499 err &= ~MRVL88X2011_LOOPBACK;
1500
1501 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1502 MRVL88X2011_PMA_PMD_CTL_1, err);
1503 if (err < 0)
1504 return err;
1505
1506 /* Enable PMD */
1507 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1508 MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX);
1509 }
1510
1511
1512 static int xcvr_diag_bcm870x(struct niu *np)
1513 {
1514 u16 analog_stat0, tx_alarm_status;
1515 int err = 0;
1516
1517 #if 1
1518 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1519 MII_STAT1000);
1520 if (err < 0)
1521 return err;
1522 pr_info(PFX "Port %u PMA_PMD(MII_STAT1000) [%04x]\n",
1523 np->port, err);
1524
1525 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
1526 if (err < 0)
1527 return err;
1528 pr_info(PFX "Port %u USER_DEV3(0x20) [%04x]\n",
1529 np->port, err);
1530
1531 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1532 MII_NWAYTEST);
1533 if (err < 0)
1534 return err;
1535 pr_info(PFX "Port %u PHYXS(MII_NWAYTEST) [%04x]\n",
1536 np->port, err);
1537 #endif
1538
1539 /* XXX dig this out it might not be so useful XXX */
1540 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1541 BCM8704_USER_ANALOG_STATUS0);
1542 if (err < 0)
1543 return err;
1544 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1545 BCM8704_USER_ANALOG_STATUS0);
1546 if (err < 0)
1547 return err;
1548 analog_stat0 = err;
1549
1550 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1551 BCM8704_USER_TX_ALARM_STATUS);
1552 if (err < 0)
1553 return err;
1554 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1555 BCM8704_USER_TX_ALARM_STATUS);
1556 if (err < 0)
1557 return err;
1558 tx_alarm_status = err;
1559
1560 if (analog_stat0 != 0x03fc) {
1561 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) {
1562 pr_info(PFX "Port %u cable not connected "
1563 "or bad cable.\n", np->port);
1564 } else if (analog_stat0 == 0x639c) {
1565 pr_info(PFX "Port %u optical module is bad "
1566 "or missing.\n", np->port);
1567 }
1568 }
1569
1570 return 0;
1571 }
1572
1573 static int xcvr_10g_set_lb_bcm870x(struct niu *np)
1574 {
1575 struct niu_link_config *lp = &np->link_config;
1576 int err;
1577
1578 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1579 MII_BMCR);
1580 if (err < 0)
1581 return err;
1582
1583 err &= ~BMCR_LOOPBACK;
1584
1585 if (lp->loopback_mode == LOOPBACK_MAC)
1586 err |= BMCR_LOOPBACK;
1587
1588 err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1589 MII_BMCR, err);
1590 if (err)
1591 return err;
1592
1593 return 0;
1594 }
1595
1596 static int xcvr_init_10g_bcm8706(struct niu *np)
1597 {
1598 int err = 0;
1599 u64 val;
1600
1601 if ((np->flags & NIU_FLAGS_HOTPLUG_PHY) &&
1602 (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) == 0)
1603 return err;
1604
1605 val = nr64_mac(XMAC_CONFIG);
1606 val &= ~XMAC_CONFIG_LED_POLARITY;
1607 val |= XMAC_CONFIG_FORCE_LED_ON;
1608 nw64_mac(XMAC_CONFIG, val);
1609
1610 val = nr64(MIF_CONFIG);
1611 val |= MIF_CONFIG_INDIRECT_MODE;
1612 nw64(MIF_CONFIG, val);
1613
1614 err = bcm8704_reset(np);
1615 if (err)
1616 return err;
1617
1618 err = xcvr_10g_set_lb_bcm870x(np);
1619 if (err)
1620 return err;
1621
1622 err = bcm8706_init_user_dev3(np);
1623 if (err)
1624 return err;
1625
1626 err = xcvr_diag_bcm870x(np);
1627 if (err)
1628 return err;
1629
1630 return 0;
1631 }
1632
1633 static int xcvr_init_10g_bcm8704(struct niu *np)
1634 {
1635 int err;
1636
1637 err = bcm8704_reset(np);
1638 if (err)
1639 return err;
1640
1641 err = bcm8704_init_user_dev3(np);
1642 if (err)
1643 return err;
1644
1645 err = xcvr_10g_set_lb_bcm870x(np);
1646 if (err)
1647 return err;
1648
1649 err = xcvr_diag_bcm870x(np);
1650 if (err)
1651 return err;
1652
1653 return 0;
1654 }
1655
1656 static int xcvr_init_10g(struct niu *np)
1657 {
1658 int phy_id, err;
1659 u64 val;
1660
1661 val = nr64_mac(XMAC_CONFIG);
1662 val &= ~XMAC_CONFIG_LED_POLARITY;
1663 val |= XMAC_CONFIG_FORCE_LED_ON;
1664 nw64_mac(XMAC_CONFIG, val);
1665
1666 /* XXX shared resource, lock parent XXX */
1667 val = nr64(MIF_CONFIG);
1668 val |= MIF_CONFIG_INDIRECT_MODE;
1669 nw64(MIF_CONFIG, val);
1670
1671 phy_id = phy_decode(np->parent->port_phy, np->port);
1672 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1673
1674 /* handle different phy types */
1675 switch (phy_id & NIU_PHY_ID_MASK) {
1676 case NIU_PHY_ID_MRVL88X2011:
1677 err = xcvr_init_10g_mrvl88x2011(np);
1678 break;
1679
1680 default: /* bcom 8704 */
1681 err = xcvr_init_10g_bcm8704(np);
1682 break;
1683 }
1684
1685 return 0;
1686 }
1687
1688 static int mii_reset(struct niu *np)
1689 {
1690 int limit, err;
1691
1692 err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
1693 if (err)
1694 return err;
1695
1696 limit = 1000;
1697 while (--limit >= 0) {
1698 udelay(500);
1699 err = mii_read(np, np->phy_addr, MII_BMCR);
1700 if (err < 0)
1701 return err;
1702 if (!(err & BMCR_RESET))
1703 break;
1704 }
1705 if (limit < 0) {
1706 dev_err(np->device, PFX "Port %u MII would not reset, "
1707 "bmcr[%04x]\n", np->port, err);
1708 return -ENODEV;
1709 }
1710
1711 return 0;
1712 }
1713
1714 static int xcvr_init_1g_rgmii(struct niu *np)
1715 {
1716 int err;
1717 u64 val;
1718 u16 bmcr, bmsr, estat;
1719
1720 val = nr64(MIF_CONFIG);
1721 val &= ~MIF_CONFIG_INDIRECT_MODE;
1722 nw64(MIF_CONFIG, val);
1723
1724 err = mii_reset(np);
1725 if (err)
1726 return err;
1727
1728 err = mii_read(np, np->phy_addr, MII_BMSR);
1729 if (err < 0)
1730 return err;
1731 bmsr = err;
1732
1733 estat = 0;
1734 if (bmsr & BMSR_ESTATEN) {
1735 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1736 if (err < 0)
1737 return err;
1738 estat = err;
1739 }
1740
1741 bmcr = 0;
1742 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1743 if (err)
1744 return err;
1745
1746 if (bmsr & BMSR_ESTATEN) {
1747 u16 ctrl1000 = 0;
1748
1749 if (estat & ESTATUS_1000_TFULL)
1750 ctrl1000 |= ADVERTISE_1000FULL;
1751 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1752 if (err)
1753 return err;
1754 }
1755
1756 bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX);
1757
1758 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1759 if (err)
1760 return err;
1761
1762 err = mii_read(np, np->phy_addr, MII_BMCR);
1763 if (err < 0)
1764 return err;
1765 bmcr = mii_read(np, np->phy_addr, MII_BMCR);
1766
1767 err = mii_read(np, np->phy_addr, MII_BMSR);
1768 if (err < 0)
1769 return err;
1770
1771 return 0;
1772 }
1773
1774 static int mii_init_common(struct niu *np)
1775 {
1776 struct niu_link_config *lp = &np->link_config;
1777 u16 bmcr, bmsr, adv, estat;
1778 int err;
1779
1780 err = mii_reset(np);
1781 if (err)
1782 return err;
1783
1784 err = mii_read(np, np->phy_addr, MII_BMSR);
1785 if (err < 0)
1786 return err;
1787 bmsr = err;
1788
1789 estat = 0;
1790 if (bmsr & BMSR_ESTATEN) {
1791 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1792 if (err < 0)
1793 return err;
1794 estat = err;
1795 }
1796
1797 bmcr = 0;
1798 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1799 if (err)
1800 return err;
1801
1802 if (lp->loopback_mode == LOOPBACK_MAC) {
1803 bmcr |= BMCR_LOOPBACK;
1804 if (lp->active_speed == SPEED_1000)
1805 bmcr |= BMCR_SPEED1000;
1806 if (lp->active_duplex == DUPLEX_FULL)
1807 bmcr |= BMCR_FULLDPLX;
1808 }
1809
1810 if (lp->loopback_mode == LOOPBACK_PHY) {
1811 u16 aux;
1812
1813 aux = (BCM5464R_AUX_CTL_EXT_LB |
1814 BCM5464R_AUX_CTL_WRITE_1);
1815 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
1816 if (err)
1817 return err;
1818 }
1819
1820 if (lp->autoneg) {
1821 u16 ctrl1000;
1822
1823 adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1824 if ((bmsr & BMSR_10HALF) &&
1825 (lp->advertising & ADVERTISED_10baseT_Half))
1826 adv |= ADVERTISE_10HALF;
1827 if ((bmsr & BMSR_10FULL) &&
1828 (lp->advertising & ADVERTISED_10baseT_Full))
1829 adv |= ADVERTISE_10FULL;
1830 if ((bmsr & BMSR_100HALF) &&
1831 (lp->advertising & ADVERTISED_100baseT_Half))
1832 adv |= ADVERTISE_100HALF;
1833 if ((bmsr & BMSR_100FULL) &&
1834 (lp->advertising & ADVERTISED_100baseT_Full))
1835 adv |= ADVERTISE_100FULL;
1836 err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
1837 if (err)
1838 return err;
1839
1840 if (likely(bmsr & BMSR_ESTATEN)) {
1841 ctrl1000 = 0;
1842 if ((estat & ESTATUS_1000_THALF) &&
1843 (lp->advertising & ADVERTISED_1000baseT_Half))
1844 ctrl1000 |= ADVERTISE_1000HALF;
1845 if ((estat & ESTATUS_1000_TFULL) &&
1846 (lp->advertising & ADVERTISED_1000baseT_Full))
1847 ctrl1000 |= ADVERTISE_1000FULL;
1848 err = mii_write(np, np->phy_addr,
1849 MII_CTRL1000, ctrl1000);
1850 if (err)
1851 return err;
1852 }
1853
1854 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1855 } else {
1856 /* !lp->autoneg */
1857 int fulldpx;
1858
1859 if (lp->duplex == DUPLEX_FULL) {
1860 bmcr |= BMCR_FULLDPLX;
1861 fulldpx = 1;
1862 } else if (lp->duplex == DUPLEX_HALF)
1863 fulldpx = 0;
1864 else
1865 return -EINVAL;
1866
1867 if (lp->speed == SPEED_1000) {
1868 /* if X-full requested while not supported, or
1869 X-half requested while not supported... */
1870 if ((fulldpx && !(estat & ESTATUS_1000_TFULL)) ||
1871 (!fulldpx && !(estat & ESTATUS_1000_THALF)))
1872 return -EINVAL;
1873 bmcr |= BMCR_SPEED1000;
1874 } else if (lp->speed == SPEED_100) {
1875 if ((fulldpx && !(bmsr & BMSR_100FULL)) ||
1876 (!fulldpx && !(bmsr & BMSR_100HALF)))
1877 return -EINVAL;
1878 bmcr |= BMCR_SPEED100;
1879 } else if (lp->speed == SPEED_10) {
1880 if ((fulldpx && !(bmsr & BMSR_10FULL)) ||
1881 (!fulldpx && !(bmsr & BMSR_10HALF)))
1882 return -EINVAL;
1883 } else
1884 return -EINVAL;
1885 }
1886
1887 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1888 if (err)
1889 return err;
1890
1891 #if 0
1892 err = mii_read(np, np->phy_addr, MII_BMCR);
1893 if (err < 0)
1894 return err;
1895 bmcr = err;
1896
1897 err = mii_read(np, np->phy_addr, MII_BMSR);
1898 if (err < 0)
1899 return err;
1900 bmsr = err;
1901
1902 pr_info(PFX "Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
1903 np->port, bmcr, bmsr);
1904 #endif
1905
1906 return 0;
1907 }
1908
1909 static int xcvr_init_1g(struct niu *np)
1910 {
1911 u64 val;
1912
1913 /* XXX shared resource, lock parent XXX */
1914 val = nr64(MIF_CONFIG);
1915 val &= ~MIF_CONFIG_INDIRECT_MODE;
1916 nw64(MIF_CONFIG, val);
1917
1918 return mii_init_common(np);
1919 }
1920
1921 static int niu_xcvr_init(struct niu *np)
1922 {
1923 const struct niu_phy_ops *ops = np->phy_ops;
1924 int err;
1925
1926 err = 0;
1927 if (ops->xcvr_init)
1928 err = ops->xcvr_init(np);
1929
1930 return err;
1931 }
1932
1933 static int niu_serdes_init(struct niu *np)
1934 {
1935 const struct niu_phy_ops *ops = np->phy_ops;
1936 int err;
1937
1938 err = 0;
1939 if (ops->serdes_init)
1940 err = ops->serdes_init(np);
1941
1942 return err;
1943 }
1944
1945 static void niu_init_xif(struct niu *);
1946 static void niu_handle_led(struct niu *, int status);
1947
1948 static int niu_link_status_common(struct niu *np, int link_up)
1949 {
1950 struct niu_link_config *lp = &np->link_config;
1951 struct net_device *dev = np->dev;
1952 unsigned long flags;
1953
1954 if (!netif_carrier_ok(dev) && link_up) {
1955 niuinfo(LINK, "%s: Link is up at %s, %s duplex\n",
1956 dev->name,
1957 (lp->active_speed == SPEED_10000 ?
1958 "10Gb/sec" :
1959 (lp->active_speed == SPEED_1000 ?
1960 "1Gb/sec" :
1961 (lp->active_speed == SPEED_100 ?
1962 "100Mbit/sec" : "10Mbit/sec"))),
1963 (lp->active_duplex == DUPLEX_FULL ?
1964 "full" : "half"));
1965
1966 spin_lock_irqsave(&np->lock, flags);
1967 niu_init_xif(np);
1968 niu_handle_led(np, 1);
1969 spin_unlock_irqrestore(&np->lock, flags);
1970
1971 netif_carrier_on(dev);
1972 } else if (netif_carrier_ok(dev) && !link_up) {
1973 niuwarn(LINK, "%s: Link is down\n", dev->name);
1974 spin_lock_irqsave(&np->lock, flags);
1975 niu_handle_led(np, 0);
1976 spin_unlock_irqrestore(&np->lock, flags);
1977 netif_carrier_off(dev);
1978 }
1979
1980 return 0;
1981 }
1982
1983 static int link_status_10g_mrvl(struct niu *np, int *link_up_p)
1984 {
1985 int err, link_up, pma_status, pcs_status;
1986
1987 link_up = 0;
1988
1989 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1990 MRVL88X2011_10G_PMD_STATUS_2);
1991 if (err < 0)
1992 goto out;
1993
1994 /* Check PMA/PMD Register: 1.0001.2 == 1 */
1995 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1996 MRVL88X2011_PMA_PMD_STATUS_1);
1997 if (err < 0)
1998 goto out;
1999
2000 pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
2001
2002 /* Check PMC Register : 3.0001.2 == 1: read twice */
2003 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
2004 MRVL88X2011_PMA_PMD_STATUS_1);
2005 if (err < 0)
2006 goto out;
2007
2008 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
2009 MRVL88X2011_PMA_PMD_STATUS_1);
2010 if (err < 0)
2011 goto out;
2012
2013 pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
2014
2015 /* Check XGXS Register : 4.0018.[0-3,12] */
2016 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR,
2017 MRVL88X2011_10G_XGXS_LANE_STAT);
2018 if (err < 0)
2019 goto out;
2020
2021 if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 |
2022 PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 |
2023 PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC |
2024 0x800))
2025 link_up = (pma_status && pcs_status) ? 1 : 0;
2026
2027 np->link_config.active_speed = SPEED_10000;
2028 np->link_config.active_duplex = DUPLEX_FULL;
2029 err = 0;
2030 out:
2031 mrvl88x2011_act_led(np, (link_up ?
2032 MRVL88X2011_LED_CTL_PCS_ACT :
2033 MRVL88X2011_LED_CTL_OFF));
2034
2035 *link_up_p = link_up;
2036 return err;
2037 }
2038
2039 static int link_status_10g_bcm8706(struct niu *np, int *link_up_p)
2040 {
2041 int err, link_up;
2042 link_up = 0;
2043
2044 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2045 BCM8704_PMD_RCV_SIGDET);
2046 if (err < 0 || err == 0xffff)
2047 goto out;
2048 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2049 err = 0;
2050 goto out;
2051 }
2052
2053 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2054 BCM8704_PCS_10G_R_STATUS);
2055 if (err < 0)
2056 goto out;
2057
2058 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2059 err = 0;
2060 goto out;
2061 }
2062
2063 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2064 BCM8704_PHYXS_XGXS_LANE_STAT);
2065 if (err < 0)
2066 goto out;
2067 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2068 PHYXS_XGXS_LANE_STAT_MAGIC |
2069 PHYXS_XGXS_LANE_STAT_PATTEST |
2070 PHYXS_XGXS_LANE_STAT_LANE3 |
2071 PHYXS_XGXS_LANE_STAT_LANE2 |
2072 PHYXS_XGXS_LANE_STAT_LANE1 |
2073 PHYXS_XGXS_LANE_STAT_LANE0)) {
2074 err = 0;
2075 np->link_config.active_speed = SPEED_INVALID;
2076 np->link_config.active_duplex = DUPLEX_INVALID;
2077 goto out;
2078 }
2079
2080 link_up = 1;
2081 np->link_config.active_speed = SPEED_10000;
2082 np->link_config.active_duplex = DUPLEX_FULL;
2083 err = 0;
2084
2085 out:
2086 *link_up_p = link_up;
2087 return err;
2088 }
2089
2090 static int link_status_10g_bcom(struct niu *np, int *link_up_p)
2091 {
2092 int err, link_up;
2093
2094 link_up = 0;
2095
2096 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2097 BCM8704_PMD_RCV_SIGDET);
2098 if (err < 0)
2099 goto out;
2100 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2101 err = 0;
2102 goto out;
2103 }
2104
2105 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2106 BCM8704_PCS_10G_R_STATUS);
2107 if (err < 0)
2108 goto out;
2109 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2110 err = 0;
2111 goto out;
2112 }
2113
2114 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2115 BCM8704_PHYXS_XGXS_LANE_STAT);
2116 if (err < 0)
2117 goto out;
2118
2119 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2120 PHYXS_XGXS_LANE_STAT_MAGIC |
2121 PHYXS_XGXS_LANE_STAT_LANE3 |
2122 PHYXS_XGXS_LANE_STAT_LANE2 |
2123 PHYXS_XGXS_LANE_STAT_LANE1 |
2124 PHYXS_XGXS_LANE_STAT_LANE0)) {
2125 err = 0;
2126 goto out;
2127 }
2128
2129 link_up = 1;
2130 np->link_config.active_speed = SPEED_10000;
2131 np->link_config.active_duplex = DUPLEX_FULL;
2132 err = 0;
2133
2134 out:
2135 *link_up_p = link_up;
2136 return err;
2137 }
2138
2139 static int link_status_10g(struct niu *np, int *link_up_p)
2140 {
2141 unsigned long flags;
2142 int err = -EINVAL;
2143
2144 spin_lock_irqsave(&np->lock, flags);
2145
2146 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2147 int phy_id;
2148
2149 phy_id = phy_decode(np->parent->port_phy, np->port);
2150 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
2151
2152 /* handle different phy types */
2153 switch (phy_id & NIU_PHY_ID_MASK) {
2154 case NIU_PHY_ID_MRVL88X2011:
2155 err = link_status_10g_mrvl(np, link_up_p);
2156 break;
2157
2158 default: /* bcom 8704 */
2159 err = link_status_10g_bcom(np, link_up_p);
2160 break;
2161 }
2162 }
2163
2164 spin_unlock_irqrestore(&np->lock, flags);
2165
2166 return err;
2167 }
2168
2169 static int niu_10g_phy_present(struct niu *np)
2170 {
2171 u64 sig, mask, val;
2172
2173 sig = nr64(ESR_INT_SIGNALS);
2174 switch (np->port) {
2175 case 0:
2176 mask = ESR_INT_SIGNALS_P0_BITS;
2177 val = (ESR_INT_SRDY0_P0 |
2178 ESR_INT_DET0_P0 |
2179 ESR_INT_XSRDY_P0 |
2180 ESR_INT_XDP_P0_CH3 |
2181 ESR_INT_XDP_P0_CH2 |
2182 ESR_INT_XDP_P0_CH1 |
2183 ESR_INT_XDP_P0_CH0);
2184 break;
2185
2186 case 1:
2187 mask = ESR_INT_SIGNALS_P1_BITS;
2188 val = (ESR_INT_SRDY0_P1 |
2189 ESR_INT_DET0_P1 |
2190 ESR_INT_XSRDY_P1 |
2191 ESR_INT_XDP_P1_CH3 |
2192 ESR_INT_XDP_P1_CH2 |
2193 ESR_INT_XDP_P1_CH1 |
2194 ESR_INT_XDP_P1_CH0);
2195 break;
2196
2197 default:
2198 return 0;
2199 }
2200
2201 if ((sig & mask) != val)
2202 return 0;
2203 return 1;
2204 }
2205
2206 static int link_status_10g_hotplug(struct niu *np, int *link_up_p)
2207 {
2208 unsigned long flags;
2209 int err = 0;
2210 int phy_present;
2211 int phy_present_prev;
2212
2213 spin_lock_irqsave(&np->lock, flags);
2214
2215 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2216 phy_present_prev = (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) ?
2217 1 : 0;
2218 phy_present = niu_10g_phy_present(np);
2219 if (phy_present != phy_present_prev) {
2220 /* state change */
2221 if (phy_present) {
2222 /* A NEM was just plugged in */
2223 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2224 if (np->phy_ops->xcvr_init)
2225 err = np->phy_ops->xcvr_init(np);
2226 if (err) {
2227 err = mdio_read(np, np->phy_addr,
2228 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
2229 if (err == 0xffff) {
2230 /* No mdio, back-to-back XAUI */
2231 goto out;
2232 }
2233 /* debounce */
2234 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2235 }
2236 } else {
2237 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2238 *link_up_p = 0;
2239 niuwarn(LINK, "%s: Hotplug PHY Removed\n",
2240 np->dev->name);
2241 }
2242 }
2243 out:
2244 if (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) {
2245 err = link_status_10g_bcm8706(np, link_up_p);
2246 if (err == 0xffff) {
2247 /* No mdio, back-to-back XAUI: it is C10NEM */
2248 *link_up_p = 1;
2249 np->link_config.active_speed = SPEED_10000;
2250 np->link_config.active_duplex = DUPLEX_FULL;
2251 }
2252 }
2253 }
2254
2255 spin_unlock_irqrestore(&np->lock, flags);
2256
2257 return 0;
2258 }
2259
2260 static int niu_link_status(struct niu *np, int *link_up_p)
2261 {
2262 const struct niu_phy_ops *ops = np->phy_ops;
2263 int err;
2264
2265 err = 0;
2266 if (ops->link_status)
2267 err = ops->link_status(np, link_up_p);
2268
2269 return err;
2270 }
2271
2272 static void niu_timer(unsigned long __opaque)
2273 {
2274 struct niu *np = (struct niu *) __opaque;
2275 unsigned long off;
2276 int err, link_up;
2277
2278 err = niu_link_status(np, &link_up);
2279 if (!err)
2280 niu_link_status_common(np, link_up);
2281
2282 if (netif_carrier_ok(np->dev))
2283 off = 5 * HZ;
2284 else
2285 off = 1 * HZ;
2286 np->timer.expires = jiffies + off;
2287
2288 add_timer(&np->timer);
2289 }
2290
2291 static const struct niu_phy_ops phy_ops_10g_serdes = {
2292 .serdes_init = serdes_init_10g_serdes,
2293 .link_status = link_status_10g_serdes,
2294 };
2295
2296 static const struct niu_phy_ops phy_ops_10g_serdes_niu = {
2297 .serdes_init = serdes_init_niu_10g_serdes,
2298 .link_status = link_status_10g_serdes,
2299 };
2300
2301 static const struct niu_phy_ops phy_ops_1g_serdes_niu = {
2302 .serdes_init = serdes_init_niu_1g_serdes,
2303 .link_status = link_status_1g_serdes,
2304 };
2305
2306 static const struct niu_phy_ops phy_ops_1g_rgmii = {
2307 .xcvr_init = xcvr_init_1g_rgmii,
2308 .link_status = link_status_1g_rgmii,
2309 };
2310
2311 static const struct niu_phy_ops phy_ops_10g_fiber_niu = {
2312 .serdes_init = serdes_init_niu_10g_fiber,
2313 .xcvr_init = xcvr_init_10g,
2314 .link_status = link_status_10g,
2315 };
2316
2317 static const struct niu_phy_ops phy_ops_10g_fiber = {
2318 .serdes_init = serdes_init_10g,
2319 .xcvr_init = xcvr_init_10g,
2320 .link_status = link_status_10g,
2321 };
2322
2323 static const struct niu_phy_ops phy_ops_10g_fiber_hotplug = {
2324 .serdes_init = serdes_init_10g,
2325 .xcvr_init = xcvr_init_10g_bcm8706,
2326 .link_status = link_status_10g_hotplug,
2327 };
2328
2329 static const struct niu_phy_ops phy_ops_niu_10g_hotplug = {
2330 .serdes_init = serdes_init_niu_10g_fiber,
2331 .xcvr_init = xcvr_init_10g_bcm8706,
2332 .link_status = link_status_10g_hotplug,
2333 };
2334
2335 static const struct niu_phy_ops phy_ops_10g_copper = {
2336 .serdes_init = serdes_init_10g,
2337 .link_status = link_status_10g, /* XXX */
2338 };
2339
2340 static const struct niu_phy_ops phy_ops_1g_fiber = {
2341 .serdes_init = serdes_init_1g,
2342 .xcvr_init = xcvr_init_1g,
2343 .link_status = link_status_1g,
2344 };
2345
2346 static const struct niu_phy_ops phy_ops_1g_copper = {
2347 .xcvr_init = xcvr_init_1g,
2348 .link_status = link_status_1g,
2349 };
2350
2351 struct niu_phy_template {
2352 const struct niu_phy_ops *ops;
2353 u32 phy_addr_base;
2354 };
2355
2356 static const struct niu_phy_template phy_template_niu_10g_fiber = {
2357 .ops = &phy_ops_10g_fiber_niu,
2358 .phy_addr_base = 16,
2359 };
2360
2361 static const struct niu_phy_template phy_template_niu_10g_serdes = {
2362 .ops = &phy_ops_10g_serdes_niu,
2363 .phy_addr_base = 0,
2364 };
2365
2366 static const struct niu_phy_template phy_template_niu_1g_serdes = {
2367 .ops = &phy_ops_1g_serdes_niu,
2368 .phy_addr_base = 0,
2369 };
2370
2371 static const struct niu_phy_template phy_template_10g_fiber = {
2372 .ops = &phy_ops_10g_fiber,
2373 .phy_addr_base = 8,
2374 };
2375
2376 static const struct niu_phy_template phy_template_10g_fiber_hotplug = {
2377 .ops = &phy_ops_10g_fiber_hotplug,
2378 .phy_addr_base = 8,
2379 };
2380
2381 static const struct niu_phy_template phy_template_niu_10g_hotplug = {
2382 .ops = &phy_ops_niu_10g_hotplug,
2383 .phy_addr_base = 8,
2384 };
2385
2386 static const struct niu_phy_template phy_template_10g_copper = {
2387 .ops = &phy_ops_10g_copper,
2388 .phy_addr_base = 10,
2389 };
2390
2391 static const struct niu_phy_template phy_template_1g_fiber = {
2392 .ops = &phy_ops_1g_fiber,
2393 .phy_addr_base = 0,
2394 };
2395
2396 static const struct niu_phy_template phy_template_1g_copper = {
2397 .ops = &phy_ops_1g_copper,
2398 .phy_addr_base = 0,
2399 };
2400
2401 static const struct niu_phy_template phy_template_1g_rgmii = {
2402 .ops = &phy_ops_1g_rgmii,
2403 .phy_addr_base = 0,
2404 };
2405
2406 static const struct niu_phy_template phy_template_10g_serdes = {
2407 .ops = &phy_ops_10g_serdes,
2408 .phy_addr_base = 0,
2409 };
2410
2411 static int niu_atca_port_num[4] = {
2412 0, 0, 11, 10
2413 };
2414
2415 static int serdes_init_10g_serdes(struct niu *np)
2416 {
2417 struct niu_link_config *lp = &np->link_config;
2418 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
2419 u64 ctrl_val, test_cfg_val, sig, mask, val;
2420 u64 reset_val;
2421
2422 switch (np->port) {
2423 case 0:
2424 reset_val = ENET_SERDES_RESET_0;
2425 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
2426 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
2427 pll_cfg = ENET_SERDES_0_PLL_CFG;
2428 break;
2429 case 1:
2430 reset_val = ENET_SERDES_RESET_1;
2431 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
2432 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
2433 pll_cfg = ENET_SERDES_1_PLL_CFG;
2434 break;
2435
2436 default:
2437 return -EINVAL;
2438 }
2439 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
2440 ENET_SERDES_CTRL_SDET_1 |
2441 ENET_SERDES_CTRL_SDET_2 |
2442 ENET_SERDES_CTRL_SDET_3 |
2443 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
2444 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
2445 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
2446 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
2447 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
2448 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
2449 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
2450 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
2451 test_cfg_val = 0;
2452
2453 if (lp->loopback_mode == LOOPBACK_PHY) {
2454 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
2455 ENET_SERDES_TEST_MD_0_SHIFT) |
2456 (ENET_TEST_MD_PAD_LOOPBACK <<
2457 ENET_SERDES_TEST_MD_1_SHIFT) |
2458 (ENET_TEST_MD_PAD_LOOPBACK <<
2459 ENET_SERDES_TEST_MD_2_SHIFT) |
2460 (ENET_TEST_MD_PAD_LOOPBACK <<
2461 ENET_SERDES_TEST_MD_3_SHIFT));
2462 }
2463
2464 esr_reset(np);
2465 nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2);
2466 nw64(ctrl_reg, ctrl_val);
2467 nw64(test_cfg_reg, test_cfg_val);
2468
2469 /* Initialize all 4 lanes of the SERDES. */
2470 for (i = 0; i < 4; i++) {
2471 u32 rxtx_ctrl, glue0;
2472 int err;
2473
2474 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
2475 if (err)
2476 return err;
2477 err = esr_read_glue0(np, i, &glue0);
2478 if (err)
2479 return err;
2480
2481 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
2482 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
2483 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
2484
2485 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
2486 ESR_GLUE_CTRL0_THCNT |
2487 ESR_GLUE_CTRL0_BLTIME);
2488 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
2489 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
2490 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
2491 (BLTIME_300_CYCLES <<
2492 ESR_GLUE_CTRL0_BLTIME_SHIFT));
2493
2494 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
2495 if (err)
2496 return err;
2497 err = esr_write_glue0(np, i, glue0);
2498 if (err)
2499 return err;
2500 }
2501
2502
2503 sig = nr64(ESR_INT_SIGNALS);
2504 switch (np->port) {
2505 case 0:
2506 mask = ESR_INT_SIGNALS_P0_BITS;
2507 val = (ESR_INT_SRDY0_P0 |
2508 ESR_INT_DET0_P0 |
2509 ESR_INT_XSRDY_P0 |
2510 ESR_INT_XDP_P0_CH3 |
2511 ESR_INT_XDP_P0_CH2 |
2512 ESR_INT_XDP_P0_CH1 |
2513 ESR_INT_XDP_P0_CH0);
2514 break;
2515
2516 case 1:
2517 mask = ESR_INT_SIGNALS_P1_BITS;
2518 val = (ESR_INT_SRDY0_P1 |
2519 ESR_INT_DET0_P1 |
2520 ESR_INT_XSRDY_P1 |
2521 ESR_INT_XDP_P1_CH3 |
2522 ESR_INT_XDP_P1_CH2 |
2523 ESR_INT_XDP_P1_CH1 |
2524 ESR_INT_XDP_P1_CH0);
2525 break;
2526
2527 default:
2528 return -EINVAL;
2529 }
2530
2531 if ((sig & mask) != val) {
2532 int err;
2533 err = serdes_init_1g_serdes(np);
2534 if (!err) {
2535 np->flags &= ~NIU_FLAGS_10G;
2536 np->mac_xcvr = MAC_XCVR_PCS;
2537 } else {
2538 dev_err(np->device, PFX "Port %u 10G/1G SERDES Link Failed \n",
2539 np->port);
2540 return -ENODEV;
2541 }
2542 }
2543
2544 return 0;
2545 }
2546
2547 static int niu_determine_phy_disposition(struct niu *np)
2548 {
2549 struct niu_parent *parent = np->parent;
2550 u8 plat_type = parent->plat_type;
2551 const struct niu_phy_template *tp;
2552 u32 phy_addr_off = 0;
2553
2554 if (plat_type == PLAT_TYPE_NIU) {
2555 switch (np->flags &
2556 (NIU_FLAGS_10G |
2557 NIU_FLAGS_FIBER |
2558 NIU_FLAGS_XCVR_SERDES)) {
2559 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2560 /* 10G Serdes */
2561 tp = &phy_template_niu_10g_serdes;
2562 break;
2563 case NIU_FLAGS_XCVR_SERDES:
2564 /* 1G Serdes */
2565 tp = &phy_template_niu_1g_serdes;
2566 break;
2567 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2568 /* 10G Fiber */
2569 default:
2570 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2571 tp = &phy_template_niu_10g_hotplug;
2572 if (np->port == 0)
2573 phy_addr_off = 8;
2574 if (np->port == 1)
2575 phy_addr_off = 12;
2576 } else {
2577 tp = &phy_template_niu_10g_fiber;
2578 phy_addr_off += np->port;
2579 }
2580 break;
2581 }
2582 } else {
2583 switch (np->flags &
2584 (NIU_FLAGS_10G |
2585 NIU_FLAGS_FIBER |
2586 NIU_FLAGS_XCVR_SERDES)) {
2587 case 0:
2588 /* 1G copper */
2589 tp = &phy_template_1g_copper;
2590 if (plat_type == PLAT_TYPE_VF_P0)
2591 phy_addr_off = 10;
2592 else if (plat_type == PLAT_TYPE_VF_P1)
2593 phy_addr_off = 26;
2594
2595 phy_addr_off += (np->port ^ 0x3);
2596 break;
2597
2598 case NIU_FLAGS_10G:
2599 /* 10G copper */
2600 tp = &phy_template_10g_copper;
2601 break;
2602
2603 case NIU_FLAGS_FIBER:
2604 /* 1G fiber */
2605 tp = &phy_template_1g_fiber;
2606 break;
2607
2608 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2609 /* 10G fiber */
2610 tp = &phy_template_10g_fiber;
2611 if (plat_type == PLAT_TYPE_VF_P0 ||
2612 plat_type == PLAT_TYPE_VF_P1)
2613 phy_addr_off = 8;
2614 phy_addr_off += np->port;
2615 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2616 tp = &phy_template_10g_fiber_hotplug;
2617 if (np->port == 0)
2618 phy_addr_off = 8;
2619 if (np->port == 1)
2620 phy_addr_off = 12;
2621 }
2622 break;
2623
2624 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2625 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
2626 case NIU_FLAGS_XCVR_SERDES:
2627 switch(np->port) {
2628 case 0:
2629 case 1:
2630 tp = &phy_template_10g_serdes;
2631 break;
2632 case 2:
2633 case 3:
2634 tp = &phy_template_1g_rgmii;
2635 break;
2636 default:
2637 return -EINVAL;
2638 break;
2639 }
2640 phy_addr_off = niu_atca_port_num[np->port];
2641 break;
2642
2643 default:
2644 return -EINVAL;
2645 }
2646 }
2647
2648 np->phy_ops = tp->ops;
2649 np->phy_addr = tp->phy_addr_base + phy_addr_off;
2650
2651 return 0;
2652 }
2653
2654 static int niu_init_link(struct niu *np)
2655 {
2656 struct niu_parent *parent = np->parent;
2657 int err, ignore;
2658
2659 if (parent->plat_type == PLAT_TYPE_NIU) {
2660 err = niu_xcvr_init(np);
2661 if (err)
2662 return err;
2663 msleep(200);
2664 }
2665 err = niu_serdes_init(np);
2666 if (err && !(np->flags & NIU_FLAGS_HOTPLUG_PHY))
2667 return err;
2668 msleep(200);
2669 err = niu_xcvr_init(np);
2670 if (!err || (np->flags & NIU_FLAGS_HOTPLUG_PHY))
2671 niu_link_status(np, &ignore);
2672 return 0;
2673 }
2674
2675 static void niu_set_primary_mac(struct niu *np, unsigned char *addr)
2676 {
2677 u16 reg0 = addr[4] << 8 | addr[5];
2678 u16 reg1 = addr[2] << 8 | addr[3];
2679 u16 reg2 = addr[0] << 8 | addr[1];
2680
2681 if (np->flags & NIU_FLAGS_XMAC) {
2682 nw64_mac(XMAC_ADDR0, reg0);
2683 nw64_mac(XMAC_ADDR1, reg1);
2684 nw64_mac(XMAC_ADDR2, reg2);
2685 } else {
2686 nw64_mac(BMAC_ADDR0, reg0);
2687 nw64_mac(BMAC_ADDR1, reg1);
2688 nw64_mac(BMAC_ADDR2, reg2);
2689 }
2690 }
2691
2692 static int niu_num_alt_addr(struct niu *np)
2693 {
2694 if (np->flags & NIU_FLAGS_XMAC)
2695 return XMAC_NUM_ALT_ADDR;
2696 else
2697 return BMAC_NUM_ALT_ADDR;
2698 }
2699
2700 static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr)
2701 {
2702 u16 reg0 = addr[4] << 8 | addr[5];
2703 u16 reg1 = addr[2] << 8 | addr[3];
2704 u16 reg2 = addr[0] << 8 | addr[1];
2705
2706 if (index >= niu_num_alt_addr(np))
2707 return -EINVAL;
2708
2709 if (np->flags & NIU_FLAGS_XMAC) {
2710 nw64_mac(XMAC_ALT_ADDR0(index), reg0);
2711 nw64_mac(XMAC_ALT_ADDR1(index), reg1);
2712 nw64_mac(XMAC_ALT_ADDR2(index), reg2);
2713 } else {
2714 nw64_mac(BMAC_ALT_ADDR0(index), reg0);
2715 nw64_mac(BMAC_ALT_ADDR1(index), reg1);
2716 nw64_mac(BMAC_ALT_ADDR2(index), reg2);
2717 }
2718
2719 return 0;
2720 }
2721
2722 static int niu_enable_alt_mac(struct niu *np, int index, int on)
2723 {
2724 unsigned long reg;
2725 u64 val, mask;
2726
2727 if (index >= niu_num_alt_addr(np))
2728 return -EINVAL;
2729
2730 if (np->flags & NIU_FLAGS_XMAC) {
2731 reg = XMAC_ADDR_CMPEN;
2732 mask = 1 << index;
2733 } else {
2734 reg = BMAC_ADDR_CMPEN;
2735 mask = 1 << (index + 1);
2736 }
2737
2738 val = nr64_mac(reg);
2739 if (on)
2740 val |= mask;
2741 else
2742 val &= ~mask;
2743 nw64_mac(reg, val);
2744
2745 return 0;
2746 }
2747
2748 static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg,
2749 int num, int mac_pref)
2750 {
2751 u64 val = nr64_mac(reg);
2752 val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
2753 val |= num;
2754 if (mac_pref)
2755 val |= HOST_INFO_MPR;
2756 nw64_mac(reg, val);
2757 }
2758
2759 static int __set_rdc_table_num(struct niu *np,
2760 int xmac_index, int bmac_index,
2761 int rdc_table_num, int mac_pref)
2762 {
2763 unsigned long reg;
2764
2765 if (rdc_table_num & ~HOST_INFO_MACRDCTBLN)
2766 return -EINVAL;
2767 if (np->flags & NIU_FLAGS_XMAC)
2768 reg = XMAC_HOST_INFO(xmac_index);
2769 else
2770 reg = BMAC_HOST_INFO(bmac_index);
2771 __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref);
2772 return 0;
2773 }
2774
2775 static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num,
2776 int mac_pref)
2777 {
2778 return __set_rdc_table_num(np, 17, 0, table_num, mac_pref);
2779 }
2780
2781 static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num,
2782 int mac_pref)
2783 {
2784 return __set_rdc_table_num(np, 16, 8, table_num, mac_pref);
2785 }
2786
2787 static int niu_set_alt_mac_rdc_table(struct niu *np, int idx,
2788 int table_num, int mac_pref)
2789 {
2790 if (idx >= niu_num_alt_addr(np))
2791 return -EINVAL;
2792 return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref);
2793 }
2794
2795 static u64 vlan_entry_set_parity(u64 reg_val)
2796 {
2797 u64 port01_mask;
2798 u64 port23_mask;
2799
2800 port01_mask = 0x00ff;
2801 port23_mask = 0xff00;
2802
2803 if (hweight64(reg_val & port01_mask) & 1)
2804 reg_val |= ENET_VLAN_TBL_PARITY0;
2805 else
2806 reg_val &= ~ENET_VLAN_TBL_PARITY0;
2807
2808 if (hweight64(reg_val & port23_mask) & 1)
2809 reg_val |= ENET_VLAN_TBL_PARITY1;
2810 else
2811 reg_val &= ~ENET_VLAN_TBL_PARITY1;
2812
2813 return reg_val;
2814 }
2815
2816 static void vlan_tbl_write(struct niu *np, unsigned long index,
2817 int port, int vpr, int rdc_table)
2818 {
2819 u64 reg_val = nr64(ENET_VLAN_TBL(index));
2820
2821 reg_val &= ~((ENET_VLAN_TBL_VPR |
2822 ENET_VLAN_TBL_VLANRDCTBLN) <<
2823 ENET_VLAN_TBL_SHIFT(port));
2824 if (vpr)
2825 reg_val |= (ENET_VLAN_TBL_VPR <<
2826 ENET_VLAN_TBL_SHIFT(port));
2827 reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
2828
2829 reg_val = vlan_entry_set_parity(reg_val);
2830
2831 nw64(ENET_VLAN_TBL(index), reg_val);
2832 }
2833
2834 static void vlan_tbl_clear(struct niu *np)
2835 {
2836 int i;
2837
2838 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++)
2839 nw64(ENET_VLAN_TBL(i), 0);
2840 }
2841
2842 static int tcam_wait_bit(struct niu *np, u64 bit)
2843 {
2844 int limit = 1000;
2845
2846 while (--limit > 0) {
2847 if (nr64(TCAM_CTL) & bit)
2848 break;
2849 udelay(1);
2850 }
2851 if (limit < 0)
2852 return -ENODEV;
2853
2854 return 0;
2855 }
2856
2857 static int tcam_flush(struct niu *np, int index)
2858 {
2859 nw64(TCAM_KEY_0, 0x00);
2860 nw64(TCAM_KEY_MASK_0, 0xff);
2861 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2862
2863 return tcam_wait_bit(np, TCAM_CTL_STAT);
2864 }
2865
2866 #if 0
2867 static int tcam_read(struct niu *np, int index,
2868 u64 *key, u64 *mask)
2869 {
2870 int err;
2871
2872 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
2873 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2874 if (!err) {
2875 key[0] = nr64(TCAM_KEY_0);
2876 key[1] = nr64(TCAM_KEY_1);
2877 key[2] = nr64(TCAM_KEY_2);
2878 key[3] = nr64(TCAM_KEY_3);
2879 mask[0] = nr64(TCAM_KEY_MASK_0);
2880 mask[1] = nr64(TCAM_KEY_MASK_1);
2881 mask[2] = nr64(TCAM_KEY_MASK_2);
2882 mask[3] = nr64(TCAM_KEY_MASK_3);
2883 }
2884 return err;
2885 }
2886 #endif
2887
2888 static int tcam_write(struct niu *np, int index,
2889 u64 *key, u64 *mask)
2890 {
2891 nw64(TCAM_KEY_0, key[0]);
2892 nw64(TCAM_KEY_1, key[1]);
2893 nw64(TCAM_KEY_2, key[2]);
2894 nw64(TCAM_KEY_3, key[3]);
2895 nw64(TCAM_KEY_MASK_0, mask[0]);
2896 nw64(TCAM_KEY_MASK_1, mask[1]);
2897 nw64(TCAM_KEY_MASK_2, mask[2]);
2898 nw64(TCAM_KEY_MASK_3, mask[3]);
2899 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2900
2901 return tcam_wait_bit(np, TCAM_CTL_STAT);
2902 }
2903
2904 #if 0
2905 static int tcam_assoc_read(struct niu *np, int index, u64 *data)
2906 {
2907 int err;
2908
2909 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
2910 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2911 if (!err)
2912 *data = nr64(TCAM_KEY_1);
2913
2914 return err;
2915 }
2916 #endif
2917
2918 static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data)
2919 {
2920 nw64(TCAM_KEY_1, assoc_data);
2921 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
2922
2923 return tcam_wait_bit(np, TCAM_CTL_STAT);
2924 }
2925
2926 static void tcam_enable(struct niu *np, int on)
2927 {
2928 u64 val = nr64(FFLP_CFG_1);
2929
2930 if (on)
2931 val &= ~FFLP_CFG_1_TCAM_DIS;
2932 else
2933 val |= FFLP_CFG_1_TCAM_DIS;
2934 nw64(FFLP_CFG_1, val);
2935 }
2936
2937 static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio)
2938 {
2939 u64 val = nr64(FFLP_CFG_1);
2940
2941 val &= ~(FFLP_CFG_1_FFLPINITDONE |
2942 FFLP_CFG_1_CAMLAT |
2943 FFLP_CFG_1_CAMRATIO);
2944 val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
2945 val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
2946 nw64(FFLP_CFG_1, val);
2947
2948 val = nr64(FFLP_CFG_1);
2949 val |= FFLP_CFG_1_FFLPINITDONE;
2950 nw64(FFLP_CFG_1, val);
2951 }
2952
2953 static int tcam_user_eth_class_enable(struct niu *np, unsigned long class,
2954 int on)
2955 {
2956 unsigned long reg;
2957 u64 val;
2958
2959 if (class < CLASS_CODE_ETHERTYPE1 ||
2960 class > CLASS_CODE_ETHERTYPE2)
2961 return -EINVAL;
2962
2963 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2964 val = nr64(reg);
2965 if (on)
2966 val |= L2_CLS_VLD;
2967 else
2968 val &= ~L2_CLS_VLD;
2969 nw64(reg, val);
2970
2971 return 0;
2972 }
2973
2974 #if 0
2975 static int tcam_user_eth_class_set(struct niu *np, unsigned long class,
2976 u64 ether_type)
2977 {
2978 unsigned long reg;
2979 u64 val;
2980
2981 if (class < CLASS_CODE_ETHERTYPE1 ||
2982 class > CLASS_CODE_ETHERTYPE2 ||
2983 (ether_type & ~(u64)0xffff) != 0)
2984 return -EINVAL;
2985
2986 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2987 val = nr64(reg);
2988 val &= ~L2_CLS_ETYPE;
2989 val |= (ether_type << L2_CLS_ETYPE_SHIFT);
2990 nw64(reg, val);
2991
2992 return 0;
2993 }
2994 #endif
2995
2996 static int tcam_user_ip_class_enable(struct niu *np, unsigned long class,
2997 int on)
2998 {
2999 unsigned long reg;
3000 u64 val;
3001
3002 if (class < CLASS_CODE_USER_PROG1 ||
3003 class > CLASS_CODE_USER_PROG4)
3004 return -EINVAL;
3005
3006 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
3007 val = nr64(reg);
3008 if (on)
3009 val |= L3_CLS_VALID;
3010 else
3011 val &= ~L3_CLS_VALID;
3012 nw64(reg, val);
3013
3014 return 0;
3015 }
3016
3017 static int tcam_user_ip_class_set(struct niu *np, unsigned long class,
3018 int ipv6, u64 protocol_id,
3019 u64 tos_mask, u64 tos_val)
3020 {
3021 unsigned long reg;
3022 u64 val;
3023
3024 if (class < CLASS_CODE_USER_PROG1 ||
3025 class > CLASS_CODE_USER_PROG4 ||
3026 (protocol_id & ~(u64)0xff) != 0 ||
3027 (tos_mask & ~(u64)0xff) != 0 ||
3028 (tos_val & ~(u64)0xff) != 0)
3029 return -EINVAL;
3030
3031 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
3032 val = nr64(reg);
3033 val &= ~(L3_CLS_IPVER | L3_CLS_PID |
3034 L3_CLS_TOSMASK | L3_CLS_TOS);
3035 if (ipv6)
3036 val |= L3_CLS_IPVER;
3037 val |= (protocol_id << L3_CLS_PID_SHIFT);
3038 val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
3039 val |= (tos_val << L3_CLS_TOS_SHIFT);
3040 nw64(reg, val);
3041
3042 return 0;
3043 }
3044
3045 static int tcam_early_init(struct niu *np)
3046 {
3047 unsigned long i;
3048 int err;
3049
3050 tcam_enable(np, 0);
3051 tcam_set_lat_and_ratio(np,
3052 DEFAULT_TCAM_LATENCY,
3053 DEFAULT_TCAM_ACCESS_RATIO);
3054 for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) {
3055 err = tcam_user_eth_class_enable(np, i, 0);
3056 if (err)
3057 return err;
3058 }
3059 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) {
3060 err = tcam_user_ip_class_enable(np, i, 0);
3061 if (err)
3062 return err;
3063 }
3064
3065 return 0;
3066 }
3067
3068 static int tcam_flush_all(struct niu *np)
3069 {
3070 unsigned long i;
3071
3072 for (i = 0; i < np->parent->tcam_num_entries; i++) {
3073 int err = tcam_flush(np, i);
3074 if (err)
3075 return err;
3076 }
3077 return 0;
3078 }
3079
3080 static u64 hash_addr_regval(unsigned long index, unsigned long num_entries)
3081 {
3082 return ((u64)index | (num_entries == 1 ?
3083 HASH_TBL_ADDR_AUTOINC : 0));
3084 }
3085
3086 #if 0
3087 static int hash_read(struct niu *np, unsigned long partition,
3088 unsigned long index, unsigned long num_entries,
3089 u64 *data)
3090 {
3091 u64 val = hash_addr_regval(index, num_entries);
3092 unsigned long i;
3093
3094 if (partition >= FCRAM_NUM_PARTITIONS ||
3095 index + num_entries > FCRAM_SIZE)
3096 return -EINVAL;
3097
3098 nw64(HASH_TBL_ADDR(partition), val);
3099 for (i = 0; i < num_entries; i++)
3100 data[i] = nr64(HASH_TBL_DATA(partition));
3101
3102 return 0;
3103 }
3104 #endif
3105
3106 static int hash_write(struct niu *np, unsigned long partition,
3107 unsigned long index, unsigned long num_entries,
3108 u64 *data)
3109 {
3110 u64 val = hash_addr_regval(index, num_entries);
3111 unsigned long i;
3112
3113 if (partition >= FCRAM_NUM_PARTITIONS ||
3114 index + (num_entries * 8) > FCRAM_SIZE)
3115 return -EINVAL;
3116
3117 nw64(HASH_TBL_ADDR(partition), val);
3118 for (i = 0; i < num_entries; i++)
3119 nw64(HASH_TBL_DATA(partition), data[i]);
3120
3121 return 0;
3122 }
3123
3124 static void fflp_reset(struct niu *np)
3125 {
3126 u64 val;
3127
3128 nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
3129 udelay(10);
3130 nw64(FFLP_CFG_1, 0);
3131
3132 val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
3133 nw64(FFLP_CFG_1, val);
3134 }
3135
3136 static void fflp_set_timings(struct niu *np)
3137 {
3138 u64 val = nr64(FFLP_CFG_1);
3139
3140 val &= ~FFLP_CFG_1_FFLPINITDONE;
3141 val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
3142 nw64(FFLP_CFG_1, val);
3143
3144 val = nr64(FFLP_CFG_1);
3145 val |= FFLP_CFG_1_FFLPINITDONE;
3146 nw64(FFLP_CFG_1, val);
3147
3148 val = nr64(FCRAM_REF_TMR);
3149 val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
3150 val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
3151 val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
3152 nw64(FCRAM_REF_TMR, val);
3153 }
3154
3155 static int fflp_set_partition(struct niu *np, u64 partition,
3156 u64 mask, u64 base, int enable)
3157 {
3158 unsigned long reg;
3159 u64 val;
3160
3161 if (partition >= FCRAM_NUM_PARTITIONS ||
3162 (mask & ~(u64)0x1f) != 0 ||
3163 (base & ~(u64)0x1f) != 0)
3164 return -EINVAL;
3165
3166 reg = FLW_PRT_SEL(partition);
3167
3168 val = nr64(reg);
3169 val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
3170 val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
3171 val |= (base << FLW_PRT_SEL_BASE_SHIFT);
3172 if (enable)
3173 val |= FLW_PRT_SEL_EXT;
3174 nw64(reg, val);
3175
3176 return 0;
3177 }
3178
3179 static int fflp_disable_all_partitions(struct niu *np)
3180 {
3181 unsigned long i;
3182
3183 for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) {
3184 int err = fflp_set_partition(np, 0, 0, 0, 0);
3185 if (err)
3186 return err;
3187 }
3188 return 0;
3189 }
3190
3191 static void fflp_llcsnap_enable(struct niu *np, int on)
3192 {
3193 u64 val = nr64(FFLP_CFG_1);
3194
3195 if (on)
3196 val |= FFLP_CFG_1_LLCSNAP;
3197 else
3198 val &= ~FFLP_CFG_1_LLCSNAP;
3199 nw64(FFLP_CFG_1, val);
3200 }
3201
3202 static void fflp_errors_enable(struct niu *np, int on)
3203 {
3204 u64 val = nr64(FFLP_CFG_1);
3205
3206 if (on)
3207 val &= ~FFLP_CFG_1_ERRORDIS;
3208 else
3209 val |= FFLP_CFG_1_ERRORDIS;
3210 nw64(FFLP_CFG_1, val);
3211 }
3212
3213 static int fflp_hash_clear(struct niu *np)
3214 {
3215 struct fcram_hash_ipv4 ent;
3216 unsigned long i;
3217
3218 /* IPV4 hash entry with valid bit clear, rest is don't care. */
3219 memset(&ent, 0, sizeof(ent));
3220 ent.header = HASH_HEADER_EXT;
3221
3222 for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) {
3223 int err = hash_write(np, 0, i, 1, (u64 *) &ent);
3224 if (err)
3225 return err;
3226 }
3227 return 0;
3228 }
3229
3230 static int fflp_early_init(struct niu *np)
3231 {
3232 struct niu_parent *parent;
3233 unsigned long flags;
3234 int err;
3235
3236 niu_lock_parent(np, flags);
3237
3238 parent = np->parent;
3239 err = 0;
3240 if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) {
3241 niudbg(PROBE, "fflp_early_init: Initting hw on port %u\n",
3242 np->port);
3243 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3244 fflp_reset(np);
3245 fflp_set_timings(np);
3246 err = fflp_disable_all_partitions(np);
3247 if (err) {
3248 niudbg(PROBE, "fflp_disable_all_partitions "
3249 "failed, err=%d\n", err);
3250 goto out;
3251 }
3252 }
3253
3254 err = tcam_early_init(np);
3255 if (err) {
3256 niudbg(PROBE, "tcam_early_init failed, err=%d\n",
3257 err);
3258 goto out;
3259 }
3260 fflp_llcsnap_enable(np, 1);
3261 fflp_errors_enable(np, 0);
3262 nw64(H1POLY, 0);
3263 nw64(H2POLY, 0);
3264
3265 err = tcam_flush_all(np);
3266 if (err) {
3267 niudbg(PROBE, "tcam_flush_all failed, err=%d\n",
3268 err);
3269 goto out;
3270 }
3271 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3272 err = fflp_hash_clear(np);
3273 if (err) {
3274 niudbg(PROBE, "fflp_hash_clear failed, "
3275 "err=%d\n", err);
3276 goto out;
3277 }
3278 }
3279
3280 vlan_tbl_clear(np);
3281
3282 niudbg(PROBE, "fflp_early_init: Success\n");
3283 parent->flags |= PARENT_FLGS_CLS_HWINIT;
3284 }
3285 out:
3286 niu_unlock_parent(np, flags);
3287 return err;
3288 }
3289
3290 static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key)
3291 {
3292 if (class_code < CLASS_CODE_USER_PROG1 ||
3293 class_code > CLASS_CODE_SCTP_IPV6)
3294 return -EINVAL;
3295
3296 nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3297 return 0;
3298 }
3299
3300 static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key)
3301 {
3302 if (class_code < CLASS_CODE_USER_PROG1 ||
3303 class_code > CLASS_CODE_SCTP_IPV6)
3304 return -EINVAL;
3305
3306 nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3307 return 0;
3308 }
3309
3310 /* Entries for the ports are interleaved in the TCAM */
3311 static u16 tcam_get_index(struct niu *np, u16 idx)
3312 {
3313 /* One entry reserved for IP fragment rule */
3314 if (idx >= (np->clas.tcam_sz - 1))
3315 idx = 0;
3316 return (np->clas.tcam_top + ((idx+1) * np->parent->num_ports));
3317 }
3318
3319 static u16 tcam_get_size(struct niu *np)
3320 {
3321 /* One entry reserved for IP fragment rule */
3322 return np->clas.tcam_sz - 1;
3323 }
3324
3325 static u16 tcam_get_valid_entry_cnt(struct niu *np)
3326 {
3327 /* One entry reserved for IP fragment rule */
3328 return np->clas.tcam_valid_entries - 1;
3329 }
3330
3331 static void niu_rx_skb_append(struct sk_buff *skb, struct page *page,
3332 u32 offset, u32 size)
3333 {
3334 int i = skb_shinfo(skb)->nr_frags;
3335 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3336
3337 frag->page = page;
3338 frag->page_offset = offset;
3339 frag->size = size;
3340
3341 skb->len += size;
3342 skb->data_len += size;
3343 skb->truesize += size;
3344
3345 skb_shinfo(skb)->nr_frags = i + 1;
3346 }
3347
3348 static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a)
3349 {
3350 a >>= PAGE_SHIFT;
3351 a ^= (a >> ilog2(MAX_RBR_RING_SIZE));
3352
3353 return (a & (MAX_RBR_RING_SIZE - 1));
3354 }
3355
3356 static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr,
3357 struct page ***link)
3358 {
3359 unsigned int h = niu_hash_rxaddr(rp, addr);
3360 struct page *p, **pp;
3361
3362 addr &= PAGE_MASK;
3363 pp = &rp->rxhash[h];
3364 for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) {
3365 if (p->index == addr) {
3366 *link = pp;
3367 break;
3368 }
3369 }
3370
3371 return p;
3372 }
3373
3374 static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base)
3375 {
3376 unsigned int h = niu_hash_rxaddr(rp, base);
3377
3378 page->index = base;
3379 page->mapping = (struct address_space *) rp->rxhash[h];
3380 rp->rxhash[h] = page;
3381 }
3382
3383 static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp,
3384 gfp_t mask, int start_index)
3385 {
3386 struct page *page;
3387 u64 addr;
3388 int i;
3389
3390 page = alloc_page(mask);
3391 if (!page)
3392 return -ENOMEM;
3393
3394 addr = np->ops->map_page(np->device, page, 0,
3395 PAGE_SIZE, DMA_FROM_DEVICE);
3396
3397 niu_hash_page(rp, page, addr);
3398 if (rp->rbr_blocks_per_page > 1)
3399 atomic_add(rp->rbr_blocks_per_page - 1,
3400 &compound_head(page)->_count);
3401
3402 for (i = 0; i < rp->rbr_blocks_per_page; i++) {
3403 __le32 *rbr = &rp->rbr[start_index + i];
3404
3405 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT);
3406 addr += rp->rbr_block_size;
3407 }
3408
3409 return 0;
3410 }
3411
3412 static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3413 {
3414 int index = rp->rbr_index;
3415
3416 rp->rbr_pending++;
3417 if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) {
3418 int err = niu_rbr_add_page(np, rp, mask, index);
3419
3420 if (unlikely(err)) {
3421 rp->rbr_pending--;
3422 return;
3423 }
3424
3425 rp->rbr_index += rp->rbr_blocks_per_page;
3426 BUG_ON(rp->rbr_index > rp->rbr_table_size);
3427 if (rp->rbr_index == rp->rbr_table_size)
3428 rp->rbr_index = 0;
3429
3430 if (rp->rbr_pending >= rp->rbr_kick_thresh) {
3431 nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
3432 rp->rbr_pending = 0;
3433 }
3434 }
3435 }
3436
3437 static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp)
3438 {
3439 unsigned int index = rp->rcr_index;
3440 int num_rcr = 0;
3441
3442 rp->rx_dropped++;
3443 while (1) {
3444 struct page *page, **link;
3445 u64 addr, val;
3446 u32 rcr_size;
3447
3448 num_rcr++;
3449
3450 val = le64_to_cpup(&rp->rcr[index]);
3451 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3452 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3453 page = niu_find_rxpage(rp, addr, &link);
3454
3455 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3456 RCR_ENTRY_PKTBUFSZ_SHIFT];
3457 if ((page->index + PAGE_SIZE) - rcr_size == addr) {
3458 *link = (struct page *) page->mapping;
3459 np->ops->unmap_page(np->device, page->index,
3460 PAGE_SIZE, DMA_FROM_DEVICE);
3461 page->index = 0;
3462 page->mapping = NULL;
3463 __free_page(page);
3464 rp->rbr_refill_pending++;
3465 }
3466
3467 index = NEXT_RCR(rp, index);
3468 if (!(val & RCR_ENTRY_MULTI))
3469 break;
3470
3471 }
3472 rp->rcr_index = index;
3473
3474 return num_rcr;
3475 }
3476
3477 static int niu_process_rx_pkt(struct napi_struct *napi, struct niu *np,
3478 struct rx_ring_info *rp)
3479 {
3480 unsigned int index = rp->rcr_index;
3481 struct sk_buff *skb;
3482 int len, num_rcr;
3483
3484 skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE);
3485 if (unlikely(!skb))
3486 return niu_rx_pkt_ignore(np, rp);
3487
3488 num_rcr = 0;
3489 while (1) {
3490 struct page *page, **link;
3491 u32 rcr_size, append_size;
3492 u64 addr, val, off;
3493
3494 num_rcr++;
3495
3496 val = le64_to_cpup(&rp->rcr[index]);
3497
3498 len = (val & RCR_ENTRY_L2_LEN) >>
3499 RCR_ENTRY_L2_LEN_SHIFT;
3500 len -= ETH_FCS_LEN;
3501
3502 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3503 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3504 page = niu_find_rxpage(rp, addr, &link);
3505
3506 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3507 RCR_ENTRY_PKTBUFSZ_SHIFT];
3508
3509 off = addr & ~PAGE_MASK;
3510 append_size = rcr_size;
3511 if (num_rcr == 1) {
3512 int ptype;
3513
3514 off += 2;
3515 append_size -= 2;
3516
3517 ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
3518 if ((ptype == RCR_PKT_TYPE_TCP ||
3519 ptype == RCR_PKT_TYPE_UDP) &&
3520 !(val & (RCR_ENTRY_NOPORT |
3521 RCR_ENTRY_ERROR)))
3522 skb->ip_summed = CHECKSUM_UNNECESSARY;
3523 else
3524 skb->ip_summed = CHECKSUM_NONE;
3525 }
3526 if (!(val & RCR_ENTRY_MULTI))
3527 append_size = len - skb->len;
3528
3529 niu_rx_skb_append(skb, page, off, append_size);
3530 if ((page->index + rp->rbr_block_size) - rcr_size == addr) {
3531 *link = (struct page *) page->mapping;
3532 np->ops->unmap_page(np->device, page->index,
3533 PAGE_SIZE, DMA_FROM_DEVICE);
3534 page->index = 0;
3535 page->mapping = NULL;
3536 rp->rbr_refill_pending++;
3537 } else
3538 get_page(page);
3539
3540 index = NEXT_RCR(rp, index);
3541 if (!(val & RCR_ENTRY_MULTI))
3542 break;
3543
3544 }
3545 rp->rcr_index = index;
3546
3547 skb_reserve(skb, NET_IP_ALIGN);
3548 __pskb_pull_tail(skb, min(len, NIU_RXPULL_MAX));
3549
3550 rp->rx_packets++;
3551 rp->rx_bytes += skb->len;
3552
3553 skb->protocol = eth_type_trans(skb, np->dev);
3554 skb_record_rx_queue(skb, rp->rx_channel);
3555 napi_gro_receive(napi, skb);
3556
3557 return num_rcr;
3558 }
3559
3560 static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3561 {
3562 int blocks_per_page = rp->rbr_blocks_per_page;
3563 int err, index = rp->rbr_index;
3564
3565 err = 0;
3566 while (index < (rp->rbr_table_size - blocks_per_page)) {
3567 err = niu_rbr_add_page(np, rp, mask, index);
3568 if (err)
3569 break;
3570
3571 index += blocks_per_page;
3572 }
3573
3574 rp->rbr_index = index;
3575 return err;
3576 }
3577
3578 static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp)
3579 {
3580 int i;
3581
3582 for (i = 0; i < MAX_RBR_RING_SIZE; i++) {
3583 struct page *page;
3584
3585 page = rp->rxhash[i];
3586 while (page) {
3587 struct page *next = (struct page *) page->mapping;
3588 u64 base = page->index;
3589
3590 np->ops->unmap_page(np->device, base, PAGE_SIZE,
3591 DMA_FROM_DEVICE);
3592 page->index = 0;
3593 page->mapping = NULL;
3594
3595 __free_page(page);
3596
3597 page = next;
3598 }
3599 }
3600
3601 for (i = 0; i < rp->rbr_table_size; i++)
3602 rp->rbr[i] = cpu_to_le32(0);
3603 rp->rbr_index = 0;
3604 }
3605
3606 static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx)
3607 {
3608 struct tx_buff_info *tb = &rp->tx_buffs[idx];
3609 struct sk_buff *skb = tb->skb;
3610 struct tx_pkt_hdr *tp;
3611 u64 tx_flags;
3612 int i, len;
3613
3614 tp = (struct tx_pkt_hdr *) skb->data;
3615 tx_flags = le64_to_cpup(&tp->flags);
3616
3617 rp->tx_packets++;
3618 rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) -
3619 ((tx_flags & TXHDR_PAD) / 2));
3620
3621 len = skb_headlen(skb);
3622 np->ops->unmap_single(np->device, tb->mapping,
3623 len, DMA_TO_DEVICE);
3624
3625 if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK)
3626 rp->mark_pending--;
3627
3628 tb->skb = NULL;
3629 do {
3630 idx = NEXT_TX(rp, idx);
3631 len -= MAX_TX_DESC_LEN;
3632 } while (len > 0);
3633
3634 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3635 tb = &rp->tx_buffs[idx];
3636 BUG_ON(tb->skb != NULL);
3637 np->ops->unmap_page(np->device, tb->mapping,
3638 skb_shinfo(skb)->frags[i].size,
3639 DMA_TO_DEVICE);
3640 idx = NEXT_TX(rp, idx);
3641 }
3642
3643 dev_kfree_skb(skb);
3644
3645 return idx;
3646 }
3647
3648 #define NIU_TX_WAKEUP_THRESH(rp) ((rp)->pending / 4)
3649
3650 static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
3651 {
3652 struct netdev_queue *txq;
3653 u16 pkt_cnt, tmp;
3654 int cons, index;
3655 u64 cs;
3656
3657 index = (rp - np->tx_rings);
3658 txq = netdev_get_tx_queue(np->dev, index);
3659
3660 cs = rp->tx_cs;
3661 if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK))))
3662 goto out;
3663
3664 tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT;
3665 pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) &
3666 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT);
3667
3668 rp->last_pkt_cnt = tmp;
3669
3670 cons = rp->cons;
3671
3672 niudbg(TX_DONE, "%s: niu_tx_work() pkt_cnt[%u] cons[%d]\n",
3673 np->dev->name, pkt_cnt, cons);
3674
3675 while (pkt_cnt--)
3676 cons = release_tx_packet(np, rp, cons);
3677
3678 rp->cons = cons;
3679 smp_mb();
3680
3681 out:
3682 if (unlikely(netif_tx_queue_stopped(txq) &&
3683 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) {
3684 __netif_tx_lock(txq, smp_processor_id());
3685 if (netif_tx_queue_stopped(txq) &&
3686 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))
3687 netif_tx_wake_queue(txq);
3688 __netif_tx_unlock(txq);
3689 }
3690 }
3691
3692 static inline void niu_sync_rx_discard_stats(struct niu *np,
3693 struct rx_ring_info *rp,
3694 const int limit)
3695 {
3696 /* This elaborate scheme is needed for reading the RX discard
3697 * counters, as they are only 16-bit and can overflow quickly,
3698 * and because the overflow indication bit is not usable as
3699 * the counter value does not wrap, but remains at max value
3700 * 0xFFFF.
3701 *
3702 * In theory and in practice counters can be lost in between
3703 * reading nr64() and clearing the counter nw64(). For this
3704 * reason, the number of counter clearings nw64() is
3705 * limited/reduced though the limit parameter.
3706 */
3707 int rx_channel = rp->rx_channel;
3708 u32 misc, wred;
3709
3710 /* RXMISC (Receive Miscellaneous Discard Count), covers the
3711 * following discard events: IPP (Input Port Process),
3712 * FFLP/TCAM, Full RCR (Receive Completion Ring) RBR (Receive
3713 * Block Ring) prefetch buffer is empty.
3714 */
3715 misc = nr64(RXMISC(rx_channel));
3716 if (unlikely((misc & RXMISC_COUNT) > limit)) {
3717 nw64(RXMISC(rx_channel), 0);
3718 rp->rx_errors += misc & RXMISC_COUNT;
3719
3720 if (unlikely(misc & RXMISC_OFLOW))
3721 dev_err(np->device, "rx-%d: Counter overflow "
3722 "RXMISC discard\n", rx_channel);
3723
3724 niudbg(RX_ERR, "%s-rx-%d: MISC drop=%u over=%u\n",
3725 np->dev->name, rx_channel, misc, misc-limit);
3726 }
3727
3728 /* WRED (Weighted Random Early Discard) by hardware */
3729 wred = nr64(RED_DIS_CNT(rx_channel));
3730 if (unlikely((wred & RED_DIS_CNT_COUNT) > limit)) {
3731 nw64(RED_DIS_CNT(rx_channel), 0);
3732 rp->rx_dropped += wred & RED_DIS_CNT_COUNT;
3733
3734 if (unlikely(wred & RED_DIS_CNT_OFLOW))
3735 dev_err(np->device, "rx-%d: Counter overflow "
3736 "WRED discard\n", rx_channel);
3737
3738 niudbg(RX_ERR, "%s-rx-%d: WRED drop=%u over=%u\n",
3739 np->dev->name, rx_channel, wred, wred-limit);
3740 }
3741 }
3742
3743 static int niu_rx_work(struct napi_struct *napi, struct niu *np,
3744 struct rx_ring_info *rp, int budget)
3745 {
3746 int qlen, rcr_done = 0, work_done = 0;
3747 struct rxdma_mailbox *mbox = rp->mbox;
3748 u64 stat;
3749
3750 #if 1
3751 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3752 qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
3753 #else
3754 stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
3755 qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN);
3756 #endif
3757 mbox->rx_dma_ctl_stat = 0;
3758 mbox->rcrstat_a = 0;
3759
3760 niudbg(RX_STATUS, "%s: niu_rx_work(chan[%d]), stat[%llx] qlen=%d\n",
3761 np->dev->name, rp->rx_channel, (unsigned long long) stat, qlen);
3762
3763 rcr_done = work_done = 0;
3764 qlen = min(qlen, budget);
3765 while (work_done < qlen) {
3766 rcr_done += niu_process_rx_pkt(napi, np, rp);
3767 work_done++;
3768 }
3769
3770 if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) {
3771 unsigned int i;
3772
3773 for (i = 0; i < rp->rbr_refill_pending; i++)
3774 niu_rbr_refill(np, rp, GFP_ATOMIC);
3775 rp->rbr_refill_pending = 0;
3776 }
3777
3778 stat = (RX_DMA_CTL_STAT_MEX |
3779 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) |
3780 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT));
3781
3782 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
3783
3784 /* Only sync discards stats when qlen indicate potential for drops */
3785 if (qlen > 10)
3786 niu_sync_rx_discard_stats(np, rp, 0x7FFF);
3787
3788 return work_done;
3789 }
3790
3791 static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget)
3792 {
3793 u64 v0 = lp->v0;
3794 u32 tx_vec = (v0 >> 32);
3795 u32 rx_vec = (v0 & 0xffffffff);
3796 int i, work_done = 0;
3797
3798 niudbg(INTR, "%s: niu_poll_core() v0[%016llx]\n",
3799 np->dev->name, (unsigned long long) v0);
3800
3801 for (i = 0; i < np->num_tx_rings; i++) {
3802 struct tx_ring_info *rp = &np->tx_rings[i];
3803 if (tx_vec & (1 << rp->tx_channel))
3804 niu_tx_work(np, rp);
3805 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
3806 }
3807
3808 for (i = 0; i < np->num_rx_rings; i++) {
3809 struct rx_ring_info *rp = &np->rx_rings[i];
3810
3811 if (rx_vec & (1 << rp->rx_channel)) {
3812 int this_work_done;
3813
3814 this_work_done = niu_rx_work(&lp->napi, np, rp,
3815 budget);
3816
3817 budget -= this_work_done;
3818 work_done += this_work_done;
3819 }
3820 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
3821 }
3822
3823 return work_done;
3824 }
3825
3826 static int niu_poll(struct napi_struct *napi, int budget)
3827 {
3828 struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi);
3829 struct niu *np = lp->np;
3830 int work_done;
3831
3832 work_done = niu_poll_core(np, lp, budget);
3833
3834 if (work_done < budget) {
3835 napi_complete(napi);
3836 niu_ldg_rearm(np, lp, 1);
3837 }
3838 return work_done;
3839 }
3840
3841 static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp,
3842 u64 stat)
3843 {
3844 dev_err(np->device, PFX "%s: RX channel %u errors ( ",
3845 np->dev->name, rp->rx_channel);
3846
3847 if (stat & RX_DMA_CTL_STAT_RBR_TMOUT)
3848 printk("RBR_TMOUT ");
3849 if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR)
3850 printk("RSP_CNT ");
3851 if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS)
3852 printk("BYTE_EN_BUS ");
3853 if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR)
3854 printk("RSP_DAT ");
3855 if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR)
3856 printk("RCR_ACK ");
3857 if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR)
3858 printk("RCR_SHA_PAR ");
3859 if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR)
3860 printk("RBR_PRE_PAR ");
3861 if (stat & RX_DMA_CTL_STAT_CONFIG_ERR)
3862 printk("CONFIG ");
3863 if (stat & RX_DMA_CTL_STAT_RCRINCON)
3864 printk("RCRINCON ");
3865 if (stat & RX_DMA_CTL_STAT_RCRFULL)
3866 printk("RCRFULL ");
3867 if (stat & RX_DMA_CTL_STAT_RBRFULL)
3868 printk("RBRFULL ");
3869 if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE)
3870 printk("RBRLOGPAGE ");
3871 if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE)
3872 printk("CFIGLOGPAGE ");
3873 if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR)
3874 printk("DC_FIDO ");
3875
3876 printk(")\n");
3877 }
3878
3879 static int niu_rx_error(struct niu *np, struct rx_ring_info *rp)
3880 {
3881 u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3882 int err = 0;
3883
3884
3885 if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL |
3886 RX_DMA_CTL_STAT_PORT_FATAL))
3887 err = -EINVAL;
3888
3889 if (err) {
3890 dev_err(np->device, PFX "%s: RX channel %u error, stat[%llx]\n",
3891 np->dev->name, rp->rx_channel,
3892 (unsigned long long) stat);
3893
3894 niu_log_rxchan_errors(np, rp, stat);
3895 }
3896
3897 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
3898 stat & RX_DMA_CTL_WRITE_CLEAR_ERRS);
3899
3900 return err;
3901 }
3902
3903 static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp,
3904 u64 cs)
3905 {
3906 dev_err(np->device, PFX "%s: TX channel %u errors ( ",
3907 np->dev->name, rp->tx_channel);
3908
3909 if (cs & TX_CS_MBOX_ERR)
3910 printk("MBOX ");
3911 if (cs & TX_CS_PKT_SIZE_ERR)
3912 printk("PKT_SIZE ");
3913 if (cs & TX_CS_TX_RING_OFLOW)
3914 printk("TX_RING_OFLOW ");
3915 if (cs & TX_CS_PREF_BUF_PAR_ERR)
3916 printk("PREF_BUF_PAR ");
3917 if (cs & TX_CS_NACK_PREF)
3918 printk("NACK_PREF ");
3919 if (cs & TX_CS_NACK_PKT_RD)
3920 printk("NACK_PKT_RD ");
3921 if (cs & TX_CS_CONF_PART_ERR)
3922 printk("CONF_PART ");
3923 if (cs & TX_CS_PKT_PRT_ERR)
3924 printk("PKT_PTR ");
3925
3926 printk(")\n");
3927 }
3928
3929 static int niu_tx_error(struct niu *np, struct tx_ring_info *rp)
3930 {
3931 u64 cs, logh, logl;
3932
3933 cs = nr64(TX_CS(rp->tx_channel));
3934 logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
3935 logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
3936
3937 dev_err(np->device, PFX "%s: TX channel %u error, "
3938 "cs[%llx] logh[%llx] logl[%llx]\n",
3939 np->dev->name, rp->tx_channel,
3940 (unsigned long long) cs,
3941 (unsigned long long) logh,
3942 (unsigned long long) logl);
3943
3944 niu_log_txchan_errors(np, rp, cs);
3945
3946 return -ENODEV;
3947 }
3948
3949 static int niu_mif_interrupt(struct niu *np)
3950 {
3951 u64 mif_status = nr64(MIF_STATUS);
3952 int phy_mdint = 0;
3953
3954 if (np->flags & NIU_FLAGS_XMAC) {
3955 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS);
3956
3957 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT)
3958 phy_mdint = 1;
3959 }
3960
3961 dev_err(np->device, PFX "%s: MIF interrupt, "
3962 "stat[%llx] phy_mdint(%d)\n",
3963 np->dev->name, (unsigned long long) mif_status, phy_mdint);
3964
3965 return -ENODEV;
3966 }
3967
3968 static void niu_xmac_interrupt(struct niu *np)
3969 {
3970 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
3971 u64 val;
3972
3973 val = nr64_mac(XTXMAC_STATUS);
3974 if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
3975 mp->tx_frames += TXMAC_FRM_CNT_COUNT;
3976 if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
3977 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT;
3978 if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
3979 mp->tx_fifo_errors++;
3980 if (val & XTXMAC_STATUS_TXMAC_OFLOW)
3981 mp->tx_overflow_errors++;
3982 if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
3983 mp->tx_max_pkt_size_errors++;
3984 if (val & XTXMAC_STATUS_TXMAC_UFLOW)
3985 mp->tx_underflow_errors++;
3986
3987 val = nr64_mac(XRXMAC_STATUS);
3988 if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
3989 mp->rx_local_faults++;
3990 if (val & XRXMAC_STATUS_RFLT_DET)
3991 mp->rx_remote_faults++;
3992 if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
3993 mp->rx_link_faults += LINK_FAULT_CNT_COUNT;
3994 if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
3995 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT;
3996 if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
3997 mp->rx_frags += RXMAC_FRAG_CNT_COUNT;
3998 if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
3999 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT;
4000 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
4001 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
4002 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
4003 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
4004 if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
4005 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT;
4006 if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
4007 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT;
4008 if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
4009 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT;
4010 if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
4011 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT;
4012 if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
4013 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT;
4014 if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
4015 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT;
4016 if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
4017 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT;
4018 if (val & XRXMAC_STAT_MSK_RXOCTET_CNT_EXP)
4019 mp->rx_octets += RXMAC_BT_CNT_COUNT;
4020 if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
4021 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT;
4022 if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
4023 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT;
4024 if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
4025 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT;
4026 if (val & XRXMAC_STATUS_RXUFLOW)
4027 mp->rx_underflows++;
4028 if (val & XRXMAC_STATUS_RXOFLOW)
4029 mp->rx_overflows++;
4030
4031 val = nr64_mac(XMAC_FC_STAT);
4032 if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
4033 mp->pause_off_state++;
4034 if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
4035 mp->pause_on_state++;
4036 if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
4037 mp->pause_received++;
4038 }
4039
4040 static void niu_bmac_interrupt(struct niu *np)
4041 {
4042 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
4043 u64 val;
4044
4045 val = nr64_mac(BTXMAC_STATUS);
4046 if (val & BTXMAC_STATUS_UNDERRUN)
4047 mp->tx_underflow_errors++;
4048 if (val & BTXMAC_STATUS_MAX_PKT_ERR)
4049 mp->tx_max_pkt_size_errors++;
4050 if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
4051 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT;
4052 if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
4053 mp->tx_frames += BTXMAC_FRM_CNT_COUNT;
4054
4055 val = nr64_mac(BRXMAC_STATUS);
4056 if (val & BRXMAC_STATUS_OVERFLOW)
4057 mp->rx_overflows++;
4058 if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
4059 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT;
4060 if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
4061 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4062 if (val & BRXMAC_STATUS_CRC_ERR_EXP)
4063 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4064 if (val & BRXMAC_STATUS_LEN_ERR_EXP)
4065 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT;
4066
4067 val = nr64_mac(BMAC_CTRL_STATUS);
4068 if (val & BMAC_CTRL_STATUS_NOPAUSE)
4069 mp->pause_off_state++;
4070 if (val & BMAC_CTRL_STATUS_PAUSE)
4071 mp->pause_on_state++;
4072 if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
4073 mp->pause_received++;
4074 }
4075
4076 static int niu_mac_interrupt(struct niu *np)
4077 {
4078 if (np->flags & NIU_FLAGS_XMAC)
4079 niu_xmac_interrupt(np);
4080 else
4081 niu_bmac_interrupt(np);
4082
4083 return 0;
4084 }
4085
4086 static void niu_log_device_error(struct niu *np, u64 stat)
4087 {
4088 dev_err(np->device, PFX "%s: Core device errors ( ",
4089 np->dev->name);
4090
4091 if (stat & SYS_ERR_MASK_META2)
4092 printk("META2 ");
4093 if (stat & SYS_ERR_MASK_META1)
4094 printk("META1 ");
4095 if (stat & SYS_ERR_MASK_PEU)
4096 printk("PEU ");
4097 if (stat & SYS_ERR_MASK_TXC)
4098 printk("TXC ");
4099 if (stat & SYS_ERR_MASK_RDMC)
4100 printk("RDMC ");
4101 if (stat & SYS_ERR_MASK_TDMC)
4102 printk("TDMC ");
4103 if (stat & SYS_ERR_MASK_ZCP)
4104 printk("ZCP ");
4105 if (stat & SYS_ERR_MASK_FFLP)
4106 printk("FFLP ");
4107 if (stat & SYS_ERR_MASK_IPP)
4108 printk("IPP ");
4109 if (stat & SYS_ERR_MASK_MAC)
4110 printk("MAC ");
4111 if (stat & SYS_ERR_MASK_SMX)
4112 printk("SMX ");
4113
4114 printk(")\n");
4115 }
4116
4117 static int niu_device_error(struct niu *np)
4118 {
4119 u64 stat = nr64(SYS_ERR_STAT);
4120
4121 dev_err(np->device, PFX "%s: Core device error, stat[%llx]\n",
4122 np->dev->name, (unsigned long long) stat);
4123
4124 niu_log_device_error(np, stat);
4125
4126 return -ENODEV;
4127 }
4128
4129 static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp,
4130 u64 v0, u64 v1, u64 v2)
4131 {
4132
4133 int i, err = 0;
4134
4135 lp->v0 = v0;
4136 lp->v1 = v1;
4137 lp->v2 = v2;
4138
4139 if (v1 & 0x00000000ffffffffULL) {
4140 u32 rx_vec = (v1 & 0xffffffff);
4141
4142 for (i = 0; i < np->num_rx_rings; i++) {
4143 struct rx_ring_info *rp = &np->rx_rings[i];
4144
4145 if (rx_vec & (1 << rp->rx_channel)) {
4146 int r = niu_rx_error(np, rp);
4147 if (r) {
4148 err = r;
4149 } else {
4150 if (!v0)
4151 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
4152 RX_DMA_CTL_STAT_MEX);
4153 }
4154 }
4155 }
4156 }
4157 if (v1 & 0x7fffffff00000000ULL) {
4158 u32 tx_vec = (v1 >> 32) & 0x7fffffff;
4159
4160 for (i = 0; i < np->num_tx_rings; i++) {
4161 struct tx_ring_info *rp = &np->tx_rings[i];
4162
4163 if (tx_vec & (1 << rp->tx_channel)) {
4164 int r = niu_tx_error(np, rp);
4165 if (r)
4166 err = r;
4167 }
4168 }
4169 }
4170 if ((v0 | v1) & 0x8000000000000000ULL) {
4171 int r = niu_mif_interrupt(np);
4172 if (r)
4173 err = r;
4174 }
4175 if (v2) {
4176 if (v2 & 0x01ef) {
4177 int r = niu_mac_interrupt(np);
4178 if (r)
4179 err = r;
4180 }
4181 if (v2 & 0x0210) {
4182 int r = niu_device_error(np);
4183 if (r)
4184 err = r;
4185 }
4186 }
4187
4188 if (err)
4189 niu_enable_interrupts(np, 0);
4190
4191 return err;
4192 }
4193
4194 static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp,
4195 int ldn)
4196 {
4197 struct rxdma_mailbox *mbox = rp->mbox;
4198 u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
4199
4200 stat_write = (RX_DMA_CTL_STAT_RCRTHRES |
4201 RX_DMA_CTL_STAT_RCRTO);
4202 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
4203
4204 niudbg(INTR, "%s: rxchan_intr stat[%llx]\n",
4205 np->dev->name, (unsigned long long) stat);
4206 }
4207
4208 static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp,
4209 int ldn)
4210 {
4211 rp->tx_cs = nr64(TX_CS(rp->tx_channel));
4212
4213 niudbg(INTR, "%s: txchan_intr cs[%llx]\n",
4214 np->dev->name, (unsigned long long) rp->tx_cs);
4215 }
4216
4217 static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)
4218 {
4219 struct niu_parent *parent = np->parent;
4220 u32 rx_vec, tx_vec;
4221 int i;
4222
4223 tx_vec = (v0 >> 32);
4224 rx_vec = (v0 & 0xffffffff);
4225
4226 for (i = 0; i < np->num_rx_rings; i++) {
4227 struct rx_ring_info *rp = &np->rx_rings[i];
4228 int ldn = LDN_RXDMA(rp->rx_channel);
4229
4230 if (parent->ldg_map[ldn] != ldg)
4231 continue;
4232
4233 nw64(LD_IM0(ldn), LD_IM0_MASK);
4234 if (rx_vec & (1 << rp->rx_channel))
4235 niu_rxchan_intr(np, rp, ldn);
4236 }
4237
4238 for (i = 0; i < np->num_tx_rings; i++) {
4239 struct tx_ring_info *rp = &np->tx_rings[i];
4240 int ldn = LDN_TXDMA(rp->tx_channel);
4241
4242 if (parent->ldg_map[ldn] != ldg)
4243 continue;
4244
4245 nw64(LD_IM0(ldn), LD_IM0_MASK);
4246 if (tx_vec & (1 << rp->tx_channel))
4247 niu_txchan_intr(np, rp, ldn);
4248 }
4249 }
4250
4251 static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp,
4252 u64 v0, u64 v1, u64 v2)
4253 {
4254 if (likely(napi_schedule_prep(&lp->napi))) {
4255 lp->v0 = v0;
4256 lp->v1 = v1;
4257 lp->v2 = v2;
4258 __niu_fastpath_interrupt(np, lp->ldg_num, v0);
4259 __napi_schedule(&lp->napi);
4260 }
4261 }
4262
4263 static irqreturn_t niu_interrupt(int irq, void *dev_id)
4264 {
4265 struct niu_ldg *lp = dev_id;
4266 struct niu *np = lp->np;
4267 int ldg = lp->ldg_num;
4268 unsigned long flags;
4269 u64 v0, v1, v2;
4270
4271 if (netif_msg_intr(np))
4272 printk(KERN_DEBUG PFX "niu_interrupt() ldg[%p](%d) ",
4273 lp, ldg);
4274
4275 spin_lock_irqsave(&np->lock, flags);
4276
4277 v0 = nr64(LDSV0(ldg));
4278 v1 = nr64(LDSV1(ldg));
4279 v2 = nr64(LDSV2(ldg));
4280
4281 if (netif_msg_intr(np))
4282 printk("v0[%llx] v1[%llx] v2[%llx]\n",
4283 (unsigned long long) v0,
4284 (unsigned long long) v1,
4285 (unsigned long long) v2);
4286
4287 if (unlikely(!v0 && !v1 && !v2)) {
4288 spin_unlock_irqrestore(&np->lock, flags);
4289 return IRQ_NONE;
4290 }
4291
4292 if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {
4293 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);
4294 if (err)
4295 goto out;
4296 }
4297 if (likely(v0 & ~((u64)1 << LDN_MIF)))
4298 niu_schedule_napi(np, lp, v0, v1, v2);
4299 else
4300 niu_ldg_rearm(np, lp, 1);
4301 out:
4302 spin_unlock_irqrestore(&np->lock, flags);
4303
4304 return IRQ_HANDLED;
4305 }
4306
4307 static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp)
4308 {
4309 if (rp->mbox) {
4310 np->ops->free_coherent(np->device,
4311 sizeof(struct rxdma_mailbox),
4312 rp->mbox, rp->mbox_dma);
4313 rp->mbox = NULL;
4314 }
4315 if (rp->rcr) {
4316 np->ops->free_coherent(np->device,
4317 MAX_RCR_RING_SIZE * sizeof(__le64),
4318 rp->rcr, rp->rcr_dma);
4319 rp->rcr = NULL;
4320 rp->rcr_table_size = 0;
4321 rp->rcr_index = 0;
4322 }
4323 if (rp->rbr) {
4324 niu_rbr_free(np, rp);
4325
4326 np->ops->free_coherent(np->device,
4327 MAX_RBR_RING_SIZE * sizeof(__le32),
4328 rp->rbr, rp->rbr_dma);
4329 rp->rbr = NULL;
4330 rp->rbr_table_size = 0;
4331 rp->rbr_index = 0;
4332 }
4333 kfree(rp->rxhash);
4334 rp->rxhash = NULL;
4335 }
4336
4337 static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp)
4338 {
4339 if (rp->mbox) {
4340 np->ops->free_coherent(np->device,
4341 sizeof(struct txdma_mailbox),
4342 rp->mbox, rp->mbox_dma);
4343 rp->mbox = NULL;
4344 }
4345 if (rp->descr) {
4346 int i;
4347
4348 for (i = 0; i < MAX_TX_RING_SIZE; i++) {
4349 if (rp->tx_buffs[i].skb)
4350 (void) release_tx_packet(np, rp, i);
4351 }
4352
4353 np->ops->free_coherent(np->device,
4354 MAX_TX_RING_SIZE * sizeof(__le64),
4355 rp->descr, rp->descr_dma);
4356 rp->descr = NULL;
4357 rp->pending = 0;
4358 rp->prod = 0;
4359 rp->cons = 0;
4360 rp->wrap_bit = 0;
4361 }
4362 }
4363
4364 static void niu_free_channels(struct niu *np)
4365 {
4366 int i;
4367
4368 if (np->rx_rings) {
4369 for (i = 0; i < np->num_rx_rings; i++) {
4370 struct rx_ring_info *rp = &np->rx_rings[i];
4371
4372 niu_free_rx_ring_info(np, rp);
4373 }
4374 kfree(np->rx_rings);
4375 np->rx_rings = NULL;
4376 np->num_rx_rings = 0;
4377 }
4378
4379 if (np->tx_rings) {
4380 for (i = 0; i < np->num_tx_rings; i++) {
4381 struct tx_ring_info *rp = &np->tx_rings[i];
4382
4383 niu_free_tx_ring_info(np, rp);
4384 }
4385 kfree(np->tx_rings);
4386 np->tx_rings = NULL;
4387 np->num_tx_rings = 0;
4388 }
4389 }
4390
4391 static int niu_alloc_rx_ring_info(struct niu *np,
4392 struct rx_ring_info *rp)
4393 {
4394 BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64);
4395
4396 rp->rxhash = kzalloc(MAX_RBR_RING_SIZE * sizeof(struct page *),
4397 GFP_KERNEL);
4398 if (!rp->rxhash)
4399 return -ENOMEM;
4400
4401 rp->mbox = np->ops->alloc_coherent(np->device,
4402 sizeof(struct rxdma_mailbox),
4403 &rp->mbox_dma, GFP_KERNEL);
4404 if (!rp->mbox)
4405 return -ENOMEM;
4406 if ((unsigned long)rp->mbox & (64UL - 1)) {
4407 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4408 "RXDMA mailbox %p\n", np->dev->name, rp->mbox);
4409 return -EINVAL;
4410 }
4411
4412 rp->rcr = np->ops->alloc_coherent(np->device,
4413 MAX_RCR_RING_SIZE * sizeof(__le64),
4414 &rp->rcr_dma, GFP_KERNEL);
4415 if (!rp->rcr)
4416 return -ENOMEM;
4417 if ((unsigned long)rp->rcr & (64UL - 1)) {
4418 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4419 "RXDMA RCR table %p\n", np->dev->name, rp->rcr);
4420 return -EINVAL;
4421 }
4422 rp->rcr_table_size = MAX_RCR_RING_SIZE;
4423 rp->rcr_index = 0;
4424
4425 rp->rbr = np->ops->alloc_coherent(np->device,
4426 MAX_RBR_RING_SIZE * sizeof(__le32),
4427 &rp->rbr_dma, GFP_KERNEL);
4428 if (!rp->rbr)
4429 return -ENOMEM;
4430 if ((unsigned long)rp->rbr & (64UL - 1)) {
4431 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4432 "RXDMA RBR table %p\n", np->dev->name, rp->rbr);
4433 return -EINVAL;
4434 }
4435 rp->rbr_table_size = MAX_RBR_RING_SIZE;
4436 rp->rbr_index = 0;
4437 rp->rbr_pending = 0;
4438
4439 return 0;
4440 }
4441
4442 static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp)
4443 {
4444 int mtu = np->dev->mtu;
4445
4446 /* These values are recommended by the HW designers for fair
4447 * utilization of DRR amongst the rings.
4448 */
4449 rp->max_burst = mtu + 32;
4450 if (rp->max_burst > 4096)
4451 rp->max_burst = 4096;
4452 }
4453
4454 static int niu_alloc_tx_ring_info(struct niu *np,
4455 struct tx_ring_info *rp)
4456 {
4457 BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64);
4458
4459 rp->mbox = np->ops->alloc_coherent(np->device,
4460 sizeof(struct txdma_mailbox),
4461 &rp->mbox_dma, GFP_KERNEL);
4462 if (!rp->mbox)
4463 return -ENOMEM;
4464 if ((unsigned long)rp->mbox & (64UL - 1)) {
4465 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4466 "TXDMA mailbox %p\n", np->dev->name, rp->mbox);
4467 return -EINVAL;
4468 }
4469
4470 rp->descr = np->ops->alloc_coherent(np->device,
4471 MAX_TX_RING_SIZE * sizeof(__le64),
4472 &rp->descr_dma, GFP_KERNEL);
4473 if (!rp->descr)
4474 return -ENOMEM;
4475 if ((unsigned long)rp->descr & (64UL - 1)) {
4476 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4477 "TXDMA descr table %p\n", np->dev->name, rp->descr);
4478 return -EINVAL;
4479 }
4480
4481 rp->pending = MAX_TX_RING_SIZE;
4482 rp->prod = 0;
4483 rp->cons = 0;
4484 rp->wrap_bit = 0;
4485
4486 /* XXX make these configurable... XXX */
4487 rp->mark_freq = rp->pending / 4;
4488
4489 niu_set_max_burst(np, rp);
4490
4491 return 0;
4492 }
4493
4494 static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp)
4495 {
4496 u16 bss;
4497
4498 bss = min(PAGE_SHIFT, 15);
4499
4500 rp->rbr_block_size = 1 << bss;
4501 rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss);
4502
4503 rp->rbr_sizes[0] = 256;
4504 rp->rbr_sizes[1] = 1024;
4505 if (np->dev->mtu > ETH_DATA_LEN) {
4506 switch (PAGE_SIZE) {
4507 case 4 * 1024:
4508 rp->rbr_sizes[2] = 4096;
4509 break;
4510
4511 default:
4512 rp->rbr_sizes[2] = 8192;
4513 break;
4514 }
4515 } else {
4516 rp->rbr_sizes[2] = 2048;
4517 }
4518 rp->rbr_sizes[3] = rp->rbr_block_size;
4519 }
4520
4521 static int niu_alloc_channels(struct niu *np)
4522 {
4523 struct niu_parent *parent = np->parent;
4524 int first_rx_channel, first_tx_channel;
4525 int i, port, err;
4526
4527 port = np->port;
4528 first_rx_channel = first_tx_channel = 0;
4529 for (i = 0; i < port; i++) {
4530 first_rx_channel += parent->rxchan_per_port[i];
4531 first_tx_channel += parent->txchan_per_port[i];
4532 }
4533
4534 np->num_rx_rings = parent->rxchan_per_port[port];
4535 np->num_tx_rings = parent->txchan_per_port[port];
4536
4537 np->dev->real_num_tx_queues = np->num_tx_rings;
4538
4539 np->rx_rings = kzalloc(np->num_rx_rings * sizeof(struct rx_ring_info),
4540 GFP_KERNEL);
4541 err = -ENOMEM;
4542 if (!np->rx_rings)
4543 goto out_err;
4544
4545 for (i = 0; i < np->num_rx_rings; i++) {
4546 struct rx_ring_info *rp = &np->rx_rings[i];
4547
4548 rp->np = np;
4549 rp->rx_channel = first_rx_channel + i;
4550
4551 err = niu_alloc_rx_ring_info(np, rp);
4552 if (err)
4553 goto out_err;
4554
4555 niu_size_rbr(np, rp);
4556
4557 /* XXX better defaults, configurable, etc... XXX */
4558 rp->nonsyn_window = 64;
4559 rp->nonsyn_threshold = rp->rcr_table_size - 64;
4560 rp->syn_window = 64;
4561 rp->syn_threshold = rp->rcr_table_size - 64;
4562 rp->rcr_pkt_threshold = 16;
4563 rp->rcr_timeout = 8;
4564 rp->rbr_kick_thresh = RBR_REFILL_MIN;
4565 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page)
4566 rp->rbr_kick_thresh = rp->rbr_blocks_per_page;
4567
4568 err = niu_rbr_fill(np, rp, GFP_KERNEL);
4569 if (err)
4570 return err;
4571 }
4572
4573 np->tx_rings = kzalloc(np->num_tx_rings * sizeof(struct tx_ring_info),
4574 GFP_KERNEL);
4575 err = -ENOMEM;
4576 if (!np->tx_rings)
4577 goto out_err;
4578
4579 for (i = 0; i < np->num_tx_rings; i++) {
4580 struct tx_ring_info *rp = &np->tx_rings[i];
4581
4582 rp->np = np;
4583 rp->tx_channel = first_tx_channel + i;
4584
4585 err = niu_alloc_tx_ring_info(np, rp);
4586 if (err)
4587 goto out_err;
4588 }
4589
4590 return 0;
4591
4592 out_err:
4593 niu_free_channels(np);
4594 return err;
4595 }
4596
4597 static int niu_tx_cs_sng_poll(struct niu *np, int channel)
4598 {
4599 int limit = 1000;
4600
4601 while (--limit > 0) {
4602 u64 val = nr64(TX_CS(channel));
4603 if (val & TX_CS_SNG_STATE)
4604 return 0;
4605 }
4606 return -ENODEV;
4607 }
4608
4609 static int niu_tx_channel_stop(struct niu *np, int channel)
4610 {
4611 u64 val = nr64(TX_CS(channel));
4612
4613 val |= TX_CS_STOP_N_GO;
4614 nw64(TX_CS(channel), val);
4615
4616 return niu_tx_cs_sng_poll(np, channel);
4617 }
4618
4619 static int niu_tx_cs_reset_poll(struct niu *np, int channel)
4620 {
4621 int limit = 1000;
4622
4623 while (--limit > 0) {
4624 u64 val = nr64(TX_CS(channel));
4625 if (!(val & TX_CS_RST))
4626 return 0;
4627 }
4628 return -ENODEV;
4629 }
4630
4631 static int niu_tx_channel_reset(struct niu *np, int channel)
4632 {
4633 u64 val = nr64(TX_CS(channel));
4634 int err;
4635
4636 val |= TX_CS_RST;
4637 nw64(TX_CS(channel), val);
4638
4639 err = niu_tx_cs_reset_poll(np, channel);
4640 if (!err)
4641 nw64(TX_RING_KICK(channel), 0);
4642
4643 return err;
4644 }
4645
4646 static int niu_tx_channel_lpage_init(struct niu *np, int channel)
4647 {
4648 u64 val;
4649
4650 nw64(TX_LOG_MASK1(channel), 0);
4651 nw64(TX_LOG_VAL1(channel), 0);
4652 nw64(TX_LOG_MASK2(channel), 0);
4653 nw64(TX_LOG_VAL2(channel), 0);
4654 nw64(TX_LOG_PAGE_RELO1(channel), 0);
4655 nw64(TX_LOG_PAGE_RELO2(channel), 0);
4656 nw64(TX_LOG_PAGE_HDL(channel), 0);
4657
4658 val = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
4659 val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
4660 nw64(TX_LOG_PAGE_VLD(channel), val);
4661
4662 /* XXX TXDMA 32bit mode? XXX */
4663
4664 return 0;
4665 }
4666
4667 static void niu_txc_enable_port(struct niu *np, int on)
4668 {
4669 unsigned long flags;
4670 u64 val, mask;
4671
4672 niu_lock_parent(np, flags);
4673 val = nr64(TXC_CONTROL);
4674 mask = (u64)1 << np->port;
4675 if (on) {
4676 val |= TXC_CONTROL_ENABLE | mask;
4677 } else {
4678 val &= ~mask;
4679 if ((val & ~TXC_CONTROL_ENABLE) == 0)
4680 val &= ~TXC_CONTROL_ENABLE;
4681 }
4682 nw64(TXC_CONTROL, val);
4683 niu_unlock_parent(np, flags);
4684 }
4685
4686 static void niu_txc_set_imask(struct niu *np, u64 imask)
4687 {
4688 unsigned long flags;
4689 u64 val;
4690
4691 niu_lock_parent(np, flags);
4692 val = nr64(TXC_INT_MASK);
4693 val &= ~TXC_INT_MASK_VAL(np->port);
4694 val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
4695 niu_unlock_parent(np, flags);
4696 }
4697
4698 static void niu_txc_port_dma_enable(struct niu *np, int on)
4699 {
4700 u64 val = 0;
4701
4702 if (on) {
4703 int i;
4704
4705 for (i = 0; i < np->num_tx_rings; i++)
4706 val |= (1 << np->tx_rings[i].tx_channel);
4707 }
4708 nw64(TXC_PORT_DMA(np->port), val);
4709 }
4710
4711 static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4712 {
4713 int err, channel = rp->tx_channel;
4714 u64 val, ring_len;
4715
4716 err = niu_tx_channel_stop(np, channel);
4717 if (err)
4718 return err;
4719
4720 err = niu_tx_channel_reset(np, channel);
4721 if (err)
4722 return err;
4723
4724 err = niu_tx_channel_lpage_init(np, channel);
4725 if (err)
4726 return err;
4727
4728 nw64(TXC_DMA_MAX(channel), rp->max_burst);
4729 nw64(TX_ENT_MSK(channel), 0);
4730
4731 if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE |
4732 TX_RNG_CFIG_STADDR)) {
4733 dev_err(np->device, PFX "%s: TX ring channel %d "
4734 "DMA addr (%llx) is not aligned.\n",
4735 np->dev->name, channel,
4736 (unsigned long long) rp->descr_dma);
4737 return -EINVAL;
4738 }
4739
4740 /* The length field in TX_RNG_CFIG is measured in 64-byte
4741 * blocks. rp->pending is the number of TX descriptors in
4742 * our ring, 8 bytes each, thus we divide by 8 bytes more
4743 * to get the proper value the chip wants.
4744 */
4745 ring_len = (rp->pending / 8);
4746
4747 val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
4748 rp->descr_dma);
4749 nw64(TX_RNG_CFIG(channel), val);
4750
4751 if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) ||
4752 ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) {
4753 dev_err(np->device, PFX "%s: TX ring channel %d "
4754 "MBOX addr (%llx) is has illegal bits.\n",
4755 np->dev->name, channel,
4756 (unsigned long long) rp->mbox_dma);
4757 return -EINVAL;
4758 }
4759 nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
4760 nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
4761
4762 nw64(TX_CS(channel), 0);
4763
4764 rp->last_pkt_cnt = 0;
4765
4766 return 0;
4767 }
4768
4769 static void niu_init_rdc_groups(struct niu *np)
4770 {
4771 struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
4772 int i, first_table_num = tp->first_table_num;
4773
4774 for (i = 0; i < tp->num_tables; i++) {
4775 struct rdc_table *tbl = &tp->tables[i];
4776 int this_table = first_table_num + i;
4777 int slot;
4778
4779 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++)
4780 nw64(RDC_TBL(this_table, slot),
4781 tbl->rxdma_channel[slot]);
4782 }
4783
4784 nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
4785 }
4786
4787 static void niu_init_drr_weight(struct niu *np)
4788 {
4789 int type = phy_decode(np->parent->port_phy, np->port);
4790 u64 val;
4791
4792 switch (type) {
4793 case PORT_TYPE_10G:
4794 val = PT_DRR_WEIGHT_DEFAULT_10G;
4795 break;
4796
4797 case PORT_TYPE_1G:
4798 default:
4799 val = PT_DRR_WEIGHT_DEFAULT_1G;
4800 break;
4801 }
4802 nw64(PT_DRR_WT(np->port), val);
4803 }
4804
4805 static int niu_init_hostinfo(struct niu *np)
4806 {
4807 struct niu_parent *parent = np->parent;
4808 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4809 int i, err, num_alt = niu_num_alt_addr(np);
4810 int first_rdc_table = tp->first_table_num;
4811
4812 err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4813 if (err)
4814 return err;
4815
4816 err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4817 if (err)
4818 return err;
4819
4820 for (i = 0; i < num_alt; i++) {
4821 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
4822 if (err)
4823 return err;
4824 }
4825
4826 return 0;
4827 }
4828
4829 static int niu_rx_channel_reset(struct niu *np, int channel)
4830 {
4831 return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel),
4832 RXDMA_CFIG1_RST, 1000, 10,
4833 "RXDMA_CFIG1");
4834 }
4835
4836 static int niu_rx_channel_lpage_init(struct niu *np, int channel)
4837 {
4838 u64 val;
4839
4840 nw64(RX_LOG_MASK1(channel), 0);
4841 nw64(RX_LOG_VAL1(channel), 0);
4842 nw64(RX_LOG_MASK2(channel), 0);
4843 nw64(RX_LOG_VAL2(channel), 0);
4844 nw64(RX_LOG_PAGE_RELO1(channel), 0);
4845 nw64(RX_LOG_PAGE_RELO2(channel), 0);
4846 nw64(RX_LOG_PAGE_HDL(channel), 0);
4847
4848 val = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
4849 val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
4850 nw64(RX_LOG_PAGE_VLD(channel), val);
4851
4852 return 0;
4853 }
4854
4855 static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp)
4856 {
4857 u64 val;
4858
4859 val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
4860 ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) |
4861 ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) |
4862 ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT));
4863 nw64(RDC_RED_PARA(rp->rx_channel), val);
4864 }
4865
4866 static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret)
4867 {
4868 u64 val = 0;
4869
4870 *ret = 0;
4871 switch (rp->rbr_block_size) {
4872 case 4 * 1024:
4873 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
4874 break;
4875 case 8 * 1024:
4876 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
4877 break;
4878 case 16 * 1024:
4879 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
4880 break;
4881 case 32 * 1024:
4882 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
4883 break;
4884 default:
4885 return -EINVAL;
4886 }
4887 val |= RBR_CFIG_B_VLD2;
4888 switch (rp->rbr_sizes[2]) {
4889 case 2 * 1024:
4890 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
4891 break;
4892 case 4 * 1024:
4893 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
4894 break;
4895 case 8 * 1024:
4896 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
4897 break;
4898 case 16 * 1024:
4899 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
4900 break;
4901
4902 default:
4903 return -EINVAL;
4904 }
4905 val |= RBR_CFIG_B_VLD1;
4906 switch (rp->rbr_sizes[1]) {
4907 case 1 * 1024:
4908 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
4909 break;
4910 case 2 * 1024:
4911 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
4912 break;
4913 case 4 * 1024:
4914 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
4915 break;
4916 case 8 * 1024:
4917 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
4918 break;
4919
4920 default:
4921 return -EINVAL;
4922 }
4923 val |= RBR_CFIG_B_VLD0;
4924 switch (rp->rbr_sizes[0]) {
4925 case 256:
4926 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
4927 break;
4928 case 512:
4929 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
4930 break;
4931 case 1 * 1024:
4932 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
4933 break;
4934 case 2 * 1024:
4935 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
4936 break;
4937
4938 default:
4939 return -EINVAL;
4940 }
4941
4942 *ret = val;
4943 return 0;
4944 }
4945
4946 static int niu_enable_rx_channel(struct niu *np, int channel, int on)
4947 {
4948 u64 val = nr64(RXDMA_CFIG1(channel));
4949 int limit;
4950
4951 if (on)
4952 val |= RXDMA_CFIG1_EN;
4953 else
4954 val &= ~RXDMA_CFIG1_EN;
4955 nw64(RXDMA_CFIG1(channel), val);
4956
4957 limit = 1000;
4958 while (--limit > 0) {
4959 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
4960 break;
4961 udelay(10);
4962 }
4963 if (limit <= 0)
4964 return -ENODEV;
4965 return 0;
4966 }
4967
4968 static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4969 {
4970 int err, channel = rp->rx_channel;
4971 u64 val;
4972
4973 err = niu_rx_channel_reset(np, channel);
4974 if (err)
4975 return err;
4976
4977 err = niu_rx_channel_lpage_init(np, channel);
4978 if (err)
4979 return err;
4980
4981 niu_rx_channel_wred_init(np, rp);
4982
4983 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
4984 nw64(RX_DMA_CTL_STAT(channel),
4985 (RX_DMA_CTL_STAT_MEX |
4986 RX_DMA_CTL_STAT_RCRTHRES |
4987 RX_DMA_CTL_STAT_RCRTO |
4988 RX_DMA_CTL_STAT_RBR_EMPTY));
4989 nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
4990 nw64(RXDMA_CFIG2(channel), (rp->mbox_dma & 0x00000000ffffffc0));
4991 nw64(RBR_CFIG_A(channel),
4992 ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) |
4993 (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR)));
4994 err = niu_compute_rbr_cfig_b(rp, &val);
4995 if (err)
4996 return err;
4997 nw64(RBR_CFIG_B(channel), val);
4998 nw64(RCRCFIG_A(channel),
4999 ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) |
5000 (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR)));
5001 nw64(RCRCFIG_B(channel),
5002 ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) |
5003 RCRCFIG_B_ENTOUT |
5004 ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT));
5005
5006 err = niu_enable_rx_channel(np, channel, 1);
5007 if (err)
5008 return err;
5009
5010 nw64(RBR_KICK(channel), rp->rbr_index);
5011
5012 val = nr64(RX_DMA_CTL_STAT(channel));
5013 val |= RX_DMA_CTL_STAT_RBR_EMPTY;
5014 nw64(RX_DMA_CTL_STAT(channel), val);
5015
5016 return 0;
5017 }
5018
5019 static int niu_init_rx_channels(struct niu *np)
5020 {
5021 unsigned long flags;
5022 u64 seed = jiffies_64;
5023 int err, i;
5024
5025 niu_lock_parent(np, flags);
5026 nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
5027 nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
5028 niu_unlock_parent(np, flags);
5029
5030 /* XXX RXDMA 32bit mode? XXX */
5031
5032 niu_init_rdc_groups(np);
5033 niu_init_drr_weight(np);
5034
5035 err = niu_init_hostinfo(np);
5036 if (err)
5037 return err;
5038
5039 for (i = 0; i < np->num_rx_rings; i++) {
5040 struct rx_ring_info *rp = &np->rx_rings[i];
5041
5042 err = niu_init_one_rx_channel(np, rp);
5043 if (err)
5044 return err;
5045 }
5046
5047 return 0;
5048 }
5049
5050 static int niu_set_ip_frag_rule(struct niu *np)
5051 {
5052 struct niu_parent *parent = np->parent;
5053 struct niu_classifier *cp = &np->clas;
5054 struct niu_tcam_entry *tp;
5055 int index, err;
5056
5057 index = cp->tcam_top;
5058 tp = &parent->tcam[index];
5059
5060 /* Note that the noport bit is the same in both ipv4 and
5061 * ipv6 format TCAM entries.
5062 */
5063 memset(tp, 0, sizeof(*tp));
5064 tp->key[1] = TCAM_V4KEY1_NOPORT;
5065 tp->key_mask[1] = TCAM_V4KEY1_NOPORT;
5066 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
5067 ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT));
5068 err = tcam_write(np, index, tp->key, tp->key_mask);
5069 if (err)
5070 return err;
5071 err = tcam_assoc_write(np, index, tp->assoc_data);
5072 if (err)
5073 return err;
5074 tp->valid = 1;
5075 cp->tcam_valid_entries++;
5076
5077 return 0;
5078 }
5079
5080 static int niu_init_classifier_hw(struct niu *np)
5081 {
5082 struct niu_parent *parent = np->parent;
5083 struct niu_classifier *cp = &np->clas;
5084 int i, err;
5085
5086 nw64(H1POLY, cp->h1_init);
5087 nw64(H2POLY, cp->h2_init);
5088
5089 err = niu_init_hostinfo(np);
5090 if (err)
5091 return err;
5092
5093 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) {
5094 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i];
5095
5096 vlan_tbl_write(np, i, np->port,
5097 vp->vlan_pref, vp->rdc_num);
5098 }
5099
5100 for (i = 0; i < cp->num_alt_mac_mappings; i++) {
5101 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i];
5102
5103 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
5104 ap->rdc_num, ap->mac_pref);
5105 if (err)
5106 return err;
5107 }
5108
5109 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
5110 int index = i - CLASS_CODE_USER_PROG1;
5111
5112 err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
5113 if (err)
5114 return err;
5115 err = niu_set_flow_key(np, i, parent->flow_key[index]);
5116 if (err)
5117 return err;
5118 }
5119
5120 err = niu_set_ip_frag_rule(np);
5121 if (err)
5122 return err;
5123
5124 tcam_enable(np, 1);
5125
5126 return 0;
5127 }
5128
5129 static int niu_zcp_write(struct niu *np, int index, u64 *data)
5130 {
5131 nw64(ZCP_RAM_DATA0, data[0]);
5132 nw64(ZCP_RAM_DATA1, data[1]);
5133 nw64(ZCP_RAM_DATA2, data[2]);
5134 nw64(ZCP_RAM_DATA3, data[3]);
5135 nw64(ZCP_RAM_DATA4, data[4]);
5136 nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
5137 nw64(ZCP_RAM_ACC,
5138 (ZCP_RAM_ACC_WRITE |
5139 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5140 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5141
5142 return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5143 1000, 100);
5144 }
5145
5146 static int niu_zcp_read(struct niu *np, int index, u64 *data)
5147 {
5148 int err;
5149
5150 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5151 1000, 100);
5152 if (err) {
5153 dev_err(np->device, PFX "%s: ZCP read busy won't clear, "
5154 "ZCP_RAM_ACC[%llx]\n", np->dev->name,
5155 (unsigned long long) nr64(ZCP_RAM_ACC));
5156 return err;
5157 }
5158
5159 nw64(ZCP_RAM_ACC,
5160 (ZCP_RAM_ACC_READ |
5161 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5162 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5163
5164 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5165 1000, 100);
5166 if (err) {
5167 dev_err(np->device, PFX "%s: ZCP read busy2 won't clear, "
5168 "ZCP_RAM_ACC[%llx]\n", np->dev->name,
5169 (unsigned long long) nr64(ZCP_RAM_ACC));
5170 return err;
5171 }
5172
5173 data[0] = nr64(ZCP_RAM_DATA0);
5174 data[1] = nr64(ZCP_RAM_DATA1);
5175 data[2] = nr64(ZCP_RAM_DATA2);
5176 data[3] = nr64(ZCP_RAM_DATA3);
5177 data[4] = nr64(ZCP_RAM_DATA4);
5178
5179 return 0;
5180 }
5181
5182 static void niu_zcp_cfifo_reset(struct niu *np)
5183 {
5184 u64 val = nr64(RESET_CFIFO);
5185
5186 val |= RESET_CFIFO_RST(np->port);
5187 nw64(RESET_CFIFO, val);
5188 udelay(10);
5189
5190 val &= ~RESET_CFIFO_RST(np->port);
5191 nw64(RESET_CFIFO, val);
5192 }
5193
5194 static int niu_init_zcp(struct niu *np)
5195 {
5196 u64 data[5], rbuf[5];
5197 int i, max, err;
5198
5199 if (np->parent->plat_type != PLAT_TYPE_NIU) {
5200 if (np->port == 0 || np->port == 1)
5201 max = ATLAS_P0_P1_CFIFO_ENTRIES;
5202 else
5203 max = ATLAS_P2_P3_CFIFO_ENTRIES;
5204 } else
5205 max = NIU_CFIFO_ENTRIES;
5206
5207 data[0] = 0;
5208 data[1] = 0;
5209 data[2] = 0;
5210 data[3] = 0;
5211 data[4] = 0;
5212
5213 for (i = 0; i < max; i++) {
5214 err = niu_zcp_write(np, i, data);
5215 if (err)
5216 return err;
5217 err = niu_zcp_read(np, i, rbuf);
5218 if (err)
5219 return err;
5220 }
5221
5222 niu_zcp_cfifo_reset(np);
5223 nw64(CFIFO_ECC(np->port), 0);
5224 nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
5225 (void) nr64(ZCP_INT_STAT);
5226 nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
5227
5228 return 0;
5229 }
5230
5231 static void niu_ipp_write(struct niu *np, int index, u64 *data)
5232 {
5233 u64 val = nr64_ipp(IPP_CFIG);
5234
5235 nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
5236 nw64_ipp(IPP_DFIFO_WR_PTR, index);
5237 nw64_ipp(IPP_DFIFO_WR0, data[0]);
5238 nw64_ipp(IPP_DFIFO_WR1, data[1]);
5239 nw64_ipp(IPP_DFIFO_WR2, data[2]);
5240 nw64_ipp(IPP_DFIFO_WR3, data[3]);
5241 nw64_ipp(IPP_DFIFO_WR4, data[4]);
5242 nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
5243 }
5244
5245 static void niu_ipp_read(struct niu *np, int index, u64 *data)
5246 {
5247 nw64_ipp(IPP_DFIFO_RD_PTR, index);
5248 data[0] = nr64_ipp(IPP_DFIFO_RD0);
5249 data[1] = nr64_ipp(IPP_DFIFO_RD1);
5250 data[2] = nr64_ipp(IPP_DFIFO_RD2);
5251 data[3] = nr64_ipp(IPP_DFIFO_RD3);
5252 data[4] = nr64_ipp(IPP_DFIFO_RD4);
5253 }
5254
5255 static int niu_ipp_reset(struct niu *np)
5256 {
5257 return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST,
5258 1000, 100, "IPP_CFIG");
5259 }
5260
5261 static int niu_init_ipp(struct niu *np)
5262 {
5263 u64 data[5], rbuf[5], val;
5264 int i, max, err;
5265
5266 if (np->parent->plat_type != PLAT_TYPE_NIU) {
5267 if (np->port == 0 || np->port == 1)
5268 max = ATLAS_P0_P1_DFIFO_ENTRIES;
5269 else
5270 max = ATLAS_P2_P3_DFIFO_ENTRIES;
5271 } else
5272 max = NIU_DFIFO_ENTRIES;
5273
5274 data[0] = 0;
5275 data[1] = 0;
5276 data[2] = 0;
5277 data[3] = 0;
5278 data[4] = 0;
5279
5280 for (i = 0; i < max; i++) {
5281 niu_ipp_write(np, i, data);
5282 niu_ipp_read(np, i, rbuf);
5283 }
5284
5285 (void) nr64_ipp(IPP_INT_STAT);
5286 (void) nr64_ipp(IPP_INT_STAT);
5287
5288 err = niu_ipp_reset(np);
5289 if (err)
5290 return err;
5291
5292 (void) nr64_ipp(IPP_PKT_DIS);
5293 (void) nr64_ipp(IPP_BAD_CS_CNT);
5294 (void) nr64_ipp(IPP_ECC);
5295
5296 (void) nr64_ipp(IPP_INT_STAT);
5297
5298 nw64_ipp(IPP_MSK, ~IPP_MSK_ALL);
5299
5300 val = nr64_ipp(IPP_CFIG);
5301 val &= ~IPP_CFIG_IP_MAX_PKT;
5302 val |= (IPP_CFIG_IPP_ENABLE |
5303 IPP_CFIG_DFIFO_ECC_EN |
5304 IPP_CFIG_DROP_BAD_CRC |
5305 IPP_CFIG_CKSUM_EN |
5306 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT));
5307 nw64_ipp(IPP_CFIG, val);
5308
5309 return 0;
5310 }
5311
5312 static void niu_handle_led(struct niu *np, int status)
5313 {
5314 u64 val;
5315 val = nr64_mac(XMAC_CONFIG);
5316
5317 if ((np->flags & NIU_FLAGS_10G) != 0 &&
5318 (np->flags & NIU_FLAGS_FIBER) != 0) {
5319 if (status) {
5320 val |= XMAC_CONFIG_LED_POLARITY;
5321 val &= ~XMAC_CONFIG_FORCE_LED_ON;
5322 } else {
5323 val |= XMAC_CONFIG_FORCE_LED_ON;
5324 val &= ~XMAC_CONFIG_LED_POLARITY;
5325 }
5326 }
5327
5328 nw64_mac(XMAC_CONFIG, val);
5329 }
5330
5331 static void niu_init_xif_xmac(struct niu *np)
5332 {
5333 struct niu_link_config *lp = &np->link_config;
5334 u64 val;
5335
5336 if (np->flags & NIU_FLAGS_XCVR_SERDES) {
5337 val = nr64(MIF_CONFIG);
5338 val |= MIF_CONFIG_ATCA_GE;
5339 nw64(MIF_CONFIG, val);
5340 }
5341
5342 val = nr64_mac(XMAC_CONFIG);
5343 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5344
5345 val |= XMAC_CONFIG_TX_OUTPUT_EN;
5346
5347 if (lp->loopback_mode == LOOPBACK_MAC) {
5348 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5349 val |= XMAC_CONFIG_LOOPBACK;
5350 } else {
5351 val &= ~XMAC_CONFIG_LOOPBACK;
5352 }
5353
5354 if (np->flags & NIU_FLAGS_10G) {
5355 val &= ~XMAC_CONFIG_LFS_DISABLE;
5356 } else {
5357 val |= XMAC_CONFIG_LFS_DISABLE;
5358 if (!(np->flags & NIU_FLAGS_FIBER) &&
5359 !(np->flags & NIU_FLAGS_XCVR_SERDES))
5360 val |= XMAC_CONFIG_1G_PCS_BYPASS;
5361 else
5362 val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
5363 }
5364
5365 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5366
5367 if (lp->active_speed == SPEED_100)
5368 val |= XMAC_CONFIG_SEL_CLK_25MHZ;
5369 else
5370 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
5371
5372 nw64_mac(XMAC_CONFIG, val);
5373
5374 val = nr64_mac(XMAC_CONFIG);
5375 val &= ~XMAC_CONFIG_MODE_MASK;
5376 if (np->flags & NIU_FLAGS_10G) {
5377 val |= XMAC_CONFIG_MODE_XGMII;
5378 } else {
5379 if (lp->active_speed == SPEED_1000)
5380 val |= XMAC_CONFIG_MODE_GMII;
5381 else
5382 val |= XMAC_CONFIG_MODE_MII;
5383 }
5384
5385 nw64_mac(XMAC_CONFIG, val);
5386 }
5387
5388 static void niu_init_xif_bmac(struct niu *np)
5389 {
5390 struct niu_link_config *lp = &np->link_config;
5391 u64 val;
5392
5393 val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
5394
5395 if (lp->loopback_mode == LOOPBACK_MAC)
5396 val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
5397 else
5398 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
5399
5400 if (lp->active_speed == SPEED_1000)
5401 val |= BMAC_XIF_CONFIG_GMII_MODE;
5402 else
5403 val &= ~BMAC_XIF_CONFIG_GMII_MODE;
5404
5405 val &= ~(BMAC_XIF_CONFIG_LINK_LED |
5406 BMAC_XIF_CONFIG_LED_POLARITY);
5407
5408 if (!(np->flags & NIU_FLAGS_10G) &&
5409 !(np->flags & NIU_FLAGS_FIBER) &&
5410 lp->active_speed == SPEED_100)
5411 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
5412 else
5413 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
5414
5415 nw64_mac(BMAC_XIF_CONFIG, val);
5416 }
5417
5418 static void niu_init_xif(struct niu *np)
5419 {
5420 if (np->flags & NIU_FLAGS_XMAC)
5421 niu_init_xif_xmac(np);
5422 else
5423 niu_init_xif_bmac(np);
5424 }
5425
5426 static void niu_pcs_mii_reset(struct niu *np)
5427 {
5428 int limit = 1000;
5429 u64 val = nr64_pcs(PCS_MII_CTL);
5430 val |= PCS_MII_CTL_RST;
5431 nw64_pcs(PCS_MII_CTL, val);
5432 while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) {
5433 udelay(100);
5434 val = nr64_pcs(PCS_MII_CTL);
5435 }
5436 }
5437
5438 static void niu_xpcs_reset(struct niu *np)
5439 {
5440 int limit = 1000;
5441 u64 val = nr64_xpcs(XPCS_CONTROL1);
5442 val |= XPCS_CONTROL1_RESET;
5443 nw64_xpcs(XPCS_CONTROL1, val);
5444 while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) {
5445 udelay(100);
5446 val = nr64_xpcs(XPCS_CONTROL1);
5447 }
5448 }
5449
5450 static int niu_init_pcs(struct niu *np)
5451 {
5452 struct niu_link_config *lp = &np->link_config;
5453 u64 val;
5454
5455 switch (np->flags & (NIU_FLAGS_10G |
5456 NIU_FLAGS_FIBER |
5457 NIU_FLAGS_XCVR_SERDES)) {
5458 case NIU_FLAGS_FIBER:
5459 /* 1G fiber */
5460 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5461 nw64_pcs(PCS_DPATH_MODE, 0);
5462 niu_pcs_mii_reset(np);
5463 break;
5464
5465 case NIU_FLAGS_10G:
5466 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
5467 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
5468 /* 10G SERDES */
5469 if (!(np->flags & NIU_FLAGS_XMAC))
5470 return -EINVAL;
5471
5472 /* 10G copper or fiber */
5473 val = nr64_mac(XMAC_CONFIG);
5474 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5475 nw64_mac(XMAC_CONFIG, val);
5476
5477 niu_xpcs_reset(np);
5478
5479 val = nr64_xpcs(XPCS_CONTROL1);
5480 if (lp->loopback_mode == LOOPBACK_PHY)
5481 val |= XPCS_CONTROL1_LOOPBACK;
5482 else
5483 val &= ~XPCS_CONTROL1_LOOPBACK;
5484 nw64_xpcs(XPCS_CONTROL1, val);
5485
5486 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0);
5487 (void) nr64_xpcs(XPCS_SYMERR_CNT01);
5488 (void) nr64_xpcs(XPCS_SYMERR_CNT23);
5489 break;
5490
5491
5492 case NIU_FLAGS_XCVR_SERDES:
5493 /* 1G SERDES */
5494 niu_pcs_mii_reset(np);
5495 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5496 nw64_pcs(PCS_DPATH_MODE, 0);
5497 break;
5498
5499 case 0:
5500 /* 1G copper */
5501 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
5502 /* 1G RGMII FIBER */
5503 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII);
5504 niu_pcs_mii_reset(np);
5505 break;
5506
5507 default:
5508 return -EINVAL;
5509 }
5510
5511 return 0;
5512 }
5513
5514 static int niu_reset_tx_xmac(struct niu *np)
5515 {
5516 return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST,
5517 (XTXMAC_SW_RST_REG_RS |
5518 XTXMAC_SW_RST_SOFT_RST),
5519 1000, 100, "XTXMAC_SW_RST");
5520 }
5521
5522 static int niu_reset_tx_bmac(struct niu *np)
5523 {
5524 int limit;
5525
5526 nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET);
5527 limit = 1000;
5528 while (--limit >= 0) {
5529 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET))
5530 break;
5531 udelay(100);
5532 }
5533 if (limit < 0) {
5534 dev_err(np->device, PFX "Port %u TX BMAC would not reset, "
5535 "BTXMAC_SW_RST[%llx]\n",
5536 np->port,
5537 (unsigned long long) nr64_mac(BTXMAC_SW_RST));
5538 return -ENODEV;
5539 }
5540
5541 return 0;
5542 }
5543
5544 static int niu_reset_tx_mac(struct niu *np)
5545 {
5546 if (np->flags & NIU_FLAGS_XMAC)
5547 return niu_reset_tx_xmac(np);
5548 else
5549 return niu_reset_tx_bmac(np);
5550 }
5551
5552 static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max)
5553 {
5554 u64 val;
5555
5556 val = nr64_mac(XMAC_MIN);
5557 val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
5558 XMAC_MIN_RX_MIN_PKT_SIZE);
5559 val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
5560 val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
5561 nw64_mac(XMAC_MIN, val);
5562
5563 nw64_mac(XMAC_MAX, max);
5564
5565 nw64_mac(XTXMAC_STAT_MSK, ~(u64)0);
5566
5567 val = nr64_mac(XMAC_IPG);
5568 if (np->flags & NIU_FLAGS_10G) {
5569 val &= ~XMAC_IPG_IPG_XGMII;
5570 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
5571 } else {
5572 val &= ~XMAC_IPG_IPG_MII_GMII;
5573 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
5574 }
5575 nw64_mac(XMAC_IPG, val);
5576
5577 val = nr64_mac(XMAC_CONFIG);
5578 val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
5579 XMAC_CONFIG_STRETCH_MODE |
5580 XMAC_CONFIG_VAR_MIN_IPG_EN |
5581 XMAC_CONFIG_TX_ENABLE);
5582 nw64_mac(XMAC_CONFIG, val);
5583
5584 nw64_mac(TXMAC_FRM_CNT, 0);
5585 nw64_mac(TXMAC_BYTE_CNT, 0);
5586 }
5587
5588 static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max)
5589 {
5590 u64 val;
5591
5592 nw64_mac(BMAC_MIN_FRAME, min);
5593 nw64_mac(BMAC_MAX_FRAME, max);
5594
5595 nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0);
5596 nw64_mac(BMAC_CTRL_TYPE, 0x8808);
5597 nw64_mac(BMAC_PREAMBLE_SIZE, 7);
5598
5599 val = nr64_mac(BTXMAC_CONFIG);
5600 val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
5601 BTXMAC_CONFIG_ENABLE);
5602 nw64_mac(BTXMAC_CONFIG, val);
5603 }
5604
5605 static void niu_init_tx_mac(struct niu *np)
5606 {
5607 u64 min, max;
5608
5609 min = 64;
5610 if (np->dev->mtu > ETH_DATA_LEN)
5611 max = 9216;
5612 else
5613 max = 1522;
5614
5615 /* The XMAC_MIN register only accepts values for TX min which
5616 * have the low 3 bits cleared.
5617 */
5618 BUILD_BUG_ON(min & 0x7);
5619
5620 if (np->flags & NIU_FLAGS_XMAC)
5621 niu_init_tx_xmac(np, min, max);
5622 else
5623 niu_init_tx_bmac(np, min, max);
5624 }
5625
5626 static int niu_reset_rx_xmac(struct niu *np)
5627 {
5628 int limit;
5629
5630 nw64_mac(XRXMAC_SW_RST,
5631 XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST);
5632 limit = 1000;
5633 while (--limit >= 0) {
5634 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS |
5635 XRXMAC_SW_RST_SOFT_RST)))
5636 break;
5637 udelay(100);
5638 }
5639 if (limit < 0) {
5640 dev_err(np->device, PFX "Port %u RX XMAC would not reset, "
5641 "XRXMAC_SW_RST[%llx]\n",
5642 np->port,
5643 (unsigned long long) nr64_mac(XRXMAC_SW_RST));
5644 return -ENODEV;
5645 }
5646
5647 return 0;
5648 }
5649
5650 static int niu_reset_rx_bmac(struct niu *np)
5651 {
5652 int limit;
5653
5654 nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET);
5655 limit = 1000;
5656 while (--limit >= 0) {
5657 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET))
5658 break;
5659 udelay(100);
5660 }
5661 if (limit < 0) {
5662 dev_err(np->device, PFX "Port %u RX BMAC would not reset, "
5663 "BRXMAC_SW_RST[%llx]\n",
5664 np->port,
5665 (unsigned long long) nr64_mac(BRXMAC_SW_RST));
5666 return -ENODEV;
5667 }
5668
5669 return 0;
5670 }
5671
5672 static int niu_reset_rx_mac(struct niu *np)
5673 {
5674 if (np->flags & NIU_FLAGS_XMAC)
5675 return niu_reset_rx_xmac(np);
5676 else
5677 return niu_reset_rx_bmac(np);
5678 }
5679
5680 static void niu_init_rx_xmac(struct niu *np)
5681 {
5682 struct niu_parent *parent = np->parent;
5683 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5684 int first_rdc_table = tp->first_table_num;
5685 unsigned long i;
5686 u64 val;
5687
5688 nw64_mac(XMAC_ADD_FILT0, 0);
5689 nw64_mac(XMAC_ADD_FILT1, 0);
5690 nw64_mac(XMAC_ADD_FILT2, 0);
5691 nw64_mac(XMAC_ADD_FILT12_MASK, 0);
5692 nw64_mac(XMAC_ADD_FILT00_MASK, 0);
5693 for (i = 0; i < MAC_NUM_HASH; i++)
5694 nw64_mac(XMAC_HASH_TBL(i), 0);
5695 nw64_mac(XRXMAC_STAT_MSK, ~(u64)0);
5696 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5697 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5698
5699 val = nr64_mac(XMAC_CONFIG);
5700 val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
5701 XMAC_CONFIG_PROMISCUOUS |
5702 XMAC_CONFIG_PROMISC_GROUP |
5703 XMAC_CONFIG_ERR_CHK_DIS |
5704 XMAC_CONFIG_RX_CRC_CHK_DIS |
5705 XMAC_CONFIG_RESERVED_MULTICAST |
5706 XMAC_CONFIG_RX_CODEV_CHK_DIS |
5707 XMAC_CONFIG_ADDR_FILTER_EN |
5708 XMAC_CONFIG_RCV_PAUSE_ENABLE |
5709 XMAC_CONFIG_STRIP_CRC |
5710 XMAC_CONFIG_PASS_FLOW_CTRL |
5711 XMAC_CONFIG_MAC2IPP_PKT_CNT_EN);
5712 val |= (XMAC_CONFIG_HASH_FILTER_EN);
5713 nw64_mac(XMAC_CONFIG, val);
5714
5715 nw64_mac(RXMAC_BT_CNT, 0);
5716 nw64_mac(RXMAC_BC_FRM_CNT, 0);
5717 nw64_mac(RXMAC_MC_FRM_CNT, 0);
5718 nw64_mac(RXMAC_FRAG_CNT, 0);
5719 nw64_mac(RXMAC_HIST_CNT1, 0);
5720 nw64_mac(RXMAC_HIST_CNT2, 0);
5721 nw64_mac(RXMAC_HIST_CNT3, 0);
5722 nw64_mac(RXMAC_HIST_CNT4, 0);
5723 nw64_mac(RXMAC_HIST_CNT5, 0);
5724 nw64_mac(RXMAC_HIST_CNT6, 0);
5725 nw64_mac(RXMAC_HIST_CNT7, 0);
5726 nw64_mac(RXMAC_MPSZER_CNT, 0);
5727 nw64_mac(RXMAC_CRC_ER_CNT, 0);
5728 nw64_mac(RXMAC_CD_VIO_CNT, 0);
5729 nw64_mac(LINK_FAULT_CNT, 0);
5730 }
5731
5732 static void niu_init_rx_bmac(struct niu *np)
5733 {
5734 struct niu_parent *parent = np->parent;
5735 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5736 int first_rdc_table = tp->first_table_num;
5737 unsigned long i;
5738 u64 val;
5739
5740 nw64_mac(BMAC_ADD_FILT0, 0);
5741 nw64_mac(BMAC_ADD_FILT1, 0);
5742 nw64_mac(BMAC_ADD_FILT2, 0);
5743 nw64_mac(BMAC_ADD_FILT12_MASK, 0);
5744 nw64_mac(BMAC_ADD_FILT00_MASK, 0);
5745 for (i = 0; i < MAC_NUM_HASH; i++)
5746 nw64_mac(BMAC_HASH_TBL(i), 0);
5747 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5748 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5749 nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0);
5750
5751 val = nr64_mac(BRXMAC_CONFIG);
5752 val &= ~(BRXMAC_CONFIG_ENABLE |
5753 BRXMAC_CONFIG_STRIP_PAD |
5754 BRXMAC_CONFIG_STRIP_FCS |
5755 BRXMAC_CONFIG_PROMISC |
5756 BRXMAC_CONFIG_PROMISC_GRP |
5757 BRXMAC_CONFIG_ADDR_FILT_EN |
5758 BRXMAC_CONFIG_DISCARD_DIS);
5759 val |= (BRXMAC_CONFIG_HASH_FILT_EN);
5760 nw64_mac(BRXMAC_CONFIG, val);
5761
5762 val = nr64_mac(BMAC_ADDR_CMPEN);
5763 val |= BMAC_ADDR_CMPEN_EN0;
5764 nw64_mac(BMAC_ADDR_CMPEN, val);
5765 }
5766
5767 static void niu_init_rx_mac(struct niu *np)
5768 {
5769 niu_set_primary_mac(np, np->dev->dev_addr);
5770
5771 if (np->flags & NIU_FLAGS_XMAC)
5772 niu_init_rx_xmac(np);
5773 else
5774 niu_init_rx_bmac(np);
5775 }
5776
5777 static void niu_enable_tx_xmac(struct niu *np, int on)
5778 {
5779 u64 val = nr64_mac(XMAC_CONFIG);
5780
5781 if (on)
5782 val |= XMAC_CONFIG_TX_ENABLE;
5783 else
5784 val &= ~XMAC_CONFIG_TX_ENABLE;
5785 nw64_mac(XMAC_CONFIG, val);
5786 }
5787
5788 static void niu_enable_tx_bmac(struct niu *np, int on)
5789 {
5790 u64 val = nr64_mac(BTXMAC_CONFIG);
5791
5792 if (on)
5793 val |= BTXMAC_CONFIG_ENABLE;
5794 else
5795 val &= ~BTXMAC_CONFIG_ENABLE;
5796 nw64_mac(BTXMAC_CONFIG, val);
5797 }
5798
5799 static void niu_enable_tx_mac(struct niu *np, int on)
5800 {
5801 if (np->flags & NIU_FLAGS_XMAC)
5802 niu_enable_tx_xmac(np, on);
5803 else
5804 niu_enable_tx_bmac(np, on);
5805 }
5806
5807 static void niu_enable_rx_xmac(struct niu *np, int on)
5808 {
5809 u64 val = nr64_mac(XMAC_CONFIG);
5810
5811 val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
5812 XMAC_CONFIG_PROMISCUOUS);
5813
5814 if (np->flags & NIU_FLAGS_MCAST)
5815 val |= XMAC_CONFIG_HASH_FILTER_EN;
5816 if (np->flags & NIU_FLAGS_PROMISC)
5817 val |= XMAC_CONFIG_PROMISCUOUS;
5818
5819 if (on)
5820 val |= XMAC_CONFIG_RX_MAC_ENABLE;
5821 else
5822 val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
5823 nw64_mac(XMAC_CONFIG, val);
5824 }
5825
5826 static void niu_enable_rx_bmac(struct niu *np, int on)
5827 {
5828 u64 val = nr64_mac(BRXMAC_CONFIG);
5829
5830 val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
5831 BRXMAC_CONFIG_PROMISC);
5832
5833 if (np->flags & NIU_FLAGS_MCAST)
5834 val |= BRXMAC_CONFIG_HASH_FILT_EN;
5835 if (np->flags & NIU_FLAGS_PROMISC)
5836 val |= BRXMAC_CONFIG_PROMISC;
5837
5838 if (on)
5839 val |= BRXMAC_CONFIG_ENABLE;
5840 else
5841 val &= ~BRXMAC_CONFIG_ENABLE;
5842 nw64_mac(BRXMAC_CONFIG, val);
5843 }
5844
5845 static void niu_enable_rx_mac(struct niu *np, int on)
5846 {
5847 if (np->flags & NIU_FLAGS_XMAC)
5848 niu_enable_rx_xmac(np, on);
5849 else
5850 niu_enable_rx_bmac(np, on);
5851 }
5852
5853 static int niu_init_mac(struct niu *np)
5854 {
5855 int err;
5856
5857 niu_init_xif(np);
5858 err = niu_init_pcs(np);
5859 if (err)
5860 return err;
5861
5862 err = niu_reset_tx_mac(np);
5863 if (err)
5864 return err;
5865 niu_init_tx_mac(np);
5866 err = niu_reset_rx_mac(np);
5867 if (err)
5868 return err;
5869 niu_init_rx_mac(np);
5870
5871 /* This looks hookey but the RX MAC reset we just did will
5872 * undo some of the state we setup in niu_init_tx_mac() so we
5873 * have to call it again. In particular, the RX MAC reset will
5874 * set the XMAC_MAX register back to it's default value.
5875 */
5876 niu_init_tx_mac(np);
5877 niu_enable_tx_mac(np, 1);
5878
5879 niu_enable_rx_mac(np, 1);
5880
5881 return 0;
5882 }
5883
5884 static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5885 {
5886 (void) niu_tx_channel_stop(np, rp->tx_channel);
5887 }
5888
5889 static void niu_stop_tx_channels(struct niu *np)
5890 {
5891 int i;
5892
5893 for (i = 0; i < np->num_tx_rings; i++) {
5894 struct tx_ring_info *rp = &np->tx_rings[i];
5895
5896 niu_stop_one_tx_channel(np, rp);
5897 }
5898 }
5899
5900 static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5901 {
5902 (void) niu_tx_channel_reset(np, rp->tx_channel);
5903 }
5904
5905 static void niu_reset_tx_channels(struct niu *np)
5906 {
5907 int i;
5908
5909 for (i = 0; i < np->num_tx_rings; i++) {
5910 struct tx_ring_info *rp = &np->tx_rings[i];
5911
5912 niu_reset_one_tx_channel(np, rp);
5913 }
5914 }
5915
5916 static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5917 {
5918 (void) niu_enable_rx_channel(np, rp->rx_channel, 0);
5919 }
5920
5921 static void niu_stop_rx_channels(struct niu *np)
5922 {
5923 int i;
5924
5925 for (i = 0; i < np->num_rx_rings; i++) {
5926 struct rx_ring_info *rp = &np->rx_rings[i];
5927
5928 niu_stop_one_rx_channel(np, rp);
5929 }
5930 }
5931
5932 static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5933 {
5934 int channel = rp->rx_channel;
5935
5936 (void) niu_rx_channel_reset(np, channel);
5937 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
5938 nw64(RX_DMA_CTL_STAT(channel), 0);
5939 (void) niu_enable_rx_channel(np, channel, 0);
5940 }
5941
5942 static void niu_reset_rx_channels(struct niu *np)
5943 {
5944 int i;
5945
5946 for (i = 0; i < np->num_rx_rings; i++) {
5947 struct rx_ring_info *rp = &np->rx_rings[i];
5948
5949 niu_reset_one_rx_channel(np, rp);
5950 }
5951 }
5952
5953 static void niu_disable_ipp(struct niu *np)
5954 {
5955 u64 rd, wr, val;
5956 int limit;
5957
5958 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5959 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5960 limit = 100;
5961 while (--limit >= 0 && (rd != wr)) {
5962 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5963 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5964 }
5965 if (limit < 0 &&
5966 (rd != 0 && wr != 1)) {
5967 dev_err(np->device, PFX "%s: IPP would not quiesce, "
5968 "rd_ptr[%llx] wr_ptr[%llx]\n",
5969 np->dev->name,
5970 (unsigned long long) nr64_ipp(IPP_DFIFO_RD_PTR),
5971 (unsigned long long) nr64_ipp(IPP_DFIFO_WR_PTR));
5972 }
5973
5974 val = nr64_ipp(IPP_CFIG);
5975 val &= ~(IPP_CFIG_IPP_ENABLE |
5976 IPP_CFIG_DFIFO_ECC_EN |
5977 IPP_CFIG_DROP_BAD_CRC |
5978 IPP_CFIG_CKSUM_EN);
5979 nw64_ipp(IPP_CFIG, val);
5980
5981 (void) niu_ipp_reset(np);
5982 }
5983
5984 static int niu_init_hw(struct niu *np)
5985 {
5986 int i, err;
5987
5988 niudbg(IFUP, "%s: Initialize TXC\n", np->dev->name);
5989 niu_txc_enable_port(np, 1);
5990 niu_txc_port_dma_enable(np, 1);
5991 niu_txc_set_imask(np, 0);
5992
5993 niudbg(IFUP, "%s: Initialize TX channels\n", np->dev->name);
5994 for (i = 0; i < np->num_tx_rings; i++) {
5995 struct tx_ring_info *rp = &np->tx_rings[i];
5996
5997 err = niu_init_one_tx_channel(np, rp);
5998 if (err)
5999 return err;
6000 }
6001
6002 niudbg(IFUP, "%s: Initialize RX channels\n", np->dev->name);
6003 err = niu_init_rx_channels(np);
6004 if (err)
6005 goto out_uninit_tx_channels;
6006
6007 niudbg(IFUP, "%s: Initialize classifier\n", np->dev->name);
6008 err = niu_init_classifier_hw(np);
6009 if (err)
6010 goto out_uninit_rx_channels;
6011
6012 niudbg(IFUP, "%s: Initialize ZCP\n", np->dev->name);
6013 err = niu_init_zcp(np);
6014 if (err)
6015 goto out_uninit_rx_channels;
6016
6017 niudbg(IFUP, "%s: Initialize IPP\n", np->dev->name);
6018 err = niu_init_ipp(np);
6019 if (err)
6020 goto out_uninit_rx_channels;
6021
6022 niudbg(IFUP, "%s: Initialize MAC\n", np->dev->name);
6023 err = niu_init_mac(np);
6024 if (err)
6025 goto out_uninit_ipp;
6026
6027 return 0;
6028
6029 out_uninit_ipp:
6030 niudbg(IFUP, "%s: Uninit IPP\n", np->dev->name);
6031 niu_disable_ipp(np);
6032
6033 out_uninit_rx_channels:
6034 niudbg(IFUP, "%s: Uninit RX channels\n", np->dev->name);
6035 niu_stop_rx_channels(np);
6036 niu_reset_rx_channels(np);
6037
6038 out_uninit_tx_channels:
6039 niudbg(IFUP, "%s: Uninit TX channels\n", np->dev->name);
6040 niu_stop_tx_channels(np);
6041 niu_reset_tx_channels(np);
6042
6043 return err;
6044 }
6045
6046 static void niu_stop_hw(struct niu *np)
6047 {
6048 niudbg(IFDOWN, "%s: Disable interrupts\n", np->dev->name);
6049 niu_enable_interrupts(np, 0);
6050
6051 niudbg(IFDOWN, "%s: Disable RX MAC\n", np->dev->name);
6052 niu_enable_rx_mac(np, 0);
6053
6054 niudbg(IFDOWN, "%s: Disable IPP\n", np->dev->name);
6055 niu_disable_ipp(np);
6056
6057 niudbg(IFDOWN, "%s: Stop TX channels\n", np->dev->name);
6058 niu_stop_tx_channels(np);
6059
6060 niudbg(IFDOWN, "%s: Stop RX channels\n", np->dev->name);
6061 niu_stop_rx_channels(np);
6062
6063 niudbg(IFDOWN, "%s: Reset TX channels\n", np->dev->name);
6064 niu_reset_tx_channels(np);
6065
6066 niudbg(IFDOWN, "%s: Reset RX channels\n", np->dev->name);
6067 niu_reset_rx_channels(np);
6068 }
6069
6070 static void niu_set_irq_name(struct niu *np)
6071 {
6072 int port = np->port;
6073 int i, j = 1;
6074
6075 sprintf(np->irq_name[0], "%s:MAC", np->dev->name);
6076
6077 if (port == 0) {
6078 sprintf(np->irq_name[1], "%s:MIF", np->dev->name);
6079 sprintf(np->irq_name[2], "%s:SYSERR", np->dev->name);
6080 j = 3;
6081 }
6082
6083 for (i = 0; i < np->num_ldg - j; i++) {
6084 if (i < np->num_rx_rings)
6085 sprintf(np->irq_name[i+j], "%s-rx-%d",
6086 np->dev->name, i);
6087 else if (i < np->num_tx_rings + np->num_rx_rings)
6088 sprintf(np->irq_name[i+j], "%s-tx-%d", np->dev->name,
6089 i - np->num_rx_rings);
6090 }
6091 }
6092
6093 static int niu_request_irq(struct niu *np)
6094 {
6095 int i, j, err;
6096
6097 niu_set_irq_name(np);
6098
6099 err = 0;
6100 for (i = 0; i < np->num_ldg; i++) {
6101 struct niu_ldg *lp = &np->ldg[i];
6102
6103 err = request_irq(lp->irq, niu_interrupt,
6104 IRQF_SHARED | IRQF_SAMPLE_RANDOM,
6105 np->irq_name[i], lp);
6106 if (err)
6107 goto out_free_irqs;
6108
6109 }
6110
6111 return 0;
6112
6113 out_free_irqs:
6114 for (j = 0; j < i; j++) {
6115 struct niu_ldg *lp = &np->ldg[j];
6116
6117 free_irq(lp->irq, lp);
6118 }
6119 return err;
6120 }
6121
6122 static void niu_free_irq(struct niu *np)
6123 {
6124 int i;
6125
6126 for (i = 0; i < np->num_ldg; i++) {
6127 struct niu_ldg *lp = &np->ldg[i];
6128
6129 free_irq(lp->irq, lp);
6130 }
6131 }
6132
6133 static void niu_enable_napi(struct niu *np)
6134 {
6135 int i;
6136
6137 for (i = 0; i < np->num_ldg; i++)
6138 napi_enable(&np->ldg[i].napi);
6139 }
6140
6141 static void niu_disable_napi(struct niu *np)
6142 {
6143 int i;
6144
6145 for (i = 0; i < np->num_ldg; i++)
6146 napi_disable(&np->ldg[i].napi);
6147 }
6148
6149 static int niu_open(struct net_device *dev)
6150 {
6151 struct niu *np = netdev_priv(dev);
6152 int err;
6153
6154 netif_carrier_off(dev);
6155
6156 err = niu_alloc_channels(np);
6157 if (err)
6158 goto out_err;
6159
6160 err = niu_enable_interrupts(np, 0);
6161 if (err)
6162 goto out_free_channels;
6163
6164 err = niu_request_irq(np);
6165 if (err)
6166 goto out_free_channels;
6167
6168 niu_enable_napi(np);
6169
6170 spin_lock_irq(&np->lock);
6171
6172 err = niu_init_hw(np);
6173 if (!err) {
6174 init_timer(&np->timer);
6175 np->timer.expires = jiffies + HZ;
6176 np->timer.data = (unsigned long) np;
6177 np->timer.function = niu_timer;
6178
6179 err = niu_enable_interrupts(np, 1);
6180 if (err)
6181 niu_stop_hw(np);
6182 }
6183
6184 spin_unlock_irq(&np->lock);
6185
6186 if (err) {
6187 niu_disable_napi(np);
6188 goto out_free_irq;
6189 }
6190
6191 netif_tx_start_all_queues(dev);
6192
6193 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6194 netif_carrier_on(dev);
6195
6196 add_timer(&np->timer);
6197
6198 return 0;
6199
6200 out_free_irq:
6201 niu_free_irq(np);
6202
6203 out_free_channels:
6204 niu_free_channels(np);
6205
6206 out_err:
6207 return err;
6208 }
6209
6210 static void niu_full_shutdown(struct niu *np, struct net_device *dev)
6211 {
6212 cancel_work_sync(&np->reset_task);
6213
6214 niu_disable_napi(np);
6215 netif_tx_stop_all_queues(dev);
6216
6217 del_timer_sync(&np->timer);
6218
6219 spin_lock_irq(&np->lock);
6220
6221 niu_stop_hw(np);
6222
6223 spin_unlock_irq(&np->lock);
6224 }
6225
6226 static int niu_close(struct net_device *dev)
6227 {
6228 struct niu *np = netdev_priv(dev);
6229
6230 niu_full_shutdown(np, dev);
6231
6232 niu_free_irq(np);
6233
6234 niu_free_channels(np);
6235
6236 niu_handle_led(np, 0);
6237
6238 return 0;
6239 }
6240
6241 static void niu_sync_xmac_stats(struct niu *np)
6242 {
6243 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
6244
6245 mp->tx_frames += nr64_mac(TXMAC_FRM_CNT);
6246 mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT);
6247
6248 mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT);
6249 mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT);
6250 mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT);
6251 mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT);
6252 mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT);
6253 mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1);
6254 mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2);
6255 mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3);
6256 mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4);
6257 mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5);
6258 mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6);
6259 mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7);
6260 mp->rx_octets += nr64_mac(RXMAC_BT_CNT);
6261 mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT);
6262 mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT);
6263 mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT);
6264 }
6265
6266 static void niu_sync_bmac_stats(struct niu *np)
6267 {
6268 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
6269
6270 mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT);
6271 mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT);
6272
6273 mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT);
6274 mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6275 mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6276 mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT);
6277 }
6278
6279 static void niu_sync_mac_stats(struct niu *np)
6280 {
6281 if (np->flags & NIU_FLAGS_XMAC)
6282 niu_sync_xmac_stats(np);
6283 else
6284 niu_sync_bmac_stats(np);
6285 }
6286
6287 static void niu_get_rx_stats(struct niu *np)
6288 {
6289 unsigned long pkts, dropped, errors, bytes;
6290 int i;
6291
6292 pkts = dropped = errors = bytes = 0;
6293 for (i = 0; i < np->num_rx_rings; i++) {
6294 struct rx_ring_info *rp = &np->rx_rings[i];
6295
6296 niu_sync_rx_discard_stats(np, rp, 0);
6297
6298 pkts += rp->rx_packets;
6299 bytes += rp->rx_bytes;
6300 dropped += rp->rx_dropped;
6301 errors += rp->rx_errors;
6302 }
6303 np->dev->stats.rx_packets = pkts;
6304 np->dev->stats.rx_bytes = bytes;
6305 np->dev->stats.rx_dropped = dropped;
6306 np->dev->stats.rx_errors = errors;
6307 }
6308
6309 static void niu_get_tx_stats(struct niu *np)
6310 {
6311 unsigned long pkts, errors, bytes;
6312 int i;
6313
6314 pkts = errors = bytes = 0;
6315 for (i = 0; i < np->num_tx_rings; i++) {
6316 struct tx_ring_info *rp = &np->tx_rings[i];
6317
6318 pkts += rp->tx_packets;
6319 bytes += rp->tx_bytes;
6320 errors += rp->tx_errors;
6321 }
6322 np->dev->stats.tx_packets = pkts;
6323 np->dev->stats.tx_bytes = bytes;
6324 np->dev->stats.tx_errors = errors;
6325 }
6326
6327 static struct net_device_stats *niu_get_stats(struct net_device *dev)
6328 {
6329 struct niu *np = netdev_priv(dev);
6330
6331 niu_get_rx_stats(np);
6332 niu_get_tx_stats(np);
6333
6334 return &dev->stats;
6335 }
6336
6337 static void niu_load_hash_xmac(struct niu *np, u16 *hash)
6338 {
6339 int i;
6340
6341 for (i = 0; i < 16; i++)
6342 nw64_mac(XMAC_HASH_TBL(i), hash[i]);
6343 }
6344
6345 static void niu_load_hash_bmac(struct niu *np, u16 *hash)
6346 {
6347 int i;
6348
6349 for (i = 0; i < 16; i++)
6350 nw64_mac(BMAC_HASH_TBL(i), hash[i]);
6351 }
6352
6353 static void niu_load_hash(struct niu *np, u16 *hash)
6354 {
6355 if (np->flags & NIU_FLAGS_XMAC)
6356 niu_load_hash_xmac(np, hash);
6357 else
6358 niu_load_hash_bmac(np, hash);
6359 }
6360
6361 static void niu_set_rx_mode(struct net_device *dev)
6362 {
6363 struct niu *np = netdev_priv(dev);
6364 int i, alt_cnt, err;
6365 struct dev_addr_list *addr;
6366 struct netdev_hw_addr *ha;
6367 unsigned long flags;
6368 u16 hash[16] = { 0, };
6369
6370 spin_lock_irqsave(&np->lock, flags);
6371 niu_enable_rx_mac(np, 0);
6372
6373 np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC);
6374 if (dev->flags & IFF_PROMISC)
6375 np->flags |= NIU_FLAGS_PROMISC;
6376 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 0))
6377 np->flags |= NIU_FLAGS_MCAST;
6378
6379 alt_cnt = dev->uc.count;
6380 if (alt_cnt > niu_num_alt_addr(np)) {
6381 alt_cnt = 0;
6382 np->flags |= NIU_FLAGS_PROMISC;
6383 }
6384
6385 if (alt_cnt) {
6386 int index = 0;
6387
6388 list_for_each_entry(ha, &dev->uc.list, list) {
6389 err = niu_set_alt_mac(np, index, ha->addr);
6390 if (err)
6391 printk(KERN_WARNING PFX "%s: Error %d "
6392 "adding alt mac %d\n",
6393 dev->name, err, index);
6394 err = niu_enable_alt_mac(np, index, 1);
6395 if (err)
6396 printk(KERN_WARNING PFX "%s: Error %d "
6397 "enabling alt mac %d\n",
6398 dev->name, err, index);
6399
6400 index++;
6401 }
6402 } else {
6403 int alt_start;
6404 if (np->flags & NIU_FLAGS_XMAC)
6405 alt_start = 0;
6406 else
6407 alt_start = 1;
6408 for (i = alt_start; i < niu_num_alt_addr(np); i++) {
6409 err = niu_enable_alt_mac(np, i, 0);
6410 if (err)
6411 printk(KERN_WARNING PFX "%s: Error %d "
6412 "disabling alt mac %d\n",
6413 dev->name, err, i);
6414 }
6415 }
6416 if (dev->flags & IFF_ALLMULTI) {
6417 for (i = 0; i < 16; i++)
6418 hash[i] = 0xffff;
6419 } else if (dev->mc_count > 0) {
6420 for (addr = dev->mc_list; addr; addr = addr->next) {
6421 u32 crc = ether_crc_le(ETH_ALEN, addr->da_addr);
6422
6423 crc >>= 24;
6424 hash[crc >> 4] |= (1 << (15 - (crc & 0xf)));
6425 }
6426 }
6427
6428 if (np->flags & NIU_FLAGS_MCAST)
6429 niu_load_hash(np, hash);
6430
6431 niu_enable_rx_mac(np, 1);
6432 spin_unlock_irqrestore(&np->lock, flags);
6433 }
6434
6435 static int niu_set_mac_addr(struct net_device *dev, void *p)
6436 {
6437 struct niu *np = netdev_priv(dev);
6438 struct sockaddr *addr = p;
6439 unsigned long flags;
6440
6441 if (!is_valid_ether_addr(addr->sa_data))
6442 return -EINVAL;
6443
6444 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
6445
6446 if (!netif_running(dev))
6447 return 0;
6448
6449 spin_lock_irqsave(&np->lock, flags);
6450 niu_enable_rx_mac(np, 0);
6451 niu_set_primary_mac(np, dev->dev_addr);
6452 niu_enable_rx_mac(np, 1);
6453 spin_unlock_irqrestore(&np->lock, flags);
6454
6455 return 0;
6456 }
6457
6458 static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6459 {
6460 return -EOPNOTSUPP;
6461 }
6462
6463 static void niu_netif_stop(struct niu *np)
6464 {
6465 np->dev->trans_start = jiffies; /* prevent tx timeout */
6466
6467 niu_disable_napi(np);
6468
6469 netif_tx_disable(np->dev);
6470 }
6471
6472 static void niu_netif_start(struct niu *np)
6473 {
6474 /* NOTE: unconditional netif_wake_queue is only appropriate
6475 * so long as all callers are assured to have free tx slots
6476 * (such as after niu_init_hw).
6477 */
6478 netif_tx_wake_all_queues(np->dev);
6479
6480 niu_enable_napi(np);
6481
6482 niu_enable_interrupts(np, 1);
6483 }
6484
6485 static void niu_reset_buffers(struct niu *np)
6486 {
6487 int i, j, k, err;
6488
6489 if (np->rx_rings) {
6490 for (i = 0; i < np->num_rx_rings; i++) {
6491 struct rx_ring_info *rp = &np->rx_rings[i];
6492
6493 for (j = 0, k = 0; j < MAX_RBR_RING_SIZE; j++) {
6494 struct page *page;
6495
6496 page = rp->rxhash[j];
6497 while (page) {
6498 struct page *next =
6499 (struct page *) page->mapping;
6500 u64 base = page->index;
6501 base = base >> RBR_DESCR_ADDR_SHIFT;
6502 rp->rbr[k++] = cpu_to_le32(base);
6503 page = next;
6504 }
6505 }
6506 for (; k < MAX_RBR_RING_SIZE; k++) {
6507 err = niu_rbr_add_page(np, rp, GFP_ATOMIC, k);
6508 if (unlikely(err))
6509 break;
6510 }
6511
6512 rp->rbr_index = rp->rbr_table_size - 1;
6513 rp->rcr_index = 0;
6514 rp->rbr_pending = 0;
6515 rp->rbr_refill_pending = 0;
6516 }
6517 }
6518 if (np->tx_rings) {
6519 for (i = 0; i < np->num_tx_rings; i++) {
6520 struct tx_ring_info *rp = &np->tx_rings[i];
6521
6522 for (j = 0; j < MAX_TX_RING_SIZE; j++) {
6523 if (rp->tx_buffs[j].skb)
6524 (void) release_tx_packet(np, rp, j);
6525 }
6526
6527 rp->pending = MAX_TX_RING_SIZE;
6528 rp->prod = 0;
6529 rp->cons = 0;
6530 rp->wrap_bit = 0;
6531 }
6532 }
6533 }
6534
6535 static void niu_reset_task(struct work_struct *work)
6536 {
6537 struct niu *np = container_of(work, struct niu, reset_task);
6538 unsigned long flags;
6539 int err;
6540
6541 spin_lock_irqsave(&np->lock, flags);
6542 if (!netif_running(np->dev)) {
6543 spin_unlock_irqrestore(&np->lock, flags);
6544 return;
6545 }
6546
6547 spin_unlock_irqrestore(&np->lock, flags);
6548
6549 del_timer_sync(&np->timer);
6550
6551 niu_netif_stop(np);
6552
6553 spin_lock_irqsave(&np->lock, flags);
6554
6555 niu_stop_hw(np);
6556
6557 spin_unlock_irqrestore(&np->lock, flags);
6558
6559 niu_reset_buffers(np);
6560
6561 spin_lock_irqsave(&np->lock, flags);
6562
6563 err = niu_init_hw(np);
6564 if (!err) {
6565 np->timer.expires = jiffies + HZ;
6566 add_timer(&np->timer);
6567 niu_netif_start(np);
6568 }
6569
6570 spin_unlock_irqrestore(&np->lock, flags);
6571 }
6572
6573 static void niu_tx_timeout(struct net_device *dev)
6574 {
6575 struct niu *np = netdev_priv(dev);
6576
6577 dev_err(np->device, PFX "%s: Transmit timed out, resetting\n",
6578 dev->name);
6579
6580 schedule_work(&np->reset_task);
6581 }
6582
6583 static void niu_set_txd(struct tx_ring_info *rp, int index,
6584 u64 mapping, u64 len, u64 mark,
6585 u64 n_frags)
6586 {
6587 __le64 *desc = &rp->descr[index];
6588
6589 *desc = cpu_to_le64(mark |
6590 (n_frags << TX_DESC_NUM_PTR_SHIFT) |
6591 (len << TX_DESC_TR_LEN_SHIFT) |
6592 (mapping & TX_DESC_SAD));
6593 }
6594
6595 static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr,
6596 u64 pad_bytes, u64 len)
6597 {
6598 u16 eth_proto, eth_proto_inner;
6599 u64 csum_bits, l3off, ihl, ret;
6600 u8 ip_proto;
6601 int ipv6;
6602
6603 eth_proto = be16_to_cpu(ehdr->h_proto);
6604 eth_proto_inner = eth_proto;
6605 if (eth_proto == ETH_P_8021Q) {
6606 struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr;
6607 __be16 val = vp->h_vlan_encapsulated_proto;
6608
6609 eth_proto_inner = be16_to_cpu(val);
6610 }
6611
6612 ipv6 = ihl = 0;
6613 switch (skb->protocol) {
6614 case cpu_to_be16(ETH_P_IP):
6615 ip_proto = ip_hdr(skb)->protocol;
6616 ihl = ip_hdr(skb)->ihl;
6617 break;
6618 case cpu_to_be16(ETH_P_IPV6):
6619 ip_proto = ipv6_hdr(skb)->nexthdr;
6620 ihl = (40 >> 2);
6621 ipv6 = 1;
6622 break;
6623 default:
6624 ip_proto = ihl = 0;
6625 break;
6626 }
6627
6628 csum_bits = TXHDR_CSUM_NONE;
6629 if (skb->ip_summed == CHECKSUM_PARTIAL) {
6630 u64 start, stuff;
6631
6632 csum_bits = (ip_proto == IPPROTO_TCP ?
6633 TXHDR_CSUM_TCP :
6634 (ip_proto == IPPROTO_UDP ?
6635 TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP));
6636
6637 start = skb_transport_offset(skb) -
6638 (pad_bytes + sizeof(struct tx_pkt_hdr));
6639 stuff = start + skb->csum_offset;
6640
6641 csum_bits |= (start / 2) << TXHDR_L4START_SHIFT;
6642 csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT;
6643 }
6644
6645 l3off = skb_network_offset(skb) -
6646 (pad_bytes + sizeof(struct tx_pkt_hdr));
6647
6648 ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) |
6649 (len << TXHDR_LEN_SHIFT) |
6650 ((l3off / 2) << TXHDR_L3START_SHIFT) |
6651 (ihl << TXHDR_IHL_SHIFT) |
6652 ((eth_proto_inner < 1536) ? TXHDR_LLC : 0) |
6653 ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) |
6654 (ipv6 ? TXHDR_IP_VER : 0) |
6655 csum_bits);
6656
6657 return ret;
6658 }
6659
6660 static int niu_start_xmit(struct sk_buff *skb, struct net_device *dev)
6661 {
6662 struct niu *np = netdev_priv(dev);
6663 unsigned long align, headroom;
6664 struct netdev_queue *txq;
6665 struct tx_ring_info *rp;
6666 struct tx_pkt_hdr *tp;
6667 unsigned int len, nfg;
6668 struct ethhdr *ehdr;
6669 int prod, i, tlen;
6670 u64 mapping, mrk;
6671
6672 i = skb_get_queue_mapping(skb);
6673 rp = &np->tx_rings[i];
6674 txq = netdev_get_tx_queue(dev, i);
6675
6676 if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) {
6677 netif_tx_stop_queue(txq);
6678 dev_err(np->device, PFX "%s: BUG! Tx ring full when "
6679 "queue awake!\n", dev->name);
6680 rp->tx_errors++;
6681 return NETDEV_TX_BUSY;
6682 }
6683
6684 if (skb->len < ETH_ZLEN) {
6685 unsigned int pad_bytes = ETH_ZLEN - skb->len;
6686
6687 if (skb_pad(skb, pad_bytes))
6688 goto out;
6689 skb_put(skb, pad_bytes);
6690 }
6691
6692 len = sizeof(struct tx_pkt_hdr) + 15;
6693 if (skb_headroom(skb) < len) {
6694 struct sk_buff *skb_new;
6695
6696 skb_new = skb_realloc_headroom(skb, len);
6697 if (!skb_new) {
6698 rp->tx_errors++;
6699 goto out_drop;
6700 }
6701 kfree_skb(skb);
6702 skb = skb_new;
6703 } else
6704 skb_orphan(skb);
6705
6706 align = ((unsigned long) skb->data & (16 - 1));
6707 headroom = align + sizeof(struct tx_pkt_hdr);
6708
6709 ehdr = (struct ethhdr *) skb->data;
6710 tp = (struct tx_pkt_hdr *) skb_push(skb, headroom);
6711
6712 len = skb->len - sizeof(struct tx_pkt_hdr);
6713 tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len));
6714 tp->resv = 0;
6715
6716 len = skb_headlen(skb);
6717 mapping = np->ops->map_single(np->device, skb->data,
6718 len, DMA_TO_DEVICE);
6719
6720 prod = rp->prod;
6721
6722 rp->tx_buffs[prod].skb = skb;
6723 rp->tx_buffs[prod].mapping = mapping;
6724
6725 mrk = TX_DESC_SOP;
6726 if (++rp->mark_counter == rp->mark_freq) {
6727 rp->mark_counter = 0;
6728 mrk |= TX_DESC_MARK;
6729 rp->mark_pending++;
6730 }
6731
6732 tlen = len;
6733 nfg = skb_shinfo(skb)->nr_frags;
6734 while (tlen > 0) {
6735 tlen -= MAX_TX_DESC_LEN;
6736 nfg++;
6737 }
6738
6739 while (len > 0) {
6740 unsigned int this_len = len;
6741
6742 if (this_len > MAX_TX_DESC_LEN)
6743 this_len = MAX_TX_DESC_LEN;
6744
6745 niu_set_txd(rp, prod, mapping, this_len, mrk, nfg);
6746 mrk = nfg = 0;
6747
6748 prod = NEXT_TX(rp, prod);
6749 mapping += this_len;
6750 len -= this_len;
6751 }
6752
6753 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6754 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6755
6756 len = frag->size;
6757 mapping = np->ops->map_page(np->device, frag->page,
6758 frag->page_offset, len,
6759 DMA_TO_DEVICE);
6760
6761 rp->tx_buffs[prod].skb = NULL;
6762 rp->tx_buffs[prod].mapping = mapping;
6763
6764 niu_set_txd(rp, prod, mapping, len, 0, 0);
6765
6766 prod = NEXT_TX(rp, prod);
6767 }
6768
6769 if (prod < rp->prod)
6770 rp->wrap_bit ^= TX_RING_KICK_WRAP;
6771 rp->prod = prod;
6772
6773 nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3));
6774
6775 if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) {
6776 netif_tx_stop_queue(txq);
6777 if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))
6778 netif_tx_wake_queue(txq);
6779 }
6780
6781 out:
6782 return NETDEV_TX_OK;
6783
6784 out_drop:
6785 rp->tx_errors++;
6786 kfree_skb(skb);
6787 goto out;
6788 }
6789
6790 static int niu_change_mtu(struct net_device *dev, int new_mtu)
6791 {
6792 struct niu *np = netdev_priv(dev);
6793 int err, orig_jumbo, new_jumbo;
6794
6795 if (new_mtu < 68 || new_mtu > NIU_MAX_MTU)
6796 return -EINVAL;
6797
6798 orig_jumbo = (dev->mtu > ETH_DATA_LEN);
6799 new_jumbo = (new_mtu > ETH_DATA_LEN);
6800
6801 dev->mtu = new_mtu;
6802
6803 if (!netif_running(dev) ||
6804 (orig_jumbo == new_jumbo))
6805 return 0;
6806
6807 niu_full_shutdown(np, dev);
6808
6809 niu_free_channels(np);
6810
6811 niu_enable_napi(np);
6812
6813 err = niu_alloc_channels(np);
6814 if (err)
6815 return err;
6816
6817 spin_lock_irq(&np->lock);
6818
6819 err = niu_init_hw(np);
6820 if (!err) {
6821 init_timer(&np->timer);
6822 np->timer.expires = jiffies + HZ;
6823 np->timer.data = (unsigned long) np;
6824 np->timer.function = niu_timer;
6825
6826 err = niu_enable_interrupts(np, 1);
6827 if (err)
6828 niu_stop_hw(np);
6829 }
6830
6831 spin_unlock_irq(&np->lock);
6832
6833 if (!err) {
6834 netif_tx_start_all_queues(dev);
6835 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6836 netif_carrier_on(dev);
6837
6838 add_timer(&np->timer);
6839 }
6840
6841 return err;
6842 }
6843
6844 static void niu_get_drvinfo(struct net_device *dev,
6845 struct ethtool_drvinfo *info)
6846 {
6847 struct niu *np = netdev_priv(dev);
6848 struct niu_vpd *vpd = &np->vpd;
6849
6850 strcpy(info->driver, DRV_MODULE_NAME);
6851 strcpy(info->version, DRV_MODULE_VERSION);
6852 sprintf(info->fw_version, "%d.%d",
6853 vpd->fcode_major, vpd->fcode_minor);
6854 if (np->parent->plat_type != PLAT_TYPE_NIU)
6855 strcpy(info->bus_info, pci_name(np->pdev));
6856 }
6857
6858 static int niu_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6859 {
6860 struct niu *np = netdev_priv(dev);
6861 struct niu_link_config *lp;
6862
6863 lp = &np->link_config;
6864
6865 memset(cmd, 0, sizeof(*cmd));
6866 cmd->phy_address = np->phy_addr;
6867 cmd->supported = lp->supported;
6868 cmd->advertising = lp->active_advertising;
6869 cmd->autoneg = lp->active_autoneg;
6870 cmd->speed = lp->active_speed;
6871 cmd->duplex = lp->active_duplex;
6872 cmd->port = (np->flags & NIU_FLAGS_FIBER) ? PORT_FIBRE : PORT_TP;
6873 cmd->transceiver = (np->flags & NIU_FLAGS_XCVR_SERDES) ?
6874 XCVR_EXTERNAL : XCVR_INTERNAL;
6875
6876 return 0;
6877 }
6878
6879 static int niu_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6880 {
6881 struct niu *np = netdev_priv(dev);
6882 struct niu_link_config *lp = &np->link_config;
6883
6884 lp->advertising = cmd->advertising;
6885 lp->speed = cmd->speed;
6886 lp->duplex = cmd->duplex;
6887 lp->autoneg = cmd->autoneg;
6888 return niu_init_link(np);
6889 }
6890
6891 static u32 niu_get_msglevel(struct net_device *dev)
6892 {
6893 struct niu *np = netdev_priv(dev);
6894 return np->msg_enable;
6895 }
6896
6897 static void niu_set_msglevel(struct net_device *dev, u32 value)
6898 {
6899 struct niu *np = netdev_priv(dev);
6900 np->msg_enable = value;
6901 }
6902
6903 static int niu_nway_reset(struct net_device *dev)
6904 {
6905 struct niu *np = netdev_priv(dev);
6906
6907 if (np->link_config.autoneg)
6908 return niu_init_link(np);
6909
6910 return 0;
6911 }
6912
6913 static int niu_get_eeprom_len(struct net_device *dev)
6914 {
6915 struct niu *np = netdev_priv(dev);
6916
6917 return np->eeprom_len;
6918 }
6919
6920 static int niu_get_eeprom(struct net_device *dev,
6921 struct ethtool_eeprom *eeprom, u8 *data)
6922 {
6923 struct niu *np = netdev_priv(dev);
6924 u32 offset, len, val;
6925
6926 offset = eeprom->offset;
6927 len = eeprom->len;
6928
6929 if (offset + len < offset)
6930 return -EINVAL;
6931 if (offset >= np->eeprom_len)
6932 return -EINVAL;
6933 if (offset + len > np->eeprom_len)
6934 len = eeprom->len = np->eeprom_len - offset;
6935
6936 if (offset & 3) {
6937 u32 b_offset, b_count;
6938
6939 b_offset = offset & 3;
6940 b_count = 4 - b_offset;
6941 if (b_count > len)
6942 b_count = len;
6943
6944 val = nr64(ESPC_NCR((offset - b_offset) / 4));
6945 memcpy(data, ((char *)&val) + b_offset, b_count);
6946 data += b_count;
6947 len -= b_count;
6948 offset += b_count;
6949 }
6950 while (len >= 4) {
6951 val = nr64(ESPC_NCR(offset / 4));
6952 memcpy(data, &val, 4);
6953 data += 4;
6954 len -= 4;
6955 offset += 4;
6956 }
6957 if (len) {
6958 val = nr64(ESPC_NCR(offset / 4));
6959 memcpy(data, &val, len);
6960 }
6961 return 0;
6962 }
6963
6964 static void niu_ethflow_to_l3proto(int flow_type, u8 *pid)
6965 {
6966 switch (flow_type) {
6967 case TCP_V4_FLOW:
6968 case TCP_V6_FLOW:
6969 *pid = IPPROTO_TCP;
6970 break;
6971 case UDP_V4_FLOW:
6972 case UDP_V6_FLOW:
6973 *pid = IPPROTO_UDP;
6974 break;
6975 case SCTP_V4_FLOW:
6976 case SCTP_V6_FLOW:
6977 *pid = IPPROTO_SCTP;
6978 break;
6979 case AH_V4_FLOW:
6980 case AH_V6_FLOW:
6981 *pid = IPPROTO_AH;
6982 break;
6983 case ESP_V4_FLOW:
6984 case ESP_V6_FLOW:
6985 *pid = IPPROTO_ESP;
6986 break;
6987 default:
6988 *pid = 0;
6989 break;
6990 }
6991 }
6992
6993 static int niu_class_to_ethflow(u64 class, int *flow_type)
6994 {
6995 switch (class) {
6996 case CLASS_CODE_TCP_IPV4:
6997 *flow_type = TCP_V4_FLOW;
6998 break;
6999 case CLASS_CODE_UDP_IPV4:
7000 *flow_type = UDP_V4_FLOW;
7001 break;
7002 case CLASS_CODE_AH_ESP_IPV4:
7003 *flow_type = AH_V4_FLOW;
7004 break;
7005 case CLASS_CODE_SCTP_IPV4:
7006 *flow_type = SCTP_V4_FLOW;
7007 break;
7008 case CLASS_CODE_TCP_IPV6:
7009 *flow_type = TCP_V6_FLOW;
7010 break;
7011 case CLASS_CODE_UDP_IPV6:
7012 *flow_type = UDP_V6_FLOW;
7013 break;
7014 case CLASS_CODE_AH_ESP_IPV6:
7015 *flow_type = AH_V6_FLOW;
7016 break;
7017 case CLASS_CODE_SCTP_IPV6:
7018 *flow_type = SCTP_V6_FLOW;
7019 break;
7020 case CLASS_CODE_USER_PROG1:
7021 case CLASS_CODE_USER_PROG2:
7022 case CLASS_CODE_USER_PROG3:
7023 case CLASS_CODE_USER_PROG4:
7024 *flow_type = IP_USER_FLOW;
7025 break;
7026 default:
7027 return 0;
7028 }
7029
7030 return 1;
7031 }
7032
7033 static int niu_ethflow_to_class(int flow_type, u64 *class)
7034 {
7035 switch (flow_type) {
7036 case TCP_V4_FLOW:
7037 *class = CLASS_CODE_TCP_IPV4;
7038 break;
7039 case UDP_V4_FLOW:
7040 *class = CLASS_CODE_UDP_IPV4;
7041 break;
7042 case AH_V4_FLOW:
7043 case ESP_V4_FLOW:
7044 *class = CLASS_CODE_AH_ESP_IPV4;
7045 break;
7046 case SCTP_V4_FLOW:
7047 *class = CLASS_CODE_SCTP_IPV4;
7048 break;
7049 case TCP_V6_FLOW:
7050 *class = CLASS_CODE_TCP_IPV6;
7051 break;
7052 case UDP_V6_FLOW:
7053 *class = CLASS_CODE_UDP_IPV6;
7054 break;
7055 case AH_V6_FLOW:
7056 case ESP_V6_FLOW:
7057 *class = CLASS_CODE_AH_ESP_IPV6;
7058 break;
7059 case SCTP_V6_FLOW:
7060 *class = CLASS_CODE_SCTP_IPV6;
7061 break;
7062 default:
7063 return 0;
7064 }
7065
7066 return 1;
7067 }
7068
7069 static u64 niu_flowkey_to_ethflow(u64 flow_key)
7070 {
7071 u64 ethflow = 0;
7072
7073 if (flow_key & FLOW_KEY_L2DA)
7074 ethflow |= RXH_L2DA;
7075 if (flow_key & FLOW_KEY_VLAN)
7076 ethflow |= RXH_VLAN;
7077 if (flow_key & FLOW_KEY_IPSA)
7078 ethflow |= RXH_IP_SRC;
7079 if (flow_key & FLOW_KEY_IPDA)
7080 ethflow |= RXH_IP_DST;
7081 if (flow_key & FLOW_KEY_PROTO)
7082 ethflow |= RXH_L3_PROTO;
7083 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT))
7084 ethflow |= RXH_L4_B_0_1;
7085 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT))
7086 ethflow |= RXH_L4_B_2_3;
7087
7088 return ethflow;
7089
7090 }
7091
7092 static int niu_ethflow_to_flowkey(u64 ethflow, u64 *flow_key)
7093 {
7094 u64 key = 0;
7095
7096 if (ethflow & RXH_L2DA)
7097 key |= FLOW_KEY_L2DA;
7098 if (ethflow & RXH_VLAN)
7099 key |= FLOW_KEY_VLAN;
7100 if (ethflow & RXH_IP_SRC)
7101 key |= FLOW_KEY_IPSA;
7102 if (ethflow & RXH_IP_DST)
7103 key |= FLOW_KEY_IPDA;
7104 if (ethflow & RXH_L3_PROTO)
7105 key |= FLOW_KEY_PROTO;
7106 if (ethflow & RXH_L4_B_0_1)
7107 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT);
7108 if (ethflow & RXH_L4_B_2_3)
7109 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT);
7110
7111 *flow_key = key;
7112
7113 return 1;
7114
7115 }
7116
7117 static int niu_get_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
7118 {
7119 u64 class;
7120
7121 nfc->data = 0;
7122
7123 if (!niu_ethflow_to_class(nfc->flow_type, &class))
7124 return -EINVAL;
7125
7126 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7127 TCAM_KEY_DISC)
7128 nfc->data = RXH_DISCARD;
7129 else
7130 nfc->data = niu_flowkey_to_ethflow(np->parent->flow_key[class -
7131 CLASS_CODE_USER_PROG1]);
7132 return 0;
7133 }
7134
7135 static void niu_get_ip4fs_from_tcam_key(struct niu_tcam_entry *tp,
7136 struct ethtool_rx_flow_spec *fsp)
7137 {
7138
7139 fsp->h_u.tcp_ip4_spec.ip4src = (tp->key[3] & TCAM_V4KEY3_SADDR) >>
7140 TCAM_V4KEY3_SADDR_SHIFT;
7141 fsp->h_u.tcp_ip4_spec.ip4dst = (tp->key[3] & TCAM_V4KEY3_DADDR) >>
7142 TCAM_V4KEY3_DADDR_SHIFT;
7143 fsp->m_u.tcp_ip4_spec.ip4src = (tp->key_mask[3] & TCAM_V4KEY3_SADDR) >>
7144 TCAM_V4KEY3_SADDR_SHIFT;
7145 fsp->m_u.tcp_ip4_spec.ip4dst = (tp->key_mask[3] & TCAM_V4KEY3_DADDR) >>
7146 TCAM_V4KEY3_DADDR_SHIFT;
7147
7148 fsp->h_u.tcp_ip4_spec.ip4src =
7149 cpu_to_be32(fsp->h_u.tcp_ip4_spec.ip4src);
7150 fsp->m_u.tcp_ip4_spec.ip4src =
7151 cpu_to_be32(fsp->m_u.tcp_ip4_spec.ip4src);
7152 fsp->h_u.tcp_ip4_spec.ip4dst =
7153 cpu_to_be32(fsp->h_u.tcp_ip4_spec.ip4dst);
7154 fsp->m_u.tcp_ip4_spec.ip4dst =
7155 cpu_to_be32(fsp->m_u.tcp_ip4_spec.ip4dst);
7156
7157 fsp->h_u.tcp_ip4_spec.tos = (tp->key[2] & TCAM_V4KEY2_TOS) >>
7158 TCAM_V4KEY2_TOS_SHIFT;
7159 fsp->m_u.tcp_ip4_spec.tos = (tp->key_mask[2] & TCAM_V4KEY2_TOS) >>
7160 TCAM_V4KEY2_TOS_SHIFT;
7161
7162 switch (fsp->flow_type) {
7163 case TCP_V4_FLOW:
7164 case UDP_V4_FLOW:
7165 case SCTP_V4_FLOW:
7166 fsp->h_u.tcp_ip4_spec.psrc =
7167 ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7168 TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7169 fsp->h_u.tcp_ip4_spec.pdst =
7170 ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7171 TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7172 fsp->m_u.tcp_ip4_spec.psrc =
7173 ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7174 TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7175 fsp->m_u.tcp_ip4_spec.pdst =
7176 ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7177 TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7178
7179 fsp->h_u.tcp_ip4_spec.psrc =
7180 cpu_to_be16(fsp->h_u.tcp_ip4_spec.psrc);
7181 fsp->h_u.tcp_ip4_spec.pdst =
7182 cpu_to_be16(fsp->h_u.tcp_ip4_spec.pdst);
7183 fsp->m_u.tcp_ip4_spec.psrc =
7184 cpu_to_be16(fsp->m_u.tcp_ip4_spec.psrc);
7185 fsp->m_u.tcp_ip4_spec.pdst =
7186 cpu_to_be16(fsp->m_u.tcp_ip4_spec.pdst);
7187 break;
7188 case AH_V4_FLOW:
7189 case ESP_V4_FLOW:
7190 fsp->h_u.ah_ip4_spec.spi =
7191 (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7192 TCAM_V4KEY2_PORT_SPI_SHIFT;
7193 fsp->m_u.ah_ip4_spec.spi =
7194 (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7195 TCAM_V4KEY2_PORT_SPI_SHIFT;
7196
7197 fsp->h_u.ah_ip4_spec.spi =
7198 cpu_to_be32(fsp->h_u.ah_ip4_spec.spi);
7199 fsp->m_u.ah_ip4_spec.spi =
7200 cpu_to_be32(fsp->m_u.ah_ip4_spec.spi);
7201 break;
7202 case IP_USER_FLOW:
7203 fsp->h_u.usr_ip4_spec.l4_4_bytes =
7204 (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7205 TCAM_V4KEY2_PORT_SPI_SHIFT;
7206 fsp->m_u.usr_ip4_spec.l4_4_bytes =
7207 (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7208 TCAM_V4KEY2_PORT_SPI_SHIFT;
7209
7210 fsp->h_u.usr_ip4_spec.l4_4_bytes =
7211 cpu_to_be32(fsp->h_u.usr_ip4_spec.l4_4_bytes);
7212 fsp->m_u.usr_ip4_spec.l4_4_bytes =
7213 cpu_to_be32(fsp->m_u.usr_ip4_spec.l4_4_bytes);
7214
7215 fsp->h_u.usr_ip4_spec.proto =
7216 (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7217 TCAM_V4KEY2_PROTO_SHIFT;
7218 fsp->m_u.usr_ip4_spec.proto =
7219 (tp->key_mask[2] & TCAM_V4KEY2_PROTO) >>
7220 TCAM_V4KEY2_PROTO_SHIFT;
7221
7222 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
7223 break;
7224 default:
7225 break;
7226 }
7227 }
7228
7229 static int niu_get_ethtool_tcam_entry(struct niu *np,
7230 struct ethtool_rxnfc *nfc)
7231 {
7232 struct niu_parent *parent = np->parent;
7233 struct niu_tcam_entry *tp;
7234 struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7235 u16 idx;
7236 u64 class;
7237 int ret = 0;
7238
7239 idx = tcam_get_index(np, (u16)nfc->fs.location);
7240
7241 tp = &parent->tcam[idx];
7242 if (!tp->valid) {
7243 pr_info(PFX "niu%d: %s entry [%d] invalid for idx[%d]\n",
7244 parent->index, np->dev->name, (u16)nfc->fs.location, idx);
7245 return -EINVAL;
7246 }
7247
7248 /* fill the flow spec entry */
7249 class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7250 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7251 ret = niu_class_to_ethflow(class, &fsp->flow_type);
7252
7253 if (ret < 0) {
7254 pr_info(PFX "niu%d: %s niu_class_to_ethflow failed\n",
7255 parent->index, np->dev->name);
7256 ret = -EINVAL;
7257 goto out;
7258 }
7259
7260 if (fsp->flow_type == AH_V4_FLOW || fsp->flow_type == AH_V6_FLOW) {
7261 u32 proto = (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7262 TCAM_V4KEY2_PROTO_SHIFT;
7263 if (proto == IPPROTO_ESP) {
7264 if (fsp->flow_type == AH_V4_FLOW)
7265 fsp->flow_type = ESP_V4_FLOW;
7266 else
7267 fsp->flow_type = ESP_V6_FLOW;
7268 }
7269 }
7270
7271 switch (fsp->flow_type) {
7272 case TCP_V4_FLOW:
7273 case UDP_V4_FLOW:
7274 case SCTP_V4_FLOW:
7275 case AH_V4_FLOW:
7276 case ESP_V4_FLOW:
7277 niu_get_ip4fs_from_tcam_key(tp, fsp);
7278 break;
7279 case TCP_V6_FLOW:
7280 case UDP_V6_FLOW:
7281 case SCTP_V6_FLOW:
7282 case AH_V6_FLOW:
7283 case ESP_V6_FLOW:
7284 /* Not yet implemented */
7285 ret = -EINVAL;
7286 break;
7287 case IP_USER_FLOW:
7288 niu_get_ip4fs_from_tcam_key(tp, fsp);
7289 break;
7290 default:
7291 ret = -EINVAL;
7292 break;
7293 }
7294
7295 if (ret < 0)
7296 goto out;
7297
7298 if (tp->assoc_data & TCAM_ASSOCDATA_DISC)
7299 fsp->ring_cookie = RX_CLS_FLOW_DISC;
7300 else
7301 fsp->ring_cookie = (tp->assoc_data & TCAM_ASSOCDATA_OFFSET) >>
7302 TCAM_ASSOCDATA_OFFSET_SHIFT;
7303
7304 /* put the tcam size here */
7305 nfc->data = tcam_get_size(np);
7306 out:
7307 return ret;
7308 }
7309
7310 static int niu_get_ethtool_tcam_all(struct niu *np,
7311 struct ethtool_rxnfc *nfc,
7312 u32 *rule_locs)
7313 {
7314 struct niu_parent *parent = np->parent;
7315 struct niu_tcam_entry *tp;
7316 int i, idx, cnt;
7317 u16 n_entries;
7318 unsigned long flags;
7319
7320
7321 /* put the tcam size here */
7322 nfc->data = tcam_get_size(np);
7323
7324 niu_lock_parent(np, flags);
7325 n_entries = nfc->rule_cnt;
7326 for (cnt = 0, i = 0; i < nfc->data; i++) {
7327 idx = tcam_get_index(np, i);
7328 tp = &parent->tcam[idx];
7329 if (!tp->valid)
7330 continue;
7331 rule_locs[cnt] = i;
7332 cnt++;
7333 }
7334 niu_unlock_parent(np, flags);
7335
7336 if (n_entries != cnt) {
7337 /* print warning, this should not happen */
7338 pr_info(PFX "niu%d: %s In niu_get_ethtool_tcam_all, "
7339 "n_entries[%d] != cnt[%d]!!!\n\n",
7340 np->parent->index, np->dev->name, n_entries, cnt);
7341 }
7342
7343 return 0;
7344 }
7345
7346 static int niu_get_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
7347 void *rule_locs)
7348 {
7349 struct niu *np = netdev_priv(dev);
7350 int ret = 0;
7351
7352 switch (cmd->cmd) {
7353 case ETHTOOL_GRXFH:
7354 ret = niu_get_hash_opts(np, cmd);
7355 break;
7356 case ETHTOOL_GRXRINGS:
7357 cmd->data = np->num_rx_rings;
7358 break;
7359 case ETHTOOL_GRXCLSRLCNT:
7360 cmd->rule_cnt = tcam_get_valid_entry_cnt(np);
7361 break;
7362 case ETHTOOL_GRXCLSRULE:
7363 ret = niu_get_ethtool_tcam_entry(np, cmd);
7364 break;
7365 case ETHTOOL_GRXCLSRLALL:
7366 ret = niu_get_ethtool_tcam_all(np, cmd, (u32 *)rule_locs);
7367 break;
7368 default:
7369 ret = -EINVAL;
7370 break;
7371 }
7372
7373 return ret;
7374 }
7375
7376 static int niu_set_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
7377 {
7378 u64 class;
7379 u64 flow_key = 0;
7380 unsigned long flags;
7381
7382 if (!niu_ethflow_to_class(nfc->flow_type, &class))
7383 return -EINVAL;
7384
7385 if (class < CLASS_CODE_USER_PROG1 ||
7386 class > CLASS_CODE_SCTP_IPV6)
7387 return -EINVAL;
7388
7389 if (nfc->data & RXH_DISCARD) {
7390 niu_lock_parent(np, flags);
7391 flow_key = np->parent->tcam_key[class -
7392 CLASS_CODE_USER_PROG1];
7393 flow_key |= TCAM_KEY_DISC;
7394 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7395 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7396 niu_unlock_parent(np, flags);
7397 return 0;
7398 } else {
7399 /* Discard was set before, but is not set now */
7400 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7401 TCAM_KEY_DISC) {
7402 niu_lock_parent(np, flags);
7403 flow_key = np->parent->tcam_key[class -
7404 CLASS_CODE_USER_PROG1];
7405 flow_key &= ~TCAM_KEY_DISC;
7406 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1),
7407 flow_key);
7408 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] =
7409 flow_key;
7410 niu_unlock_parent(np, flags);
7411 }
7412 }
7413
7414 if (!niu_ethflow_to_flowkey(nfc->data, &flow_key))
7415 return -EINVAL;
7416
7417 niu_lock_parent(np, flags);
7418 nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7419 np->parent->flow_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7420 niu_unlock_parent(np, flags);
7421
7422 return 0;
7423 }
7424
7425 static void niu_get_tcamkey_from_ip4fs(struct ethtool_rx_flow_spec *fsp,
7426 struct niu_tcam_entry *tp,
7427 int l2_rdc_tab, u64 class)
7428 {
7429 u8 pid = 0;
7430 u32 sip, dip, sipm, dipm, spi, spim;
7431 u16 sport, dport, spm, dpm;
7432
7433 sip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4src);
7434 sipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4src);
7435 dip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4dst);
7436 dipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4dst);
7437
7438 tp->key[0] = class << TCAM_V4KEY0_CLASS_CODE_SHIFT;
7439 tp->key_mask[0] = TCAM_V4KEY0_CLASS_CODE;
7440 tp->key[1] = (u64)l2_rdc_tab << TCAM_V4KEY1_L2RDCNUM_SHIFT;
7441 tp->key_mask[1] = TCAM_V4KEY1_L2RDCNUM;
7442
7443 tp->key[3] = (u64)sip << TCAM_V4KEY3_SADDR_SHIFT;
7444 tp->key[3] |= dip;
7445
7446 tp->key_mask[3] = (u64)sipm << TCAM_V4KEY3_SADDR_SHIFT;
7447 tp->key_mask[3] |= dipm;
7448
7449 tp->key[2] |= ((u64)fsp->h_u.tcp_ip4_spec.tos <<
7450 TCAM_V4KEY2_TOS_SHIFT);
7451 tp->key_mask[2] |= ((u64)fsp->m_u.tcp_ip4_spec.tos <<
7452 TCAM_V4KEY2_TOS_SHIFT);
7453 switch (fsp->flow_type) {
7454 case TCP_V4_FLOW:
7455 case UDP_V4_FLOW:
7456 case SCTP_V4_FLOW:
7457 sport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.psrc);
7458 spm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.psrc);
7459 dport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.pdst);
7460 dpm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.pdst);
7461
7462 tp->key[2] |= (((u64)sport << 16) | dport);
7463 tp->key_mask[2] |= (((u64)spm << 16) | dpm);
7464 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7465 break;
7466 case AH_V4_FLOW:
7467 case ESP_V4_FLOW:
7468 spi = be32_to_cpu(fsp->h_u.ah_ip4_spec.spi);
7469 spim = be32_to_cpu(fsp->m_u.ah_ip4_spec.spi);
7470
7471 tp->key[2] |= spi;
7472 tp->key_mask[2] |= spim;
7473 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7474 break;
7475 case IP_USER_FLOW:
7476 spi = be32_to_cpu(fsp->h_u.usr_ip4_spec.l4_4_bytes);
7477 spim = be32_to_cpu(fsp->m_u.usr_ip4_spec.l4_4_bytes);
7478
7479 tp->key[2] |= spi;
7480 tp->key_mask[2] |= spim;
7481 pid = fsp->h_u.usr_ip4_spec.proto;
7482 break;
7483 default:
7484 break;
7485 }
7486
7487 tp->key[2] |= ((u64)pid << TCAM_V4KEY2_PROTO_SHIFT);
7488 if (pid) {
7489 tp->key_mask[2] |= TCAM_V4KEY2_PROTO;
7490 }
7491 }
7492
7493 static int niu_add_ethtool_tcam_entry(struct niu *np,
7494 struct ethtool_rxnfc *nfc)
7495 {
7496 struct niu_parent *parent = np->parent;
7497 struct niu_tcam_entry *tp;
7498 struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7499 struct niu_rdc_tables *rdc_table = &parent->rdc_group_cfg[np->port];
7500 int l2_rdc_table = rdc_table->first_table_num;
7501 u16 idx;
7502 u64 class;
7503 unsigned long flags;
7504 int err, ret;
7505
7506 ret = 0;
7507
7508 idx = nfc->fs.location;
7509 if (idx >= tcam_get_size(np))
7510 return -EINVAL;
7511
7512 if (fsp->flow_type == IP_USER_FLOW) {
7513 int i;
7514 int add_usr_cls = 0;
7515 int ipv6 = 0;
7516 struct ethtool_usrip4_spec *uspec = &fsp->h_u.usr_ip4_spec;
7517 struct ethtool_usrip4_spec *umask = &fsp->m_u.usr_ip4_spec;
7518
7519 niu_lock_parent(np, flags);
7520
7521 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7522 if (parent->l3_cls[i]) {
7523 if (uspec->proto == parent->l3_cls_pid[i]) {
7524 class = parent->l3_cls[i];
7525 parent->l3_cls_refcnt[i]++;
7526 add_usr_cls = 1;
7527 break;
7528 }
7529 } else {
7530 /* Program new user IP class */
7531 switch (i) {
7532 case 0:
7533 class = CLASS_CODE_USER_PROG1;
7534 break;
7535 case 1:
7536 class = CLASS_CODE_USER_PROG2;
7537 break;
7538 case 2:
7539 class = CLASS_CODE_USER_PROG3;
7540 break;
7541 case 3:
7542 class = CLASS_CODE_USER_PROG4;
7543 break;
7544 default:
7545 break;
7546 }
7547 if (uspec->ip_ver == ETH_RX_NFC_IP6)
7548 ipv6 = 1;
7549 ret = tcam_user_ip_class_set(np, class, ipv6,
7550 uspec->proto,
7551 uspec->tos,
7552 umask->tos);
7553 if (ret)
7554 goto out;
7555
7556 ret = tcam_user_ip_class_enable(np, class, 1);
7557 if (ret)
7558 goto out;
7559 parent->l3_cls[i] = class;
7560 parent->l3_cls_pid[i] = uspec->proto;
7561 parent->l3_cls_refcnt[i]++;
7562 add_usr_cls = 1;
7563 break;
7564 }
7565 }
7566 if (!add_usr_cls) {
7567 pr_info(PFX "niu%d: %s niu_add_ethtool_tcam_entry: "
7568 "Could not find/insert class for pid %d\n",
7569 parent->index, np->dev->name, uspec->proto);
7570 ret = -EINVAL;
7571 goto out;
7572 }
7573 niu_unlock_parent(np, flags);
7574 } else {
7575 if (!niu_ethflow_to_class(fsp->flow_type, &class)) {
7576 return -EINVAL;
7577 }
7578 }
7579
7580 niu_lock_parent(np, flags);
7581
7582 idx = tcam_get_index(np, idx);
7583 tp = &parent->tcam[idx];
7584
7585 memset(tp, 0, sizeof(*tp));
7586
7587 /* fill in the tcam key and mask */
7588 switch (fsp->flow_type) {
7589 case TCP_V4_FLOW:
7590 case UDP_V4_FLOW:
7591 case SCTP_V4_FLOW:
7592 case AH_V4_FLOW:
7593 case ESP_V4_FLOW:
7594 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class);
7595 break;
7596 case TCP_V6_FLOW:
7597 case UDP_V6_FLOW:
7598 case SCTP_V6_FLOW:
7599 case AH_V6_FLOW:
7600 case ESP_V6_FLOW:
7601 /* Not yet implemented */
7602 pr_info(PFX "niu%d: %s In niu_add_ethtool_tcam_entry: "
7603 "flow %d for IPv6 not implemented\n\n",
7604 parent->index, np->dev->name, fsp->flow_type);
7605 ret = -EINVAL;
7606 goto out;
7607 case IP_USER_FLOW:
7608 if (fsp->h_u.usr_ip4_spec.ip_ver == ETH_RX_NFC_IP4) {
7609 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table,
7610 class);
7611 } else {
7612 /* Not yet implemented */
7613 pr_info(PFX "niu%d: %s In niu_add_ethtool_tcam_entry: "
7614 "usr flow for IPv6 not implemented\n\n",
7615 parent->index, np->dev->name);
7616 ret = -EINVAL;
7617 goto out;
7618 }
7619 break;
7620 default:
7621 pr_info(PFX "niu%d: %s In niu_add_ethtool_tcam_entry: "
7622 "Unknown flow type %d\n\n",
7623 parent->index, np->dev->name, fsp->flow_type);
7624 ret = -EINVAL;
7625 goto out;
7626 }
7627
7628 /* fill in the assoc data */
7629 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) {
7630 tp->assoc_data = TCAM_ASSOCDATA_DISC;
7631 } else {
7632 if (fsp->ring_cookie >= np->num_rx_rings) {
7633 pr_info(PFX "niu%d: %s In niu_add_ethtool_tcam_entry: "
7634 "Invalid RX ring %lld\n\n",
7635 parent->index, np->dev->name,
7636 (long long) fsp->ring_cookie);
7637 ret = -EINVAL;
7638 goto out;
7639 }
7640 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
7641 (fsp->ring_cookie <<
7642 TCAM_ASSOCDATA_OFFSET_SHIFT));
7643 }
7644
7645 err = tcam_write(np, idx, tp->key, tp->key_mask);
7646 if (err) {
7647 ret = -EINVAL;
7648 goto out;
7649 }
7650 err = tcam_assoc_write(np, idx, tp->assoc_data);
7651 if (err) {
7652 ret = -EINVAL;
7653 goto out;
7654 }
7655
7656 /* validate the entry */