1 /*
2 * Copyright (C) 2003 - 2009 NetXen, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
19 *
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
22 *
23 * Contact Information:
24 * info@netxen.com
25 * NetXen Inc,
26 * 18922 Forge Drive
27 * Cupertino, CA 95014-0701
28 *
29 */
30
31 #include "netxen_nic.h"
32
33 #define NETXEN_GB_MAC_SOFT_RESET 0x80000000
34 #define NETXEN_GB_MAC_RESET_PROT_BLK 0x000F0000
35 #define NETXEN_GB_MAC_ENABLE_TX_RX 0x00000005
36 #define NETXEN_GB_MAC_PAUSED_FRMS 0x00000020
37
38 static long phy_lock_timeout = 100000000;
39
40 static int phy_lock(struct netxen_adapter *adapter)
41 {
42 int i;
43 int done = 0, timeout = 0;
44
45 while (!done) {
46 done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM3_LOCK));
47 if (done == 1)
48 break;
49 if (timeout >= phy_lock_timeout) {
50 return -1;
51 }
52 timeout++;
53 if (!in_atomic())
54 schedule();
55 else {
56 for (i = 0; i < 20; i++)
57 cpu_relax();
58 }
59 }
60
61 NXWR32(adapter, NETXEN_PHY_LOCK_ID, PHY_LOCK_DRIVER);
62 return 0;
63 }
64
65 static int phy_unlock(struct netxen_adapter *adapter)
66 {
67 adapter->pci_read_immediate(adapter, NETXEN_PCIE_REG(PCIE_SEM3_UNLOCK));
68
69 return 0;
70 }
71
72 /*
73 * netxen_niu_gbe_phy_read - read a register from the GbE PHY via
74 * mii management interface.
75 *
76 * Note: The MII management interface goes through port 0.
77 * Individual phys are addressed as follows:
78 * @param phy [15:8] phy id
79 * @param reg [7:0] register number
80 *
81 * @returns 0 on success
82 * -1 on error
83 *
84 */
85 int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg,
86 __u32 * readval)
87 {
88 long timeout = 0;
89 long result = 0;
90 long restore = 0;
91 long phy = adapter->physical_port;
92 __u32 address;
93 __u32 command;
94 __u32 status;
95 __u32 mac_cfg0;
96
97 if (phy_lock(adapter) != 0) {
98 return -1;
99 }
100
101 /*
102 * MII mgmt all goes through port 0 MAC interface,
103 * so it cannot be in reset
104 */
105
106 mac_cfg0 = NXRD32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0));
107 if (netxen_gb_get_soft_reset(mac_cfg0)) {
108 __u32 temp;
109 temp = 0;
110 netxen_gb_tx_reset_pb(temp);
111 netxen_gb_rx_reset_pb(temp);
112 netxen_gb_tx_reset_mac(temp);
113 netxen_gb_rx_reset_mac(temp);
114 if (NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0), temp))
115 return -EIO;
116 restore = 1;
117 }
118
119 address = 0;
120 netxen_gb_mii_mgmt_reg_addr(address, reg);
121 netxen_gb_mii_mgmt_phy_addr(address, phy);
122 if (NXWR32(adapter, NETXEN_NIU_GB_MII_MGMT_ADDR(0), address))
123 return -EIO;
124 command = 0; /* turn off any prior activity */
125 if (NXWR32(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0), command))
126 return -EIO;
127 /* send read command */
128 netxen_gb_mii_mgmt_set_read_cycle(command);
129 if (NXWR32(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0), command))
130 return -EIO;
131
132 status = 0;
133 do {
134 status = NXRD32(adapter, NETXEN_NIU_GB_MII_MGMT_INDICATE(0));
135 timeout++;
136 } while ((netxen_get_gb_mii_mgmt_busy(status)
137 || netxen_get_gb_mii_mgmt_notvalid(status))
138 && (timeout++ < NETXEN_NIU_PHY_WAITMAX));
139
140 if (timeout < NETXEN_NIU_PHY_WAITMAX) {
141 *readval = NXRD32(adapter, NETXEN_NIU_GB_MII_MGMT_STATUS(0));
142 result = 0;
143 } else
144 result = -1;
145
146 if (restore)
147 if (NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0), mac_cfg0))
148 return -EIO;
149 phy_unlock(adapter);
150 return result;
151 }
152
153 /*
154 * netxen_niu_gbe_phy_write - write a register to the GbE PHY via
155 * mii management interface.
156 *
157 * Note: The MII management interface goes through port 0.
158 * Individual phys are addressed as follows:
159 * @param phy [15:8] phy id
160 * @param reg [7:0] register number
161 *
162 * @returns 0 on success
163 * -1 on error
164 *
165 */
166 int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter, long reg,
167 __u32 val)
168 {
169 long timeout = 0;
170 long result = 0;
171 long restore = 0;
172 long phy = adapter->physical_port;
173 __u32 address;
174 __u32 command;
175 __u32 status;
176 __u32 mac_cfg0;
177
178 /*
179 * MII mgmt all goes through port 0 MAC interface, so it
180 * cannot be in reset
181 */
182
183 mac_cfg0 = NXRD32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0));
184 if (netxen_gb_get_soft_reset(mac_cfg0)) {
185 __u32 temp;
186 temp = 0;
187 netxen_gb_tx_reset_pb(temp);
188 netxen_gb_rx_reset_pb(temp);
189 netxen_gb_tx_reset_mac(temp);
190 netxen_gb_rx_reset_mac(temp);
191
192 if (NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0), temp))
193 return -EIO;
194 restore = 1;
195 }
196
197 command = 0; /* turn off any prior activity */
198 if (NXWR32(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0), command))
199 return -EIO;
200
201 address = 0;
202 netxen_gb_mii_mgmt_reg_addr(address, reg);
203 netxen_gb_mii_mgmt_phy_addr(address, phy);
204 if (NXWR32(adapter, NETXEN_NIU_GB_MII_MGMT_ADDR(0), address))
205 return -EIO;
206
207 if (NXWR32(adapter, NETXEN_NIU_GB_MII_MGMT_CTRL(0), val))
208 return -EIO;
209
210 status = 0;
211 do {
212 status = NXRD32(adapter, NETXEN_NIU_GB_MII_MGMT_INDICATE(0));
213 timeout++;
214 } while ((netxen_get_gb_mii_mgmt_busy(status))
215 && (timeout++ < NETXEN_NIU_PHY_WAITMAX));
216
217 if (timeout < NETXEN_NIU_PHY_WAITMAX)
218 result = 0;
219 else
220 result = -EIO;
221
222 /* restore the state of port 0 MAC in case we tampered with it */
223 if (restore)
224 if (NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0), mac_cfg0))
225 return -EIO;
226
227 return result;
228 }
229
230 int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter)
231 {
232 NXWR32(adapter, NETXEN_NIU_INT_MASK, 0x3f);
233 return 0;
234 }
235
236 int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter)
237 {
238 int result = 0;
239 __u32 enable = 0;
240 netxen_set_phy_int_link_status_changed(enable);
241 netxen_set_phy_int_autoneg_completed(enable);
242 netxen_set_phy_int_speed_changed(enable);
243
244 if (0 !=
245 netxen_niu_gbe_phy_write(adapter,
246 NETXEN_NIU_GB_MII_MGMT_ADDR_INT_ENABLE,
247 enable))
248 result = -EIO;
249
250 return result;
251 }
252
253 int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter)
254 {
255 NXWR32(adapter, NETXEN_NIU_INT_MASK, 0x7f);
256 return 0;
257 }
258
259 int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter)
260 {
261 int result = 0;
262 if (0 !=
263 netxen_niu_gbe_phy_write(adapter,
264 NETXEN_NIU_GB_MII_MGMT_ADDR_INT_ENABLE, 0))
265 result = -EIO;
266
267 return result;
268 }
269
270 static int netxen_niu_gbe_clear_phy_interrupts(struct netxen_adapter *adapter)
271 {
272 int result = 0;
273 if (0 !=
274 netxen_niu_gbe_phy_write(adapter,
275 NETXEN_NIU_GB_MII_MGMT_ADDR_INT_STATUS,
276 -EIO))
277 result = -EIO;
278
279 return result;
280 }
281
282 /*
283 * netxen_niu_gbe_set_mii_mode- Set 10/100 Mbit Mode for GbE MAC
284 *
285 */
286 static void netxen_niu_gbe_set_mii_mode(struct netxen_adapter *adapter,
287 int port, long enable)
288 {
289 NXWR32(adapter, NETXEN_NIU_MODE, 0x2);
290 NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), 0x80000000);
291 NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), 0x0000f0025);
292 NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_1(port), 0xf1ff);
293 NXWR32(adapter, NETXEN_NIU_GB0_GMII_MODE + (port << 3), 0);
294 NXWR32(adapter, NETXEN_NIU_GB0_MII_MODE + (port << 3), 1);
295 NXWR32(adapter, (NETXEN_NIU_GB0_HALF_DUPLEX + port * 4), 0);
296 NXWR32(adapter, NETXEN_NIU_GB_MII_MGMT_CONFIG(port), 0x7);
297
298 if (enable) {
299 /*
300 * Do NOT enable flow control until a suitable solution for
301 * shutting down pause frames is found.
302 */
303 NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), 0x5);
304 }
305
306 if (netxen_niu_gbe_enable_phy_interrupts(adapter))
307 printk(KERN_ERR "ERROR enabling PHY interrupts\n");
308 if (netxen_niu_gbe_clear_phy_interrupts(adapter))
309 printk(KERN_ERR "ERROR clearing PHY interrupts\n");
310 }
311
312 /*
313 * netxen_niu_gbe_set_gmii_mode- Set GbE Mode for GbE MAC
314 */
315 static void netxen_niu_gbe_set_gmii_mode(struct netxen_adapter *adapter,
316 int port, long enable)
317 {
318 NXWR32(adapter, NETXEN_NIU_MODE, 0x2);
319 NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), 0x80000000);
320 NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), 0x0000f0025);
321 NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_1(port), 0xf2ff);
322 NXWR32(adapter, NETXEN_NIU_GB0_MII_MODE + (port << 3), 0);
323 NXWR32(adapter, NETXEN_NIU_GB0_GMII_MODE + (port << 3), 1);
324 NXWR32(adapter, (NETXEN_NIU_GB0_HALF_DUPLEX + port * 4), 0);
325 NXWR32(adapter, NETXEN_NIU_GB_MII_MGMT_CONFIG(port), 0x7);
326
327 if (enable) {
328 /*
329 * Do NOT enable flow control until a suitable solution for
330 * shutting down pause frames is found.
331 */
332 NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), 0x5);
333 }
334
335 if (netxen_niu_gbe_enable_phy_interrupts(adapter))
336 printk(KERN_ERR "ERROR enabling PHY interrupts\n");
337 if (netxen_niu_gbe_clear_phy_interrupts(adapter))
338 printk(KERN_ERR "ERROR clearing PHY interrupts\n");
339 }
340
341 int netxen_niu_gbe_init_port(struct netxen_adapter *adapter, int port)
342 {
343 int result = 0;
344 __u32 status;
345
346 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
347 return 0;
348
349 if (adapter->disable_phy_interrupts)
350 adapter->disable_phy_interrupts(adapter);
351 mdelay(2);
352
353 if (0 == netxen_niu_gbe_phy_read(adapter,
354 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS, &status)) {
355 if (netxen_get_phy_link(status)) {
356 if (netxen_get_phy_speed(status) == 2) {
357 netxen_niu_gbe_set_gmii_mode(adapter, port, 1);
358 } else if ((netxen_get_phy_speed(status) == 1)
359 || (netxen_get_phy_speed(status) == 0)) {
360 netxen_niu_gbe_set_mii_mode(adapter, port, 1);
361 } else {
362 result = -1;
363 }
364
365 } else {
366 /*
367 * We don't have link. Cable must be unconnected.
368 * Enable phy interrupts so we take action when
369 * plugged in.
370 */
371
372 NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
373 NETXEN_GB_MAC_SOFT_RESET);
374 NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
375 NETXEN_GB_MAC_RESET_PROT_BLK |
376 NETXEN_GB_MAC_ENABLE_TX_RX |
377 NETXEN_GB_MAC_PAUSED_FRMS);
378 if (netxen_niu_gbe_clear_phy_interrupts(adapter))
379 printk(KERN_ERR
380 "ERROR clearing PHY interrupts\n");
381 if (netxen_niu_gbe_enable_phy_interrupts(adapter))
382 printk(KERN_ERR
383 "ERROR enabling PHY interrupts\n");
384 if (netxen_niu_gbe_clear_phy_interrupts(adapter))
385 printk(KERN_ERR
386 "ERROR clearing PHY interrupts\n");
387 result = -1;
388 }
389 } else {
390 result = -EIO;
391 }
392 return result;
393 }
394
395 int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port)
396 {
397 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
398 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1+(0x10000*port), 0x1447);
399 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0+(0x10000*port), 0x5);
400 }
401
402 return 0;
403 }
404
405 /* Disable a GbE interface */
406 int netxen_niu_disable_gbe_port(struct netxen_adapter *adapter)
407 {
408 __u32 mac_cfg0;
409 u32 port = adapter->physical_port;
410
411 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
412 return 0;
413
414 if (port > NETXEN_NIU_MAX_GBE_PORTS)
415 return -EINVAL;
416 mac_cfg0 = 0;
417 netxen_gb_soft_reset(mac_cfg0);
418 if (NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), mac_cfg0))
419 return -EIO;
420 return 0;
421 }
422
423 /* Disable an XG interface */
424 int netxen_niu_disable_xg_port(struct netxen_adapter *adapter)
425 {
426 __u32 mac_cfg;
427 u32 port = adapter->physical_port;
428
429 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
430 return 0;
431
432 if (port > NETXEN_NIU_MAX_XG_PORTS)
433 return -EINVAL;
434
435 mac_cfg = 0;
436 if (NXWR32(adapter,
437 NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg))
438 return -EIO;
439 return 0;
440 }
441
442 /* Set promiscuous mode for a GbE interface */
443 int netxen_niu_set_promiscuous_mode(struct netxen_adapter *adapter,
444 u32 mode)
445 {
446 __u32 reg;
447 u32 port = adapter->physical_port;
448
449 if (port > NETXEN_NIU_MAX_GBE_PORTS)
450 return -EINVAL;
451
452 /* save previous contents */
453 reg = NXRD32(adapter, NETXEN_NIU_GB_DROP_WRONGADDR);
454 if (mode == NETXEN_NIU_PROMISC_MODE) {
455 switch (port) {
456 case 0:
457 netxen_clear_gb_drop_gb0(reg);
458 break;
459 case 1:
460 netxen_clear_gb_drop_gb1(reg);
461 break;
462 case 2:
463 netxen_clear_gb_drop_gb2(reg);
464 break;
465 case 3:
466 netxen_clear_gb_drop_gb3(reg);
467 break;
468 default:
469 return -EIO;
470 }
471 } else {
472 switch (port) {
473 case 0:
474 netxen_set_gb_drop_gb0(reg);
475 break;
476 case 1:
477 netxen_set_gb_drop_gb1(reg);
478 break;
479 case 2:
480 netxen_set_gb_drop_gb2(reg);
481 break;
482 case 3:
483 netxen_set_gb_drop_gb3(reg);
484 break;
485 default:
486 return -EIO;
487 }
488 }
489 if (NXWR32(adapter, NETXEN_NIU_GB_DROP_WRONGADDR, reg))
490 return -EIO;
491 return 0;
492 }
493
494 int netxen_niu_xg_set_promiscuous_mode(struct netxen_adapter *adapter,
495 u32 mode)
496 {
497 __u32 reg;
498 u32 port = adapter->physical_port;
499
500 if (port > NETXEN_NIU_MAX_XG_PORTS)
501 return -EINVAL;
502
503 reg = NXRD32(adapter, NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port));
504 if (mode == NETXEN_NIU_PROMISC_MODE)
505 reg = (reg | 0x2000UL);
506 else
507 reg = (reg & ~0x2000UL);
508
509 if (mode == NETXEN_NIU_ALLMULTI_MODE)
510 reg = (reg | 0x1000UL);
511 else
512 reg = (reg & ~0x1000UL);
513
514 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port), reg);
515
516 return 0;
517 }
518
519 int netxen_p2_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr)
520 {
521 u32 mac_hi, mac_lo;
522 u32 reg_hi, reg_lo;
523
524 u8 phy = adapter->physical_port;
525 u8 phy_count = (adapter->ahw.port_type == NETXEN_NIC_XGBE) ?
526 NETXEN_NIU_MAX_XG_PORTS : NETXEN_NIU_MAX_GBE_PORTS;
527
528 if (phy >= phy_count)
529 return -EINVAL;
530
531 mac_lo = ((u32)addr[0] << 16) | ((u32)addr[1] << 24);
532 mac_hi = addr[2] | ((u32)addr[3] << 8) |
533 ((u32)addr[4] << 16) | ((u32)addr[5] << 24);
534
535 if (adapter->ahw.port_type == NETXEN_NIC_XGBE) {
536 reg_lo = NETXEN_NIU_XGE_STATION_ADDR_0_1 + (0x10000 * phy);
537 reg_hi = NETXEN_NIU_XGE_STATION_ADDR_0_HI + (0x10000 * phy);
538 } else {
539 reg_lo = NETXEN_NIU_GB_STATION_ADDR_1(phy);
540 reg_hi = NETXEN_NIU_GB_STATION_ADDR_0(phy);
541 }
542
543 /* write twice to flush */
544 if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi))
545 return -EIO;
546 if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi))
547 return -EIO;
548
549 return 0;
550 }
551
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