1 /*
2 * Copyright (C) 2003 - 2009 NetXen, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
19 *
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
22 *
23 * Contact Information:
24 * info@netxen.com
25 * NetXen Inc,
26 * 18922 Forge Drive
27 * Cupertino, CA 95014-0701
28 *
29 */
30
31 #ifndef __NETXEN_NIC_HW_H_
32 #define __NETXEN_NIC_HW_H_
33
34 #include "netxen_nic_hdr.h"
35
36 /* Hardware memory size of 128 meg */
37 #define NETXEN_MEMADDR_MAX (128 * 1024 * 1024)
38
39 struct netxen_adapter;
40
41 #define NETXEN_PCI_MAPSIZE_BYTES (NETXEN_PCI_MAPSIZE << 20)
42
43 void netxen_nic_set_link_parameters(struct netxen_adapter *adapter);
44
45 /* Nibble or Byte mode for phy interface (GbE mode only) */
46
47 #define _netxen_crb_get_bit(var, bit) ((var >> bit) & 0x1)
48
49 /*
50 * NIU GB MAC Config Register 0 (applies to GB0, GB1, GB2, GB3)
51 *
52 * Bit 0 : enable_tx => 1:enable frame xmit, 0:disable
53 * Bit 1 : tx_synced => R/O: xmit enable synched to xmit stream
54 * Bit 2 : enable_rx => 1:enable frame recv, 0:disable
55 * Bit 3 : rx_synced => R/O: recv enable synched to recv stream
56 * Bit 4 : tx_flowctl => 1:enable pause frame generation, 0:disable
57 * Bit 5 : rx_flowctl => 1:act on recv'd pause frames, 0:ignore
58 * Bit 8 : loopback => 1:loop MAC xmits to MAC recvs, 0:normal
59 * Bit 16: tx_reset_pb => 1:reset frame xmit protocol blk, 0:no-op
60 * Bit 17: rx_reset_pb => 1:reset frame recv protocol blk, 0:no-op
61 * Bit 18: tx_reset_mac => 1:reset data/ctl multiplexer blk, 0:no-op
62 * Bit 19: rx_reset_mac => 1:reset ctl frames & timers blk, 0:no-op
63 * Bit 31: soft_reset => 1:reset the MAC and the SERDES, 0:no-op
64 */
65
66 #define netxen_gb_enable_tx(config_word) \
67 ((config_word) |= 1 << 0)
68 #define netxen_gb_enable_rx(config_word) \
69 ((config_word) |= 1 << 2)
70 #define netxen_gb_tx_flowctl(config_word) \
71 ((config_word) |= 1 << 4)
72 #define netxen_gb_rx_flowctl(config_word) \
73 ((config_word) |= 1 << 5)
74 #define netxen_gb_tx_reset_pb(config_word) \
75 ((config_word) |= 1 << 16)
76 #define netxen_gb_rx_reset_pb(config_word) \
77 ((config_word) |= 1 << 17)
78 #define netxen_gb_tx_reset_mac(config_word) \
79 ((config_word) |= 1 << 18)
80 #define netxen_gb_rx_reset_mac(config_word) \
81 ((config_word) |= 1 << 19)
82 #define netxen_gb_soft_reset(config_word) \
83 ((config_word) |= 1 << 31)
84
85 #define netxen_gb_unset_tx_flowctl(config_word) \
86 ((config_word) &= ~(1 << 4))
87 #define netxen_gb_unset_rx_flowctl(config_word) \
88 ((config_word) &= ~(1 << 5))
89
90 #define netxen_gb_get_tx_synced(config_word) \
91 _netxen_crb_get_bit((config_word), 1)
92 #define netxen_gb_get_rx_synced(config_word) \
93 _netxen_crb_get_bit((config_word), 3)
94 #define netxen_gb_get_tx_flowctl(config_word) \
95 _netxen_crb_get_bit((config_word), 4)
96 #define netxen_gb_get_rx_flowctl(config_word) \
97 _netxen_crb_get_bit((config_word), 5)
98 #define netxen_gb_get_soft_reset(config_word) \
99 _netxen_crb_get_bit((config_word), 31)
100
101 #define netxen_gb_get_stationaddress_low(config_word) ((config_word) >> 16)
102
103 #define netxen_gb_set_mii_mgmt_clockselect(config_word, val) \
104 ((config_word) |= ((val) & 0x07))
105 #define netxen_gb_mii_mgmt_reset(config_word) \
106 ((config_word) |= 1 << 31)
107 #define netxen_gb_mii_mgmt_unset(config_word) \
108 ((config_word) &= ~(1 << 31))
109
110 /*
111 * NIU GB MII Mgmt Command Register (applies to GB0, GB1, GB2, GB3)
112 * Bit 0 : read_cycle => 1:perform single read cycle, 0:no-op
113 * Bit 1 : scan_cycle => 1:perform continuous read cycles, 0:no-op
114 */
115
116 #define netxen_gb_mii_mgmt_set_read_cycle(config_word) \
117 ((config_word) |= 1 << 0)
118 #define netxen_gb_mii_mgmt_reg_addr(config_word, val) \
119 ((config_word) |= ((val) & 0x1F))
120 #define netxen_gb_mii_mgmt_phy_addr(config_word, val) \
121 ((config_word) |= (((val) & 0x1F) << 8))
122
123 /*
124 * NIU GB MII Mgmt Indicators Register (applies to GB0, GB1, GB2, GB3)
125 * Read-only register.
126 * Bit 0 : busy => 1:performing an MII mgmt cycle, 0:idle
127 * Bit 1 : scanning => 1:scan operation in progress, 0:idle
128 * Bit 2 : notvalid => :mgmt result data not yet valid, 0:idle
129 */
130 #define netxen_get_gb_mii_mgmt_busy(config_word) \
131 _netxen_crb_get_bit(config_word, 0)
132 #define netxen_get_gb_mii_mgmt_scanning(config_word) \
133 _netxen_crb_get_bit(config_word, 1)
134 #define netxen_get_gb_mii_mgmt_notvalid(config_word) \
135 _netxen_crb_get_bit(config_word, 2)
136 /*
137 * NIU XG Pause Ctl Register
138 *
139 * Bit 0 : xg0_mask => 1:disable tx pause frames
140 * Bit 1 : xg0_request => 1:request single pause frame
141 * Bit 2 : xg0_on_off => 1:request is pause on, 0:off
142 * Bit 3 : xg1_mask => 1:disable tx pause frames
143 * Bit 4 : xg1_request => 1:request single pause frame
144 * Bit 5 : xg1_on_off => 1:request is pause on, 0:off
145 */
146
147 #define netxen_xg_set_xg0_mask(config_word) \
148 ((config_word) |= 1 << 0)
149 #define netxen_xg_set_xg1_mask(config_word) \
150 ((config_word) |= 1 << 3)
151
152 #define netxen_xg_get_xg0_mask(config_word) \
153 _netxen_crb_get_bit((config_word), 0)
154 #define netxen_xg_get_xg1_mask(config_word) \
155 _netxen_crb_get_bit((config_word), 3)
156
157 #define netxen_xg_unset_xg0_mask(config_word) \
158 ((config_word) &= ~(1 << 0))
159 #define netxen_xg_unset_xg1_mask(config_word) \
160 ((config_word) &= ~(1 << 3))
161
162 /*
163 * NIU XG Pause Ctl Register
164 *
165 * Bit 0 : xg0_mask => 1:disable tx pause frames
166 * Bit 1 : xg0_request => 1:request single pause frame
167 * Bit 2 : xg0_on_off => 1:request is pause on, 0:off
168 * Bit 3 : xg1_mask => 1:disable tx pause frames
169 * Bit 4 : xg1_request => 1:request single pause frame
170 * Bit 5 : xg1_on_off => 1:request is pause on, 0:off
171 */
172 #define netxen_gb_set_gb0_mask(config_word) \
173 ((config_word) |= 1 << 0)
174 #define netxen_gb_set_gb1_mask(config_word) \
175 ((config_word) |= 1 << 2)
176 #define netxen_gb_set_gb2_mask(config_word) \
177 ((config_word) |= 1 << 4)
178 #define netxen_gb_set_gb3_mask(config_word) \
179 ((config_word) |= 1 << 6)
180
181 #define netxen_gb_get_gb0_mask(config_word) \
182 _netxen_crb_get_bit((config_word), 0)
183 #define netxen_gb_get_gb1_mask(config_word) \
184 _netxen_crb_get_bit((config_word), 2)
185 #define netxen_gb_get_gb2_mask(config_word) \
186 _netxen_crb_get_bit((config_word), 4)
187 #define netxen_gb_get_gb3_mask(config_word) \
188 _netxen_crb_get_bit((config_word), 6)
189
190 #define netxen_gb_unset_gb0_mask(config_word) \
191 ((config_word) &= ~(1 << 0))
192 #define netxen_gb_unset_gb1_mask(config_word) \
193 ((config_word) &= ~(1 << 2))
194 #define netxen_gb_unset_gb2_mask(config_word) \
195 ((config_word) &= ~(1 << 4))
196 #define netxen_gb_unset_gb3_mask(config_word) \
197 ((config_word) &= ~(1 << 6))
198
199
200 /*
201 * PHY-Specific MII control/status registers.
202 */
203 #define NETXEN_NIU_GB_MII_MGMT_ADDR_CONTROL 0
204 #define NETXEN_NIU_GB_MII_MGMT_ADDR_STATUS 1
205 #define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_ID_0 2
206 #define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_ID_1 3
207 #define NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG 4
208 #define NETXEN_NIU_GB_MII_MGMT_ADDR_LNKPART 5
209 #define NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG_MORE 6
210 #define NETXEN_NIU_GB_MII_MGMT_ADDR_NEXTPAGE_XMIT 7
211 #define NETXEN_NIU_GB_MII_MGMT_ADDR_LNKPART_NEXTPAGE 8
212 #define NETXEN_NIU_GB_MII_MGMT_ADDR_1000BT_CONTROL 9
213 #define NETXEN_NIU_GB_MII_MGMT_ADDR_1000BT_STATUS 10
214 #define NETXEN_NIU_GB_MII_MGMT_ADDR_EXTENDED_STATUS 15
215 #define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL 16
216 #define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS 17
217 #define NETXEN_NIU_GB_MII_MGMT_ADDR_INT_ENABLE 18
218 #define NETXEN_NIU_GB_MII_MGMT_ADDR_INT_STATUS 19
219 #define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL_MORE 20
220 #define NETXEN_NIU_GB_MII_MGMT_ADDR_RECV_ERROR_COUNT 21
221 #define NETXEN_NIU_GB_MII_MGMT_ADDR_LED_CONTROL 24
222 #define NETXEN_NIU_GB_MII_MGMT_ADDR_LED_OVERRIDE 25
223 #define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL_MORE_YET 26
224 #define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS_MORE 27
225
226 /*
227 * PHY-Specific Status Register (reg 17).
228 *
229 * Bit 0 : jabber => 1:jabber detected, 0:not
230 * Bit 1 : polarity => 1:polarity reversed, 0:normal
231 * Bit 2 : recvpause => 1:receive pause enabled, 0:disabled
232 * Bit 3 : xmitpause => 1:transmit pause enabled, 0:disabled
233 * Bit 4 : energydetect => 1:sleep, 0:active
234 * Bit 5 : downshift => 1:downshift, 0:no downshift
235 * Bit 6 : crossover => 1:MDIX (crossover), 0:MDI (no crossover)
236 * Bits 7-9 : cablelen => not valid in 10Mb/s mode
237 * 0:<50m, 1:50-80m, 2:80-110m, 3:110-140m, 4:>140m
238 * Bit 10 : link => 1:link up, 0:link down
239 * Bit 11 : resolved => 1:speed and duplex resolved, 0:not yet
240 * Bit 12 : pagercvd => 1:page received, 0:page not received
241 * Bit 13 : duplex => 1:full duplex, 0:half duplex
242 * Bits 14-15 : speed => 0:10Mb/s, 1:100Mb/s, 2:1000Mb/s, 3:rsvd
243 */
244
245 #define netxen_get_phy_cablelen(config_word) (((config_word) >> 7) & 0x07)
246 #define netxen_get_phy_speed(config_word) (((config_word) >> 14) & 0x03)
247
248 #define netxen_set_phy_speed(config_word, val) \
249 ((config_word) |= ((val & 0x03) << 14))
250 #define netxen_set_phy_duplex(config_word) \
251 ((config_word) |= 1 << 13)
252 #define netxen_clear_phy_duplex(config_word) \
253 ((config_word) &= ~(1 << 13))
254
255 #define netxen_get_phy_jabber(config_word) \
256 _netxen_crb_get_bit(config_word, 0)
257 #define netxen_get_phy_polarity(config_word) \
258 _netxen_crb_get_bit(config_word, 1)
259 #define netxen_get_phy_recvpause(config_word) \
260 _netxen_crb_get_bit(config_word, 2)
261 #define netxen_get_phy_xmitpause(config_word) \
262 _netxen_crb_get_bit(config_word, 3)
263 #define netxen_get_phy_energydetect(config_word) \
264 _netxen_crb_get_bit(config_word, 4)
265 #define netxen_get_phy_downshift(config_word) \
266 _netxen_crb_get_bit(config_word, 5)
267 #define netxen_get_phy_crossover(config_word) \
268 _netxen_crb_get_bit(config_word, 6)
269 #define netxen_get_phy_link(config_word) \
270 _netxen_crb_get_bit(config_word, 10)
271 #define netxen_get_phy_resolved(config_word) \
272 _netxen_crb_get_bit(config_word, 11)
273 #define netxen_get_phy_pagercvd(config_word) \
274 _netxen_crb_get_bit(config_word, 12)
275 #define netxen_get_phy_duplex(config_word) \
276 _netxen_crb_get_bit(config_word, 13)
277
278 /*
279 * Interrupt Register definition
280 * This definition applies to registers 18 and 19 (int enable and int status).
281 * Bit 0 : jabber
282 * Bit 1 : polarity_changed
283 * Bit 4 : energy_detect
284 * Bit 5 : downshift
285 * Bit 6 : mdi_xover_changed
286 * Bit 7 : fifo_over_underflow
287 * Bit 8 : false_carrier
288 * Bit 9 : symbol_error
289 * Bit 10: link_status_changed
290 * Bit 11: autoneg_completed
291 * Bit 12: page_received
292 * Bit 13: duplex_changed
293 * Bit 14: speed_changed
294 * Bit 15: autoneg_error
295 */
296
297 #define netxen_get_phy_int_jabber(config_word) \
298 _netxen_crb_get_bit(config_word, 0)
299 #define netxen_get_phy_int_polarity_changed(config_word) \
300 _netxen_crb_get_bit(config_word, 1)
301 #define netxen_get_phy_int_energy_detect(config_word) \
302 _netxen_crb_get_bit(config_word, 4)
303 #define netxen_get_phy_int_downshift(config_word) \
304 _netxen_crb_get_bit(config_word, 5)
305 #define netxen_get_phy_int_mdi_xover_changed(config_word) \
306 _netxen_crb_get_bit(config_word, 6)
307 #define netxen_get_phy_int_fifo_over_underflow(config_word) \
308 _netxen_crb_get_bit(config_word, 7)
309 #define netxen_get_phy_int_false_carrier(config_word) \
310 _netxen_crb_get_bit(config_word, 8)
311 #define netxen_get_phy_int_symbol_error(config_word) \
312 _netxen_crb_get_bit(config_word, 9)
313 #define netxen_get_phy_int_link_status_changed(config_word) \
314 _netxen_crb_get_bit(config_word, 10)
315 #define netxen_get_phy_int_autoneg_completed(config_word) \
316 _netxen_crb_get_bit(config_word, 11)
317 #define netxen_get_phy_int_page_received(config_word) \
318 _netxen_crb_get_bit(config_word, 12)
319 #define netxen_get_phy_int_duplex_changed(config_word) \
320 _netxen_crb_get_bit(config_word, 13)
321 #define netxen_get_phy_int_speed_changed(config_word) \
322 _netxen_crb_get_bit(config_word, 14)
323 #define netxen_get_phy_int_autoneg_error(config_word) \
324 _netxen_crb_get_bit(config_word, 15)
325
326 #define netxen_set_phy_int_link_status_changed(config_word) \
327 ((config_word) |= 1 << 10)
328 #define netxen_set_phy_int_autoneg_completed(config_word) \
329 ((config_word) |= 1 << 11)
330 #define netxen_set_phy_int_speed_changed(config_word) \
331 ((config_word) |= 1 << 14)
332
333 /*
334 * NIU Mode Register.
335 * Bit 0 : enable FibreChannel
336 * Bit 1 : enable 10/100/1000 Ethernet
337 * Bit 2 : enable 10Gb Ethernet
338 */
339
340 #define netxen_get_niu_enable_ge(config_word) \
341 _netxen_crb_get_bit(config_word, 1)
342
343 #define NETXEN_NIU_NON_PROMISC_MODE 0
344 #define NETXEN_NIU_PROMISC_MODE 1
345 #define NETXEN_NIU_ALLMULTI_MODE 2
346
347 /*
348 * NIU GB Drop CRC Register
349 *
350 * Bit 0 : drop_gb0 => 1:drop pkts with bad CRCs, 0:pass them on
351 * Bit 1 : drop_gb1 => 1:drop pkts with bad CRCs, 0:pass them on
352 * Bit 2 : drop_gb2 => 1:drop pkts with bad CRCs, 0:pass them on
353 * Bit 3 : drop_gb3 => 1:drop pkts with bad CRCs, 0:pass them on
354 */
355
356 #define netxen_set_gb_drop_gb0(config_word) \
357 ((config_word) |= 1 << 0)
358 #define netxen_set_gb_drop_gb1(config_word) \
359 ((config_word) |= 1 << 1)
360 #define netxen_set_gb_drop_gb2(config_word) \
361 ((config_word) |= 1 << 2)
362 #define netxen_set_gb_drop_gb3(config_word) \
363 ((config_word) |= 1 << 3)
364
365 #define netxen_clear_gb_drop_gb0(config_word) \
366 ((config_word) &= ~(1 << 0))
367 #define netxen_clear_gb_drop_gb1(config_word) \
368 ((config_word) &= ~(1 << 1))
369 #define netxen_clear_gb_drop_gb2(config_word) \
370 ((config_word) &= ~(1 << 2))
371 #define netxen_clear_gb_drop_gb3(config_word) \
372 ((config_word) &= ~(1 << 3))
373
374 /*
375 * NIU XG MAC Config Register
376 *
377 * Bit 0 : tx_enable => 1:enable frame xmit, 0:disable
378 * Bit 2 : rx_enable => 1:enable frame recv, 0:disable
379 * Bit 4 : soft_reset => 1:reset the MAC , 0:no-op
380 * Bit 27: xaui_framer_reset
381 * Bit 28: xaui_rx_reset
382 * Bit 29: xaui_tx_reset
383 * Bit 30: xg_ingress_afifo_reset
384 * Bit 31: xg_egress_afifo_reset
385 */
386
387 #define netxen_xg_soft_reset(config_word) \
388 ((config_word) |= 1 << 4)
389
390 /* Set promiscuous mode for a GbE interface */
391 int netxen_niu_set_promiscuous_mode(struct netxen_adapter *adapter,
392 u32 mode);
393 int netxen_niu_xg_set_promiscuous_mode(struct netxen_adapter *adapter,
394 u32 mode);
395
396 /* Generic enable for GbE ports. Will detect the speed of the link. */
397 int netxen_niu_gbe_init_port(struct netxen_adapter *adapter, int port);
398
399 int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port);
400
401 /* Disable a GbE interface */
402 int netxen_niu_disable_gbe_port(struct netxen_adapter *adapter);
403
404 int netxen_niu_disable_xg_port(struct netxen_adapter *adapter);
405
406 typedef struct {
407 unsigned valid;
408 unsigned start_128M;
409 unsigned end_128M;
410 unsigned start_2M;
411 } crb_128M_2M_sub_block_map_t;
412
413 typedef struct {
414 crb_128M_2M_sub_block_map_t sub_block[16];
415 } crb_128M_2M_block_map_t;
416
417 #endif /* __NETXEN_NIC_HW_H_ */
418
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