1 /*
2 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
3 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34 #include <linux/init.h>
35 #include <linux/errno.h>
36 #include <linux/mm.h>
37 #include <linux/scatterlist.h>
38
39 #include <linux/mlx4/cmd.h>
40
41 #include "mlx4.h"
42 #include "icm.h"
43 #include "fw.h"
44
45 /*
46 * We allocate in as big chunks as we can, up to a maximum of 256 KB
47 * per chunk.
48 */
49 enum {
50 MLX4_ICM_ALLOC_SIZE = 1 << 18,
51 MLX4_TABLE_CHUNK_SIZE = 1 << 18
52 };
53
54 static void mlx4_free_icm_pages(struct mlx4_dev *dev, struct mlx4_icm_chunk *chunk)
55 {
56 int i;
57
58 if (chunk->nsg > 0)
59 pci_unmap_sg(dev->pdev, chunk->mem, chunk->npages,
60 PCI_DMA_BIDIRECTIONAL);
61
62 for (i = 0; i < chunk->npages; ++i)
63 __free_pages(sg_page(&chunk->mem[i]),
64 get_order(chunk->mem[i].length));
65 }
66
67 static void mlx4_free_icm_coherent(struct mlx4_dev *dev, struct mlx4_icm_chunk *chunk)
68 {
69 int i;
70
71 for (i = 0; i < chunk->npages; ++i)
72 dma_free_coherent(&dev->pdev->dev, chunk->mem[i].length,
73 lowmem_page_address(sg_page(&chunk->mem[i])),
74 sg_dma_address(&chunk->mem[i]));
75 }
76
77 void mlx4_free_icm(struct mlx4_dev *dev, struct mlx4_icm *icm, int coherent)
78 {
79 struct mlx4_icm_chunk *chunk, *tmp;
80
81 if (!icm)
82 return;
83
84 list_for_each_entry_safe(chunk, tmp, &icm->chunk_list, list) {
85 if (coherent)
86 mlx4_free_icm_coherent(dev, chunk);
87 else
88 mlx4_free_icm_pages(dev, chunk);
89
90 kfree(chunk);
91 }
92
93 kfree(icm);
94 }
95
96 static int mlx4_alloc_icm_pages(struct scatterlist *mem, int order, gfp_t gfp_mask)
97 {
98 struct page *page;
99
100 page = alloc_pages(gfp_mask, order);
101 if (!page)
102 return -ENOMEM;
103
104 sg_set_page(mem, page, PAGE_SIZE << order, 0);
105 return 0;
106 }
107
108 static int mlx4_alloc_icm_coherent(struct device *dev, struct scatterlist *mem,
109 int order, gfp_t gfp_mask)
110 {
111 void *buf = dma_alloc_coherent(dev, PAGE_SIZE << order,
112 &sg_dma_address(mem), gfp_mask);
113 if (!buf)
114 return -ENOMEM;
115
116 sg_set_buf(mem, buf, PAGE_SIZE << order);
117 BUG_ON(mem->offset);
118 sg_dma_len(mem) = PAGE_SIZE << order;
119 return 0;
120 }
121
122 struct mlx4_icm *mlx4_alloc_icm(struct mlx4_dev *dev, int npages,
123 gfp_t gfp_mask, int coherent)
124 {
125 struct mlx4_icm *icm;
126 struct mlx4_icm_chunk *chunk = NULL;
127 int cur_order;
128 int ret;
129
130 /* We use sg_set_buf for coherent allocs, which assumes low memory */
131 BUG_ON(coherent && (gfp_mask & __GFP_HIGHMEM));
132
133 icm = kmalloc(sizeof *icm, gfp_mask & ~(__GFP_HIGHMEM | __GFP_NOWARN));
134 if (!icm)
135 return NULL;
136
137 icm->refcount = 0;
138 INIT_LIST_HEAD(&icm->chunk_list);
139
140 cur_order = get_order(MLX4_ICM_ALLOC_SIZE);
141
142 while (npages > 0) {
143 if (!chunk) {
144 chunk = kmalloc(sizeof *chunk,
145 gfp_mask & ~(__GFP_HIGHMEM | __GFP_NOWARN));
146 if (!chunk)
147 goto fail;
148
149 sg_init_table(chunk->mem, MLX4_ICM_CHUNK_LEN);
150 chunk->npages = 0;
151 chunk->nsg = 0;
152 list_add_tail(&chunk->list, &icm->chunk_list);
153 }
154
155 while (1 << cur_order > npages)
156 --cur_order;
157
158 if (coherent)
159 ret = mlx4_alloc_icm_coherent(&dev->pdev->dev,
160 &chunk->mem[chunk->npages],
161 cur_order, gfp_mask);
162 else
163 ret = mlx4_alloc_icm_pages(&chunk->mem[chunk->npages],
164 cur_order, gfp_mask);
165
166 if (!ret) {
167 ++chunk->npages;
168
169 if (coherent)
170 ++chunk->nsg;
171 else if (chunk->npages == MLX4_ICM_CHUNK_LEN) {
172 chunk->nsg = pci_map_sg(dev->pdev, chunk->mem,
173 chunk->npages,
174 PCI_DMA_BIDIRECTIONAL);
175
176 if (chunk->nsg <= 0)
177 goto fail;
178
179 chunk = NULL;
180 }
181
182 npages -= 1 << cur_order;
183 } else {
184 --cur_order;
185 if (cur_order < 0)
186 goto fail;
187 }
188 }
189
190 if (!coherent && chunk) {
191 chunk->nsg = pci_map_sg(dev->pdev, chunk->mem,
192 chunk->npages,
193 PCI_DMA_BIDIRECTIONAL);
194
195 if (chunk->nsg <= 0)
196 goto fail;
197 }
198
199 return icm;
200
201 fail:
202 mlx4_free_icm(dev, icm, coherent);
203 return NULL;
204 }
205
206 static int mlx4_MAP_ICM(struct mlx4_dev *dev, struct mlx4_icm *icm, u64 virt)
207 {
208 return mlx4_map_cmd(dev, MLX4_CMD_MAP_ICM, icm, virt);
209 }
210
211 int mlx4_UNMAP_ICM(struct mlx4_dev *dev, u64 virt, u32 page_count)
212 {
213 return mlx4_cmd(dev, virt, page_count, 0, MLX4_CMD_UNMAP_ICM,
214 MLX4_CMD_TIME_CLASS_B);
215 }
216
217 int mlx4_MAP_ICM_page(struct mlx4_dev *dev, u64 dma_addr, u64 virt)
218 {
219 struct mlx4_cmd_mailbox *mailbox;
220 __be64 *inbox;
221 int err;
222
223 mailbox = mlx4_alloc_cmd_mailbox(dev);
224 if (IS_ERR(mailbox))
225 return PTR_ERR(mailbox);
226 inbox = mailbox->buf;
227
228 inbox[0] = cpu_to_be64(virt);
229 inbox[1] = cpu_to_be64(dma_addr);
230
231 err = mlx4_cmd(dev, mailbox->dma, 1, 0, MLX4_CMD_MAP_ICM,
232 MLX4_CMD_TIME_CLASS_B);
233
234 mlx4_free_cmd_mailbox(dev, mailbox);
235
236 if (!err)
237 mlx4_dbg(dev, "Mapped page at %llx to %llx for ICM.\n",
238 (unsigned long long) dma_addr, (unsigned long long) virt);
239
240 return err;
241 }
242
243 int mlx4_MAP_ICM_AUX(struct mlx4_dev *dev, struct mlx4_icm *icm)
244 {
245 return mlx4_map_cmd(dev, MLX4_CMD_MAP_ICM_AUX, icm, -1);
246 }
247
248 int mlx4_UNMAP_ICM_AUX(struct mlx4_dev *dev)
249 {
250 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_ICM_AUX, MLX4_CMD_TIME_CLASS_B);
251 }
252
253 int mlx4_table_get(struct mlx4_dev *dev, struct mlx4_icm_table *table, int obj)
254 {
255 int i = (obj & (table->num_obj - 1)) / (MLX4_TABLE_CHUNK_SIZE / table->obj_size);
256 int ret = 0;
257
258 mutex_lock(&table->mutex);
259
260 if (table->icm[i]) {
261 ++table->icm[i]->refcount;
262 goto out;
263 }
264
265 table->icm[i] = mlx4_alloc_icm(dev, MLX4_TABLE_CHUNK_SIZE >> PAGE_SHIFT,
266 (table->lowmem ? GFP_KERNEL : GFP_HIGHUSER) |
267 __GFP_NOWARN, table->coherent);
268 if (!table->icm[i]) {
269 ret = -ENOMEM;
270 goto out;
271 }
272
273 if (mlx4_MAP_ICM(dev, table->icm[i], table->virt +
274 (u64) i * MLX4_TABLE_CHUNK_SIZE)) {
275 mlx4_free_icm(dev, table->icm[i], table->coherent);
276 table->icm[i] = NULL;
277 ret = -ENOMEM;
278 goto out;
279 }
280
281 ++table->icm[i]->refcount;
282
283 out:
284 mutex_unlock(&table->mutex);
285 return ret;
286 }
287
288 void mlx4_table_put(struct mlx4_dev *dev, struct mlx4_icm_table *table, int obj)
289 {
290 int i;
291
292 i = (obj & (table->num_obj - 1)) / (MLX4_TABLE_CHUNK_SIZE / table->obj_size);
293
294 mutex_lock(&table->mutex);
295
296 if (--table->icm[i]->refcount == 0) {
297 mlx4_UNMAP_ICM(dev, table->virt + i * MLX4_TABLE_CHUNK_SIZE,
298 MLX4_TABLE_CHUNK_SIZE / MLX4_ICM_PAGE_SIZE);
299 mlx4_free_icm(dev, table->icm[i], table->coherent);
300 table->icm[i] = NULL;
301 }
302
303 mutex_unlock(&table->mutex);
304 }
305
306 void *mlx4_table_find(struct mlx4_icm_table *table, int obj, dma_addr_t *dma_handle)
307 {
308 int idx, offset, dma_offset, i;
309 struct mlx4_icm_chunk *chunk;
310 struct mlx4_icm *icm;
311 struct page *page = NULL;
312
313 if (!table->lowmem)
314 return NULL;
315
316 mutex_lock(&table->mutex);
317
318 idx = (obj & (table->num_obj - 1)) * table->obj_size;
319 icm = table->icm[idx / MLX4_TABLE_CHUNK_SIZE];
320 dma_offset = offset = idx % MLX4_TABLE_CHUNK_SIZE;
321
322 if (!icm)
323 goto out;
324
325 list_for_each_entry(chunk, &icm->chunk_list, list) {
326 for (i = 0; i < chunk->npages; ++i) {
327 if (dma_handle && dma_offset >= 0) {
328 if (sg_dma_len(&chunk->mem[i]) > dma_offset)
329 *dma_handle = sg_dma_address(&chunk->mem[i]) +
330 dma_offset;
331 dma_offset -= sg_dma_len(&chunk->mem[i]);
332 }
333 /*
334 * DMA mapping can merge pages but not split them,
335 * so if we found the page, dma_handle has already
336 * been assigned to.
337 */
338 if (chunk->mem[i].length > offset) {
339 page = sg_page(&chunk->mem[i]);
340 goto out;
341 }
342 offset -= chunk->mem[i].length;
343 }
344 }
345
346 out:
347 mutex_unlock(&table->mutex);
348 return page ? lowmem_page_address(page) + offset : NULL;
349 }
350
351 int mlx4_table_get_range(struct mlx4_dev *dev, struct mlx4_icm_table *table,
352 int start, int end)
353 {
354 int inc = MLX4_TABLE_CHUNK_SIZE / table->obj_size;
355 int i, err;
356
357 for (i = start; i <= end; i += inc) {
358 err = mlx4_table_get(dev, table, i);
359 if (err)
360 goto fail;
361 }
362
363 return 0;
364
365 fail:
366 while (i > start) {
367 i -= inc;
368 mlx4_table_put(dev, table, i);
369 }
370
371 return err;
372 }
373
374 void mlx4_table_put_range(struct mlx4_dev *dev, struct mlx4_icm_table *table,
375 int start, int end)
376 {
377 int i;
378
379 for (i = start; i <= end; i += MLX4_TABLE_CHUNK_SIZE / table->obj_size)
380 mlx4_table_put(dev, table, i);
381 }
382
383 int mlx4_init_icm_table(struct mlx4_dev *dev, struct mlx4_icm_table *table,
384 u64 virt, int obj_size, int nobj, int reserved,
385 int use_lowmem, int use_coherent)
386 {
387 int obj_per_chunk;
388 int num_icm;
389 unsigned chunk_size;
390 int i;
391
392 obj_per_chunk = MLX4_TABLE_CHUNK_SIZE / obj_size;
393 num_icm = (nobj + obj_per_chunk - 1) / obj_per_chunk;
394
395 table->icm = kcalloc(num_icm, sizeof *table->icm, GFP_KERNEL);
396 if (!table->icm)
397 return -ENOMEM;
398 table->virt = virt;
399 table->num_icm = num_icm;
400 table->num_obj = nobj;
401 table->obj_size = obj_size;
402 table->lowmem = use_lowmem;
403 table->coherent = use_coherent;
404 mutex_init(&table->mutex);
405
406 for (i = 0; i * MLX4_TABLE_CHUNK_SIZE < reserved * obj_size; ++i) {
407 chunk_size = MLX4_TABLE_CHUNK_SIZE;
408 if ((i + 1) * MLX4_TABLE_CHUNK_SIZE > nobj * obj_size)
409 chunk_size = PAGE_ALIGN(nobj * obj_size - i * MLX4_TABLE_CHUNK_SIZE);
410
411 table->icm[i] = mlx4_alloc_icm(dev, chunk_size >> PAGE_SHIFT,
412 (use_lowmem ? GFP_KERNEL : GFP_HIGHUSER) |
413 __GFP_NOWARN, use_coherent);
414 if (!table->icm[i])
415 goto err;
416 if (mlx4_MAP_ICM(dev, table->icm[i], virt + i * MLX4_TABLE_CHUNK_SIZE)) {
417 mlx4_free_icm(dev, table->icm[i], use_coherent);
418 table->icm[i] = NULL;
419 goto err;
420 }
421
422 /*
423 * Add a reference to this ICM chunk so that it never
424 * gets freed (since it contains reserved firmware objects).
425 */
426 ++table->icm[i]->refcount;
427 }
428
429 return 0;
430
431 err:
432 for (i = 0; i < num_icm; ++i)
433 if (table->icm[i]) {
434 mlx4_UNMAP_ICM(dev, virt + i * MLX4_TABLE_CHUNK_SIZE,
435 MLX4_TABLE_CHUNK_SIZE / MLX4_ICM_PAGE_SIZE);
436 mlx4_free_icm(dev, table->icm[i], use_coherent);
437 }
438
439 return -ENOMEM;
440 }
441
442 void mlx4_cleanup_icm_table(struct mlx4_dev *dev, struct mlx4_icm_table *table)
443 {
444 int i;
445
446 for (i = 0; i < table->num_icm; ++i)
447 if (table->icm[i]) {
448 mlx4_UNMAP_ICM(dev, table->virt + i * MLX4_TABLE_CHUNK_SIZE,
449 MLX4_TABLE_CHUNK_SIZE / MLX4_ICM_PAGE_SIZE);
450 mlx4_free_icm(dev, table->icm[i], table->coherent);
451 }
452
453 kfree(table->icm);
454 }
455
|
This page was automatically generated by the
LXR engine.
|