1 /*
2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34
35 #include <linux/if_vlan.h>
36
37 #include <linux/mlx4/device.h>
38 #include <linux/mlx4/cmd.h>
39
40 #include "en_port.h"
41 #include "mlx4_en.h"
42
43
44 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port,
45 u64 mac, u64 clear, u8 mode)
46 {
47 return mlx4_cmd(dev, (mac | (clear << 63)), port, mode,
48 MLX4_CMD_SET_MCAST_FLTR, MLX4_CMD_TIME_CLASS_B);
49 }
50
51 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, u8 port, struct vlan_group *grp)
52 {
53 struct mlx4_cmd_mailbox *mailbox;
54 struct mlx4_set_vlan_fltr_mbox *filter;
55 int i;
56 int j;
57 int index = 0;
58 u32 entry;
59 int err = 0;
60
61 mailbox = mlx4_alloc_cmd_mailbox(dev);
62 if (IS_ERR(mailbox))
63 return PTR_ERR(mailbox);
64
65 filter = mailbox->buf;
66 if (grp) {
67 memset(filter, 0, sizeof *filter);
68 for (i = VLAN_FLTR_SIZE - 1; i >= 0; i--) {
69 entry = 0;
70 for (j = 0; j < 32; j++)
71 if (vlan_group_get_device(grp, index++))
72 entry |= 1 << j;
73 filter->entry[i] = cpu_to_be32(entry);
74 }
75 } else {
76 /* When no vlans are configured we block all vlans */
77 memset(filter, 0, sizeof(*filter));
78 }
79 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_SET_VLAN_FLTR,
80 MLX4_CMD_TIME_CLASS_B);
81 mlx4_free_cmd_mailbox(dev, mailbox);
82 return err;
83 }
84
85
86 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
87 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx)
88 {
89 struct mlx4_cmd_mailbox *mailbox;
90 struct mlx4_set_port_general_context *context;
91 int err;
92 u32 in_mod;
93
94 mailbox = mlx4_alloc_cmd_mailbox(dev);
95 if (IS_ERR(mailbox))
96 return PTR_ERR(mailbox);
97 context = mailbox->buf;
98 memset(context, 0, sizeof *context);
99
100 context->flags = SET_PORT_GEN_ALL_VALID;
101 context->mtu = cpu_to_be16(mtu);
102 context->pptx = (pptx * (!pfctx)) << 7;
103 context->pfctx = pfctx;
104 context->pprx = (pprx * (!pfcrx)) << 7;
105 context->pfcrx = pfcrx;
106
107 in_mod = MLX4_SET_PORT_GENERAL << 8 | port;
108 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
109 MLX4_CMD_TIME_CLASS_B);
110
111 mlx4_free_cmd_mailbox(dev, mailbox);
112 return err;
113 }
114
115 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
116 u8 promisc)
117 {
118 struct mlx4_cmd_mailbox *mailbox;
119 struct mlx4_set_port_rqp_calc_context *context;
120 int err;
121 u32 in_mod;
122
123 mailbox = mlx4_alloc_cmd_mailbox(dev);
124 if (IS_ERR(mailbox))
125 return PTR_ERR(mailbox);
126 context = mailbox->buf;
127 memset(context, 0, sizeof *context);
128
129 context->base_qpn = cpu_to_be32(base_qpn);
130 context->promisc = cpu_to_be32(promisc << SET_PORT_PROMISC_SHIFT | base_qpn);
131 context->mcast = cpu_to_be32(1 << SET_PORT_PROMISC_SHIFT | base_qpn);
132 context->intra_no_vlan = 0;
133 context->no_vlan = MLX4_NO_VLAN_IDX;
134 context->intra_vlan_miss = 0;
135 context->vlan_miss = MLX4_VLAN_MISS_IDX;
136
137 in_mod = MLX4_SET_PORT_RQP_CALC << 8 | port;
138 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
139 MLX4_CMD_TIME_CLASS_B);
140
141 mlx4_free_cmd_mailbox(dev, mailbox);
142 return err;
143 }
144
145
146 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset)
147 {
148 struct mlx4_en_stat_out_mbox *mlx4_en_stats;
149 struct mlx4_en_priv *priv = netdev_priv(mdev->pndev[port]);
150 struct net_device_stats *stats = &priv->stats;
151 struct mlx4_cmd_mailbox *mailbox;
152 u64 in_mod = reset << 8 | port;
153 int err;
154 int i;
155
156 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
157 if (IS_ERR(mailbox))
158 return PTR_ERR(mailbox);
159 memset(mailbox->buf, 0, sizeof(*mlx4_en_stats));
160 err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, in_mod, 0,
161 MLX4_CMD_DUMP_ETH_STATS, MLX4_CMD_TIME_CLASS_B);
162 if (err)
163 goto out;
164
165 mlx4_en_stats = mailbox->buf;
166
167 spin_lock_bh(&priv->stats_lock);
168
169 stats->rx_packets = 0;
170 stats->rx_bytes = 0;
171 for (i = 0; i < priv->rx_ring_num; i++) {
172 stats->rx_packets += priv->rx_ring[i].packets;
173 stats->rx_bytes += priv->rx_ring[i].bytes;
174 }
175 stats->tx_packets = 0;
176 stats->tx_bytes = 0;
177 for (i = 0; i <= priv->tx_ring_num; i++) {
178 stats->tx_packets += priv->tx_ring[i].packets;
179 stats->tx_bytes += priv->tx_ring[i].bytes;
180 }
181
182 stats->rx_errors = be64_to_cpu(mlx4_en_stats->PCS) +
183 be32_to_cpu(mlx4_en_stats->RdropLength) +
184 be32_to_cpu(mlx4_en_stats->RJBBR) +
185 be32_to_cpu(mlx4_en_stats->RCRC) +
186 be32_to_cpu(mlx4_en_stats->RRUNT);
187 stats->tx_errors = be32_to_cpu(mlx4_en_stats->TDROP);
188 stats->multicast = be64_to_cpu(mlx4_en_stats->MCAST_prio_0) +
189 be64_to_cpu(mlx4_en_stats->MCAST_prio_1) +
190 be64_to_cpu(mlx4_en_stats->MCAST_prio_2) +
191 be64_to_cpu(mlx4_en_stats->MCAST_prio_3) +
192 be64_to_cpu(mlx4_en_stats->MCAST_prio_4) +
193 be64_to_cpu(mlx4_en_stats->MCAST_prio_5) +
194 be64_to_cpu(mlx4_en_stats->MCAST_prio_6) +
195 be64_to_cpu(mlx4_en_stats->MCAST_prio_7) +
196 be64_to_cpu(mlx4_en_stats->MCAST_novlan);
197 stats->collisions = 0;
198 stats->rx_length_errors = be32_to_cpu(mlx4_en_stats->RdropLength);
199 stats->rx_over_errors = be32_to_cpu(mlx4_en_stats->RdropOvflw);
200 stats->rx_crc_errors = be32_to_cpu(mlx4_en_stats->RCRC);
201 stats->rx_frame_errors = 0;
202 stats->rx_fifo_errors = be32_to_cpu(mlx4_en_stats->RdropOvflw);
203 stats->rx_missed_errors = be32_to_cpu(mlx4_en_stats->RdropOvflw);
204 stats->tx_aborted_errors = 0;
205 stats->tx_carrier_errors = 0;
206 stats->tx_fifo_errors = 0;
207 stats->tx_heartbeat_errors = 0;
208 stats->tx_window_errors = 0;
209
210 priv->pkstats.broadcast =
211 be64_to_cpu(mlx4_en_stats->RBCAST_prio_0) +
212 be64_to_cpu(mlx4_en_stats->RBCAST_prio_1) +
213 be64_to_cpu(mlx4_en_stats->RBCAST_prio_2) +
214 be64_to_cpu(mlx4_en_stats->RBCAST_prio_3) +
215 be64_to_cpu(mlx4_en_stats->RBCAST_prio_4) +
216 be64_to_cpu(mlx4_en_stats->RBCAST_prio_5) +
217 be64_to_cpu(mlx4_en_stats->RBCAST_prio_6) +
218 be64_to_cpu(mlx4_en_stats->RBCAST_prio_7) +
219 be64_to_cpu(mlx4_en_stats->RBCAST_novlan);
220 priv->pkstats.rx_prio[0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_0);
221 priv->pkstats.rx_prio[1] = be64_to_cpu(mlx4_en_stats->RTOT_prio_1);
222 priv->pkstats.rx_prio[2] = be64_to_cpu(mlx4_en_stats->RTOT_prio_2);
223 priv->pkstats.rx_prio[3] = be64_to_cpu(mlx4_en_stats->RTOT_prio_3);
224 priv->pkstats.rx_prio[4] = be64_to_cpu(mlx4_en_stats->RTOT_prio_4);
225 priv->pkstats.rx_prio[5] = be64_to_cpu(mlx4_en_stats->RTOT_prio_5);
226 priv->pkstats.rx_prio[6] = be64_to_cpu(mlx4_en_stats->RTOT_prio_6);
227 priv->pkstats.rx_prio[7] = be64_to_cpu(mlx4_en_stats->RTOT_prio_7);
228 priv->pkstats.tx_prio[0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_0);
229 priv->pkstats.tx_prio[1] = be64_to_cpu(mlx4_en_stats->TTOT_prio_1);
230 priv->pkstats.tx_prio[2] = be64_to_cpu(mlx4_en_stats->TTOT_prio_2);
231 priv->pkstats.tx_prio[3] = be64_to_cpu(mlx4_en_stats->TTOT_prio_3);
232 priv->pkstats.tx_prio[4] = be64_to_cpu(mlx4_en_stats->TTOT_prio_4);
233 priv->pkstats.tx_prio[5] = be64_to_cpu(mlx4_en_stats->TTOT_prio_5);
234 priv->pkstats.tx_prio[6] = be64_to_cpu(mlx4_en_stats->TTOT_prio_6);
235 priv->pkstats.tx_prio[7] = be64_to_cpu(mlx4_en_stats->TTOT_prio_7);
236 spin_unlock_bh(&priv->stats_lock);
237
238 out:
239 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
240 return err;
241 }
242
243
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