1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #ifndef _IXGBE_COMMON_H_
29 #define _IXGBE_COMMON_H_
30
31 #include "ixgbe_type.h"
32
33 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw);
34 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw);
35 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw);
36 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw);
37 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num);
38 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr);
39 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw);
40 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw);
41 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw);
42
43 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index);
44 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index);
45
46 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw);
47 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data);
48 s32 ixgbe_read_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 *data);
49 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
50 u16 *data);
51 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
52 u16 *checksum_val);
53 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw);
54
55 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
56 u32 enable_addr);
57 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index);
58 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw);
59 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
60 u32 mc_addr_count,
61 ixgbe_mc_addr_itr func);
62 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw,
63 struct list_head *uc_list);
64 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw);
65 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw);
66 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval);
67 s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num);
68 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packtetbuf_num);
69 s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw);
70
71 s32 ixgbe_validate_mac_addr(u8 *mac_addr);
72 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask);
73 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask);
74 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw);
75
76 s32 ixgbe_read_analog_reg8_generic(struct ixgbe_hw *hw, u32 reg, u8 *val);
77 s32 ixgbe_write_analog_reg8_generic(struct ixgbe_hw *hw, u32 reg, u8 val);
78
79 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index);
80 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index);
81
82 #define IXGBE_WRITE_REG(a, reg, value) writel((value), ((a)->hw_addr + (reg)))
83
84 #ifndef writeq
85 #define writeq(val, addr) writel((u32) (val), addr); \
86 writel((u32) (val >> 32), (addr + 4));
87 #endif
88
89 #define IXGBE_WRITE_REG64(a, reg, value) writeq((value), ((a)->hw_addr + (reg)))
90
91 #define IXGBE_READ_REG(a, reg) readl((a)->hw_addr + (reg))
92
93 #define IXGBE_WRITE_REG_ARRAY(a, reg, offset, value) (\
94 writel((value), ((a)->hw_addr + (reg) + ((offset) << 2))))
95
96 #define IXGBE_READ_REG_ARRAY(a, reg, offset) (\
97 readl((a)->hw_addr + (reg) + ((offset) << 2)))
98
99 #define IXGBE_WRITE_FLUSH(a) IXGBE_READ_REG(a, IXGBE_STATUS)
100
101 #ifdef DEBUG
102 extern char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw);
103 #define hw_dbg(hw, format, arg...) \
104 printk(KERN_DEBUG "%s: " format, ixgbe_get_hw_dev_name(hw), ##arg)
105 #else
106 #define hw_dbg(hw, format, arg...) do {} while (0)
107 #endif
108
109 #endif /* IXGBE_COMMON */
110
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