1 /*********************************************************************
2 * $Id: smsc-ircc2.c,v 1.19.2.5 2002/10/27 11:34:26 dip Exp $
3 *
4 * Description: Driver for the SMC Infrared Communications Controller
5 * Status: Experimental.
6 * Author: Daniele Peri (peri@csai.unipa.it)
7 * Created at:
8 * Modified at:
9 * Modified by:
10 *
11 * Copyright (c) 2002 Daniele Peri
12 * All Rights Reserved.
13 * Copyright (c) 2002 Jean Tourrilhes
14 *
15 *
16 * Based on smc-ircc.c:
17 *
18 * Copyright (c) 2001 Stefani Seibold
19 * Copyright (c) 1999-2001 Dag Brattli
20 * Copyright (c) 1998-1999 Thomas Davis,
21 *
22 * and irport.c:
23 *
24 * Copyright (c) 1997, 1998, 1999-2000 Dag Brattli, All Rights Reserved.
25 *
26 *
27 * This program is free software; you can redistribute it and/or
28 * modify it under the terms of the GNU General Public License as
29 * published by the Free Software Foundation; either version 2 of
30 * the License, or (at your option) any later version.
31 *
32 * This program is distributed in the hope that it will be useful,
33 * but WITHOUT ANY WARRANTY; without even the implied warranty of
34 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
35 * GNU General Public License for more details.
36 *
37 * You should have received a copy of the GNU General Public License
38 * along with this program; if not, write to the Free Software
39 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
40 * MA 02111-1307 USA
41 *
42 ********************************************************************/
43
44 #include <linux/module.h>
45 #include <linux/kernel.h>
46 #include <linux/types.h>
47 #include <linux/skbuff.h>
48 #include <linux/netdevice.h>
49 #include <linux/ioport.h>
50 #include <linux/delay.h>
51 #include <linux/slab.h>
52 #include <linux/init.h>
53 #include <linux/rtnetlink.h>
54 #include <linux/serial_reg.h>
55 #include <linux/dma-mapping.h>
56
57 #include <asm/io.h>
58 #include <asm/dma.h>
59 #include <asm/byteorder.h>
60
61 #include <linux/spinlock.h>
62 #include <linux/pm.h>
63
64 #include <net/irda/wrapper.h>
65 #include <net/irda/irda.h>
66 #include <net/irda/irda_device.h>
67
68 #include "smsc-ircc2.h"
69 #include "smsc-sio.h"
70
71 /* Types */
72
73 struct smsc_transceiver {
74 char *name;
75 void (*set_for_speed)(int fir_base, u32 speed);
76 int (*probe)(int fir_base);
77 };
78 typedef struct smsc_transceiver smsc_transceiver_t;
79
80 #if 0
81 struct smc_chip {
82 char *name;
83 u16 flags;
84 u8 devid;
85 u8 rev;
86 };
87 typedef struct smc_chip smc_chip_t;
88 #endif
89
90 struct smsc_chip {
91 char *name;
92 #if 0
93 u8 type;
94 #endif
95 u16 flags;
96 u8 devid;
97 u8 rev;
98 };
99 typedef struct smsc_chip smsc_chip_t;
100
101 struct smsc_chip_address {
102 unsigned int cfg_base;
103 unsigned int type;
104 };
105 typedef struct smsc_chip_address smsc_chip_address_t;
106
107 /* Private data for each instance */
108 struct smsc_ircc_cb {
109 struct net_device *netdev; /* Yes! we are some kind of netdevice */
110 struct net_device_stats stats;
111 struct irlap_cb *irlap; /* The link layer we are binded to */
112
113 chipio_t io; /* IrDA controller information */
114 iobuff_t tx_buff; /* Transmit buffer */
115 iobuff_t rx_buff; /* Receive buffer */
116 dma_addr_t tx_buff_dma;
117 dma_addr_t rx_buff_dma;
118
119 struct qos_info qos; /* QoS capabilities for this device */
120
121 spinlock_t lock; /* For serializing operations */
122
123 __u32 new_speed;
124 __u32 flags; /* Interface flags */
125
126 int tx_buff_offsets[10]; /* Offsets between frames in tx_buff */
127 int tx_len; /* Number of frames in tx_buff */
128
129 int transceiver;
130 struct pm_dev *pmdev;
131 };
132
133 /* Constants */
134
135 static const char *driver_name = "smsc-ircc2";
136 #define DIM(x) (sizeof(x)/(sizeof(*(x))))
137 #define SMSC_IRCC2_C_IRDA_FALLBACK_SPEED 9600
138 #define SMSC_IRCC2_C_DEFAULT_TRANSCEIVER 1
139 #define SMSC_IRCC2_C_NET_TIMEOUT 0
140 #define SMSC_IRCC2_C_SIR_STOP 0
141
142 /* Prototypes */
143
144 static int smsc_ircc_open(unsigned int firbase, unsigned int sirbase, u8 dma, u8 irq);
145 static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base);
146 static void smsc_ircc_setup_io(struct smsc_ircc_cb *self, unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq);
147 static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self);
148 static void smsc_ircc_init_chip(struct smsc_ircc_cb *self);
149 static int __exit smsc_ircc_close(struct smsc_ircc_cb *self);
150 static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self, int iobase);
151 static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self, int iobase);
152 static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self);
153 static int smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev);
154 static int smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev);
155 static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int iobase, int bofs);
156 static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self, int iobase);
157 static void smsc_ircc_change_speed(void *priv, u32 speed);
158 static void smsc_ircc_set_sir_speed(void *priv, u32 speed);
159 static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id, struct pt_regs *regs);
160 static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev);
161 static void smsc_ircc_sir_start(struct smsc_ircc_cb *self);
162 #if SMSC_IRCC2_C_SIR_STOP
163 static void smsc_ircc_sir_stop(struct smsc_ircc_cb *self);
164 #endif
165 static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self);
166 static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len);
167 static int smsc_ircc_net_open(struct net_device *dev);
168 static int smsc_ircc_net_close(struct net_device *dev);
169 static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
170 #if SMSC_IRCC2_C_NET_TIMEOUT
171 static void smsc_ircc_timeout(struct net_device *dev);
172 #endif
173 static struct net_device_stats *smsc_ircc_net_get_stats(struct net_device *dev);
174 static int smsc_ircc_pmproc(struct pm_dev *dev, pm_request_t rqst, void *data);
175 static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self);
176 static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self);
177 static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed);
178 static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self);
179
180 /* Probing */
181 static int __init smsc_ircc_look_for_chips(void);
182 static const smsc_chip_t * __init smsc_ircc_probe(unsigned short cfg_base,u8 reg,const smsc_chip_t *chip,char *type);
183 static int __init smsc_superio_flat(const smsc_chip_t *chips, unsigned short cfg_base, char *type);
184 static int __init smsc_superio_paged(const smsc_chip_t *chips, unsigned short cfg_base, char *type);
185 static int __init smsc_superio_fdc(unsigned short cfg_base);
186 static int __init smsc_superio_lpc(unsigned short cfg_base);
187
188 /* Transceivers specific functions */
189
190 static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed);
191 static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base);
192 static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed);
193 static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base);
194 static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed);
195 static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base);
196
197 /* Power Management */
198
199 static void smsc_ircc_suspend(struct smsc_ircc_cb *self);
200 static void smsc_ircc_wakeup(struct smsc_ircc_cb *self);
201 static int smsc_ircc_pmproc(struct pm_dev *dev, pm_request_t rqst, void *data);
202
203
204 /* Transceivers for SMSC-ircc */
205
206 smsc_transceiver_t smsc_transceivers[]=
207 {
208 { "Toshiba Satellite 1800 (GP data pin select)", smsc_ircc_set_transceiver_toshiba_sat1800, smsc_ircc_probe_transceiver_toshiba_sat1800},
209 { "Fast pin select", smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select, smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select},
210 { "ATC IRMode", smsc_ircc_set_transceiver_smsc_ircc_atc, smsc_ircc_probe_transceiver_smsc_ircc_atc},
211 { NULL, NULL}
212 };
213 #define SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS (DIM(smsc_transceivers)-1)
214
215 /* SMC SuperIO chipsets definitions */
216
217 #define KEY55_1 0 /* SuperIO Configuration mode with Key <0x55> */
218 #define KEY55_2 1 /* SuperIO Configuration mode with Key <0x55,0x55> */
219 #define NoIRDA 2 /* SuperIO Chip has no IRDA Port */
220 #define SIR 0 /* SuperIO Chip has only slow IRDA */
221 #define FIR 4 /* SuperIO Chip has fast IRDA */
222 #define SERx4 8 /* SuperIO Chip supports 115,2 KBaud * 4=460,8 KBaud */
223
224 static smsc_chip_t __initdata fdc_chips_flat[]=
225 {
226 /* Base address 0x3f0 or 0x370 */
227 { "37C44", KEY55_1|NoIRDA, 0x00, 0x00 }, /* This chip cannot be detected */
228 { "37C665GT", KEY55_2|NoIRDA, 0x65, 0x01 },
229 { "37C665GT", KEY55_2|NoIRDA, 0x66, 0x01 },
230 { "37C669", KEY55_2|SIR|SERx4, 0x03, 0x02 },
231 { "37C669", KEY55_2|SIR|SERx4, 0x04, 0x02 }, /* ID? */
232 { "37C78", KEY55_2|NoIRDA, 0x78, 0x00 },
233 { "37N769", KEY55_1|FIR|SERx4, 0x28, 0x00 },
234 { "37N869", KEY55_1|FIR|SERx4, 0x29, 0x00 },
235 { NULL }
236 };
237
238 static smsc_chip_t __initdata fdc_chips_paged[]=
239 {
240 /* Base address 0x3f0 or 0x370 */
241 { "37B72X", KEY55_1|SIR|SERx4, 0x4c, 0x00 },
242 { "37B77X", KEY55_1|SIR|SERx4, 0x43, 0x00 },
243 { "37B78X", KEY55_1|SIR|SERx4, 0x44, 0x00 },
244 { "37B80X", KEY55_1|SIR|SERx4, 0x42, 0x00 },
245 { "37C67X", KEY55_1|FIR|SERx4, 0x40, 0x00 },
246 { "37C93X", KEY55_2|SIR|SERx4, 0x02, 0x01 },
247 { "37C93XAPM", KEY55_1|SIR|SERx4, 0x30, 0x01 },
248 { "37C93XFR", KEY55_2|FIR|SERx4, 0x03, 0x01 },
249 { "37M707", KEY55_1|SIR|SERx4, 0x42, 0x00 },
250 { "37M81X", KEY55_1|SIR|SERx4, 0x4d, 0x00 },
251 { "37N958FR", KEY55_1|FIR|SERx4, 0x09, 0x04 },
252 { "37N971", KEY55_1|FIR|SERx4, 0x0a, 0x00 },
253 { "37N972", KEY55_1|FIR|SERx4, 0x0b, 0x00 },
254 { NULL }
255 };
256
257 static smsc_chip_t __initdata lpc_chips_flat[]=
258 {
259 /* Base address 0x2E or 0x4E */
260 { "47N227", KEY55_1|FIR|SERx4, 0x5a, 0x00 },
261 { "47N267", KEY55_1|FIR|SERx4, 0x5e, 0x00 },
262 { NULL }
263 };
264
265 static smsc_chip_t __initdata lpc_chips_paged[]=
266 {
267 /* Base address 0x2E or 0x4E */
268 { "47B27X", KEY55_1|SIR|SERx4, 0x51, 0x00 },
269 { "47B37X", KEY55_1|SIR|SERx4, 0x52, 0x00 },
270 { "47M10X", KEY55_1|SIR|SERx4, 0x59, 0x00 },
271 { "47M120", KEY55_1|NoIRDA|SERx4, 0x5c, 0x00 },
272 { "47M13X", KEY55_1|SIR|SERx4, 0x59, 0x00 },
273 { "47M14X", KEY55_1|SIR|SERx4, 0x5f, 0x00 },
274 { "47N252", KEY55_1|FIR|SERx4, 0x0e, 0x00 },
275 { "47S42X", KEY55_1|SIR|SERx4, 0x57, 0x00 },
276 { NULL }
277 };
278
279 #define SMSCSIO_TYPE_FDC 1
280 #define SMSCSIO_TYPE_LPC 2
281 #define SMSCSIO_TYPE_FLAT 4
282 #define SMSCSIO_TYPE_PAGED 8
283
284 static smsc_chip_address_t __initdata possible_addresses[]=
285 {
286 {0x3f0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED},
287 {0x370, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED},
288 {0xe0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED},
289 {0x2e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED},
290 {0x4e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED},
291 {0,0}
292 };
293
294 /* Globals */
295
296 static struct smsc_ircc_cb *dev_self[] = { NULL, NULL};
297
298 static int ircc_irq=255;
299 static int ircc_dma=255;
300 static int ircc_fir=0;
301 static int ircc_sir=0;
302 static int ircc_cfg=0;
303 static int ircc_transceiver=0;
304
305 static unsigned short dev_count=0;
306
307 static inline void register_bank(int iobase, int bank)
308 {
309 outb(((inb(iobase+IRCC_MASTER) & 0xf0) | (bank & 0x07)),
310 iobase+IRCC_MASTER);
311 }
312
313
314 /*******************************************************************************
315 *
316 *
317 * SMSC-ircc stuff
318 *
319 *
320 *******************************************************************************/
321
322 /*
323 * Function smsc_ircc_init ()
324 *
325 * Initialize chip. Just try to find out how many chips we are dealing with
326 * and where they are
327 */
328 static int __init smsc_ircc_init(void)
329 {
330 int ret=-ENODEV;
331
332 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
333
334 dev_count=0;
335
336 if ((ircc_fir>0)&&(ircc_sir>0)) {
337 MESSAGE(" Overriding FIR address 0x%04x\n", ircc_fir);
338 MESSAGE(" Overriding SIR address 0x%04x\n", ircc_sir);
339
340 if (smsc_ircc_open(ircc_fir, ircc_sir, ircc_dma, ircc_irq) == 0)
341 return 0;
342
343 return -ENODEV;
344 }
345
346 /* try user provided configuration register base address */
347 if (ircc_cfg>0) {
348 MESSAGE(" Overriding configuration address 0x%04x\n", ircc_cfg);
349 if (!smsc_superio_fdc(ircc_cfg))
350 ret = 0;
351 if (!smsc_superio_lpc(ircc_cfg))
352 ret = 0;
353 }
354
355 if(smsc_ircc_look_for_chips()>0) ret = 0;
356
357 return ret;
358 }
359
360 /*
361 * Function smsc_ircc_open (firbase, sirbase, dma, irq)
362 *
363 * Try to open driver instance
364 *
365 */
366 static int __init smsc_ircc_open(unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq)
367 {
368 struct smsc_ircc_cb *self;
369 struct net_device *dev;
370 int err;
371
372 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
373
374 err = smsc_ircc_present(fir_base, sir_base);
375 if(err)
376 goto err_out;
377
378 err = -ENOMEM;
379 if (dev_count > DIM(dev_self)) {
380 WARNING("%s(), too many devices!\n", __FUNCTION__);
381 goto err_out1;
382 }
383
384 /*
385 * Allocate new instance of the driver
386 */
387 dev = alloc_irdadev(sizeof(struct smsc_ircc_cb));
388 if (!dev) {
389 WARNING("%s() can't allocate net device\n", __FUNCTION__);
390 goto err_out1;
391 }
392
393 SET_MODULE_OWNER(dev);
394
395 dev->hard_start_xmit = smsc_ircc_hard_xmit_sir;
396 #if SMSC_IRCC2_C_NET_TIMEOUT
397 dev->tx_timeout = smsc_ircc_timeout;
398 dev->watchdog_timeo = HZ*2; /* Allow enough time for speed change */
399 #endif
400 dev->open = smsc_ircc_net_open;
401 dev->stop = smsc_ircc_net_close;
402 dev->do_ioctl = smsc_ircc_net_ioctl;
403 dev->get_stats = smsc_ircc_net_get_stats;
404
405 self = dev->priv;
406 self->netdev = dev;
407
408 /* Make ifconfig display some details */
409 dev->base_addr = self->io.fir_base = fir_base;
410 dev->irq = self->io.irq = irq;
411
412 /* Need to store self somewhere */
413 dev_self[dev_count++] = self;
414 spin_lock_init(&self->lock);
415
416 self->rx_buff.truesize = SMSC_IRCC2_RX_BUFF_TRUESIZE;
417 self->tx_buff.truesize = SMSC_IRCC2_TX_BUFF_TRUESIZE;
418
419 self->rx_buff.head =
420 dma_alloc_coherent(NULL, self->rx_buff.truesize,
421 &self->rx_buff_dma, GFP_KERNEL);
422 if (self->rx_buff.head == NULL) {
423 ERROR("%s, Can't allocate memory for receive buffer!\n",
424 driver_name);
425 goto err_out2;
426 }
427
428 self->tx_buff.head =
429 dma_alloc_coherent(NULL, self->tx_buff.truesize,
430 &self->tx_buff_dma, GFP_KERNEL);
431 if (self->tx_buff.head == NULL) {
432 ERROR("%s, Can't allocate memory for transmit buffer!\n",
433 driver_name);
434 goto err_out3;
435 }
436
437 memset(self->rx_buff.head, 0, self->rx_buff.truesize);
438 memset(self->tx_buff.head, 0, self->tx_buff.truesize);
439
440 self->rx_buff.in_frame = FALSE;
441 self->rx_buff.state = OUTSIDE_FRAME;
442 self->tx_buff.data = self->tx_buff.head;
443 self->rx_buff.data = self->rx_buff.head;
444
445 smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq);
446
447 smsc_ircc_setup_qos(self);
448
449 smsc_ircc_init_chip(self);
450
451 if(ircc_transceiver > 0 &&
452 ircc_transceiver < SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS)
453 self->transceiver = ircc_transceiver;
454 else
455 smsc_ircc_probe_transceiver(self);
456
457 err = register_netdev(self->netdev);
458 if(err) {
459 ERROR("%s, Network device registration failed!\n",
460 driver_name);
461 goto err_out4;
462 }
463
464 self->pmdev = pm_register(PM_SYS_DEV, PM_SYS_IRDA, smsc_ircc_pmproc);
465 if (self->pmdev)
466 self->pmdev->data = self;
467
468 MESSAGE("IrDA: Registered device %s\n", dev->name);
469
470 return 0;
471 err_out4:
472 dma_free_coherent(NULL, self->tx_buff.truesize,
473 self->tx_buff.head, self->tx_buff_dma);
474 err_out3:
475 dma_free_coherent(NULL, self->rx_buff.truesize,
476 self->rx_buff.head, self->rx_buff_dma);
477 err_out2:
478 free_netdev(self->netdev);
479 dev_self[--dev_count] = NULL;
480 err_out1:
481 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
482 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
483 err_out:
484 return err;
485 }
486
487 /*
488 * Function smsc_ircc_present(fir_base, sir_base)
489 *
490 * Check the smsc-ircc chip presence
491 *
492 */
493 static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base)
494 {
495 unsigned char low, high, chip, config, dma, irq, version;
496
497 if (!request_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT,
498 driver_name)) {
499 WARNING("%s: can't get fir_base of 0x%03x\n",
500 __FUNCTION__, fir_base);
501 goto out1;
502 }
503
504 if (!request_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT,
505 driver_name)) {
506 WARNING("%s: can't get sir_base of 0x%03x\n",
507 __FUNCTION__, sir_base);
508 goto out2;
509 }
510
511 register_bank(fir_base, 3);
512
513 high = inb(fir_base+IRCC_ID_HIGH);
514 low = inb(fir_base+IRCC_ID_LOW);
515 chip = inb(fir_base+IRCC_CHIP_ID);
516 version = inb(fir_base+IRCC_VERSION);
517 config = inb(fir_base+IRCC_INTERFACE);
518 dma = config & IRCC_INTERFACE_DMA_MASK;
519 irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
520
521 if (high != 0x10 || low != 0xb8 || (chip != 0xf1 && chip != 0xf2)) {
522 WARNING("%s(), addr 0x%04x - no device found!\n",
523 __FUNCTION__, fir_base);
524 goto out3;
525 }
526 MESSAGE("SMsC IrDA Controller found\n IrCC version %d.%d, "
527 "firport 0x%03x, sirport 0x%03x dma=%d, irq=%d\n",
528 chip & 0x0f, version, fir_base, sir_base, dma, irq);
529
530 return 0;
531 out3:
532 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
533 out2:
534 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
535 out1:
536 return -ENODEV;
537 }
538
539 /*
540 * Function smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq)
541 *
542 * Setup I/O
543 *
544 */
545 static void smsc_ircc_setup_io(struct smsc_ircc_cb *self,
546 unsigned int fir_base, unsigned int sir_base,
547 u8 dma, u8 irq)
548 {
549 unsigned char config, chip_dma, chip_irq;
550
551 register_bank(fir_base, 3);
552 config = inb(fir_base+IRCC_INTERFACE);
553 chip_dma = config & IRCC_INTERFACE_DMA_MASK;
554 chip_irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
555
556 self->io.fir_base = fir_base;
557 self->io.sir_base = sir_base;
558 self->io.fir_ext = SMSC_IRCC2_FIR_CHIP_IO_EXTENT;
559 self->io.sir_ext = SMSC_IRCC2_SIR_CHIP_IO_EXTENT;
560 self->io.fifo_size = SMSC_IRCC2_FIFO_SIZE;
561 self->io.speed = SMSC_IRCC2_C_IRDA_FALLBACK_SPEED;
562
563 if (irq < 255) {
564 if (irq != chip_irq)
565 MESSAGE("%s, Overriding IRQ - chip says %d, using %d\n",
566 driver_name, chip_irq, irq);
567 self->io.irq = irq;
568 }
569 else
570 self->io.irq = chip_irq;
571
572 if (dma < 255) {
573 if (dma != chip_dma)
574 MESSAGE("%s, Overriding DMA - chip says %d, using %d\n",
575 driver_name, chip_dma, dma);
576 self->io.dma = dma;
577 }
578 else
579 self->io.dma = chip_dma;
580
581 }
582
583 /*
584 * Function smsc_ircc_setup_qos(self)
585 *
586 * Setup qos
587 *
588 */
589 static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self)
590 {
591 /* Initialize QoS for this device */
592 irda_init_max_qos_capabilies(&self->qos);
593
594 self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600|
595 IR_115200|IR_576000|IR_1152000|(IR_4000000 << 8);
596
597 self->qos.min_turn_time.bits = SMSC_IRCC2_MIN_TURN_TIME;
598 self->qos.window_size.bits = SMSC_IRCC2_WINDOW_SIZE;
599 irda_qos_bits_to_value(&self->qos);
600 }
601
602 /*
603 * Function smsc_ircc_init_chip(self)
604 *
605 * Init chip
606 *
607 */
608 static void smsc_ircc_init_chip(struct smsc_ircc_cb *self)
609 {
610 int iobase, ir_mode, ctrl, fast;
611
612 ASSERT( self != NULL, return; );
613 iobase = self->io.fir_base;
614
615 ir_mode = IRCC_CFGA_IRDA_SIR_A;
616 ctrl = 0;
617 fast = 0;
618
619 register_bank(iobase, 0);
620 outb(IRCC_MASTER_RESET, iobase+IRCC_MASTER);
621 outb(0x00, iobase+IRCC_MASTER);
622
623 register_bank(iobase, 1);
624 outb(((inb(iobase+IRCC_SCE_CFGA) & 0x87) | ir_mode),
625 iobase+IRCC_SCE_CFGA);
626
627 #ifdef smsc_669 /* Uses pin 88/89 for Rx/Tx */
628 outb(((inb(iobase+IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
629 iobase+IRCC_SCE_CFGB);
630 #else
631 outb(((inb(iobase+IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
632 iobase+IRCC_SCE_CFGB);
633 #endif
634 (void) inb(iobase+IRCC_FIFO_THRESHOLD);
635 outb(SMSC_IRCC2_FIFO_THRESHOLD, iobase+IRCC_FIFO_THRESHOLD);
636
637 register_bank(iobase, 4);
638 outb((inb(iobase+IRCC_CONTROL) & 0x30) | ctrl, iobase+IRCC_CONTROL);
639
640 register_bank(iobase, 0);
641 outb(fast, iobase+IRCC_LCR_A);
642
643 smsc_ircc_set_sir_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
644
645 /* Power on device */
646 outb(0x00, iobase+IRCC_MASTER);
647 }
648
649 /*
650 * Function smsc_ircc_net_ioctl (dev, rq, cmd)
651 *
652 * Process IOCTL commands for this device
653 *
654 */
655 static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
656 {
657 struct if_irda_req *irq = (struct if_irda_req *) rq;
658 struct smsc_ircc_cb *self;
659 unsigned long flags;
660 int ret = 0;
661
662 ASSERT(dev != NULL, return -1;);
663
664 self = dev->priv;
665
666 ASSERT(self != NULL, return -1;);
667
668 IRDA_DEBUG(2, "%s(), %s, (cmd=0x%X)\n", __FUNCTION__, dev->name, cmd);
669
670 switch (cmd) {
671 case SIOCSBANDWIDTH: /* Set bandwidth */
672 if (!capable(CAP_NET_ADMIN))
673 ret = -EPERM;
674 else {
675 /* Make sure we are the only one touching
676 * self->io.speed and the hardware - Jean II */
677 spin_lock_irqsave(&self->lock, flags);
678 smsc_ircc_change_speed(self, irq->ifr_baudrate);
679 spin_unlock_irqrestore(&self->lock, flags);
680 }
681 break;
682 case SIOCSMEDIABUSY: /* Set media busy */
683 if (!capable(CAP_NET_ADMIN)) {
684 ret = -EPERM;
685 break;
686 }
687
688 irda_device_set_media_busy(self->netdev, TRUE);
689 break;
690 case SIOCGRECEIVING: /* Check if we are receiving right now */
691 irq->ifr_receiving = smsc_ircc_is_receiving(self);
692 break;
693 #if 0
694 case SIOCSDTRRTS:
695 if (!capable(CAP_NET_ADMIN)) {
696 ret = -EPERM;
697 break;
698 }
699 smsc_ircc_sir_set_dtr_rts(dev, irq->ifr_dtr, irq->ifr_rts);
700 break;
701 #endif
702 default:
703 ret = -EOPNOTSUPP;
704 }
705
706 return ret;
707 }
708
709 static struct net_device_stats *smsc_ircc_net_get_stats(struct net_device *dev)
710 {
711 struct smsc_ircc_cb *self = (struct smsc_ircc_cb *) dev->priv;
712
713 return &self->stats;
714 }
715
716 #if SMSC_IRCC2_C_NET_TIMEOUT
717 /*
718 * Function smsc_ircc_timeout (struct net_device *dev)
719 *
720 * The networking timeout management.
721 *
722 */
723
724 static void smsc_ircc_timeout(struct net_device *dev)
725 {
726 struct smsc_ircc_cb *self;
727 unsigned long flags;
728
729 self = (struct smsc_ircc_cb *) dev->priv;
730
731 WARNING("%s: transmit timed out, changing speed to: %d\n", dev->name, self->io.speed);
732 spin_lock_irqsave(&self->lock, flags);
733 smsc_ircc_sir_start(self);
734 smsc_ircc_change_speed(self, self->io.speed);
735 dev->trans_start = jiffies;
736 netif_wake_queue(dev);
737 spin_unlock_irqrestore(&self->lock, flags);
738 }
739 #endif
740
741 /*
742 * Function smsc_ircc_hard_xmit_sir (struct sk_buff *skb, struct net_device *dev)
743 *
744 * Transmits the current frame until FIFO is full, then
745 * waits until the next transmit interrupt, and continues until the
746 * frame is transmitted.
747 */
748 int smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev)
749 {
750 struct smsc_ircc_cb *self;
751 unsigned long flags;
752 int iobase;
753 s32 speed;
754
755 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
756
757 ASSERT(dev != NULL, return 0;);
758
759 self = (struct smsc_ircc_cb *) dev->priv;
760 ASSERT(self != NULL, return 0;);
761
762 iobase = self->io.sir_base;
763
764 netif_stop_queue(dev);
765
766 /* Make sure test of self->io.speed & speed change are atomic */
767 spin_lock_irqsave(&self->lock, flags);
768
769 /* Check if we need to change the speed */
770 speed = irda_get_next_speed(skb);
771 if ((speed != self->io.speed) && (speed != -1)) {
772 /* Check for empty frame */
773 if (!skb->len) {
774 /*
775 * We send frames one by one in SIR mode (no
776 * pipelining), so at this point, if we were sending
777 * a previous frame, we just received the interrupt
778 * telling us it is finished (UART_IIR_THRI).
779 * Therefore, waiting for the transmitter to really
780 * finish draining the fifo won't take too long.
781 * And the interrupt handler is not expected to run.
782 * - Jean II */
783 smsc_ircc_sir_wait_hw_transmitter_finish(self);
784 smsc_ircc_change_speed(self, speed);
785 spin_unlock_irqrestore(&self->lock, flags);
786 dev_kfree_skb(skb);
787 return 0;
788 } else {
789 self->new_speed = speed;
790 }
791 }
792
793 /* Init tx buffer */
794 self->tx_buff.data = self->tx_buff.head;
795
796 /* Copy skb to tx_buff while wrapping, stuffing and making CRC */
797 self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data,
798 self->tx_buff.truesize);
799
800 self->stats.tx_bytes += self->tx_buff.len;
801
802 /* Turn on transmit finished interrupt. Will fire immediately! */
803 outb(UART_IER_THRI, iobase+UART_IER);
804
805 spin_unlock_irqrestore(&self->lock, flags);
806
807 dev_kfree_skb(skb);
808
809 return 0;
810 }
811
812 /*
813 * Function smsc_ircc_set_fir_speed (self, baud)
814 *
815 * Change the speed of the device
816 *
817 */
818 static void smsc_ircc_set_fir_speed(struct smsc_ircc_cb *self, u32 speed)
819 {
820 int fir_base, ir_mode, ctrl, fast;
821
822 ASSERT(self != NULL, return;);
823 fir_base = self->io.fir_base;
824
825 self->io.speed = speed;
826
827 switch(speed) {
828 default:
829 case 576000:
830 ir_mode = IRCC_CFGA_IRDA_HDLC;
831 ctrl = IRCC_CRC;
832 fast = 0;
833 IRDA_DEBUG(0, "%s(), handling baud of 576000\n", __FUNCTION__);
834 break;
835 case 1152000:
836 ir_mode = IRCC_CFGA_IRDA_HDLC;
837 ctrl = IRCC_1152 | IRCC_CRC;
838 fast = IRCC_LCR_A_FAST | IRCC_LCR_A_GP_DATA;
839 IRDA_DEBUG(0, "%s(), handling baud of 1152000\n",
840 __FUNCTION__);
841 break;
842 case 4000000:
843 ir_mode = IRCC_CFGA_IRDA_4PPM;
844 ctrl = IRCC_CRC;
845 fast = IRCC_LCR_A_FAST;
846 IRDA_DEBUG(0, "%s(), handling baud of 4000000\n",
847 __FUNCTION__);
848 break;
849 }
850 #if 0
851 Now in tranceiver!
852 /* This causes an interrupt */
853 register_bank(fir_base, 0);
854 outb((inb(fir_base+IRCC_LCR_A) & 0xbf) | fast, fir_base+IRCC_LCR_A);
855 #endif
856
857 register_bank(fir_base, 1);
858 outb(((inb(fir_base+IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | ir_mode), fir_base+IRCC_SCE_CFGA);
859
860 register_bank(fir_base, 4);
861 outb((inb(fir_base+IRCC_CONTROL) & 0x30) | ctrl, fir_base+IRCC_CONTROL);
862 }
863
864 /*
865 * Function smsc_ircc_fir_start(self)
866 *
867 * Change the speed of the device
868 *
869 */
870 static void smsc_ircc_fir_start(struct smsc_ircc_cb *self)
871 {
872 struct net_device *dev;
873 int fir_base;
874
875 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
876
877 ASSERT(self != NULL, return;);
878 dev = self->netdev;
879 ASSERT(dev != NULL, return;);
880
881 fir_base = self->io.fir_base;
882
883 /* Reset everything */
884
885 /* Install FIR transmit handler */
886 dev->hard_start_xmit = smsc_ircc_hard_xmit_fir;
887
888 /* Clear FIFO */
889 outb(inb(fir_base+IRCC_LCR_A)|IRCC_LCR_A_FIFO_RESET, fir_base+IRCC_LCR_A);
890
891 /* Enable interrupt */
892 /*outb(IRCC_IER_ACTIVE_FRAME|IRCC_IER_EOM, fir_base+IRCC_IER);*/
893
894 register_bank(fir_base, 1);
895
896 /* Select the TX/RX interface */
897 #ifdef SMSC_669 /* Uses pin 88/89 for Rx/Tx */
898 outb(((inb(fir_base+IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
899 fir_base+IRCC_SCE_CFGB);
900 #else
901 outb(((inb(fir_base+IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
902 fir_base+IRCC_SCE_CFGB);
903 #endif
904 (void) inb(fir_base+IRCC_FIFO_THRESHOLD);
905
906 /* Enable SCE interrupts */
907 outb(0, fir_base+IRCC_MASTER);
908 register_bank(fir_base, 0);
909 outb(IRCC_IER_ACTIVE_FRAME|IRCC_IER_EOM, fir_base+IRCC_IER);
910 outb(IRCC_MASTER_INT_EN, fir_base+IRCC_MASTER);
911 }
912
913 /*
914 * Function smsc_ircc_fir_stop(self, baud)
915 *
916 * Change the speed of the device
917 *
918 */
919 static void smsc_ircc_fir_stop(struct smsc_ircc_cb *self)
920 {
921 int fir_base;
922
923 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
924
925 ASSERT(self != NULL, return;);
926
927 fir_base = self->io.fir_base;
928 register_bank(fir_base, 0);
929 /*outb(IRCC_MASTER_RESET, fir_base+IRCC_MASTER);*/
930 outb(inb(fir_base+IRCC_LCR_B) & IRCC_LCR_B_SIP_ENABLE, fir_base+IRCC_LCR_B);
931 }
932
933
934 /*
935 * Function smsc_ircc_change_speed(self, baud)
936 *
937 * Change the speed of the device
938 *
939 * This function *must* be called with spinlock held, because it may
940 * be called from the irq handler. - Jean II
941 */
942 static void smsc_ircc_change_speed(void *priv, u32 speed)
943 {
944 struct smsc_ircc_cb *self = (struct smsc_ircc_cb *) priv;
945 struct net_device *dev;
946 int iobase;
947 int last_speed_was_sir;
948
949 IRDA_DEBUG(0, "%s() changing speed to: %d\n", __FUNCTION__, speed);
950
951 ASSERT(self != NULL, return;);
952 dev = self->netdev;
953 iobase = self->io.fir_base;
954
955 last_speed_was_sir = self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED;
956
957 #if 0
958 /* Temp Hack */
959 speed= 1152000;
960 self->io.speed = speed;
961 last_speed_was_sir = 0;
962 smsc_ircc_fir_start(self);
963 #endif
964
965 if(self->io.speed == 0)
966 smsc_ircc_sir_start(self);
967
968 #if 0
969 if(!last_speed_was_sir) speed = self->io.speed;
970 #endif
971
972 if(self->io.speed != speed) smsc_ircc_set_transceiver_for_speed(self, speed);
973
974 self->io.speed = speed;
975
976 if(speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
977 if(!last_speed_was_sir) {
978 smsc_ircc_fir_stop(self);
979 smsc_ircc_sir_start(self);
980 }
981 smsc_ircc_set_sir_speed(self, speed);
982 }
983 else {
984 if(last_speed_was_sir) {
985 #if SMSC_IRCC2_C_SIR_STOP
986 smsc_ircc_sir_stop(self);
987 #endif
988 smsc_ircc_fir_start(self);
989 }
990 smsc_ircc_set_fir_speed(self, speed);
991
992 #if 0
993 self->tx_buff.len = 10;
994 self->tx_buff.data = self->tx_buff.head;
995
996 smsc_ircc_dma_xmit(self, iobase, 4000);
997 #endif
998 /* Be ready for incoming frames */
999 smsc_ircc_dma_receive(self, iobase);
1000 }
1001
1002 netif_wake_queue(dev);
1003 }
1004
1005 /*
1006 * Function smsc_ircc_set_sir_speed (self, speed)
1007 *
1008 * Set speed of IrDA port to specified baudrate
1009 *
1010 */
1011 void smsc_ircc_set_sir_speed(void *priv, __u32 speed)
1012 {
1013 struct smsc_ircc_cb *self = (struct smsc_ircc_cb *) priv;
1014 int iobase;
1015 int fcr; /* FIFO control reg */
1016 int lcr; /* Line control reg */
1017 int divisor;
1018
1019 IRDA_DEBUG(0, "%s(), Setting speed to: %d\n", __FUNCTION__, speed);
1020
1021 ASSERT(self != NULL, return;);
1022 iobase = self->io.sir_base;
1023
1024 /* Update accounting for new speed */
1025 self->io.speed = speed;
1026
1027 /* Turn off interrupts */
1028 outb(0, iobase+UART_IER);
1029
1030 divisor = SMSC_IRCC2_MAX_SIR_SPEED/speed;
1031
1032 fcr = UART_FCR_ENABLE_FIFO;
1033
1034 /*
1035 * Use trigger level 1 to avoid 3 ms. timeout delay at 9600 bps, and
1036 * almost 1,7 ms at 19200 bps. At speeds above that we can just forget
1037 * about this timeout since it will always be fast enough.
1038 */
1039 if (self->io.speed < 38400)
1040 fcr |= UART_FCR_TRIGGER_1;
1041 else
1042 fcr |= UART_FCR_TRIGGER_14;
1043
1044 /* IrDA ports use 8N1 */
1045 lcr = UART_LCR_WLEN8;
1046
1047 outb(UART_LCR_DLAB | lcr, iobase+UART_LCR); /* Set DLAB */
1048 outb(divisor & 0xff, iobase+UART_DLL); /* Set speed */
1049 outb(divisor >> 8, iobase+UART_DLM);
1050 outb(lcr, iobase+UART_LCR); /* Set 8N1 */
1051 outb(fcr, iobase+UART_FCR); /* Enable FIFO's */
1052
1053 /* Turn on interrups */
1054 outb(UART_IER_RLSI|UART_IER_RDI|UART_IER_THRI, iobase+UART_IER);
1055
1056 IRDA_DEBUG(2, "%s() speed changed to: %d\n", __FUNCTION__, speed);
1057 }
1058
1059
1060 /*
1061 * Function smsc_ircc_hard_xmit_fir (skb, dev)
1062 *
1063 * Transmit the frame!
1064 *
1065 */
1066 static int smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev)
1067 {
1068 struct smsc_ircc_cb *self;
1069 unsigned long flags;
1070 s32 speed;
1071 int iobase;
1072 int mtt;
1073
1074 ASSERT(dev != NULL, return 0;);
1075 self = (struct smsc_ircc_cb *) dev->priv;
1076 ASSERT(self != NULL, return 0;);
1077
1078 iobase = self->io.fir_base;
1079
1080 netif_stop_queue(dev);
1081
1082 /* Make sure test of self->io.speed & speed change are atomic */
1083 spin_lock_irqsave(&self->lock, flags);
1084
1085 /* Check if we need to change the speed after this frame */
1086 speed = irda_get_next_speed(skb);
1087 if ((speed != self->io.speed) && (speed != -1)) {
1088 /* Check for empty frame */
1089 if (!skb->len) {
1090 /* Note : you should make sure that speed changes
1091 * are not going to corrupt any outgoing frame.
1092 * Look at nsc-ircc for the gory details - Jean II */
1093 smsc_ircc_change_speed(self, speed);
1094 spin_unlock_irqrestore(&self->lock, flags);
1095 dev_kfree_skb(skb);
1096 return 0;
1097 } else
1098 self->new_speed = speed;
1099 }
1100
1101 memcpy(self->tx_buff.head, skb->data, skb->len);
1102
1103 self->tx_buff.len = skb->len;
1104 self->tx_buff.data = self->tx_buff.head;
1105
1106 mtt = irda_get_mtt(skb);
1107 if (mtt) {
1108 int bofs;
1109
1110 /*
1111 * Compute how many BOFs (STA or PA's) we need to waste the
1112 * min turn time given the speed of the link.
1113 */
1114 bofs = mtt * (self->io.speed / 1000) / 8000;
1115 if (bofs > 4095)
1116 bofs = 4095;
1117
1118 smsc_ircc_dma_xmit(self, iobase, bofs);
1119 } else {
1120 /* Transmit frame */
1121 smsc_ircc_dma_xmit(self, iobase, 0);
1122 }
1123 spin_unlock_irqrestore(&self->lock, flags);
1124 dev_kfree_skb(skb);
1125
1126 return 0;
1127 }
1128
1129 /*
1130 * Function smsc_ircc_dma_xmit (self, iobase)
1131 *
1132 * Transmit data using DMA
1133 *
1134 */
1135 static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int iobase, int bofs)
1136 {
1137 u8 ctrl;
1138
1139 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1140 #if 1
1141 /* Disable Rx */
1142 register_bank(iobase, 0);
1143 outb(0x00, iobase+IRCC_LCR_B);
1144 #endif
1145 register_bank(iobase, 1);
1146 outb(inb(iobase+IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1147 iobase+IRCC_SCE_CFGB);
1148
1149 self->io.direction = IO_XMIT;
1150
1151 /* Set BOF additional count for generating the min turn time */
1152 register_bank(iobase, 4);
1153 outb(bofs & 0xff, iobase+IRCC_BOF_COUNT_LO);
1154 ctrl = inb(iobase+IRCC_CONTROL) & 0xf0;
1155 outb(ctrl | ((bofs >> 8) & 0x0f), iobase+IRCC_BOF_COUNT_HI);
1156
1157 /* Set max Tx frame size */
1158 outb(self->tx_buff.len >> 8, iobase+IRCC_TX_SIZE_HI);
1159 outb(self->tx_buff.len & 0xff, iobase+IRCC_TX_SIZE_LO);
1160
1161 /*outb(UART_MCR_OUT2, self->io.sir_base + UART_MCR);*/
1162
1163 /* Enable burst mode chip Tx DMA */
1164 register_bank(iobase, 1);
1165 outb(inb(iobase+IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1166 IRCC_CFGB_DMA_BURST, iobase+IRCC_SCE_CFGB);
1167
1168 /* Setup DMA controller (must be done after enabling chip DMA) */
1169 irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len,
1170 DMA_TX_MODE);
1171
1172 /* Enable interrupt */
1173
1174 register_bank(iobase, 0);
1175 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase+IRCC_IER);
1176 outb(IRCC_MASTER_INT_EN, iobase+IRCC_MASTER);
1177
1178 /* Enable transmit */
1179 outb(IRCC_LCR_B_SCE_TRANSMIT | IRCC_LCR_B_SIP_ENABLE, iobase+IRCC_LCR_B);
1180 }
1181
1182 /*
1183 * Function smsc_ircc_dma_xmit_complete (self)
1184 *
1185 * The transfer of a frame in finished. This function will only be called
1186 * by the interrupt handler
1187 *
1188 */
1189 static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self, int iobase)
1190 {
1191 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1192 #if 0
1193 /* Disable Tx */
1194 register_bank(iobase, 0);
1195 outb(0x00, iobase+IRCC_LCR_B);
1196 #endif
1197 register_bank(self->io.fir_base, 1);
1198 outb(inb(self->io.fir_base+IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1199 self->io.fir_base+IRCC_SCE_CFGB);
1200
1201 /* Check for underrun! */
1202 register_bank(iobase, 0);
1203 if (inb(iobase+IRCC_LSR) & IRCC_LSR_UNDERRUN) {
1204 self->stats.tx_errors++;
1205 self->stats.tx_fifo_errors++;
1206
1207 /* Reset error condition */
1208 register_bank(iobase, 0);
1209 outb(IRCC_MASTER_ERROR_RESET, iobase+IRCC_MASTER);
1210 outb(0x00, iobase+IRCC_MASTER);
1211 } else {
1212 self->stats.tx_packets++;
1213 self->stats.tx_bytes += self->tx_buff.len;
1214 }
1215
1216 /* Check if it's time to change the speed */
1217 if (self->new_speed) {
1218 smsc_ircc_change_speed(self, self->new_speed);
1219 self->new_speed = 0;
1220 }
1221
1222 netif_wake_queue(self->netdev);
1223 }
1224
1225 /*
1226 * Function smsc_ircc_dma_receive(self)
1227 *
1228 * Get ready for receiving a frame. The device will initiate a DMA
1229 * if it starts to receive a frame.
1230 *
1231 */
1232 static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self, int iobase)
1233 {
1234 #if 0
1235 /* Turn off chip DMA */
1236 register_bank(iobase, 1);
1237 outb(inb(iobase+IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1238 iobase+IRCC_SCE_CFGB);
1239 #endif
1240
1241 /* Disable Tx */
1242 register_bank(iobase, 0);
1243 outb(0x00, iobase+IRCC_LCR_B);
1244
1245 /* Turn off chip DMA */
1246 register_bank(iobase, 1);
1247 outb(inb(iobase+IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1248 iobase+IRCC_SCE_CFGB);
1249
1250 self->io.direction = IO_RECV;
1251 self->rx_buff.data = self->rx_buff.head;
1252
1253 /* Set max Rx frame size */
1254 register_bank(iobase, 4);
1255 outb((2050 >> 8) & 0x0f, iobase+IRCC_RX_SIZE_HI);
1256 outb(2050 & 0xff, iobase+IRCC_RX_SIZE_LO);
1257
1258 /* Setup DMA controller */
1259 irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize,
1260 DMA_RX_MODE);
1261
1262 /* Enable burst mode chip Rx DMA */
1263 register_bank(iobase, 1);
1264 outb(inb(iobase+IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1265 IRCC_CFGB_DMA_BURST, iobase+IRCC_SCE_CFGB);
1266
1267 /* Enable interrupt */
1268 register_bank(iobase, 0);
1269 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase+IRCC_IER);
1270 outb(IRCC_MASTER_INT_EN, iobase+IRCC_MASTER);
1271
1272
1273 /* Enable receiver */
1274 register_bank(iobase, 0);
1275 outb(IRCC_LCR_B_SCE_RECEIVE | IRCC_LCR_B_SIP_ENABLE,
1276 iobase+IRCC_LCR_B);
1277
1278 return 0;
1279 }
1280
1281 /*
1282 * Function smsc_ircc_dma_receive_complete(self, iobase)
1283 *
1284 * Finished with receiving frames
1285 *
1286 */
1287 static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self, int iobase)
1288 {
1289 struct sk_buff *skb;
1290 int len, msgcnt, lsr;
1291
1292 register_bank(iobase, 0);
1293
1294 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1295 #if 0
1296 /* Disable Rx */
1297 register_bank(iobase, 0);
1298 outb(0x00, iobase+IRCC_LCR_B);
1299 #endif
1300 register_bank(iobase, 0);
1301 outb(inb(iobase+IRCC_LSAR) & ~IRCC_LSAR_ADDRESS_MASK, iobase+IRCC_LSAR);
1302 lsr= inb(iobase+IRCC_LSR);
1303 msgcnt = inb(iobase+IRCC_LCR_B) & 0x08;
1304
1305 IRDA_DEBUG(2, "%s: dma count = %d\n", __FUNCTION__,
1306 get_dma_residue(self->io.dma));
1307
1308 len = self->rx_buff.truesize - get_dma_residue(self->io.dma);
1309
1310 /* Look for errors
1311 */
1312
1313 if(lsr & (IRCC_LSR_FRAME_ERROR | IRCC_LSR_CRC_ERROR | IRCC_LSR_SIZE_ERROR)) {
1314 self->stats.rx_errors++;
1315 if(lsr & IRCC_LSR_FRAME_ERROR) self->stats.rx_frame_errors++;
1316 if(lsr & IRCC_LSR_CRC_ERROR) self->stats.rx_crc_errors++;
1317 if(lsr & IRCC_LSR_SIZE_ERROR) self->stats.rx_length_errors++;
1318 if(lsr & (IRCC_LSR_UNDERRUN | IRCC_LSR_OVERRUN)) self->stats.rx_length_errors++;
1319 return;
1320 }
1321 /* Remove CRC */
1322 if (self->io.speed < 4000000)
1323 len -= 2;
1324 else
1325 len -= 4;
1326
1327 if ((len < 2) || (len > 2050)) {
1328 WARNING("%s(), bogus len=%d\n", __FUNCTION__, len);
1329 return;
1330 }
1331 IRDA_DEBUG(2, "%s: msgcnt = %d, len=%d\n", __FUNCTION__, msgcnt, len);
1332
1333 skb = dev_alloc_skb(len+1);
1334 if (!skb) {
1335 WARNING("%s(), memory squeeze, dropping frame.\n",
1336 __FUNCTION__);
1337 return;
1338 }
1339 /* Make sure IP header gets aligned */
1340 skb_reserve(skb, 1);
1341
1342 memcpy(skb_put(skb, len), self->rx_buff.data, len);
1343 self->stats.rx_packets++;
1344 self->stats.rx_bytes += len;
1345
1346 skb->dev = self->netdev;
1347 skb->mac.raw = skb->data;
1348 skb->protocol = htons(ETH_P_IRDA);
1349 netif_rx(skb);
1350 }
1351
1352 /*
1353 * Function smsc_ircc_sir_receive (self)
1354 *
1355 * Receive one frame from the infrared port
1356 *
1357 */
1358 static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self)
1359 {
1360 int boguscount = 0;
1361 int iobase;
1362
1363 ASSERT(self != NULL, return;);
1364
1365 iobase = self->io.sir_base;
1366
1367 /*
1368 * Receive all characters in Rx FIFO, unwrap and unstuff them.
1369 * async_unwrap_char will deliver all found frames
1370 */
1371 do {
1372 async_unwrap_char(self->netdev, &self->stats, &self->rx_buff,
1373 inb(iobase+UART_RX));
1374
1375 /* Make sure we don't stay here to long */
1376 if (boguscount++ > 32) {
1377 IRDA_DEBUG(2, "%s(), breaking!\n", __FUNCTION__);
1378 break;
1379 }
1380 } while (inb(iobase+UART_LSR) & UART_LSR_DR);
1381 }
1382
1383
1384 /*
1385 * Function smsc_ircc_interrupt (irq, dev_id, regs)
1386 *
1387 * An interrupt from the chip has arrived. Time to do some work
1388 *
1389 */
1390 static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1391 {
1392 struct net_device *dev = (struct net_device *) dev_id;
1393 struct smsc_ircc_cb *self;
1394 int iobase, iir, lcra, lsr;
1395 irqreturn_t ret = IRQ_NONE;
1396
1397 if (dev == NULL) {
1398 printk(KERN_WARNING "%s: irq %d for unknown device.\n",
1399 driver_name, irq);
1400 goto irq_ret;
1401 }
1402 self = (struct smsc_ircc_cb *) dev->priv;
1403 ASSERT(self != NULL, return IRQ_NONE;);
1404
1405 /* Serialise the interrupt handler in various CPUs, stop Tx path */
1406 spin_lock(&self->lock);
1407
1408 /* Check if we should use the SIR interrupt handler */
1409 if (self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1410 ret = smsc_ircc_interrupt_sir(dev);
1411 goto irq_ret_unlock;
1412 }
1413
1414 iobase = self->io.fir_base;
1415
1416 register_bank(iobase, 0);
1417 iir = inb(iobase+IRCC_IIR);
1418 if (iir == 0)
1419 goto irq_ret_unlock;
1420 ret = IRQ_HANDLED;
1421
1422 /* Disable interrupts */
1423 outb(0, iobase+IRCC_IER);
1424 lcra = inb(iobase+IRCC_LCR_A);
1425 lsr = inb(iobase+IRCC_LSR);
1426
1427 IRDA_DEBUG(2, "%s(), iir = 0x%02x\n", __FUNCTION__, iir);
1428
1429 if (iir & IRCC_IIR_EOM) {
1430 if (self->io.direction == IO_RECV)
1431 smsc_ircc_dma_receive_complete(self, iobase);
1432 else
1433 smsc_ircc_dma_xmit_complete(self, iobase);
1434
1435 smsc_ircc_dma_receive(self, iobase);
1436 }
1437
1438 if (iir & IRCC_IIR_ACTIVE_FRAME) {
1439 /*printk(KERN_WARNING "%s(): Active Frame\n", __FUNCTION__);*/
1440 }
1441
1442 /* Enable interrupts again */
1443
1444 register_bank(iobase, 0);
1445 outb(IRCC_IER_ACTIVE_FRAME|IRCC_IER_EOM, iobase+IRCC_IER);
1446
1447 irq_ret_unlock:
1448 spin_unlock(&self->lock);
1449 irq_ret:
1450 return ret;
1451 }
1452
1453 /*
1454 * Function irport_interrupt_sir (irq, dev_id, regs)
1455 *
1456 * Interrupt handler for SIR modes
1457 */
1458 static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev)
1459 {
1460 struct smsc_ircc_cb *self = dev->priv;
1461 int boguscount = 0;
1462 int iobase;
1463 int iir, lsr;
1464
1465 /* Already locked comming here in smsc_ircc_interrupt() */
1466 /*spin_lock(&self->lock);*/
1467
1468 iobase = self->io.sir_base;
1469
1470 iir = inb(iobase+UART_IIR) & UART_IIR_ID;
1471 if (iir == 0)
1472 return IRQ_NONE;
1473 while (iir) {
1474 /* Clear interrupt */
1475 lsr = inb(iobase+UART_LSR);
1476
1477 IRDA_DEBUG(4, "%s(), iir=%02x, lsr=%02x, iobase=%#x\n",
1478 __FUNCTION__, iir, lsr, iobase);
1479
1480 switch (iir) {
1481 case UART_IIR_RLSI:
1482 IRDA_DEBUG(2, "%s(), RLSI\n", __FUNCTION__);
1483 break;
1484 case UART_IIR_RDI:
1485 /* Receive interrupt */
1486 smsc_ircc_sir_receive(self);
1487 break;
1488 case UART_IIR_THRI:
1489 if (lsr & UART_LSR_THRE)
1490 /* Transmitter ready for data */
1491 smsc_ircc_sir_write_wakeup(self);
1492 break;
1493 default:
1494 IRDA_DEBUG(0, "%s(), unhandled IIR=%#x\n",
1495 __FUNCTION__, iir);
1496 break;
1497 }
1498
1499 /* Make sure we don't stay here to long */
1500 if (boguscount++ > 100)
1501 break;
1502
1503 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1504 }
1505 /*spin_unlock(&self->lock);*/
1506 return IRQ_HANDLED;
1507 }
1508
1509
1510 #if 0 /* unused */
1511 /*
1512 * Function ircc_is_receiving (self)
1513 *
1514 * Return TRUE is we are currently receiving a frame
1515 *
1516 */
1517 static int ircc_is_receiving(struct smsc_ircc_cb *self)
1518 {
1519 int status = FALSE;
1520 /* int iobase; */
1521
1522 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1523
1524 ASSERT(self != NULL, return FALSE;);
1525
1526 IRDA_DEBUG(0, "%s: dma count = %d\n", __FUNCTION__,
1527 get_dma_residue(self->io.dma));
1528
1529 status = (self->rx_buff.state != OUTSIDE_FRAME);
1530
1531 return status;
1532 }
1533 #endif /* unused */
1534
1535
1536 /*
1537 * Function smsc_ircc_net_open (dev)
1538 *
1539 * Start the device
1540 *
1541 */
1542 static int smsc_ircc_net_open(struct net_device *dev)
1543 {
1544 struct smsc_ircc_cb *self;
1545 int iobase;
1546 char hwname[16];
1547 unsigned long flags;
1548
1549 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1550
1551 ASSERT(dev != NULL, return -1;);
1552 self = (struct smsc_ircc_cb *) dev->priv;
1553 ASSERT(self != NULL, return 0;);
1554
1555 iobase = self->io.fir_base;
1556
1557 if (request_irq(self->io.irq, smsc_ircc_interrupt, 0, dev->name,
1558 (void *) dev)) {
1559 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d\n",
1560 __FUNCTION__, self->io.irq);
1561 return -EAGAIN;
1562 }
1563
1564 spin_lock_irqsave(&self->lock, flags);
1565 /*smsc_ircc_sir_start(self);*/
1566 self->io.speed = 0;
1567 smsc_ircc_change_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
1568 spin_unlock_irqrestore(&self->lock, flags);
1569
1570 /* Give self a hardware name */
1571 /* It would be cool to offer the chip revision here - Jean II */
1572 sprintf(hwname, "SMSC @ 0x%03x", self->io.fir_base);
1573
1574 /*
1575 * Open new IrLAP layer instance, now that everything should be
1576 * initialized properly
1577 */
1578 self->irlap = irlap_open(dev, &self->qos, hwname);
1579
1580 /*
1581 * Always allocate the DMA channel after the IRQ,
1582 * and clean up on failure.
1583 */
1584 if (request_dma(self->io.dma, dev->name)) {
1585 smsc_ircc_net_close(dev);
1586
1587 WARNING("%s(), unable to allocate DMA=%d\n",
1588 __FUNCTION__, self->io.dma);
1589 return -EAGAIN;
1590 }
1591
1592 netif_start_queue(dev);
1593
1594 return 0;
1595 }
1596
1597 /*
1598 * Function smsc_ircc_net_close (dev)
1599 *
1600 * Stop the device
1601 *
1602 */
1603 static int smsc_ircc_net_close(struct net_device *dev)
1604 {
1605 struct smsc_ircc_cb *self;
1606 int iobase;
1607
1608 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1609
1610 ASSERT(dev != NULL, return -1;);
1611 self = (struct smsc_ircc_cb *) dev->priv;
1612 ASSERT(self != NULL, return 0;);
1613
1614 iobase = self->io.fir_base;
1615
1616 /* Stop device */
1617 netif_stop_queue(dev);
1618
1619 /* Stop and remove instance of IrLAP */
1620 if (self->irlap)
1621 irlap_close(self->irlap);
1622 self->irlap = NULL;
1623
1624 free_irq(self->io.irq, dev);
1625
1626 disable_dma(self->io.dma);
1627
1628 free_dma(self->io.dma);
1629
1630 return 0;
1631 }
1632
1633
1634 static void smsc_ircc_suspend(struct smsc_ircc_cb *self)
1635 {
1636 MESSAGE("%s, Suspending\n", driver_name);
1637
1638 if (self->io.suspended)
1639 return;
1640
1641 smsc_ircc_net_close(self->netdev);
1642
1643 self->io.suspended = 1;
1644 }
1645
1646 static void smsc_ircc_wakeup(struct smsc_ircc_cb *self)
1647 {
1648 if (!self->io.suspended)
1649 return;
1650
1651 /* The code was doing a "cli()" here, but this can't be right.
1652 * If you need protection, do it in net_open with a spinlock
1653 * or give a good reason. - Jean II */
1654
1655 smsc_ircc_net_open(self->netdev);
1656
1657 MESSAGE("%s, Waking up\n", driver_name);
1658 }
1659
1660 static int smsc_ircc_pmproc(struct pm_dev *dev, pm_request_t rqst, void *data)
1661 {
1662 struct smsc_ircc_cb *self = (struct smsc_ircc_cb*) dev->data;
1663 if (self) {
1664 switch (rqst) {
1665 case PM_SUSPEND:
1666 smsc_ircc_suspend(self);
1667 break;
1668 case PM_RESUME:
1669 smsc_ircc_wakeup(self);
1670 break;
1671 }
1672 }
1673 return 0;
1674 }
1675
1676 /*
1677 * Function smsc_ircc_close (self)
1678 *
1679 * Close driver instance
1680 *
1681 */
1682 static int __exit smsc_ircc_close(struct smsc_ircc_cb *self)
1683 {
1684 int iobase;
1685 unsigned long flags;
1686
1687 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1688
1689 ASSERT(self != NULL, return -1;);
1690
1691 iobase = self->io.fir_base;
1692
1693 if (self->pmdev)
1694 pm_unregister(self->pmdev);
1695
1696 /* Remove netdevice */
1697 unregister_netdev(self->netdev);
1698
1699 /* Make sure the irq handler is not exectuting */
1700 spin_lock_irqsave(&self->lock, flags);
1701
1702 /* Stop interrupts */
1703 register_bank(iobase, 0);
1704 outb(0, iobase+IRCC_IER);
1705 outb(IRCC_MASTER_RESET, iobase+IRCC_MASTER);
1706 outb(0x00, iobase+IRCC_MASTER);
1707 #if 0
1708 /* Reset to SIR mode */
1709 register_bank(iobase, 1);
1710 outb(IRCC_CFGA_IRDA_SIR_A|IRCC_CFGA_TX_POLARITY, iobase+IRCC_SCE_CFGA);
1711 outb(IRCC_CFGB_IR, iobase+IRCC_SCE_CFGB);
1712 #endif
1713 spin_unlock_irqrestore(&self->lock, flags);
1714
1715 /* Release the PORTS that this driver is using */
1716 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __FUNCTION__,
1717 self->io.fir_base);
1718
1719 release_region(self->io.fir_base, self->io.fir_ext);
1720
1721 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __FUNCTION__,
1722 self->io.sir_base);
1723
1724 release_region(self->io.sir_base, self->io.sir_ext);
1725
1726 if (self->tx_buff.head)
1727 dma_free_coherent(NULL, self->tx_buff.truesize,
1728 self->tx_buff.head, self->tx_buff_dma);
1729
1730 if (self->rx_buff.head)
1731 dma_free_coherent(NULL, self->rx_buff.truesize,
1732 self->rx_buff.head, self->rx_buff_dma);
1733
1734 free_netdev(self->netdev);
1735
1736 return 0;
1737 }
1738
1739 static void __exit smsc_ircc_cleanup(void)
1740 {
1741 int i;
1742
1743 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1744
1745 for (i=0; i < 2; i++) {
1746 if (dev_self[i])
1747 smsc_ircc_close(dev_self[i]);
1748 }
1749 }
1750
1751 /*
1752 * Start SIR operations
1753 *
1754 * This function *must* be called with spinlock held, because it may
1755 * be called from the irq handler (via smsc_ircc_change_speed()). - Jean II
1756 */
1757 void smsc_ircc_sir_start(struct smsc_ircc_cb *self)
1758 {
1759 struct net_device *dev;
1760 int fir_base, sir_base;
1761
1762 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1763
1764 ASSERT(self != NULL, return;);
1765 dev= self->netdev;
1766 ASSERT(dev != NULL, return;);
1767 dev->hard_start_xmit = &smsc_ircc_hard_xmit_sir;
1768
1769 fir_base = self->io.fir_base;
1770 sir_base = self->io.sir_base;
1771
1772 /* Reset everything */
1773 outb(IRCC_MASTER_RESET, fir_base+IRCC_MASTER);
1774
1775 #if SMSC_IRCC2_C_SIR_STOP
1776 /*smsc_ircc_sir_stop(self);*/
1777 #endif
1778
1779 register_bank(fir_base, 1);
1780 outb(((inb(fir_base+IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | IRCC_CFGA_IRDA_SIR_A), fir_base+IRCC_SCE_CFGA);
1781
1782 /* Initialize UART */
1783 outb(UART_LCR_WLEN8, sir_base+UART_LCR); /* Reset DLAB */
1784 outb((UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2), sir_base+UART_MCR);
1785
1786 /* Turn on interrups */
1787 outb(UART_IER_RLSI | UART_IER_RDI |UART_IER_THRI, sir_base+UART_IER);
1788
1789 IRDA_DEBUG(3, "%s() - exit\n", __FUNCTION__);
1790
1791 outb(0x00, fir_base+IRCC_MASTER);
1792 }
1793
1794 #if SMSC_IRCC2_C_SIR_STOP
1795 void smsc_ircc_sir_stop(struct smsc_ircc_cb *self)
1796 {
1797 int iobase;
1798
1799 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1800 iobase = self->io.sir_base;
1801
1802 /* Reset UART */
1803 outb(0, iobase+UART_MCR);
1804
1805 /* Turn off interrupts */
1806 outb(0, iobase+UART_IER);
1807 }
1808 #endif
1809
1810 /*
1811 * Function smsc_sir_write_wakeup (self)
1812 *
1813 * Called by the SIR interrupt handler when there's room for more data.
1814 * If we have more packets to send, we send them here.
1815 *
1816 */
1817 static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self)
1818 {
1819 int actual = 0;
1820 int iobase;
1821 int fcr;
1822
1823 ASSERT(self != NULL, return;);
1824
1825 IRDA_DEBUG(4, "%s\n", __FUNCTION__);
1826
1827 iobase = self->io.sir_base;
1828
1829 /* Finished with frame? */
1830 if (self->tx_buff.len > 0) {
1831 /* Write data left in transmit buffer */
1832 actual = smsc_ircc_sir_write(iobase, self->io.fifo_size,
1833 self->tx_buff.data, self->tx_buff.len);
1834 self->tx_buff.data += actual;
1835 self->tx_buff.len -= actual;
1836 } else {
1837
1838 /*if (self->tx_buff.len ==0) {*/
1839
1840 /*
1841 * Now serial buffer is almost free & we can start
1842 * transmission of another packet. But first we must check
1843 * if we need to change the speed of the hardware
1844 */
1845 if (self->new_speed) {
1846 IRDA_DEBUG(5, "%s(), Changing speed to %d.\n",
1847 __FUNCTION__, self->new_speed);
1848 smsc_ircc_sir_wait_hw_transmitter_finish(self);
1849 smsc_ircc_change_speed(self, self->new_speed);
1850 self->new_speed = 0;
1851 } else {
1852 /* Tell network layer that we want more frames */
1853 netif_wake_queue(self->netdev);
1854 }
1855 self->stats.tx_packets++;
1856
1857 if(self->io.speed <= 115200) {
1858 /*
1859 * Reset Rx FIFO to make sure that all reflected transmit data
1860 * is discarded. This is needed for half duplex operation
1861 */
1862 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR;
1863 if (self->io.speed < 38400)
1864 fcr |= UART_FCR_TRIGGER_1;
1865 else
1866 fcr |= UART_FCR_TRIGGER_14;
1867
1868 outb(fcr, iobase+UART_FCR);
1869
1870 /* Turn on receive interrupts */
1871 outb(UART_IER_RDI, iobase+UART_IER);
1872 }
1873 }
1874 }
1875
1876 /*
1877 * Function smsc_ircc_sir_write (iobase, fifo_size, buf, len)
1878 *
1879 * Fill Tx FIFO with transmit data
1880 *
1881 */
1882 static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len)
1883 {
1884 int actual = 0;
1885
1886 /* Tx FIFO should be empty! */
1887 if (!(inb(iobase+UART_LSR) & UART_LSR_THRE)) {
1888 WARNING("%s(), failed, fifo not empty!\n", __FUNCTION__);
1889 return 0;
1890 }
1891
1892 /* Fill FIFO with current frame */
1893 while ((fifo_size-- > 0) && (actual < len)) {
1894 /* Transmit next byte */
1895 outb(buf[actual], iobase+UART_TX);
1896 actual++;
1897 }
1898 return actual;
1899 }
1900
1901 /*
1902 * Function smsc_ircc_is_receiving (self)
1903 *
1904 * Returns true is we are currently receiving data
1905 *
1906 */
1907 static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self)
1908 {
1909 return (self->rx_buff.state != OUTSIDE_FRAME);
1910 }
1911
1912
1913 /*
1914 * Function smsc_ircc_probe_transceiver(self)
1915 *
1916 * Tries to find the used Transceiver
1917 *
1918 */
1919 static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self)
1920 {
1921 unsigned int i;
1922
1923 ASSERT(self != NULL, return;);
1924
1925 for(i=0; smsc_transceivers[i].name!=NULL; i++)
1926 if((*smsc_transceivers[i].probe)(self->io.fir_base)) {
1927 MESSAGE(" %s transceiver found\n", smsc_transceivers[i].name);
1928 self->transceiver= i+1;
1929 return;
1930 }
1931 MESSAGE("No transceiver found. Defaulting to %s\n", smsc_transceivers[SMSC_IRCC2_C_DEFAULT_TRANSCEIVER].name);
1932
1933 self->transceiver= SMSC_IRCC2_C_DEFAULT_TRANSCEIVER;
1934 }
1935
1936
1937 /*
1938 * Function smsc_ircc_set_transceiver_for_speed(self, speed)
1939 *
1940 * Set the transceiver according to the speed
1941 *
1942 */
1943 static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed)
1944 {
1945 unsigned int trx;
1946
1947 trx = self->transceiver;
1948 if(trx>0) (*smsc_transceivers[trx-1].set_for_speed)(self->io.fir_base, speed);
1949 }
1950
1951 /*
1952 * Function smsc_ircc_wait_hw_transmitter_finish ()
1953 *
1954 * Wait for the real end of HW transmission
1955 *
1956 * The UART is a strict FIFO, and we get called only when we have finished
1957 * pushing data to the FIFO, so the maximum amount of time we must wait
1958 * is only for the FIFO to drain out.
1959 *
1960 * We use a simple calibrated loop. We may need to adjust the loop
1961 * delay (udelay) to balance I/O traffic and latency. And we also need to
1962 * adjust the maximum timeout.
1963 * It would probably be better to wait for the proper interrupt,
1964 * but it doesn't seem to be available.
1965 *
1966 * We can't use jiffies or kernel timers because :
1967 * 1) We are called from the interrupt handler, which disable softirqs,
1968 * so jiffies won't be increased
1969 * 2) Jiffies granularity is usually very coarse (10ms), and we don't
1970 * want to wait that long to detect stuck hardware.
1971 * Jean II
1972 */
1973
1974 static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self)
1975 {
1976 int iobase;
1977 int count = SMSC_IRCC2_HW_TRANSMITTER_TIMEOUT_US;
1978
1979 iobase = self->io.sir_base;
1980
1981 /* Calibrated busy loop */
1982 while((count-- > 0) && !(inb(iobase+UART_LSR) & UART_LSR_TEMT))
1983 udelay(1);
1984
1985 if(count == 0)
1986 IRDA_DEBUG(0, "%s(): stuck transmitter\n", __FUNCTION__);
1987 }
1988
1989
1990 /* PROBING
1991 *
1992 *
1993 */
1994
1995 static int __init smsc_ircc_look_for_chips(void)
1996 {
1997 smsc_chip_address_t *address;
1998 char *type;
1999 unsigned int cfg_base, found;
2000
2001 found = 0;
2002 address = possible_addresses;
2003
2004 while(address->cfg_base){
2005 cfg_base = address->cfg_base;
2006
2007 /*printk(KERN_WARNING "%s(): probing: 0x%02x for: 0x%02x\n", __FUNCTION__, cfg_base, address->type);*/
2008
2009 if( address->type & SMSCSIO_TYPE_FDC){
2010 type = "FDC";
2011 if((address->type) & SMSCSIO_TYPE_FLAT) {
2012 if(!smsc_superio_flat(fdc_chips_flat,cfg_base, type)) found++;
2013 }
2014 if((address->type) & SMSCSIO_TYPE_PAGED) {
2015 if(!smsc_superio_paged(fdc_chips_paged,cfg_base, type)) found++;
2016 }
2017 }
2018 if( address->type & SMSCSIO_TYPE_LPC){
2019 type = "LPC";
2020 if((address->type) & SMSCSIO_TYPE_FLAT) {
2021 if(!smsc_superio_flat(lpc_chips_flat,cfg_base,type)) found++;
2022 }
2023 if((address->type) & SMSCSIO_TYPE_PAGED) {
2024 if(!smsc_superio_paged(lpc_chips_paged,cfg_base,"LPC")) found++;
2025 }
2026 }
2027 address++;
2028 }
2029 return found;
2030 }
2031
2032 /*
2033 * Function smsc_superio_flat (chip, base, type)
2034 *
2035 * Try to get configuration of a smc SuperIO chip with flat register model
2036 *
2037 */
2038 static int __init smsc_superio_flat(const smsc_chip_t *chips, unsigned short cfgbase, char *type)
2039 {
2040 unsigned short firbase, sirbase;
2041 u8 mode, dma, irq;
2042 int ret = -ENODEV;
2043
2044 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2045
2046 if (smsc_ircc_probe(cfgbase, SMSCSIOFLAT_DEVICEID_REG, chips, type)==NULL)
2047 return ret;
2048
2049 outb(SMSCSIOFLAT_UARTMODE0C_REG, cfgbase);
2050 mode = inb(cfgbase+1);
2051
2052 /*printk(KERN_WARNING "%s(): mode: 0x%02x\n", __FUNCTION__, mode);*/
2053
2054 if(!(mode & SMSCSIOFLAT_UART2MODE_VAL_IRDA))
2055 WARNING("%s(): IrDA not enabled\n", __FUNCTION__);
2056
2057 outb(SMSCSIOFLAT_UART2BASEADDR_REG, cfgbase);
2058 sirbase = inb(cfgbase+1) << 2;
2059
2060 /* FIR iobase */
2061 outb(SMSCSIOFLAT_FIRBASEADDR_REG, cfgbase);
2062 firbase = inb(cfgbase+1) << 3;
2063
2064 /* DMA */
2065 outb(SMSCSIOFLAT_FIRDMASELECT_REG, cfgbase);
2066 dma = inb(cfgbase+1) & SMSCSIOFLAT_FIRDMASELECT_MASK;
2067
2068 /* IRQ */
2069 outb(SMSCSIOFLAT_UARTIRQSELECT_REG, cfgbase);
2070 irq = inb(cfgbase+1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
2071
2072 MESSAGE("%s(): fir: 0x%02x, sir: 0x%02x, dma: %02d, irq: %d, mode: 0x%02x\n", __FUNCTION__, firbase, sirbase, dma, irq, mode);
2073
2074 if (firbase) {
2075 if (smsc_ircc_open(firbase, sirbase, dma, irq) == 0)
2076 ret=0;
2077 }
2078
2079 /* Exit configuration */
2080 outb(SMSCSIO_CFGEXITKEY, cfgbase);
2081
2082 return ret;
2083 }
2084
2085 /*
2086 * Function smsc_superio_paged (chip, base, type)
2087 *
2088 * Try to get configuration of a smc SuperIO chip with paged register model
2089 *
2090 */
2091 static int __init smsc_superio_paged(const smsc_chip_t *chips, unsigned short cfg_base, char *type)
2092 {
2093 unsigned short fir_io, sir_io;
2094 int ret = -ENODEV;
2095
2096 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2097
2098 if (smsc_ircc_probe(cfg_base,0x20,chips,type)==NULL)
2099 return ret;
2100
2101 /* Select logical device (UART2) */
2102 outb(0x07, cfg_base);
2103 outb(0x05, cfg_base + 1);
2104
2105 /* SIR iobase */
2106 outb(0x60, cfg_base);
2107 sir_io = inb(cfg_base + 1) << 8;
2108 outb(0x61, cfg_base);
2109 sir_io |= inb(cfg_base + 1);
2110
2111 /* Read FIR base */
2112 outb(0x62, cfg_base);
2113 fir_io = inb(cfg_base + 1) << 8;
2114 outb(0x63, cfg_base);
2115 fir_io |= inb(cfg_base + 1);
2116 outb(0x2b, cfg_base); /* ??? */
2117
2118 if (fir_io) {
2119 if (smsc_ircc_open(fir_io, sir_io, ircc_dma, ircc_irq) == 0)
2120 ret=0;
2121 }
2122
2123 /* Exit configuration */
2124 outb(SMSCSIO_CFGEXITKEY, cfg_base);
2125
2126 return ret;
2127 }
2128
2129
2130 static int __init smsc_access(unsigned short cfg_base,unsigned char reg)
2131 {
2132 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2133
2134 outb(reg, cfg_base);
2135
2136 if (inb(cfg_base)!=reg)
2137 return -1;
2138
2139 return 0;
2140 }
2141
2142 static const smsc_chip_t * __init smsc_ircc_probe(unsigned short cfg_base,u8 reg,const smsc_chip_t *chip,char *type)
2143 {
2144 u8 devid,xdevid,rev;
2145
2146 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2147
2148 /* Leave configuration */
2149
2150 outb(SMSCSIO_CFGEXITKEY, cfg_base);
2151
2152 if (inb(cfg_base) == SMSCSIO_CFGEXITKEY) /* not a smc superio chip */
2153 return NULL;
2154
2155 outb(reg, cfg_base);
2156
2157 xdevid=inb(cfg_base+1);
2158
2159 /* Enter configuration */
2160
2161 outb(SMSCSIO_CFGACCESSKEY, cfg_base);
2162
2163 #if 0
2164 if (smsc_access(cfg_base,0x55)) /* send second key and check */
2165 return NULL;
2166 #endif
2167
2168 /* probe device ID */
2169
2170 if (smsc_access(cfg_base,reg))
2171 return NULL;
2172
2173 devid=inb(cfg_base+1);
2174
2175 if (devid==0) /* typical value for unused port */
2176 return NULL;
2177
2178 if (devid==0xff) /* typical value for unused port */
2179 return NULL;
2180
2181 /* probe revision ID */
2182
2183 if (smsc_access(cfg_base,reg+1))
2184 return NULL;
2185
2186 rev=inb(cfg_base+1);
2187
2188 if (rev>=128) /* i think this will make no sense */
2189 return NULL;
2190
2191 if (devid==xdevid) /* protection against false positives */
2192 return NULL;
2193
2194 /* Check for expected device ID; are there others? */
2195
2196 while(chip->devid!=devid) {
2197
2198 chip++;
2199
2200 if (chip->name==NULL)
2201 return NULL;
2202 }
2203
2204 MESSAGE("found SMC SuperIO Chip (devid=0x%02x rev=%02X base=0x%04x): %s%s\n",devid,rev,cfg_base,type,chip->name);
2205
2206 if (chip->rev>rev){
2207 MESSAGE("Revision higher than expected\n");
2208 return NULL;
2209 }
2210
2211 if (chip->flags&NoIRDA)
2212 MESSAGE("chipset does not support IRDA\n");
2213
2214 return chip;
2215 }
2216
2217 static int __init smsc_superio_fdc(unsigned short cfg_base)
2218 {
2219 int ret = -1;
2220
2221 if (!request_region(cfg_base, 2, driver_name)) {
2222 WARNING("%s: can't get cfg_base of 0x%03x\n",
2223 __FUNCTION__, cfg_base);
2224 } else {
2225 if (!smsc_superio_flat(fdc_chips_flat,cfg_base,"FDC")
2226 ||!smsc_superio_paged(fdc_chips_paged,cfg_base,"FDC"))
2227 ret = 0;
2228
2229 release_region(cfg_base, 2);
2230 }
2231
2232 return ret;
2233 }
2234
2235 static int __init smsc_superio_lpc(unsigned short cfg_base)
2236 {
2237 int ret = -1;
2238
2239 if (!request_region(cfg_base, 2, driver_name)) {
2240 WARNING("%s: can't get cfg_base of 0x%03x\n",
2241 __FUNCTION__, cfg_base);
2242 } else {
2243 if (!smsc_superio_flat(lpc_chips_flat,cfg_base,"LPC")
2244 ||!smsc_superio_paged(lpc_chips_paged,cfg_base,"LPC"))
2245 ret = 0;
2246 release_region(cfg_base, 2);
2247 }
2248 return ret;
2249 }
2250
2251 /************************************************
2252 *
2253 * Transceivers specific functions
2254 *
2255 ************************************************/
2256
2257
2258 /*
2259 * Function smsc_ircc_set_transceiver_smsc_ircc_atc(fir_base, speed)
2260 *
2261 * Program transceiver through smsc-ircc ATC circuitry
2262 *
2263 */
2264
2265 static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed)
2266 {
2267 unsigned long jiffies_now, jiffies_timeout;
2268 u8 val;
2269
2270 jiffies_now= jiffies;
2271 jiffies_timeout= jiffies+SMSC_IRCC2_ATC_PROGRAMMING_TIMEOUT_JIFFIES;
2272
2273 /* ATC */
2274 register_bank(fir_base, 4);
2275 outb((inb(fir_base+IRCC_ATC) & IRCC_ATC_MASK) |IRCC_ATC_nPROGREADY|IRCC_ATC_ENABLE, fir_base+IRCC_ATC);
2276 while((val=(inb(fir_base+IRCC_ATC) & IRCC_ATC_nPROGREADY)) && !time_after(jiffies, jiffies_timeout));
2277 if(val)
2278 WARNING("%s(): ATC: 0x%02x\n", __FUNCTION__,
2279 inb(fir_base+IRCC_ATC));
2280 }
2281
2282 /*
2283 * Function smsc_ircc_probe_transceiver_smsc_ircc_atc(fir_base)
2284 *
2285 * Probe transceiver smsc-ircc ATC circuitry
2286 *
2287 */
2288
2289 static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base)
2290 {
2291 return 0;
2292 }
2293
2294 /*
2295 * Function smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(self, speed)
2296 *
2297 * Set transceiver
2298 *
2299 */
2300
2301 static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed)
2302 {
2303 u8 fast_mode;
2304
2305 switch(speed)
2306 {
2307 default:
2308 case 576000 :
2309 fast_mode = 0;
2310 break;
2311 case 1152000 :
2312 case 4000000 :
2313 fast_mode = IRCC_LCR_A_FAST;
2314 break;
2315
2316 }
2317 register_bank(fir_base, 0);
2318 outb((inb(fir_base+IRCC_LCR_A) & 0xbf) | fast_mode, fir_base+IRCC_LCR_A);
2319 }
2320
2321 /*
2322 * Function smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(fir_base)
2323 *
2324 * Probe transceiver
2325 *
2326 */
2327
2328 static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base)
2329 {
2330 return 0;
2331 }
2332
2333 /*
2334 * Function smsc_ircc_set_transceiver_toshiba_sat1800(fir_base, speed)
2335 *
2336 * Set transceiver
2337 *
2338 */
2339
2340 static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed)
2341 {
2342 u8 fast_mode;
2343
2344 switch(speed)
2345 {
2346 default:
2347 case 576000 :
2348 fast_mode = 0;
2349 break;
2350 case 1152000 :
2351 case 4000000 :
2352 fast_mode = /*IRCC_LCR_A_FAST |*/ IRCC_LCR_A_GP_DATA;
2353 break;
2354
2355 }
2356 /* This causes an interrupt */
2357 register_bank(fir_base, 0);
2358 outb((inb(fir_base+IRCC_LCR_A) & 0xbf) | fast_mode, fir_base+IRCC_LCR_A);
2359 }
2360
2361 /*
2362 * Function smsc_ircc_probe_transceiver_toshiba_sat1800(fir_base)
2363 *
2364 * Probe transceiver
2365 *
2366 */
2367
2368 static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base)
2369 {
2370 return 0;
2371 }
2372
2373
2374 module_init(smsc_ircc_init);
2375 module_exit(smsc_ircc_cleanup);
2376
2377 MODULE_AUTHOR("Daniele Peri <peri@csai.unipa.it>");
2378 MODULE_DESCRIPTION("SMC IrCC SIR/FIR controller driver");
2379 MODULE_LICENSE("GPL");
2380
2381 module_param(ircc_dma, int, 0);
2382 MODULE_PARM_DESC(ircc_dma, "DMA channel");
2383 module_param(ircc_irq, int, 0);
2384 MODULE_PARM_DESC(ircc_irq, "IRQ line");
2385 module_param(ircc_fir, int, 0);
2386 MODULE_PARM_DESC(ircc_fir, "FIR Base Address");
2387 module_param(ircc_sir, int, 0);
2388 MODULE_PARM_DESC(ircc_sir, "SIR Base Address");
2389 module_param(ircc_cfg, int, 0);
2390 MODULE_PARM_DESC(ircc_cfg, "Configuration register base address");
2391 module_param(ircc_transceiver, int, 0);
2392 MODULE_PARM_DESC(ircc_transceiver, "Transceiver type");
2393
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