1 /*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28
29 /* Linux PRO/1000 Ethernet Driver main header file */
30
31 #ifndef _IGB_H_
32 #define _IGB_H_
33
34 #include "e1000_mac.h"
35 #include "e1000_82575.h"
36
37 #include <linux/clocksource.h>
38 #include <linux/timecompare.h>
39 #include <linux/net_tstamp.h>
40
41 struct igb_adapter;
42
43 /* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */
44 #define IGB_START_ITR 648
45
46 /* TX/RX descriptor defines */
47 #define IGB_DEFAULT_TXD 256
48 #define IGB_MIN_TXD 80
49 #define IGB_MAX_TXD 4096
50
51 #define IGB_DEFAULT_RXD 256
52 #define IGB_MIN_RXD 80
53 #define IGB_MAX_RXD 4096
54
55 #define IGB_DEFAULT_ITR 3 /* dynamic */
56 #define IGB_MAX_ITR_USECS 10000
57 #define IGB_MIN_ITR_USECS 10
58
59 /* Transmit and receive queues */
60 #define IGB_MAX_RX_QUEUES (adapter->vfs_allocated_count ? \
61 (adapter->vfs_allocated_count > 6 ? 1 : 2) : 4)
62 #define IGB_MAX_TX_QUEUES IGB_MAX_RX_QUEUES
63 #define IGB_ABS_MAX_TX_QUEUES 4
64
65 #define IGB_MAX_VF_MC_ENTRIES 30
66 #define IGB_MAX_VF_FUNCTIONS 8
67 #define IGB_MAX_VFTA_ENTRIES 128
68
69 struct vf_data_storage {
70 unsigned char vf_mac_addresses[ETH_ALEN];
71 u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
72 u16 num_vf_mc_hashes;
73 bool clear_to_send;
74 };
75
76 /* RX descriptor control thresholds.
77 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
78 * descriptors available in its onboard memory.
79 * Setting this to 0 disables RX descriptor prefetch.
80 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
81 * available in host memory.
82 * If PTHRESH is 0, this should also be 0.
83 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
84 * descriptors until either it has this many to write back, or the
85 * ITR timer expires.
86 */
87 #define IGB_RX_PTHRESH 16
88 #define IGB_RX_HTHRESH 8
89 #define IGB_RX_WTHRESH 1
90
91 /* this is the size past which hardware will drop packets when setting LPE=0 */
92 #define MAXIMUM_ETHERNET_VLAN_SIZE 1522
93
94 /* Supported Rx Buffer Sizes */
95 #define IGB_RXBUFFER_128 128 /* Used for packet split */
96 #define IGB_RXBUFFER_256 256 /* Used for packet split */
97 #define IGB_RXBUFFER_512 512
98 #define IGB_RXBUFFER_1024 1024
99 #define IGB_RXBUFFER_2048 2048
100 #define IGB_RXBUFFER_16384 16384
101
102 #define MAX_STD_JUMBO_FRAME_SIZE 9234
103
104 /* How many Tx Descriptors do we need to call netif_wake_queue ? */
105 #define IGB_TX_QUEUE_WAKE 16
106 /* How many Rx Buffers do we bundle into one write to the hardware ? */
107 #define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */
108
109 #define AUTO_ALL_MODES 0
110 #define IGB_EEPROM_APME 0x0400
111
112 #ifndef IGB_MASTER_SLAVE
113 /* Switch to override PHY master/slave setting */
114 #define IGB_MASTER_SLAVE e1000_ms_hw_default
115 #endif
116
117 #define IGB_MNG_VLAN_NONE -1
118
119 /* wrapper around a pointer to a socket buffer,
120 * so a DMA handle can be stored along with the buffer */
121 struct igb_buffer {
122 struct sk_buff *skb;
123 dma_addr_t dma;
124 union {
125 /* TX */
126 struct {
127 unsigned long time_stamp;
128 u16 length;
129 u16 next_to_watch;
130 };
131 /* RX */
132 struct {
133 struct page *page;
134 u64 page_dma;
135 unsigned int page_offset;
136 };
137 };
138 };
139
140 struct igb_tx_queue_stats {
141 u64 packets;
142 u64 bytes;
143 };
144
145 struct igb_rx_queue_stats {
146 u64 packets;
147 u64 bytes;
148 u64 drops;
149 };
150
151 struct igb_ring {
152 struct igb_adapter *adapter; /* backlink */
153 void *desc; /* descriptor ring memory */
154 dma_addr_t dma; /* phys address of the ring */
155 unsigned int size; /* length of desc. ring in bytes */
156 unsigned int count; /* number of desc. in the ring */
157 u16 next_to_use;
158 u16 next_to_clean;
159 u16 head;
160 u16 tail;
161 struct igb_buffer *buffer_info; /* array of buffer info structs */
162
163 u32 eims_value;
164 u32 itr_val;
165 u16 itr_register;
166 u16 cpu;
167
168 u16 queue_index;
169 u16 reg_idx;
170 unsigned int total_bytes;
171 unsigned int total_packets;
172
173 union {
174 /* TX */
175 struct {
176 struct igb_tx_queue_stats tx_stats;
177 bool detect_tx_hung;
178 };
179 /* RX */
180 struct {
181 struct igb_rx_queue_stats rx_stats;
182 u64 rx_queue_drops;
183 struct napi_struct napi;
184 int set_itr;
185 struct igb_ring *buddy;
186 };
187 };
188
189 char name[IFNAMSIZ + 5];
190 };
191
192 #define E1000_RX_DESC_ADV(R, i) \
193 (&(((union e1000_adv_rx_desc *)((R).desc))[i]))
194 #define E1000_TX_DESC_ADV(R, i) \
195 (&(((union e1000_adv_tx_desc *)((R).desc))[i]))
196 #define E1000_TX_CTXTDESC_ADV(R, i) \
197 (&(((struct e1000_adv_tx_context_desc *)((R).desc))[i]))
198
199 /* board specific private data structure */
200
201 struct igb_adapter {
202 struct timer_list watchdog_timer;
203 struct timer_list phy_info_timer;
204 struct vlan_group *vlgrp;
205 u16 mng_vlan_id;
206 u32 bd_number;
207 u32 rx_buffer_len;
208 u32 wol;
209 u32 en_mng_pt;
210 u16 link_speed;
211 u16 link_duplex;
212 unsigned int total_tx_bytes;
213 unsigned int total_tx_packets;
214 unsigned int total_rx_bytes;
215 unsigned int total_rx_packets;
216 /* Interrupt Throttle Rate */
217 u32 itr;
218 u32 itr_setting;
219 u16 tx_itr;
220 u16 rx_itr;
221
222 struct work_struct reset_task;
223 struct work_struct watchdog_task;
224 bool fc_autoneg;
225 u8 tx_timeout_factor;
226 struct timer_list blink_timer;
227 unsigned long led_status;
228
229 /* TX */
230 struct igb_ring *tx_ring; /* One per active queue */
231 unsigned int restart_queue;
232 unsigned long tx_queue_len;
233 u32 txd_cmd;
234 u32 gotc;
235 u64 gotc_old;
236 u64 tpt_old;
237 u64 colc_old;
238 u32 tx_timeout_count;
239
240 /* RX */
241 struct igb_ring *rx_ring; /* One per active queue */
242 int num_tx_queues;
243 int num_rx_queues;
244
245 u64 hw_csum_err;
246 u64 hw_csum_good;
247 u32 alloc_rx_buff_failed;
248 u32 gorc;
249 u64 gorc_old;
250 u16 rx_ps_hdr_size;
251 u32 max_frame_size;
252 u32 min_frame_size;
253
254 /* OS defined structs */
255 struct net_device *netdev;
256 struct napi_struct napi;
257 struct pci_dev *pdev;
258 struct net_device_stats net_stats;
259 struct cyclecounter cycles;
260 struct timecounter clock;
261 struct timecompare compare;
262 struct hwtstamp_config hwtstamp_config;
263
264 /* structs defined in e1000_hw.h */
265 struct e1000_hw hw;
266 struct e1000_hw_stats stats;
267 struct e1000_phy_info phy_info;
268 struct e1000_phy_stats phy_stats;
269
270 u32 test_icr;
271 struct igb_ring test_tx_ring;
272 struct igb_ring test_rx_ring;
273
274 int msg_enable;
275 struct msix_entry *msix_entries;
276 u32 eims_enable_mask;
277 u32 eims_other;
278
279 /* to not mess up cache alignment, always add to the bottom */
280 unsigned long state;
281 unsigned int flags;
282 u32 eeprom_wol;
283
284 struct igb_ring *multi_tx_table[IGB_ABS_MAX_TX_QUEUES];
285 unsigned int tx_ring_count;
286 unsigned int rx_ring_count;
287 unsigned int vfs_allocated_count;
288 struct vf_data_storage *vf_data;
289 };
290
291 #define IGB_FLAG_HAS_MSI (1 << 0)
292 #define IGB_FLAG_DCA_ENABLED (1 << 1)
293 #define IGB_FLAG_QUAD_PORT_A (1 << 2)
294 #define IGB_FLAG_NEED_CTX_IDX (1 << 3)
295 #define IGB_FLAG_RX_CSUM_DISABLED (1 << 4)
296
297 enum e1000_state_t {
298 __IGB_TESTING,
299 __IGB_RESETTING,
300 __IGB_DOWN
301 };
302
303 enum igb_boards {
304 board_82575,
305 };
306
307 extern char igb_driver_name[];
308 extern char igb_driver_version[];
309
310 extern char *igb_get_hw_dev_name(struct e1000_hw *hw);
311 extern int igb_up(struct igb_adapter *);
312 extern void igb_down(struct igb_adapter *);
313 extern void igb_reinit_locked(struct igb_adapter *);
314 extern void igb_reset(struct igb_adapter *);
315 extern int igb_set_spd_dplx(struct igb_adapter *, u16);
316 extern int igb_setup_tx_resources(struct igb_adapter *, struct igb_ring *);
317 extern int igb_setup_rx_resources(struct igb_adapter *, struct igb_ring *);
318 extern void igb_free_tx_resources(struct igb_ring *);
319 extern void igb_free_rx_resources(struct igb_ring *);
320 extern void igb_update_stats(struct igb_adapter *);
321 extern void igb_set_ethtool_ops(struct net_device *);
322
323 static inline s32 igb_reset_phy(struct e1000_hw *hw)
324 {
325 if (hw->phy.ops.reset)
326 return hw->phy.ops.reset(hw);
327
328 return 0;
329 }
330
331 static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
332 {
333 if (hw->phy.ops.read_reg)
334 return hw->phy.ops.read_reg(hw, offset, data);
335
336 return 0;
337 }
338
339 static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
340 {
341 if (hw->phy.ops.write_reg)
342 return hw->phy.ops.write_reg(hw, offset, data);
343
344 return 0;
345 }
346
347 static inline s32 igb_get_phy_info(struct e1000_hw *hw)
348 {
349 if (hw->phy.ops.get_phy_info)
350 return hw->phy.ops.get_phy_info(hw);
351
352 return 0;
353 }
354
355 #endif /* _IGB_H_ */
356
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