1 #ifndef _IBM_LANA_INCLUDE_
2 #define _IBM_LANA_INCLUDE_
3
4 #ifdef _IBM_LANA_DRIVER_
5
6 /* maximum packet size */
7
8 #define PKTSIZE 1524
9
10 /* number of transmit buffers */
11
12 #define TXBUFCNT 4
13
14 /* Adapter ID's */
15 #define IBM_LANA_ID 0xffe0
16
17 /* media enumeration - defined in a way that it fits onto the LAN/A's
18 POS registers... */
19
20 typedef enum {
21 Media_10BaseT, Media_10Base5,
22 Media_Unknown, Media_10Base2, Media_Count
23 } ibmlana_medium;
24
25 /* private structure */
26
27 typedef struct {
28 unsigned int slot; /* MCA-Slot-# */
29 int realirq; /* memorizes actual IRQ, even when
30 currently not allocated */
31 ibmlana_medium medium; /* physical cannector */
32 u32 tdastart, txbufstart, /* addresses */
33 rrastart, rxbufstart, rdastart, rxbufcnt, txusedcnt;
34 int nextrxdescr, /* next rx descriptor to be used */
35 lastrxdescr, /* last free rx descriptor */
36 nexttxdescr, /* last tx descriptor to be used */
37 currtxdescr, /* tx descriptor currently tx'ed */
38 txused[TXBUFCNT]; /* busy flags */
39 void __iomem *base;
40 spinlock_t lock;
41 } ibmlana_priv;
42
43 /* this card uses quite a lot of I/O ports...luckily the MCA bus decodes
44 a full 64K I/O range... */
45
46 #define IBM_LANA_IORANGE 0xa0
47
48 /* Command Register: */
49
50 #define SONIC_CMDREG 0x00
51 #define CMDREG_HTX 0x0001 /* halt transmission */
52 #define CMDREG_TXP 0x0002 /* start transmission */
53 #define CMDREG_RXDIS 0x0004 /* disable receiver */
54 #define CMDREG_RXEN 0x0008 /* enable receiver */
55 #define CMDREG_STP 0x0010 /* stop timer */
56 #define CMDREG_ST 0x0020 /* start timer */
57 #define CMDREG_RST 0x0080 /* software reset */
58 #define CMDREG_RRRA 0x0100 /* force SONIC to read first RRA */
59 #define CMDREG_LCAM 0x0200 /* force SONIC to read CAM descrs */
60
61 /* Data Configuration Register */
62
63 #define SONIC_DCREG 0x02
64 #define DCREG_EXBUS 0x8000 /* Extended Bus Mode */
65 #define DCREG_LBR 0x2000 /* Latched Bus Retry */
66 #define DCREG_PO1 0x1000 /* Programmable Outputs */
67 #define DCREG_PO0 0x0800
68 #define DCREG_SBUS 0x0400 /* Synchronous Bus Mode */
69 #define DCREG_USR1 0x0200 /* User Definable Pins */
70 #define DCREG_USR0 0x0100
71 #define DCREG_WC0 0x0000 /* 0..3 Wait States */
72 #define DCREG_WC1 0x0040
73 #define DCREG_WC2 0x0080
74 #define DCREG_WC3 0x00c0
75 #define DCREG_DW16 0x0000 /* 16 bit Bus Mode */
76 #define DCREG_DW32 0x0020 /* 32 bit Bus Mode */
77 #define DCREG_BMS 0x0010 /* Block Mode Select */
78 #define DCREG_RFT4 0x0000 /* 4/8/16/24 bytes RX Threshold */
79 #define DCREG_RFT8 0x0004
80 #define DCREG_RFT16 0x0008
81 #define DCREG_RFT24 0x000c
82 #define DCREG_TFT8 0x0000 /* 8/16/24/28 bytes TX Threshold */
83 #define DCREG_TFT16 0x0001
84 #define DCREG_TFT24 0x0002
85 #define DCREG_TFT28 0x0003
86
87 /* Receive Control Register */
88
89 #define SONIC_RCREG 0x04
90 #define RCREG_ERR 0x8000 /* accept damaged and collided pkts */
91 #define RCREG_RNT 0x4000 /* accept packets that are < 64 */
92 #define RCREG_BRD 0x2000 /* accept broadcasts */
93 #define RCREG_PRO 0x1000 /* promiscous mode */
94 #define RCREG_AMC 0x0800 /* accept all multicasts */
95 #define RCREG_LB_NONE 0x0000 /* no loopback */
96 #define RCREG_LB_MAC 0x0200 /* MAC loopback */
97 #define RCREG_LB_ENDEC 0x0400 /* ENDEC loopback */
98 #define RCREG_LB_XVR 0x0600 /* Transceiver loopback */
99 #define RCREG_MC 0x0100 /* Multicast received */
100 #define RCREG_BC 0x0080 /* Broadcast received */
101 #define RCREG_LPKT 0x0040 /* last packet in RBA */
102 #define RCREG_CRS 0x0020 /* carrier sense present */
103 #define RCREG_COL 0x0010 /* recv'd packet with collision */
104 #define RCREG_CRCR 0x0008 /* recv'd packet with CRC error */
105 #define RCREG_FAER 0x0004 /* recv'd packet with inv. framing */
106 #define RCREG_LBK 0x0002 /* recv'd loopback packet */
107 #define RCREG_PRX 0x0001 /* recv'd packet is OK */
108
109 /* Transmit Control Register */
110
111 #define SONIC_TCREG 0x06
112 #define TCREG_PINT 0x8000 /* generate interrupt after TDA read */
113 #define TCREG_POWC 0x4000 /* timer start out of window detect */
114 #define TCREG_CRCI 0x2000 /* inhibit CRC generation */
115 #define TCREG_EXDIS 0x1000 /* disable excessive deferral timer */
116 #define TCREG_EXD 0x0400 /* excessive deferral occurred */
117 #define TCREG_DEF 0x0200 /* single deferral occurred */
118 #define TCREG_NCRS 0x0100 /* no carrier detected */
119 #define TCREG_CRSL 0x0080 /* carrier lost */
120 #define TCREG_EXC 0x0040 /* excessive collisions occurred */
121 #define TCREG_OWC 0x0020 /* out of window collision occurred */
122 #define TCREG_PMB 0x0008 /* packet monitored bad */
123 #define TCREG_FU 0x0004 /* FIFO underrun */
124 #define TCREG_BCM 0x0002 /* byte count mismatch of fragments */
125 #define TCREG_PTX 0x0001 /* packet transmitted OK */
126
127 /* Interrupt Mask Register */
128
129 #define SONIC_IMREG 0x08
130 #define IMREG_BREN 0x4000 /* interrupt when bus retry occurred */
131 #define IMREG_HBLEN 0x2000 /* interrupt when heartbeat lost */
132 #define IMREG_LCDEN 0x1000 /* interrupt when CAM loaded */
133 #define IMREG_PINTEN 0x0800 /* interrupt when PINT in TDA set */
134 #define IMREG_PRXEN 0x0400 /* interrupt when packet received */
135 #define IMREG_PTXEN 0x0200 /* interrupt when packet was sent */
136 #define IMREG_TXEREN 0x0100 /* interrupt when send failed */
137 #define IMREG_TCEN 0x0080 /* interrupt when timer completed */
138 #define IMREG_RDEEN 0x0040 /* interrupt when RDA exhausted */
139 #define IMREG_RBEEN 0x0020 /* interrupt when RBA exhausted */
140 #define IMREG_RBAEEN 0x0010 /* interrupt when RBA too short */
141 #define IMREG_CRCEN 0x0008 /* interrupt when CRC counter rolls */
142 #define IMREG_FAEEN 0x0004 /* interrupt when FAE counter rolls */
143 #define IMREG_MPEN 0x0002 /* interrupt when MP counter rolls */
144 #define IMREG_RFOEN 0x0001 /* interrupt when Rx FIFO overflows */
145
146 /* Interrupt Status Register */
147
148 #define SONIC_ISREG 0x0a
149 #define ISREG_BR 0x4000 /* bus retry occurred */
150 #define ISREG_HBL 0x2000 /* heartbeat lost */
151 #define ISREG_LCD 0x1000 /* CAM loaded */
152 #define ISREG_PINT 0x0800 /* PINT in TDA set */
153 #define ISREG_PKTRX 0x0400 /* packet received */
154 #define ISREG_TXDN 0x0200 /* packet was sent */
155 #define ISREG_TXER 0x0100 /* send failed */
156 #define ISREG_TC 0x0080 /* timer completed */
157 #define ISREG_RDE 0x0040 /* RDA exhausted */
158 #define ISREG_RBE 0x0020 /* RBA exhausted */
159 #define ISREG_RBAE 0x0010 /* RBA too short for received frame */
160 #define ISREG_CRC 0x0008 /* CRC counter rolls over */
161 #define ISREG_FAE 0x0004 /* FAE counter rolls over */
162 #define ISREG_MP 0x0002 /* MP counter rolls over */
163 #define ISREG_RFO 0x0001 /* Rx FIFO overflows */
164
165 #define SONIC_UTDA 0x0c /* current transmit descr address */
166 #define SONIC_CTDA 0x0e
167
168 #define SONIC_URDA 0x1a /* current receive descr address */
169 #define SONIC_CRDA 0x1c
170
171 #define SONIC_CRBA0 0x1e /* current receive buffer address */
172 #define SONIC_CRBA1 0x20
173
174 #define SONIC_RBWC0 0x22 /* word count in receive buffer */
175 #define SONIC_RBWC1 0x24
176
177 #define SONIC_EOBC 0x26 /* minimum space to be free in RBA */
178
179 #define SONIC_URRA 0x28 /* upper address of CDA & Recv Area */
180
181 #define SONIC_RSA 0x2a /* start of receive resource area */
182
183 #define SONIC_REA 0x2c /* end of receive resource area */
184
185 #define SONIC_RRP 0x2e /* resource read pointer */
186
187 #define SONIC_RWP 0x30 /* resource write pointer */
188
189 #define SONIC_CAMEPTR 0x42 /* CAM entry pointer */
190
191 #define SONIC_CAMADDR2 0x44 /* CAM address ports */
192 #define SONIC_CAMADDR1 0x46
193 #define SONIC_CAMADDR0 0x48
194
195 #define SONIC_CAMPTR 0x4c /* lower address of CDA */
196
197 #define SONIC_CAMCNT 0x4e /* # of CAM descriptors to load */
198
199 /* Data Configuration Register 2 */
200
201 #define SONIC_DCREG2 0x7e
202 #define DCREG2_EXPO3 0x8000 /* extended programmable outputs */
203 #define DCREG2_EXPO2 0x4000
204 #define DCREG2_EXPO1 0x2000
205 #define DCREG2_EXPO0 0x1000
206 #define DCREG2_HD 0x0800 /* heartbeat disable */
207 #define DCREG2_JD 0x0200 /* jabber timer disable */
208 #define DCREG2_AUTO 0x0100 /* enable AUI/TP auto selection */
209 #define DCREG2_XWRAP 0x0040 /* TP transceiver loopback */
210 #define DCREG2_PH 0x0010 /* HOLD request timing */
211 #define DCREG2_PCM 0x0004 /* packet compress when matched */
212 #define DCREG2_PCNM 0x0002 /* packet compress when not matched */
213 #define DCREG2_RJCM 0x0001 /* inverse packet match via CAM */
214
215 /* Board Control Register: Enable RAM, Interrupts... */
216
217 #define BCMREG 0x80
218 #define BCMREG_RAMEN 0x80 /* switch over to RAM */
219 #define BCMREG_IPEND 0x40 /* interrupt pending ? */
220 #define BCMREG_RESET 0x08 /* reset board */
221 #define BCMREG_16BIT 0x04 /* adapter in 16-bit slot */
222 #define BCMREG_RAMWIN 0x02 /* enable RAM window */
223 #define BCMREG_IEN 0x01 /* interrupt enable */
224
225 /* MAC Address PROM */
226
227 #define MACADDRPROM 0x92
228
229 /* structure of a CAM entry */
230
231 typedef struct {
232 u32 index; /* pointer into CAM area */
233 u32 addr0; /* address part (bits 0..15 used) */
234 u32 addr1;
235 u32 addr2;
236 } camentry_t;
237
238 /* structure of a receive resource */
239
240 typedef struct {
241 u32 startlo; /* start address (bits 0..15 used) */
242 u32 starthi;
243 u32 cntlo; /* size in 16-bit quantities */
244 u32 cnthi;
245 } rra_t;
246
247 /* structure of a receive descriptor */
248
249 typedef struct {
250 u32 status; /* packet status */
251 u32 length; /* length in bytes */
252 u32 startlo; /* start address */
253 u32 starthi;
254 u32 seqno; /* frame sequence */
255 u32 link; /* pointer to next descriptor */
256 /* bit 0 = EOL */
257 u32 inuse; /* !=0 --> free for SONIC to write */
258 } rda_t;
259
260 /* structure of a transmit descriptor */
261
262 typedef struct {
263 u32 status; /* transmit status */
264 u32 config; /* value for TCR */
265 u32 length; /* total length */
266 u32 fragcount; /* number of fragments */
267 u32 startlo; /* start address of fragment */
268 u32 starthi;
269 u32 fraglength; /* length of this fragment */
270 /* more address/length triplets may */
271 /* follow here */
272 u32 link; /* pointer to next descriptor */
273 /* bit 0 = EOL */
274 } tda_t;
275
276 #endif /* _IBM_LANA_DRIVER_ */
277
278 #endif /* _IBM_LANA_INCLUDE_ */
279
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