1 /*
2 * drivers/net/ibm_newemac/emac.h
3 *
4 * Register definitions for PowerPC 4xx on-chip ethernet contoller
5 *
6 * Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
7 * <benh@kernel.crashing.org>
8 *
9 * Based on the arch/ppc version of the driver:
10 *
11 * Copyright (c) 2004, 2005 Zultys Technologies.
12 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
13 *
14 * Based on original work by
15 * Matt Porter <mporter@kernel.crashing.org>
16 * Armin Kuster <akuster@mvista.com>
17 * Copyright 2002-2004 MontaVista Software Inc.
18 *
19 * This program is free software; you can redistribute it and/or modify it
20 * under the terms of the GNU General Public License as published by the
21 * Free Software Foundation; either version 2 of the License, or (at your
22 * option) any later version.
23 *
24 */
25 #ifndef __IBM_NEWEMAC_H
26 #define __IBM_NEWEMAC_H
27
28 #include <linux/types.h>
29
30 /* EMAC registers Write Access rules */
31 struct emac_regs {
32 u32 mr0; /* special */
33 u32 mr1; /* Reset */
34 u32 tmr0; /* special */
35 u32 tmr1; /* special */
36 u32 rmr; /* Reset */
37 u32 isr; /* Always */
38 u32 iser; /* Reset */
39 u32 iahr; /* Reset, R, T */
40 u32 ialr; /* Reset, R, T */
41 u32 vtpid; /* Reset, R, T */
42 u32 vtci; /* Reset, R, T */
43 u32 ptr; /* Reset, T */
44 u32 iaht1; /* Reset, R */
45 u32 iaht2; /* Reset, R */
46 u32 iaht3; /* Reset, R */
47 u32 iaht4; /* Reset, R */
48 u32 gaht1; /* Reset, R */
49 u32 gaht2; /* Reset, R */
50 u32 gaht3; /* Reset, R */
51 u32 gaht4; /* Reset, R */
52 u32 lsah;
53 u32 lsal;
54 u32 ipgvr; /* Reset, T */
55 u32 stacr; /* special */
56 u32 trtr; /* special */
57 u32 rwmr; /* Reset */
58 u32 octx;
59 u32 ocrx;
60 u32 ipcr;
61 };
62
63 /*
64 * PHY mode settings (EMAC <-> ZMII/RGMII bridge <-> PHY)
65 */
66 #define PHY_MODE_NA 0
67 #define PHY_MODE_MII 1
68 #define PHY_MODE_RMII 2
69 #define PHY_MODE_SMII 3
70 #define PHY_MODE_RGMII 4
71 #define PHY_MODE_TBI 5
72 #define PHY_MODE_GMII 6
73 #define PHY_MODE_RTBI 7
74 #define PHY_MODE_SGMII 8
75
76
77 #define EMAC_ETHTOOL_REGS_VER 0
78 #define EMAC_ETHTOOL_REGS_SIZE (sizeof(struct emac_regs) - sizeof(u32))
79 #define EMAC4_ETHTOOL_REGS_VER 1
80 #define EMAC4_ETHTOOL_REGS_SIZE sizeof(struct emac_regs)
81
82 /* EMACx_MR0 */
83 #define EMAC_MR0_RXI 0x80000000
84 #define EMAC_MR0_TXI 0x40000000
85 #define EMAC_MR0_SRST 0x20000000
86 #define EMAC_MR0_TXE 0x10000000
87 #define EMAC_MR0_RXE 0x08000000
88 #define EMAC_MR0_WKE 0x04000000
89
90 /* EMACx_MR1 */
91 #define EMAC_MR1_FDE 0x80000000
92 #define EMAC_MR1_ILE 0x40000000
93 #define EMAC_MR1_VLE 0x20000000
94 #define EMAC_MR1_EIFC 0x10000000
95 #define EMAC_MR1_APP 0x08000000
96 #define EMAC_MR1_IST 0x01000000
97
98 #define EMAC_MR1_MF_MASK 0x00c00000
99 #define EMAC_MR1_MF_10 0x00000000
100 #define EMAC_MR1_MF_100 0x00400000
101 #define EMAC_MR1_MF_1000 0x00800000
102 #define EMAC_MR1_MF_1000GPCS 0x00c00000
103 #define EMAC_MR1_MF_IPPA(id) (((id) & 0x1f) << 6)
104
105 #define EMAC_MR1_RFS_4K 0x00300000
106 #define EMAC_MR1_RFS_16K 0x00000000
107 #define EMAC_MR1_TFS_2K 0x00080000
108 #define EMAC_MR1_TR0_MULT 0x00008000
109 #define EMAC_MR1_JPSM 0x00000000
110 #define EMAC_MR1_MWSW_001 0x00000000
111 #define EMAC_MR1_BASE(opb) (EMAC_MR1_TFS_2K | EMAC_MR1_TR0_MULT)
112
113
114 #define EMAC4_MR1_RFS_2K 0x00100000
115 #define EMAC4_MR1_RFS_4K 0x00180000
116 #define EMAC4_MR1_RFS_16K 0x00280000
117 #define EMAC4_MR1_TFS_2K 0x00020000
118 #define EMAC4_MR1_TFS_4K 0x00030000
119 #define EMAC4_MR1_TR 0x00008000
120 #define EMAC4_MR1_MWSW_001 0x00001000
121 #define EMAC4_MR1_JPSM 0x00000800
122 #define EMAC4_MR1_OBCI_MASK 0x00000038
123 #define EMAC4_MR1_OBCI_50 0x00000000
124 #define EMAC4_MR1_OBCI_66 0x00000008
125 #define EMAC4_MR1_OBCI_83 0x00000010
126 #define EMAC4_MR1_OBCI_100 0x00000018
127 #define EMAC4_MR1_OBCI_100P 0x00000020
128 #define EMAC4_MR1_OBCI(freq) ((freq) <= 50 ? EMAC4_MR1_OBCI_50 : \
129 (freq) <= 66 ? EMAC4_MR1_OBCI_66 : \
130 (freq) <= 83 ? EMAC4_MR1_OBCI_83 : \
131 (freq) <= 100 ? EMAC4_MR1_OBCI_100 : \
132 EMAC4_MR1_OBCI_100P)
133
134 /* EMACx_TMR0 */
135 #define EMAC_TMR0_GNP 0x80000000
136 #define EMAC_TMR0_DEFAULT 0x00000000
137 #define EMAC4_TMR0_TFAE_2_32 0x00000001
138 #define EMAC4_TMR0_TFAE_4_64 0x00000002
139 #define EMAC4_TMR0_TFAE_8_128 0x00000003
140 #define EMAC4_TMR0_TFAE_16_256 0x00000004
141 #define EMAC4_TMR0_TFAE_32_512 0x00000005
142 #define EMAC4_TMR0_TFAE_64_1024 0x00000006
143 #define EMAC4_TMR0_TFAE_128_2048 0x00000007
144 #define EMAC4_TMR0_DEFAULT EMAC4_TMR0_TFAE_2_32
145 #define EMAC_TMR0_XMIT (EMAC_TMR0_GNP | EMAC_TMR0_DEFAULT)
146 #define EMAC4_TMR0_XMIT (EMAC_TMR0_GNP | EMAC4_TMR0_DEFAULT)
147
148 /* EMACx_TMR1 */
149
150 #define EMAC_TMR1(l,h) (((l) << 27) | (((h) & 0xff) << 16))
151 #define EMAC4_TMR1(l,h) (((l) << 27) | (((h) & 0x3ff) << 14))
152
153 /* EMACx_RMR */
154 #define EMAC_RMR_SP 0x80000000
155 #define EMAC_RMR_SFCS 0x40000000
156 #define EMAC_RMR_RRP 0x20000000
157 #define EMAC_RMR_RFP 0x10000000
158 #define EMAC_RMR_ROP 0x08000000
159 #define EMAC_RMR_RPIR 0x04000000
160 #define EMAC_RMR_PPP 0x02000000
161 #define EMAC_RMR_PME 0x01000000
162 #define EMAC_RMR_PMME 0x00800000
163 #define EMAC_RMR_IAE 0x00400000
164 #define EMAC_RMR_MIAE 0x00200000
165 #define EMAC_RMR_BAE 0x00100000
166 #define EMAC_RMR_MAE 0x00080000
167 #define EMAC_RMR_BASE 0x00000000
168 #define EMAC4_RMR_RFAF_2_32 0x00000001
169 #define EMAC4_RMR_RFAF_4_64 0x00000002
170 #define EMAC4_RMR_RFAF_8_128 0x00000003
171 #define EMAC4_RMR_RFAF_16_256 0x00000004
172 #define EMAC4_RMR_RFAF_32_512 0x00000005
173 #define EMAC4_RMR_RFAF_64_1024 0x00000006
174 #define EMAC4_RMR_RFAF_128_2048 0x00000007
175 #define EMAC4_RMR_BASE EMAC4_RMR_RFAF_128_2048
176
177 /* EMACx_ISR & EMACx_ISER */
178 #define EMAC4_ISR_TXPE 0x20000000
179 #define EMAC4_ISR_RXPE 0x10000000
180 #define EMAC4_ISR_TXUE 0x08000000
181 #define EMAC4_ISR_RXOE 0x04000000
182 #define EMAC_ISR_OVR 0x02000000
183 #define EMAC_ISR_PP 0x01000000
184 #define EMAC_ISR_BP 0x00800000
185 #define EMAC_ISR_RP 0x00400000
186 #define EMAC_ISR_SE 0x00200000
187 #define EMAC_ISR_ALE 0x00100000
188 #define EMAC_ISR_BFCS 0x00080000
189 #define EMAC_ISR_PTLE 0x00040000
190 #define EMAC_ISR_ORE 0x00020000
191 #define EMAC_ISR_IRE 0x00010000
192 #define EMAC_ISR_SQE 0x00000080
193 #define EMAC_ISR_TE 0x00000040
194 #define EMAC_ISR_MOS 0x00000002
195 #define EMAC_ISR_MOF 0x00000001
196
197 /* EMACx_STACR */
198 #define EMAC_STACR_PHYD_MASK 0xffff
199 #define EMAC_STACR_PHYD_SHIFT 16
200 #define EMAC_STACR_OC 0x00008000
201 #define EMAC_STACR_PHYE 0x00004000
202 #define EMAC_STACR_STAC_MASK 0x00003000
203 #define EMAC_STACR_STAC_READ 0x00001000
204 #define EMAC_STACR_STAC_WRITE 0x00002000
205 #define EMAC_STACR_OPBC_MASK 0x00000C00
206 #define EMAC_STACR_OPBC_50 0x00000000
207 #define EMAC_STACR_OPBC_66 0x00000400
208 #define EMAC_STACR_OPBC_83 0x00000800
209 #define EMAC_STACR_OPBC_100 0x00000C00
210 #define EMAC_STACR_OPBC(freq) ((freq) <= 50 ? EMAC_STACR_OPBC_50 : \
211 (freq) <= 66 ? EMAC_STACR_OPBC_66 : \
212 (freq) <= 83 ? EMAC_STACR_OPBC_83 : EMAC_STACR_OPBC_100)
213 #define EMAC_STACR_BASE(opb) EMAC_STACR_OPBC(opb)
214 #define EMAC4_STACR_BASE(opb) 0x00000000
215 #define EMAC_STACR_PCDA_MASK 0x1f
216 #define EMAC_STACR_PCDA_SHIFT 5
217 #define EMAC_STACR_PRA_MASK 0x1f
218 #define EMACX_STACR_STAC_MASK 0x00003800
219 #define EMACX_STACR_STAC_READ 0x00001000
220 #define EMACX_STACR_STAC_WRITE 0x00000800
221 #define EMACX_STACR_STAC_IND_ADDR 0x00002000
222 #define EMACX_STACR_STAC_IND_READ 0x00003800
223 #define EMACX_STACR_STAC_IND_READINC 0x00003000
224 #define EMACX_STACR_STAC_IND_WRITE 0x00002800
225
226
227 /* EMACx_TRTR */
228 #define EMAC_TRTR_SHIFT_EMAC4 27
229 #define EMAC_TRTR_SHIFT 24
230
231 /* EMAC specific TX descriptor control fields (write access) */
232 #define EMAC_TX_CTRL_GFCS 0x0200
233 #define EMAC_TX_CTRL_GP 0x0100
234 #define EMAC_TX_CTRL_ISA 0x0080
235 #define EMAC_TX_CTRL_RSA 0x0040
236 #define EMAC_TX_CTRL_IVT 0x0020
237 #define EMAC_TX_CTRL_RVT 0x0010
238 #define EMAC_TX_CTRL_TAH_CSUM 0x000e
239
240 /* EMAC specific TX descriptor status fields (read access) */
241 #define EMAC_TX_ST_BFCS 0x0200
242 #define EMAC_TX_ST_LCS 0x0080
243 #define EMAC_TX_ST_ED 0x0040
244 #define EMAC_TX_ST_EC 0x0020
245 #define EMAC_TX_ST_LC 0x0010
246 #define EMAC_TX_ST_MC 0x0008
247 #define EMAC_TX_ST_SC 0x0004
248 #define EMAC_TX_ST_UR 0x0002
249 #define EMAC_TX_ST_SQE 0x0001
250 #define EMAC_IS_BAD_TX (EMAC_TX_ST_LCS | EMAC_TX_ST_ED | \
251 EMAC_TX_ST_EC | EMAC_TX_ST_LC | \
252 EMAC_TX_ST_MC | EMAC_TX_ST_UR)
253 #define EMAC_IS_BAD_TX_TAH (EMAC_TX_ST_LCS | EMAC_TX_ST_ED | \
254 EMAC_TX_ST_EC | EMAC_TX_ST_LC)
255
256 /* EMAC specific RX descriptor status fields (read access) */
257 #define EMAC_RX_ST_OE 0x0200
258 #define EMAC_RX_ST_PP 0x0100
259 #define EMAC_RX_ST_BP 0x0080
260 #define EMAC_RX_ST_RP 0x0040
261 #define EMAC_RX_ST_SE 0x0020
262 #define EMAC_RX_ST_AE 0x0010
263 #define EMAC_RX_ST_BFCS 0x0008
264 #define EMAC_RX_ST_PTL 0x0004
265 #define EMAC_RX_ST_ORE 0x0002
266 #define EMAC_RX_ST_IRE 0x0001
267 #define EMAC_RX_TAH_BAD_CSUM 0x0003
268 #define EMAC_BAD_RX_MASK (EMAC_RX_ST_OE | EMAC_RX_ST_BP | \
269 EMAC_RX_ST_RP | EMAC_RX_ST_SE | \
270 EMAC_RX_ST_AE | EMAC_RX_ST_BFCS | \
271 EMAC_RX_ST_PTL | EMAC_RX_ST_ORE | \
272 EMAC_RX_ST_IRE )
273 #endif /* __IBM_NEWEMAC_H */
274
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