1 /*
2 * ibm_emac.h
3 *
4 *
5 * Armin Kuster akuster@mvista.com
6 * June, 2002
7 *
8 * Copyright 2002 MontaVista Softare Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16 #ifndef _IBM_EMAC_H_
17 #define _IBM_EMAC_H_
18 /* General defines needed for the driver */
19
20 /* Emac */
21 typedef struct emac_regs {
22 u32 em0mr0;
23 u32 em0mr1;
24 u32 em0tmr0;
25 u32 em0tmr1;
26 u32 em0rmr;
27 u32 em0isr;
28 u32 em0iser;
29 u32 em0iahr;
30 u32 em0ialr;
31 u32 em0vtpid;
32 u32 em0vtci;
33 u32 em0ptr;
34 u32 em0iaht1;
35 u32 em0iaht2;
36 u32 em0iaht3;
37 u32 em0iaht4;
38 u32 em0gaht1;
39 u32 em0gaht2;
40 u32 em0gaht3;
41 u32 em0gaht4;
42 u32 em0lsah;
43 u32 em0lsal;
44 u32 em0ipgvr;
45 u32 em0stacr;
46 u32 em0trtr;
47 u32 em0rwmr;
48 } emac_t;
49
50 /* MODE REG 0 */
51 #define EMAC_M0_RXI 0x80000000
52 #define EMAC_M0_TXI 0x40000000
53 #define EMAC_M0_SRST 0x20000000
54 #define EMAC_M0_TXE 0x10000000
55 #define EMAC_M0_RXE 0x08000000
56 #define EMAC_M0_WKE 0x04000000
57
58 /* MODE Reg 1 */
59 #define EMAC_M1_FDE 0x80000000
60 #define EMAC_M1_ILE 0x40000000
61 #define EMAC_M1_VLE 0x20000000
62 #define EMAC_M1_EIFC 0x10000000
63 #define EMAC_M1_APP 0x08000000
64 #define EMAC_M1_AEMI 0x02000000
65 #define EMAC_M1_IST 0x01000000
66 #define EMAC_M1_MF_1000GPCS 0x00c00000 /* Internal GPCS */
67 #define EMAC_M1_MF_1000MBPS 0x00800000 /* External GPCS */
68 #define EMAC_M1_MF_100MBPS 0x00400000
69 #define EMAC_M1_RFS_16K 0x00280000 /* 000 for 512 byte */
70 #define EMAC_M1_TR 0x00008000
71 #ifdef CONFIG_IBM_EMAC4
72 #define EMAC_M1_RFS_8K 0x00200000
73 #define EMAC_M1_RFS_4K 0x00180000
74 #define EMAC_M1_RFS_2K 0x00100000
75 #define EMAC_M1_RFS_1K 0x00080000
76 #define EMAC_M1_TX_FIFO_16K 0x00050000 /* 0's for 512 byte */
77 #define EMAC_M1_TX_FIFO_8K 0x00040000
78 #define EMAC_M1_TX_FIFO_4K 0x00030000
79 #define EMAC_M1_TX_FIFO_2K 0x00020000
80 #define EMAC_M1_TX_FIFO_1K 0x00010000
81 #define EMAC_M1_TX_TR 0x00008000
82 #define EMAC_M1_TX_MWSW 0x00001000 /* 0 wait for status */
83 #define EMAC_M1_JUMBO_ENABLE 0x00000800 /* Upt to 9Kr status */
84 #define EMAC_M1_OPB_CLK_66 0x00000008 /* 66Mhz */
85 #define EMAC_M1_OPB_CLK_83 0x00000010 /* 83Mhz */
86 #define EMAC_M1_OPB_CLK_100 0x00000018 /* 100Mhz */
87 #define EMAC_M1_OPB_CLK_100P 0x00000020 /* 100Mhz+ */
88 #else /* CONFIG_IBM_EMAC4 */
89 #define EMAC_M1_RFS_4K 0x00300000 /* ~4k for 512 byte */
90 #define EMAC_M1_RFS_2K 0x00200000
91 #define EMAC_M1_RFS_1K 0x00100000
92 #define EMAC_M1_TX_FIFO_2K 0x00080000 /* 0's for 512 byte */
93 #define EMAC_M1_TX_FIFO_1K 0x00040000
94 #define EMAC_M1_TR0_DEPEND 0x00010000 /* 0'x for single packet */
95 #define EMAC_M1_TR1_DEPEND 0x00004000
96 #define EMAC_M1_TR1_MULTI 0x00002000
97 #define EMAC_M1_JUMBO_ENABLE 0x00001000
98 #endif /* CONFIG_IBM_EMAC4 */
99 #define EMAC_M1_BASE (EMAC_M1_TX_FIFO_2K | \
100 EMAC_M1_APP | \
101 EMAC_M1_TR | EMAC_M1_VLE)
102
103 /* Transmit Mode Register 0 */
104 #define EMAC_TMR0_GNP0 0x80000000
105 #define EMAC_TMR0_GNP1 0x40000000
106 #define EMAC_TMR0_GNPD 0x20000000
107 #define EMAC_TMR0_FC 0x10000000
108 #define EMAC_TMR0_TFAE_2_32 0x00000001
109 #define EMAC_TMR0_TFAE_4_64 0x00000002
110 #define EMAC_TMR0_TFAE_8_128 0x00000003
111 #define EMAC_TMR0_TFAE_16_256 0x00000004
112 #define EMAC_TMR0_TFAE_32_512 0x00000005
113 #define EMAC_TMR0_TFAE_64_1024 0x00000006
114 #define EMAC_TMR0_TFAE_128_2048 0x00000007
115
116 /* Receive Mode Register */
117 #define EMAC_RMR_SP 0x80000000
118 #define EMAC_RMR_SFCS 0x40000000
119 #define EMAC_RMR_ARRP 0x20000000
120 #define EMAC_RMR_ARP 0x10000000
121 #define EMAC_RMR_AROP 0x08000000
122 #define EMAC_RMR_ARPI 0x04000000
123 #define EMAC_RMR_PPP 0x02000000
124 #define EMAC_RMR_PME 0x01000000
125 #define EMAC_RMR_PMME 0x00800000
126 #define EMAC_RMR_IAE 0x00400000
127 #define EMAC_RMR_MIAE 0x00200000
128 #define EMAC_RMR_BAE 0x00100000
129 #define EMAC_RMR_MAE 0x00080000
130 #define EMAC_RMR_RFAF_2_32 0x00000001
131 #define EMAC_RMR_RFAF_4_64 0x00000002
132 #define EMAC_RMR_RFAF_8_128 0x00000003
133 #define EMAC_RMR_RFAF_16_256 0x00000004
134 #define EMAC_RMR_RFAF_32_512 0x00000005
135 #define EMAC_RMR_RFAF_64_1024 0x00000006
136 #define EMAC_RMR_RFAF_128_2048 0x00000007
137 #define EMAC_RMR_BASE (EMAC_RMR_IAE | EMAC_RMR_BAE)
138
139 /* Interrupt Status & enable Regs */
140 #define EMAC_ISR_OVR 0x02000000
141 #define EMAC_ISR_PP 0x01000000
142 #define EMAC_ISR_BP 0x00800000
143 #define EMAC_ISR_RP 0x00400000
144 #define EMAC_ISR_SE 0x00200000
145 #define EMAC_ISR_ALE 0x00100000
146 #define EMAC_ISR_BFCS 0x00080000
147 #define EMAC_ISR_PTLE 0x00040000
148 #define EMAC_ISR_ORE 0x00020000
149 #define EMAC_ISR_IRE 0x00010000
150 #define EMAC_ISR_DBDM 0x00000200
151 #define EMAC_ISR_DB0 0x00000100
152 #define EMAC_ISR_SE0 0x00000080
153 #define EMAC_ISR_TE0 0x00000040
154 #define EMAC_ISR_DB1 0x00000020
155 #define EMAC_ISR_SE1 0x00000010
156 #define EMAC_ISR_TE1 0x00000008
157 #define EMAC_ISR_MOS 0x00000002
158 #define EMAC_ISR_MOF 0x00000001
159
160 /* STA CONTROL REG */
161 #define EMAC_STACR_OC 0x00008000
162 #define EMAC_STACR_PHYE 0x00004000
163 #define EMAC_STACR_WRITE 0x00002000
164 #define EMAC_STACR_READ 0x00001000
165 #define EMAC_STACR_CLK_83MHZ 0x00000800 /* 0's for 50Mhz */
166 #define EMAC_STACR_CLK_66MHZ 0x00000400
167 #define EMAC_STACR_CLK_100MHZ 0x00000C00
168
169 /* Transmit Request Threshold Register */
170 #define EMAC_TRTR_1600 0x18000000 /* 0's for 64 Bytes */
171 #define EMAC_TRTR_1024 0x0f000000
172 #define EMAC_TRTR_512 0x07000000
173 #define EMAC_TRTR_256 0x03000000
174 #define EMAC_TRTR_192 0x10000000
175 #define EMAC_TRTR_128 0x01000000
176
177 #define EMAC_TX_CTRL_GFCS 0x0200
178 #define EMAC_TX_CTRL_GP 0x0100
179 #define EMAC_TX_CTRL_ISA 0x0080
180 #define EMAC_TX_CTRL_RSA 0x0040
181 #define EMAC_TX_CTRL_IVT 0x0020
182 #define EMAC_TX_CTRL_RVT 0x0010
183 #define EMAC_TX_CTRL_TAH_CSUM 0x000e /* TAH only */
184 #define EMAC_TX_CTRL_TAH_SEG4 0x000a /* TAH only */
185 #define EMAC_TX_CTRL_TAH_SEG3 0x0008 /* TAH only */
186 #define EMAC_TX_CTRL_TAH_SEG2 0x0006 /* TAH only */
187 #define EMAC_TX_CTRL_TAH_SEG1 0x0004 /* TAH only */
188 #define EMAC_TX_CTRL_TAH_SEG0 0x0002 /* TAH only */
189 #define EMAC_TX_CTRL_TAH_DIS 0x0000 /* TAH only */
190
191 #define EMAC_TX_CTRL_DFLT ( \
192 MAL_TX_CTRL_INTR | EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP )
193
194 /* madmal transmit status / Control bits */
195 #define EMAC_TX_ST_BFCS 0x0200
196 #define EMAC_TX_ST_BPP 0x0100
197 #define EMAC_TX_ST_LCS 0x0080
198 #define EMAC_TX_ST_ED 0x0040
199 #define EMAC_TX_ST_EC 0x0020
200 #define EMAC_TX_ST_LC 0x0010
201 #define EMAC_TX_ST_MC 0x0008
202 #define EMAC_TX_ST_SC 0x0004
203 #define EMAC_TX_ST_UR 0x0002
204 #define EMAC_TX_ST_SQE 0x0001
205
206 /* madmal receive status / Control bits */
207 #define EMAC_RX_ST_OE 0x0200
208 #define EMAC_RX_ST_PP 0x0100
209 #define EMAC_RX_ST_BP 0x0080
210 #define EMAC_RX_ST_RP 0x0040
211 #define EMAC_RX_ST_SE 0x0020
212 #define EMAC_RX_ST_AE 0x0010
213 #define EMAC_RX_ST_BFCS 0x0008
214 #define EMAC_RX_ST_PTL 0x0004
215 #define EMAC_RX_ST_ORE 0x0002
216 #define EMAC_RX_ST_IRE 0x0001
217 #define EMAC_BAD_RX_PACKET 0x02ff
218 #define EMAC_CSUM_VER_ERROR 0x0003
219
220 /* identify a bad rx packet dependent on emac features */
221 #ifdef CONFIG_IBM_EMAC4
222 #define EMAC_IS_BAD_RX_PACKET(desc) \
223 (((desc & (EMAC_BAD_RX_PACKET & ~EMAC_CSUM_VER_ERROR)) || \
224 ((desc & EMAC_CSUM_VER_ERROR) == EMAC_RX_ST_ORE) || \
225 ((desc & EMAC_CSUM_VER_ERROR) == EMAC_RX_ST_IRE)))
226 #else
227 #define EMAC_IS_BAD_RX_PACKET(desc) \
228 (desc & EMAC_BAD_RX_PACKET)
229 #endif
230
231 /* SoC implementation specific EMAC register defaults */
232 #if defined(CONFIG_440GP)
233 #define EMAC_RWMR_DEFAULT 0x80009000
234 #define EMAC_TMR0_DEFAULT 0x00000000
235 #define EMAC_TMR1_DEFAULT 0xf8640000
236 #elif defined(CONFIG_440GX)
237 #define EMAC_RWMR_DEFAULT 0x1000a200
238 #define EMAC_TMR0_DEFAULT EMAC_TMR0_TFAE_2_32
239 #define EMAC_TMR1_DEFAULT 0xa00f0000
240 #else
241 #define EMAC_RWMR_DEFAULT 0x0f002000
242 #define EMAC_TMR0_DEFAULT 0x00000000
243 #define EMAC_TMR1_DEFAULT 0x380f0000
244 #endif /* CONFIG_440GP */
245
246 /* Revision specific EMAC register defaults */
247 #ifdef CONFIG_IBM_EMAC4
248 #define EMAC_M1_DEFAULT (EMAC_M1_BASE | \
249 EMAC_M1_OPB_CLK_83 | \
250 EMAC_M1_TX_MWSW)
251 #define EMAC_RMR_DEFAULT (EMAC_RMR_BASE | \
252 EMAC_RMR_RFAF_128_2048)
253 #define EMAC_TMR0_XMIT (EMAC_TMR0_GNP0 | \
254 EMAC_TMR0_DEFAULT)
255 #define EMAC_TRTR_DEFAULT EMAC_TRTR_1024
256 #else /* !CONFIG_IBM_EMAC4 */
257 #define EMAC_M1_DEFAULT EMAC_M1_BASE
258 #define EMAC_RMR_DEFAULT EMAC_RMR_BASE
259 #define EMAC_TMR0_XMIT EMAC_TMR0_GNP0
260 #define EMAC_TRTR_DEFAULT EMAC_TRTR_1600
261 #endif /* CONFIG_IBM_EMAC4 */
262
263 #endif
264
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