1
2 /* 8530 Serial Communications Controller Register definitions */
3 #define FLAG 0x7e
4
5 /* Write Register 0 */
6 #define R0 0 /* Register selects */
7 #define R1 1
8 #define R2 2
9 #define R3 3
10 #define R4 4
11 #define R5 5
12 #define R6 6
13 #define R7 7
14 #define R8 8
15 #define R9 9
16 #define R10 10
17 #define R11 11
18 #define R12 12
19 #define R13 13
20 #define R14 14
21 #define R15 15
22
23 #define NULLCODE 0 /* Null Code */
24 #define POINT_HIGH 0x8 /* Select upper half of registers */
25 #define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */
26 #define SEND_ABORT 0x18 /* HDLC Abort */
27 #define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */
28 #define RES_Tx_P 0x28 /* Reset TxINT Pending */
29 #define ERR_RES 0x30 /* Error Reset */
30 #define RES_H_IUS 0x38 /* Reset highest IUS */
31
32 #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
33 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
34 #define RES_EOM_L 0xC0 /* Reset EOM latch */
35
36 /* Write Register 1 */
37
38 #define EXT_INT_ENAB 0x1 /* Ext Int Enable */
39 #define TxINT_ENAB 0x2 /* Tx Int Enable */
40 #define PAR_SPEC 0x4 /* Parity is special condition */
41
42 #define RxINT_DISAB 0 /* Rx Int Disable */
43 #define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
44 #define INT_ALL_Rx 0x10 /* Int on all Rx Characters or error */
45 #define INT_ERR_Rx 0x18 /* Int on error only */
46
47 #define WT_RDY_RT 0x20 /* Wait/Ready on R/T */
48 #define WT_FN_RDYFN 0x40 /* Wait/FN/Ready FN */
49 #define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
50
51 /* Write Register #2 (Interrupt Vector) */
52
53 /* Write Register 3 */
54
55 #define RxENABLE 0x1 /* Rx Enable */
56 #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
57 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
58 #define RxCRC_ENAB 0x8 /* Rx CRC Enable */
59 #define ENT_HM 0x10 /* Enter Hunt Mode */
60 #define AUTO_ENAB 0x20 /* Auto Enables */
61 #define Rx5 0x0 /* Rx 5 Bits/Character */
62 #define Rx7 0x40 /* Rx 7 Bits/Character */
63 #define Rx6 0x80 /* Rx 6 Bits/Character */
64 #define Rx8 0xc0 /* Rx 8 Bits/Character */
65
66 /* Write Register 4 */
67
68 #define PAR_ENA 0x1 /* Parity Enable */
69 #define PAR_EVEN 0x2 /* Parity Even/Odd* */
70
71 #define SYNC_ENAB 0 /* Sync Modes Enable */
72 #define SB1 0x4 /* 1 stop bit/char */
73 #define SB15 0x8 /* 1.5 stop bits/char */
74 #define SB2 0xc /* 2 stop bits/char */
75
76 #define MONSYNC 0 /* 8 Bit Sync character */
77 #define BISYNC 0x10 /* 16 bit sync character */
78 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
79 #define EXTSYNC 0x30 /* External Sync Mode */
80
81 #define X1CLK 0x0 /* x1 clock mode */
82 #define X16CLK 0x40 /* x16 clock mode */
83 #define X32CLK 0x80 /* x32 clock mode */
84 #define X64CLK 0xC0 /* x64 clock mode */
85
86 /* Write Register 5 */
87
88 #define TxCRC_ENAB 0x1 /* Tx CRC Enable */
89 #define RTS 0x2 /* RTS */
90 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
91 #define TxENAB 0x8 /* Tx Enable */
92 #define SND_BRK 0x10 /* Send Break */
93 #define Tx5 0x0 /* Tx 5 bits (or less)/character */
94 #define Tx7 0x20 /* Tx 7 bits/character */
95 #define Tx6 0x40 /* Tx 6 bits/character */
96 #define Tx8 0x60 /* Tx 8 bits/character */
97 #define DTR 0x80 /* DTR */
98
99 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
100
101 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
102
103 /* Write Register 8 (transmit buffer) */
104
105 /* Write Register 9 (Master interrupt control) */
106 #define VIS 1 /* Vector Includes Status */
107 #define NV 2 /* No Vector */
108 #define DLC 4 /* Disable Lower Chain */
109 #define MIE 8 /* Master Interrupt Enable */
110 #define STATHI 0x10 /* Status high */
111 #define NORESET 0 /* No reset on write to R9 */
112 #define CHRB 0x40 /* Reset channel B */
113 #define CHRA 0x80 /* Reset channel A */
114 #define FHWRES 0xc0 /* Force hardware reset */
115
116 /* Write Register 10 (misc control bits) */
117 #define BIT6 1 /* 6 bit/8bit sync */
118 #define LOOPMODE 2 /* SDLC Loop mode */
119 #define ABUNDER 4 /* Abort/flag on SDLC xmit underrun */
120 #define MARKIDLE 8 /* Mark/flag on idle */
121 #define GAOP 0x10 /* Go active on poll */
122 #define NRZ 0 /* NRZ mode */
123 #define NRZI 0x20 /* NRZI mode */
124 #define FM1 0x40 /* FM1 (transition = 1) */
125 #define FM0 0x60 /* FM0 (transition = 0) */
126 #define CRCPS 0x80 /* CRC Preset I/O */
127
128 /* Write Register 11 (Clock Mode control) */
129 #define TRxCXT 0 /* TRxC = Xtal output */
130 #define TRxCTC 1 /* TRxC = Transmit clock */
131 #define TRxCBR 2 /* TRxC = BR Generator Output */
132 #define TRxCDP 3 /* TRxC = DPLL output */
133 #define TRxCOI 4 /* TRxC O/I */
134 #define TCRTxCP 0 /* Transmit clock = RTxC pin */
135 #define TCTRxCP 8 /* Transmit clock = TRxC pin */
136 #define TCBR 0x10 /* Transmit clock = BR Generator output */
137 #define TCDPLL 0x18 /* Transmit clock = DPLL output */
138 #define RCRTxCP 0 /* Receive clock = RTxC pin */
139 #define RCTRxCP 0x20 /* Receive clock = TRxC pin */
140 #define RCBR 0x40 /* Receive clock = BR Generator output */
141 #define RCDPLL 0x60 /* Receive clock = DPLL output */
142 #define RTxCX 0x80 /* RTxC Xtal/No Xtal */
143
144 /* Write Register 12 (lower byte of baud rate generator time constant) */
145
146 /* Write Register 13 (upper byte of baud rate generator time constant) */
147
148 /* Write Register 14 (Misc control bits) */
149 #define BRENABL 1 /* Baud rate generator enable */
150 #define BRSRC 2 /* Baud rate generator source */
151 #define DTRREQ 4 /* DTR/Request function */
152 #define AUTOECHO 8 /* Auto Echo */
153 #define LOOPBAK 0x10 /* Local loopback */
154 #define SEARCH 0x20 /* Enter search mode */
155 #define RMC 0x40 /* Reset missing clock */
156 #define DISDPLL 0x60 /* Disable DPLL */
157 #define SSBR 0x80 /* Set DPLL source = BR generator */
158 #define SSRTxC 0xa0 /* Set DPLL source = RTxC */
159 #define SFMM 0xc0 /* Set FM mode */
160 #define SNRZI 0xe0 /* Set NRZI mode */
161
162 /* Write Register 15 (external/status interrupt control) */
163 #define ZCIE 2 /* Zero count IE */
164 #define DCDIE 8 /* DCD IE */
165 #define SYNCIE 0x10 /* Sync/hunt IE */
166 #define CTSIE 0x20 /* CTS IE */
167 #define TxUIE 0x40 /* Tx Underrun/EOM IE */
168 #define BRKIE 0x80 /* Break/Abort IE */
169
170
171 /* Read Register 0 */
172 #define Rx_CH_AV 0x1 /* Rx Character Available */
173 #define ZCOUNT 0x2 /* Zero count */
174 #define Tx_BUF_EMP 0x4 /* Tx Buffer empty */
175 #define DCD 0x8 /* DCD */
176 #define SYNC_HUNT 0x10 /* Sync/hunt */
177 #define CTS 0x20 /* CTS */
178 #define TxEOM 0x40 /* Tx underrun */
179 #define BRK_ABRT 0x80 /* Break/Abort */
180
181 /* Read Register 1 */
182 #define ALL_SNT 0x1 /* All sent */
183 /* Residue Data for 8 Rx bits/char programmed */
184 #define RES3 0x8 /* 0/3 */
185 #define RES4 0x4 /* 0/4 */
186 #define RES5 0xc /* 0/5 */
187 #define RES6 0x2 /* 0/6 */
188 #define RES7 0xa /* 0/7 */
189 #define RES8 0x6 /* 0/8 */
190 #define RES18 0xe /* 1/8 */
191 #define RES28 0x0 /* 2/8 */
192 /* Special Rx Condition Interrupts */
193 #define PAR_ERR 0x10 /* Parity error */
194 #define Rx_OVR 0x20 /* Rx Overrun Error */
195 #define CRC_ERR 0x40 /* CRC/Framing Error */
196 #define END_FR 0x80 /* End of Frame (SDLC) */
197
198 /* Read Register 2 (channel b only) - Interrupt vector */
199
200 /* Read Register 3 (interrupt pending register) ch a only */
201 #define CHBEXT 0x1 /* Channel B Ext/Stat IP */
202 #define CHBTxIP 0x2 /* Channel B Tx IP */
203 #define CHBRxIP 0x4 /* Channel B Rx IP */
204 #define CHAEXT 0x8 /* Channel A Ext/Stat IP */
205 #define CHATxIP 0x10 /* Channel A Tx IP */
206 #define CHARxIP 0x20 /* Channel A Rx IP */
207
208 /* Read Register 8 (receive data register) */
209
210 /* Read Register 10 (misc status bits) */
211 #define ONLOOP 2 /* On loop */
212 #define LOOPSEND 0x10 /* Loop sending */
213 #define CLK2MIS 0x40 /* Two clocks missing */
214 #define CLK1MIS 0x80 /* One clock missing */
215
216 /* Read Register 12 (lower byte of baud rate generator constant) */
217
218 /* Read Register 13 (upper byte of baud rate generator constant) */
219
220 /* Read Register 15 (value of WR 15) */
221
222 /* Z85C30/Z85230 Enhanced SCC register definitions */
223
224 /* Write Register 7' (SDLC/HDLC Programmable Enhancements) */
225 #define AUTOTXF 0x01 /* Auto Tx Flag */
226 #define AUTOEOM 0x02 /* Auto EOM Latch Reset */
227 #define AUTORTS 0x04 /* Auto RTS */
228 #define TXDNRZI 0x08 /* TxD Pulled High in SDLC NRZI mode */
229 #define RXFIFOH 0x08 /* Z85230: Int on RX FIFO half full */
230 #define FASTDTR 0x10 /* Fast DTR/REQ Mode */
231 #define CRCCBCR 0x20 /* CRC Check Bytes Completely Received */
232 #define TXFIFOE 0x20 /* Z85230: Int on TX FIFO completely empty */
233 #define EXTRDEN 0x40 /* Extended Read Enabled */
234
235 /* Write Register 15 (external/status interrupt control) */
236 #define SHDLCE 1 /* SDLC/HDLC Enhancements Enable */
237 #define FIFOE 4 /* FIFO Enable */
238
239 /* Read Register 6 (frame status FIFO) */
240 #define BCLSB 0xff /* LSB of 14 bits count */
241
242 /* Read Register 7 (frame status FIFO) */
243 #define BCMSB 0x3f /* MSB of 14 bits count */
244 #define FDA 0x40 /* FIFO Data Available Status */
245 #define FOS 0x80 /* FIFO Overflow Status */
246
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