1 /*
2 * $Id: dmascc.c,v 1.27 2000/06/01 14:46:23 oe1kib Exp $
3 *
4 * Driver for high-speed SCC boards (those with DMA support)
5 * Copyright (C) 1997-2000 Klaus Kudielka
6 *
7 * S5SCC/DMA support by Janko Koleznik S52HI
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
25
26 #include <linux/module.h>
27 #include <linux/delay.h>
28 #include <linux/errno.h>
29 #include <linux/if_arp.h>
30 #include <linux/in.h>
31 #include <linux/init.h>
32 #include <linux/interrupt.h>
33 #include <linux/ioport.h>
34 #include <linux/kernel.h>
35 #include <linux/mm.h>
36 #include <linux/netdevice.h>
37 #include <linux/rtnetlink.h>
38 #include <linux/sockios.h>
39 #include <linux/workqueue.h>
40 #include <asm/atomic.h>
41 #include <asm/bitops.h>
42 #include <asm/dma.h>
43 #include <asm/io.h>
44 #include <asm/irq.h>
45 #include <asm/uaccess.h>
46 #include <net/ax25.h>
47 #include "z8530.h"
48
49
50 /* Number of buffers per channel */
51
52 #define NUM_TX_BUF 2 /* NUM_TX_BUF >= 1 (min. 2 recommended) */
53 #define NUM_RX_BUF 6 /* NUM_RX_BUF >= 1 (min. 2 recommended) */
54 #define BUF_SIZE 1576 /* BUF_SIZE >= mtu + hard_header_len */
55
56
57 /* Cards supported */
58
59 #define HW_PI { "Ottawa PI", 0x300, 0x20, 0x10, 8, \
60 0, 8, 1843200, 3686400 }
61 #define HW_PI2 { "Ottawa PI2", 0x300, 0x20, 0x10, 8, \
62 0, 8, 3686400, 7372800 }
63 #define HW_TWIN { "Gracilis PackeTwin", 0x200, 0x10, 0x10, 32, \
64 0, 4, 6144000, 6144000 }
65 #define HW_S5 { "S5SCC/DMA", 0x200, 0x10, 0x10, 32, \
66 0, 8, 4915200, 9830400 }
67
68 #define HARDWARE { HW_PI, HW_PI2, HW_TWIN, HW_S5 }
69
70 #define TMR_0_HZ 25600 /* Frequency of timer 0 */
71
72 #define TYPE_PI 0
73 #define TYPE_PI2 1
74 #define TYPE_TWIN 2
75 #define TYPE_S5 3
76 #define NUM_TYPES 4
77
78 #define MAX_NUM_DEVS 32
79
80
81 /* SCC chips supported */
82
83 #define Z8530 0
84 #define Z85C30 1
85 #define Z85230 2
86
87 #define CHIPNAMES { "Z8530", "Z85C30", "Z85230" }
88
89
90 /* I/O registers */
91
92 /* 8530 registers relative to card base */
93 #define SCCB_CMD 0x00
94 #define SCCB_DATA 0x01
95 #define SCCA_CMD 0x02
96 #define SCCA_DATA 0x03
97
98 /* 8253/8254 registers relative to card base */
99 #define TMR_CNT0 0x00
100 #define TMR_CNT1 0x01
101 #define TMR_CNT2 0x02
102 #define TMR_CTRL 0x03
103
104 /* Additional PI/PI2 registers relative to card base */
105 #define PI_DREQ_MASK 0x04
106
107 /* Additional PackeTwin registers relative to card base */
108 #define TWIN_INT_REG 0x08
109 #define TWIN_CLR_TMR1 0x09
110 #define TWIN_CLR_TMR2 0x0a
111 #define TWIN_SPARE_1 0x0b
112 #define TWIN_DMA_CFG 0x08
113 #define TWIN_SERIAL_CFG 0x09
114 #define TWIN_DMA_CLR_FF 0x0a
115 #define TWIN_SPARE_2 0x0b
116
117
118 /* PackeTwin I/O register values */
119
120 /* INT_REG */
121 #define TWIN_SCC_MSK 0x01
122 #define TWIN_TMR1_MSK 0x02
123 #define TWIN_TMR2_MSK 0x04
124 #define TWIN_INT_MSK 0x07
125
126 /* SERIAL_CFG */
127 #define TWIN_DTRA_ON 0x01
128 #define TWIN_DTRB_ON 0x02
129 #define TWIN_EXTCLKA 0x04
130 #define TWIN_EXTCLKB 0x08
131 #define TWIN_LOOPA_ON 0x10
132 #define TWIN_LOOPB_ON 0x20
133 #define TWIN_EI 0x80
134
135 /* DMA_CFG */
136 #define TWIN_DMA_HDX_T1 0x08
137 #define TWIN_DMA_HDX_R1 0x0a
138 #define TWIN_DMA_HDX_T3 0x14
139 #define TWIN_DMA_HDX_R3 0x16
140 #define TWIN_DMA_FDX_T3R1 0x1b
141 #define TWIN_DMA_FDX_T1R3 0x1d
142
143
144 /* Status values */
145
146 #define IDLE 0
147 #define TX_HEAD 1
148 #define TX_DATA 2
149 #define TX_PAUSE 3
150 #define TX_TAIL 4
151 #define RTS_OFF 5
152 #define WAIT 6
153 #define DCD_ON 7
154 #define RX_ON 8
155 #define DCD_OFF 9
156
157
158 /* Ioctls */
159
160 #define SIOCGSCCPARAM SIOCDEVPRIVATE
161 #define SIOCSSCCPARAM (SIOCDEVPRIVATE+1)
162
163
164 /* Data types */
165
166 struct scc_param {
167 int pclk_hz; /* frequency of BRG input (don't change) */
168 int brg_tc; /* BRG terminal count; BRG disabled if < 0 */
169 int nrzi; /* 0 (nrz), 1 (nrzi) */
170 int clocks; /* see dmascc_cfg documentation */
171 int txdelay; /* [1/TMR_0_HZ] */
172 int txtimeout; /* [1/HZ] */
173 int txtail; /* [1/TMR_0_HZ] */
174 int waittime; /* [1/TMR_0_HZ] */
175 int slottime; /* [1/TMR_0_HZ] */
176 int persist; /* 1 ... 256 */
177 int dma; /* -1 (disable), 0, 1, 3 */
178 int txpause; /* [1/TMR_0_HZ] */
179 int rtsoff; /* [1/TMR_0_HZ] */
180 int dcdon; /* [1/TMR_0_HZ] */
181 int dcdoff; /* [1/TMR_0_HZ] */
182 };
183
184 struct scc_hardware {
185 char *name;
186 int io_region;
187 int io_delta;
188 int io_size;
189 int num_devs;
190 int scc_offset;
191 int tmr_offset;
192 int tmr_hz;
193 int pclk_hz;
194 };
195
196 struct scc_priv {
197 int type;
198 int chip;
199 struct net_device *dev;
200 struct scc_info *info;
201 struct net_device_stats stats;
202 int channel;
203 int card_base, scc_cmd, scc_data;
204 int tmr_cnt, tmr_ctrl, tmr_mode;
205 struct scc_param param;
206 char rx_buf[NUM_RX_BUF][BUF_SIZE];
207 int rx_len[NUM_RX_BUF];
208 int rx_ptr;
209 struct work_struct rx_work;
210 int rx_head, rx_tail, rx_count;
211 int rx_over;
212 char tx_buf[NUM_TX_BUF][BUF_SIZE];
213 int tx_len[NUM_TX_BUF];
214 int tx_ptr;
215 int tx_head, tx_tail, tx_count;
216 int state;
217 unsigned long tx_start;
218 int rr0;
219 spinlock_t *register_lock; /* Per scc_info */
220 spinlock_t ring_lock;
221 };
222
223 struct scc_info {
224 int irq_used;
225 int twin_serial_cfg;
226 struct net_device *dev[2];
227 struct scc_priv priv[2];
228 struct scc_info *next;
229 spinlock_t register_lock; /* Per device register lock */
230 };
231
232
233 /* Function declarations */
234 static int setup_adapter(int card_base, int type, int n) __init;
235
236 static void write_scc(struct scc_priv *priv, int reg, int val);
237 static void write_scc_data(struct scc_priv *priv, int val, int fast);
238 static int read_scc(struct scc_priv *priv, int reg);
239 static int read_scc_data(struct scc_priv *priv);
240
241 static int scc_open(struct net_device *dev);
242 static int scc_close(struct net_device *dev);
243 static int scc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
244 static int scc_send_packet(struct sk_buff *skb, struct net_device *dev);
245 static struct net_device_stats *scc_get_stats(struct net_device *dev);
246 static int scc_set_mac_address(struct net_device *dev, void *sa);
247
248 static inline void tx_on(struct scc_priv *priv);
249 static inline void rx_on(struct scc_priv *priv);
250 static inline void rx_off(struct scc_priv *priv);
251 static void start_timer(struct scc_priv *priv, int t, int r15);
252 static inline unsigned char random(void);
253
254 static inline void z8530_isr(struct scc_info *info);
255 static irqreturn_t scc_isr(int irq, void *dev_id, struct pt_regs * regs);
256 static void rx_isr(struct scc_priv *priv);
257 static void special_condition(struct scc_priv *priv, int rc);
258 static void rx_bh(void *arg);
259 static void tx_isr(struct scc_priv *priv);
260 static void es_isr(struct scc_priv *priv);
261 static void tm_isr(struct scc_priv *priv);
262
263
264 /* Initialization variables */
265
266 static int io[MAX_NUM_DEVS] __initdata = { 0, };
267 /* Beware! hw[] is also used in cleanup_module(). */
268 static struct scc_hardware hw[NUM_TYPES] __initdata_or_module = HARDWARE;
269 static char ax25_broadcast[7] __initdata =
270 { 'Q'<<1, 'S'<<1, 'T'<<1, ' '<<1, ' '<<1, ' '<<1, ''<<1 };
271 static char ax25_test[7] __initdata =
272 { 'L'<<1, 'I'<<1, 'N'<<1, 'U'<<1, 'X'<<1, ' '<<1, '1'<<1 };
273
274
275 /* Global variables */
276
277 static struct scc_info *first;
278 static unsigned long rand;
279
280
281 MODULE_AUTHOR("Klaus Kudielka");
282 MODULE_DESCRIPTION("Driver for high-speed SCC boards");
283 MODULE_PARM(io, "1-" __MODULE_STRING(MAX_NUM_DEVS) "i");
284 MODULE_LICENSE("GPL");
285
286 static void __exit dmascc_exit(void) {
287 int i;
288 struct scc_info *info;
289
290 while (first) {
291 info = first;
292
293 /* Unregister devices */
294 for (i = 0; i < 2; i++)
295 unregister_netdev(info->dev[i]);
296
297 /* Reset board */
298 if (info->priv[0].type == TYPE_TWIN)
299 outb(0, info->dev[0]->base_addr + TWIN_SERIAL_CFG);
300 write_scc(&info->priv[0], R9, FHWRES);
301 release_region(info->dev[0]->base_addr,
302 hw[info->priv[0].type].io_size);
303
304 for (i = 0; i < 2; i++)
305 free_netdev(info->dev[i]);
306
307 /* Free memory */
308 first = info->next;
309 kfree(info);
310 }
311 }
312
313 #ifndef MODULE
314 void __init dmascc_setup(char *str, int *ints) {
315 int i;
316
317 for (i = 0; i < MAX_NUM_DEVS && i < ints[0]; i++)
318 io[i] = ints[i+1];
319 }
320 #endif
321
322 static int __init dmascc_init(void) {
323 int h, i, j, n;
324 int base[MAX_NUM_DEVS], tcmd[MAX_NUM_DEVS], t0[MAX_NUM_DEVS],
325 t1[MAX_NUM_DEVS];
326 unsigned t_val;
327 unsigned long time, start[MAX_NUM_DEVS], delay[MAX_NUM_DEVS],
328 counting[MAX_NUM_DEVS];
329
330 /* Initialize random number generator */
331 rand = jiffies;
332 /* Cards found = 0 */
333 n = 0;
334 /* Warning message */
335 if (!io[0]) printk(KERN_INFO "dmascc: autoprobing (dangerous)\n");
336
337 /* Run autodetection for each card type */
338 for (h = 0; h < NUM_TYPES; h++) {
339
340 if (io[0]) {
341 /* User-specified I/O address regions */
342 for (i = 0; i < hw[h].num_devs; i++) base[i] = 0;
343 for (i = 0; i < MAX_NUM_DEVS && io[i]; i++) {
344 j = (io[i] - hw[h].io_region) / hw[h].io_delta;
345 if (j >= 0 &&
346 j < hw[h].num_devs &&
347 hw[h].io_region + j * hw[h].io_delta == io[i]) {
348 base[j] = io[i];
349 }
350 }
351 } else {
352 /* Default I/O address regions */
353 for (i = 0; i < hw[h].num_devs; i++) {
354 base[i] = hw[h].io_region + i * hw[h].io_delta;
355 }
356 }
357
358 /* Check valid I/O address regions */
359 for (i = 0; i < hw[h].num_devs; i++)
360 if (base[i]) {
361 if (!request_region(base[i], hw[h].io_size, "dmascc"))
362 base[i] = 0;
363 else {
364 tcmd[i] = base[i] + hw[h].tmr_offset + TMR_CTRL;
365 t0[i] = base[i] + hw[h].tmr_offset + TMR_CNT0;
366 t1[i] = base[i] + hw[h].tmr_offset + TMR_CNT1;
367 }
368 }
369
370 /* Start timers */
371 for (i = 0; i < hw[h].num_devs; i++)
372 if (base[i]) {
373 /* Timer 0: LSB+MSB, Mode 3, TMR_0_HZ */
374 outb(0x36, tcmd[i]);
375 outb((hw[h].tmr_hz/TMR_0_HZ) & 0xFF, t0[i]);
376 outb((hw[h].tmr_hz/TMR_0_HZ) >> 8, t0[i]);
377 /* Timer 1: LSB+MSB, Mode 0, HZ/10 */
378 outb(0x70, tcmd[i]);
379 outb((TMR_0_HZ/HZ*10) & 0xFF, t1[i]);
380 outb((TMR_0_HZ/HZ*10) >> 8, t1[i]);
381 start[i] = jiffies;
382 delay[i] = 0;
383 counting[i] = 1;
384 /* Timer 2: LSB+MSB, Mode 0 */
385 outb(0xb0, tcmd[i]);
386 }
387 time = jiffies;
388 /* Wait until counter registers are loaded */
389 udelay(2000000/TMR_0_HZ);
390
391 /* Timing loop */
392 while (jiffies - time < 13) {
393 for (i = 0; i < hw[h].num_devs; i++)
394 if (base[i] && counting[i]) {
395 /* Read back Timer 1: latch; read LSB; read MSB */
396 outb(0x40, tcmd[i]);
397 t_val = inb(t1[i]) + (inb(t1[i]) << 8);
398 /* Also check whether counter did wrap */
399 if (t_val == 0 || t_val > TMR_0_HZ/HZ*10) counting[i] = 0;
400 delay[i] = jiffies - start[i];
401 }
402 }
403
404 /* Evaluate measurements */
405 for (i = 0; i < hw[h].num_devs; i++)
406 if (base[i]) {
407 if ((delay[i] >= 9 && delay[i] <= 11)&&
408 /* Ok, we have found an adapter */
409 (setup_adapter(base[i], h, n) == 0))
410 n++;
411 else
412 release_region(base[i], hw[h].io_size);
413 }
414
415 } /* NUM_TYPES */
416
417 /* If any adapter was successfully initialized, return ok */
418 if (n) return 0;
419
420 /* If no adapter found, return error */
421 printk(KERN_INFO "dmascc: no adapters found\n");
422 return -EIO;
423 }
424
425 module_init(dmascc_init);
426 module_exit(dmascc_exit);
427
428 static void dev_setup(struct net_device *dev)
429 {
430 dev->type = ARPHRD_AX25;
431 dev->hard_header_len = 73;
432 dev->mtu = 1500;
433 dev->addr_len = 7;
434 dev->tx_queue_len = 64;
435 memcpy(dev->broadcast, ax25_broadcast, 7);
436 memcpy(dev->dev_addr, ax25_test, 7);
437 }
438
439 static int __init setup_adapter(int card_base, int type, int n)
440 {
441 int i, irq, chip;
442 struct scc_info *info;
443 struct net_device *dev;
444 struct scc_priv *priv;
445 unsigned long time;
446 unsigned int irqs;
447 int tmr_base = card_base + hw[type].tmr_offset;
448 int scc_base = card_base + hw[type].scc_offset;
449 char *chipnames[] = CHIPNAMES;
450
451 /* Allocate memory */
452 info = kmalloc(sizeof(struct scc_info), GFP_KERNEL | GFP_DMA);
453 if (!info) {
454 printk(KERN_ERR "dmascc: "
455 "could not allocate memory for %s at %#3x\n",
456 hw[type].name, card_base);
457 goto out;
458 }
459
460 /* Initialize what is necessary for write_scc and write_scc_data */
461 memset(info, 0, sizeof(struct scc_info));
462
463 info->dev[0] = alloc_netdev(0, "", dev_setup);
464 if (!info->dev[0]) {
465 printk(KERN_ERR "dmascc: "
466 "could not allocate memory for %s at %#3x\n",
467 hw[type].name, card_base);
468 goto out1;
469 }
470
471 info->dev[1] = alloc_netdev(0, "", dev_setup);
472 if (!info->dev[1]) {
473 printk(KERN_ERR "dmascc: "
474 "could not allocate memory for %s at %#3x\n",
475 hw[type].name, card_base);
476 goto out2;
477 }
478 spin_lock_init(&info->register_lock);
479
480 priv = &info->priv[0];
481 priv->type = type;
482 priv->card_base = card_base;
483 priv->scc_cmd = scc_base + SCCA_CMD;
484 priv->scc_data = scc_base + SCCA_DATA;
485 priv->register_lock = &info->register_lock;
486
487 /* Reset SCC */
488 write_scc(priv, R9, FHWRES | MIE | NV);
489
490 /* Determine type of chip by enabling SDLC/HDLC enhancements */
491 write_scc(priv, R15, SHDLCE);
492 if (!read_scc(priv, R15)) {
493 /* WR7' not present. This is an ordinary Z8530 SCC. */
494 chip = Z8530;
495 } else {
496 /* Put one character in TX FIFO */
497 write_scc_data(priv, 0, 0);
498 if (read_scc(priv, R0) & Tx_BUF_EMP) {
499 /* TX FIFO not full. This is a Z85230 ESCC with a 4-byte FIFO. */
500 chip = Z85230;
501 } else {
502 /* TX FIFO full. This is a Z85C30 SCC with a 1-byte FIFO. */
503 chip = Z85C30;
504 }
505 }
506 write_scc(priv, R15, 0);
507
508 /* Start IRQ auto-detection */
509 irqs = probe_irq_on();
510
511 /* Enable interrupts */
512 if (type == TYPE_TWIN) {
513 outb(0, card_base + TWIN_DMA_CFG);
514 inb(card_base + TWIN_CLR_TMR1);
515 inb(card_base + TWIN_CLR_TMR2);
516 info->twin_serial_cfg = TWIN_EI;
517 outb(info->twin_serial_cfg, card_base + TWIN_SERIAL_CFG);
518 } else {
519 write_scc(priv, R15, CTSIE);
520 write_scc(priv, R0, RES_EXT_INT);
521 write_scc(priv, R1, EXT_INT_ENAB);
522 }
523
524 /* Start timer */
525 outb(1, tmr_base + TMR_CNT1);
526 outb(0, tmr_base + TMR_CNT1);
527
528 /* Wait and detect IRQ */
529 time = jiffies; while (jiffies - time < 2 + HZ / TMR_0_HZ);
530 irq = probe_irq_off(irqs);
531
532 /* Clear pending interrupt, disable interrupts */
533 if (type == TYPE_TWIN) {
534 inb(card_base + TWIN_CLR_TMR1);
535 } else {
536 write_scc(priv, R1, 0);
537 write_scc(priv, R15, 0);
538 write_scc(priv, R0, RES_EXT_INT);
539 }
540
541 if (irq <= 0) {
542 printk(KERN_ERR "dmascc: could not find irq of %s at %#3x (irq=%d)\n",
543 hw[type].name, card_base, irq);
544 goto out3;
545 }
546
547 /* Set up data structures */
548 for (i = 0; i < 2; i++) {
549 dev = info->dev[i];
550 priv = &info->priv[i];
551 priv->type = type;
552 priv->chip = chip;
553 priv->dev = dev;
554 priv->info = info;
555 priv->channel = i;
556 spin_lock_init(&priv->ring_lock);
557 priv->register_lock = &info->register_lock;
558 priv->card_base = card_base;
559 priv->scc_cmd = scc_base + (i ? SCCB_CMD : SCCA_CMD);
560 priv->scc_data = scc_base + (i ? SCCB_DATA : SCCA_DATA);
561 priv->tmr_cnt = tmr_base + (i ? TMR_CNT2 : TMR_CNT1);
562 priv->tmr_ctrl = tmr_base + TMR_CTRL;
563 priv->tmr_mode = i ? 0xb0 : 0x70;
564 priv->param.pclk_hz = hw[type].pclk_hz;
565 priv->param.brg_tc = -1;
566 priv->param.clocks = TCTRxCP | RCRTxCP;
567 priv->param.persist = 256;
568 priv->param.dma = -1;
569 INIT_WORK(&priv->rx_work, rx_bh, priv);
570 dev->priv = priv;
571 sprintf(dev->name, "dmascc%i", 2*n+i);
572 SET_MODULE_OWNER(dev);
573 dev->base_addr = card_base;
574 dev->irq = irq;
575 dev->open = scc_open;
576 dev->stop = scc_close;
577 dev->do_ioctl = scc_ioctl;
578 dev->hard_start_xmit = scc_send_packet;
579 dev->get_stats = scc_get_stats;
580 dev->hard_header = ax25_encapsulate;
581 dev->rebuild_header = ax25_rebuild_header;
582 dev->set_mac_address = scc_set_mac_address;
583 }
584 if (register_netdev(info->dev[0])) {
585 printk(KERN_ERR "dmascc: could not register %s\n",
586 info->dev[0]->name);
587 goto out3;
588 }
589 if (register_netdev(info->dev[1])) {
590 printk(KERN_ERR "dmascc: could not register %s\n",
591 info->dev[1]->name);
592 goto out4;
593 }
594
595
596 info->next = first;
597 first = info;
598 printk(KERN_INFO "dmascc: found %s (%s) at %#3x, irq %d\n", hw[type].name,
599 chipnames[chip], card_base, irq);
600 return 0;
601
602 out4:
603 unregister_netdev(info->dev[0]);
604 out3:
605 if (info->priv[0].type == TYPE_TWIN)
606 outb(0, info->dev[0]->base_addr + TWIN_SERIAL_CFG);
607 write_scc(&info->priv[0], R9, FHWRES);
608 free_netdev(info->dev[1]);
609 out2:
610 free_netdev(info->dev[0]);
611 out1:
612 kfree(info);
613 out:
614 return -1;
615 }
616
617
618 /* Driver functions */
619
620 static void write_scc(struct scc_priv *priv, int reg, int val) {
621 unsigned long flags;
622 switch (priv->type) {
623 case TYPE_S5:
624 if (reg) outb(reg, priv->scc_cmd);
625 outb(val, priv->scc_cmd);
626 return;
627 case TYPE_TWIN:
628 if (reg) outb_p(reg, priv->scc_cmd);
629 outb_p(val, priv->scc_cmd);
630 return;
631 default:
632 spin_lock_irqsave(priv->register_lock, flags);
633 outb_p(0, priv->card_base + PI_DREQ_MASK);
634 if (reg) outb_p(reg, priv->scc_cmd);
635 outb_p(val, priv->scc_cmd);
636 outb(1, priv->card_base + PI_DREQ_MASK);
637 spin_unlock_irqrestore(priv->register_lock, flags);
638 return;
639 }
640 }
641
642
643 static void write_scc_data(struct scc_priv *priv, int val, int fast) {
644 unsigned long flags;
645 switch (priv->type) {
646 case TYPE_S5:
647 outb(val, priv->scc_data);
648 return;
649 case TYPE_TWIN:
650 outb_p(val, priv->scc_data);
651 return;
652 default:
653 if (fast) outb_p(val, priv->scc_data);
654 else {
655 spin_lock_irqsave(priv->register_lock, flags);
656 outb_p(0, priv->card_base + PI_DREQ_MASK);
657 outb_p(val, priv->scc_data);
658 outb(1, priv->card_base + PI_DREQ_MASK);
659 spin_unlock_irqrestore(priv->register_lock, flags);
660 }
661 return;
662 }
663 }
664
665
666 static int read_scc(struct scc_priv *priv, int reg) {
667 int rc;
668 unsigned long flags;
669 switch (priv->type) {
670 case TYPE_S5:
671 if (reg) outb(reg, priv->scc_cmd);
672 return inb(priv->scc_cmd);
673 case TYPE_TWIN:
674 if (reg) outb_p(reg, priv->scc_cmd);
675 return inb_p(priv->scc_cmd);
676 default:
677 spin_lock_irqsave(priv->register_lock, flags);
678 outb_p(0, priv->card_base + PI_DREQ_MASK);
679 if (reg) outb_p(reg, priv->scc_cmd);
680 rc = inb_p(priv->scc_cmd);
681 outb(1, priv->card_base + PI_DREQ_MASK);
682 spin_unlock_irqrestore(priv->register_lock, flags);
683 return rc;
684 }
685 }
686
687
688 static int read_scc_data(struct scc_priv *priv) {
689 int rc;
690 unsigned long flags;
691 switch (priv->type) {
692 case TYPE_S5:
693 return inb(priv->scc_data);
694 case TYPE_TWIN:
695 return inb_p(priv->scc_data);
696 default:
697 spin_lock_irqsave(priv->register_lock, flags);
698 outb_p(0, priv->card_base + PI_DREQ_MASK);
699 rc = inb_p(priv->scc_data);
700 outb(1, priv->card_base + PI_DREQ_MASK);
701 spin_unlock_irqrestore(priv->register_lock, flags);
702 return rc;
703 }
704 }
705
706
707 static int scc_open(struct net_device *dev) {
708 struct scc_priv *priv = dev->priv;
709 struct scc_info *info = priv->info;
710 int card_base = priv->card_base;
711
712 /* Request IRQ if not already used by other channel */
713 if (!info->irq_used) {
714 if (request_irq(dev->irq, scc_isr, 0, "dmascc", info)) {
715 return -EAGAIN;
716 }
717 }
718 info->irq_used++;
719
720 /* Request DMA if required */
721 if (priv->param.dma >= 0) {
722 if (request_dma(priv->param.dma, "dmascc")) {
723 if (--info->irq_used == 0) free_irq(dev->irq, info);
724 return -EAGAIN;
725 } else {
726 unsigned long flags = claim_dma_lock();
727 clear_dma_ff(priv->param.dma);
728 release_dma_lock(flags);
729 }
730 }
731
732 /* Initialize local variables */
733 priv->rx_ptr = 0;
734 priv->rx_over = 0;
735 priv->rx_head = priv->rx_tail = priv->rx_count = 0;
736 priv->state = IDLE;
737 priv->tx_head = priv->tx_tail = priv->tx_count = 0;
738 priv->tx_ptr = 0;
739
740 /* Reset channel */
741 write_scc(priv, R9, (priv->channel ? CHRB : CHRA) | MIE | NV);
742 /* X1 clock, SDLC mode */
743 write_scc(priv, R4, SDLC | X1CLK);
744 /* DMA */
745 write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN);
746 /* 8 bit RX char, RX disable */
747 write_scc(priv, R3, Rx8);
748 /* 8 bit TX char, TX disable */
749 write_scc(priv, R5, Tx8);
750 /* SDLC address field */
751 write_scc(priv, R6, 0);
752 /* SDLC flag */
753 write_scc(priv, R7, FLAG);
754 switch (priv->chip) {
755 case Z85C30:
756 /* Select WR7' */
757 write_scc(priv, R15, SHDLCE);
758 /* Auto EOM reset */
759 write_scc(priv, R7, AUTOEOM);
760 write_scc(priv, R15, 0);
761 break;
762 case Z85230:
763 /* Select WR7' */
764 write_scc(priv, R15, SHDLCE);
765 /* The following bits are set (see 2.5.2.1):
766 - Automatic EOM reset
767 - Interrupt request if RX FIFO is half full
768 This bit should be ignored in DMA mode (according to the
769 documentation), but actually isn't. The receiver doesn't work if
770 it is set. Thus, we have to clear it in DMA mode.
771 - Interrupt/DMA request if TX FIFO is completely empty
772 a) If set, the ESCC behaves as if it had no TX FIFO (Z85C30
773 compatibility).
774 b) If cleared, DMA requests may follow each other very quickly,
775 filling up the TX FIFO.
776 Advantage: TX works even in case of high bus latency.
777 Disadvantage: Edge-triggered DMA request circuitry may miss
778 a request. No more data is delivered, resulting
779 in a TX FIFO underrun.
780 Both PI2 and S5SCC/DMA seem to work fine with TXFIFOE cleared.
781 The PackeTwin doesn't. I don't know about the PI, but let's
782 assume it behaves like the PI2.
783 */
784 if (priv->param.dma >= 0) {
785 if (priv->type == TYPE_TWIN) write_scc(priv, R7, AUTOEOM | TXFIFOE);
786 else write_scc(priv, R7, AUTOEOM);
787 } else {
788 write_scc(priv, R7, AUTOEOM | RXFIFOH);
789 }
790 write_scc(priv, R15, 0);
791 break;
792 }
793 /* Preset CRC, NRZ(I) encoding */
794 write_scc(priv, R10, CRCPS | (priv->param.nrzi ? NRZI : NRZ));
795
796 /* Configure baud rate generator */
797 if (priv->param.brg_tc >= 0) {
798 /* Program BR generator */
799 write_scc(priv, R12, priv->param.brg_tc & 0xFF);
800 write_scc(priv, R13, (priv->param.brg_tc>>8) & 0xFF);
801 /* BRG source = SYS CLK; enable BRG; DTR REQ function (required by
802 PackeTwin, not connected on the PI2); set DPLL source to BRG */
803 write_scc(priv, R14, SSBR | DTRREQ | BRSRC | BRENABL);
804 /* Enable DPLL */
805 write_scc(priv, R14, SEARCH | DTRREQ | BRSRC | BRENABL);
806 } else {
807 /* Disable BR generator */
808 write_scc(priv, R14, DTRREQ | BRSRC);
809 }
810
811 /* Configure clocks */
812 if (priv->type == TYPE_TWIN) {
813 /* Disable external TX clock receiver */
814 outb((info->twin_serial_cfg &=
815 ~(priv->channel ? TWIN_EXTCLKB : TWIN_EXTCLKA)),
816 card_base + TWIN_SERIAL_CFG);
817 }
818 write_scc(priv, R11, priv->param.clocks);
819 if ((priv->type == TYPE_TWIN) && !(priv->param.clocks & TRxCOI)) {
820 /* Enable external TX clock receiver */
821 outb((info->twin_serial_cfg |=
822 (priv->channel ? TWIN_EXTCLKB : TWIN_EXTCLKA)),
823 card_base + TWIN_SERIAL_CFG);
824 }
825
826 /* Configure PackeTwin */
827 if (priv->type == TYPE_TWIN) {
828 /* Assert DTR, enable interrupts */
829 outb((info->twin_serial_cfg |= TWIN_EI |
830 (priv->channel ? TWIN_DTRB_ON : TWIN_DTRA_ON)),
831 card_base + TWIN_SERIAL_CFG);
832 }
833
834 /* Read current status */
835 priv->rr0 = read_scc(priv, R0);
836 /* Enable DCD interrupt */
837 write_scc(priv, R15, DCDIE);
838
839 netif_start_queue(dev);
840
841 return 0;
842 }
843
844
845 static int scc_close(struct net_device *dev) {
846 struct scc_priv *priv = dev->priv;
847 struct scc_info *info = priv->info;
848 int card_base = priv->card_base;
849
850 netif_stop_queue(dev);
851
852 if (priv->type == TYPE_TWIN) {
853 /* Drop DTR */
854 outb((info->twin_serial_cfg &=
855 (priv->channel ? ~TWIN_DTRB_ON : ~TWIN_DTRA_ON)),
856 card_base + TWIN_SERIAL_CFG);
857 }
858
859 /* Reset channel, free DMA and IRQ */
860 write_scc(priv, R9, (priv->channel ? CHRB : CHRA) | MIE | NV);
861 if (priv->param.dma >= 0) {
862 if (priv->type == TYPE_TWIN) outb(0, card_base + TWIN_DMA_CFG);
863 free_dma(priv->param.dma);
864 }
865 if (--info->irq_used == 0) free_irq(dev->irq, info);
866
867 return 0;
868 }
869
870
871 static int scc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) {
872 struct scc_priv *priv = dev->priv;
873
874 switch (cmd) {
875 case SIOCGSCCPARAM:
876 if (copy_to_user(ifr->ifr_data, &priv->param, sizeof(struct scc_param)))
877 return -EFAULT;
878 return 0;
879 case SIOCSSCCPARAM:
880 if (!capable(CAP_NET_ADMIN)) return -EPERM;
881 if (netif_running(dev)) return -EAGAIN;
882 if (copy_from_user(&priv->param, ifr->ifr_data, sizeof(struct scc_param)))
883 return -EFAULT;
884 return 0;
885 default:
886 return -EINVAL;
887 }
888 }
889
890
891 static int scc_send_packet(struct sk_buff *skb, struct net_device *dev) {
892 struct scc_priv *priv = dev->priv;
893 unsigned long flags;
894 int i;
895
896 /* Temporarily stop the scheduler feeding us packets */
897 netif_stop_queue(dev);
898
899 /* Transfer data to DMA buffer */
900 i = priv->tx_head;
901 memcpy(priv->tx_buf[i], skb->data+1, skb->len-1);
902 priv->tx_len[i] = skb->len-1;
903
904 /* Clear interrupts while we touch our circular buffers */
905
906 spin_lock_irqsave(&priv->ring_lock, flags);
907 /* Move the ring buffer's head */
908 priv->tx_head = (i + 1) % NUM_TX_BUF;
909 priv->tx_count++;
910
911 /* If we just filled up the last buffer, leave queue stopped.
912 The higher layers must wait until we have a DMA buffer
913 to accept the data. */
914 if (priv->tx_count < NUM_TX_BUF) netif_wake_queue(dev);
915
916 /* Set new TX state */
917 if (priv->state == IDLE) {
918 /* Assert RTS, start timer */
919 priv->state = TX_HEAD;
920 priv->tx_start = jiffies;
921 write_scc(priv, R5, TxCRC_ENAB | RTS | TxENAB | Tx8);
922 write_scc(priv, R15, 0);
923 start_timer(priv, priv->param.txdelay, 0);
924 }
925
926 /* Turn interrupts back on and free buffer */
927 spin_unlock_irqrestore(&priv->ring_lock, flags);
928 dev_kfree_skb(skb);
929
930 return 0;
931 }
932
933
934 static struct net_device_stats *scc_get_stats(struct net_device *dev) {
935 struct scc_priv *priv = dev->priv;
936
937 return &priv->stats;
938 }
939
940
941 static int scc_set_mac_address(struct net_device *dev, void *sa) {
942 memcpy(dev->dev_addr, ((struct sockaddr *)sa)->sa_data, dev->addr_len);
943 return 0;
944 }
945
946
947 static inline void tx_on(struct scc_priv *priv) {
948 int i, n;
949 unsigned long flags;
950
951 if (priv->param.dma >= 0) {
952 n = (priv->chip == Z85230) ? 3 : 1;
953 /* Program DMA controller */
954 flags = claim_dma_lock();
955 set_dma_mode(priv->param.dma, DMA_MODE_WRITE);
956 set_dma_addr(priv->param.dma, (int) priv->tx_buf[priv->tx_tail]+n);
957 set_dma_count(priv->param.dma, priv->tx_len[priv->tx_tail]-n);
958 release_dma_lock(flags);
959 /* Enable TX underrun interrupt */
960 write_scc(priv, R15, TxUIE);
961 /* Configure DREQ */
962 if (priv->type == TYPE_TWIN)
963 outb((priv->param.dma == 1) ? TWIN_DMA_HDX_T1 : TWIN_DMA_HDX_T3,
964 priv->card_base + TWIN_DMA_CFG);
965 else
966 write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN | WT_RDY_ENAB);
967 /* Write first byte(s) */
968 spin_lock_irqsave(priv->register_lock, flags);
969 for (i = 0; i < n; i++)
970 write_scc_data(priv, priv->tx_buf[priv->tx_tail][i], 1);
971 enable_dma(priv->param.dma);
972 spin_unlock_irqrestore(priv->register_lock, flags);
973 } else {
974 write_scc(priv, R15, TxUIE);
975 write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN | TxINT_ENAB);
976 tx_isr(priv);
977 }
978 /* Reset EOM latch if we do not have the AUTOEOM feature */
979 if (priv->chip == Z8530) write_scc(priv, R0, RES_EOM_L);
980 }
981
982
983 static inline void rx_on(struct scc_priv *priv) {
984 unsigned long flags;
985
986 /* Clear RX FIFO */
987 while (read_scc(priv, R0) & Rx_CH_AV) read_scc_data(priv);
988 priv->rx_over = 0;
989 if (priv->param.dma >= 0) {
990 /* Program DMA controller */
991 flags = claim_dma_lock();
992 set_dma_mode(priv->param.dma, DMA_MODE_READ);
993 set_dma_addr(priv->param.dma, (int) priv->rx_buf[priv->rx_head]);
994 set_dma_count(priv->param.dma, BUF_SIZE);
995 release_dma_lock(flags);
996 enable_dma(priv->param.dma);
997 /* Configure PackeTwin DMA */
998 if (priv->type == TYPE_TWIN) {
999 outb((priv->param.dma == 1) ? TWIN_DMA_HDX_R1 : TWIN_DMA_HDX_R3,
1000 priv->card_base + TWIN_DMA_CFG);
1001 }
1002 /* Sp. cond. intr. only, ext int enable, RX DMA enable */
1003 write_scc(priv, R1, EXT_INT_ENAB | INT_ERR_Rx |
1004 WT_RDY_RT | WT_FN_RDYFN | WT_RDY_ENAB);
1005 } else {
1006 /* Reset current frame */
1007 priv->rx_ptr = 0;
1008 /* Intr. on all Rx characters and Sp. cond., ext int enable */
1009 write_scc(priv, R1, EXT_INT_ENAB | INT_ALL_Rx | WT_RDY_RT |
1010 WT_FN_RDYFN);
1011 }
1012 write_scc(priv, R0, ERR_RES);
1013 write_scc(priv, R3, RxENABLE | Rx8 | RxCRC_ENAB);
1014 }
1015
1016
1017 static inline void rx_off(struct scc_priv *priv) {
1018 /* Disable receiver */
1019 write_scc(priv, R3, Rx8);
1020 /* Disable DREQ / RX interrupt */
1021 if (priv->param.dma >= 0 && priv->type == TYPE_TWIN)
1022 outb(0, priv->card_base + TWIN_DMA_CFG);
1023 else
1024 write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN);
1025 /* Disable DMA */
1026 if (priv->param.dma >= 0) disable_dma(priv->param.dma);
1027 }
1028
1029
1030 static void start_timer(struct scc_priv *priv, int t, int r15) {
1031 unsigned long flags;
1032
1033 outb(priv->tmr_mode, priv->tmr_ctrl);
1034 if (t == 0) {
1035 tm_isr(priv);
1036 } else if (t > 0) {
1037 save_flags(flags);
1038 cli();
1039 outb(t & 0xFF, priv->tmr_cnt);
1040 outb((t >> 8) & 0xFF, priv->tmr_cnt);
1041 if (priv->type != TYPE_TWIN) {
1042 write_scc(priv, R15, r15 | CTSIE);
1043 priv->rr0 |= CTS;
1044 }
1045 restore_flags(flags);
1046 }
1047 }
1048
1049
1050 static inline unsigned char random(void) {
1051 /* See "Numerical Recipes in C", second edition, p. 284 */
1052 rand = rand * 1664525L + 1013904223L;
1053 return (unsigned char) (rand >> 24);
1054 }
1055
1056 static inline void z8530_isr(struct scc_info *info) {
1057 int is, i = 100;
1058
1059 while ((is = read_scc(&info->priv[0], R3)) && i--) {
1060 if (is & CHARxIP) {
1061 rx_isr(&info->priv[0]);
1062 } else if (is & CHATxIP) {
1063 tx_isr(&info->priv[0]);
1064 } else if (is & CHAEXT) {
1065 es_isr(&info->priv[0]);
1066 } else if (is & CHBRxIP) {
1067 rx_isr(&info->priv[1]);
1068 } else if (is & CHBTxIP) {
1069 tx_isr(&info->priv[1]);
1070 } else {
1071 es_isr(&info->priv[1]);
1072 }
1073 write_scc(&info->priv[0], R0, RES_H_IUS);
1074 i++;
1075 }
1076 if (i < 0) {
1077 printk(KERN_ERR "dmascc: stuck in ISR with RR3=0x%02x.\n", is);
1078 }
1079 /* Ok, no interrupts pending from this 8530. The INT line should
1080 be inactive now. */
1081 }
1082
1083
1084 static irqreturn_t scc_isr(int irq, void *dev_id, struct pt_regs * regs) {
1085 struct scc_info *info = dev_id;
1086
1087 spin_lock(info->priv[0].register_lock);
1088 /* At this point interrupts are enabled, and the interrupt under service
1089 is already acknowledged, but masked off.
1090
1091 Interrupt processing: We loop until we know that the IRQ line is
1092 low. If another positive edge occurs afterwards during the ISR,
1093 another interrupt will be triggered by the interrupt controller
1094 as soon as the IRQ level is enabled again (see asm/irq.h).
1095
1096 Bottom-half handlers will be processed after scc_isr(). This is
1097 important, since we only have small ringbuffers and want new data
1098 to be fetched/delivered immediately. */
1099
1100 if (info->priv[0].type == TYPE_TWIN) {
1101 int is, card_base = info->priv[0].card_base;
1102 while ((is = ~inb(card_base + TWIN_INT_REG)) &
1103 TWIN_INT_MSK) {
1104 if (is & TWIN_SCC_MSK) {
1105 z8530_isr(info);
1106 } else if (is & TWIN_TMR1_MSK) {
1107 inb(card_base + TWIN_CLR_TMR1);
1108 tm_isr(&info->priv[0]);
1109 } else {
1110 inb(card_base + TWIN_CLR_TMR2);
1111 tm_isr(&info->priv[1]);
1112 }
1113 }
1114 } else z8530_isr(info);
1115 spin_unlock(info->priv[0].register_lock);
1116 return IRQ_HANDLED;
1117 }
1118
1119
1120 static void rx_isr(struct scc_priv *priv) {
1121 if (priv->param.dma >= 0) {
1122 /* Check special condition and perform error reset. See 2.4.7.5. */
1123 special_condition(priv, read_scc(priv, R1));
1124 write_scc(priv, R0, ERR_RES);
1125 } else {
1126 /* Check special condition for each character. Error reset not necessary.
1127 Same algorithm for SCC and ESCC. See 2.4.7.1 and 2.4.7.4. */
1128 int rc;
1129 while (read_scc(priv, R0) & Rx_CH_AV) {
1130 rc = read_scc(priv, R1);
1131 if (priv->rx_ptr < BUF_SIZE)
1132 priv->rx_buf[priv->rx_head][priv->rx_ptr++] =
1133 read_scc_data(priv);
1134 else {
1135 priv->rx_over = 2;
1136 read_scc_data(priv);
1137 }
1138 special_condition(priv, rc);
1139 }
1140 }
1141 }
1142
1143
1144 static void special_condition(struct scc_priv *priv, int rc) {
1145 int cb;
1146 unsigned long flags;
1147
1148 /* See Figure 2-15. Only overrun and EOF need to be checked. */
1149
1150 if (rc & Rx_OVR) {
1151 /* Receiver overrun */
1152 priv->rx_over = 1;
1153 if (priv->param.dma < 0) write_scc(priv, R0, ERR_RES);
1154 } else if (rc & END_FR) {
1155 /* End of frame. Get byte count */
1156 if (priv->param.dma >= 0) {
1157 flags = claim_dma_lock();
1158 cb = BUF_SIZE - get_dma_residue(priv->param.dma) - 2;
1159 release_dma_lock(flags);
1160 } else {
1161 cb = priv->rx_ptr - 2;
1162 }
1163 if (priv->rx_over) {
1164 /* We had an overrun */
1165 priv->stats.rx_errors++;
1166 if (priv->rx_over == 2) priv->stats.rx_length_errors++;
1167 else priv->stats.rx_fifo_errors++;
1168 priv->rx_over = 0;
1169 } else if (rc & CRC_ERR) {
1170 /* Count invalid CRC only if packet length >= minimum */
1171 if (cb >= 15) {
1172 priv->stats.rx_errors++;
1173 priv->stats.rx_crc_errors++;
1174 }
1175 } else {
1176 if (cb >= 15) {
1177 if (priv->rx_count < NUM_RX_BUF - 1) {
1178 /* Put good frame in FIFO */
1179 priv->rx_len[priv->rx_head] = cb;
1180 priv->rx_head = (priv->rx_head + 1) % NUM_RX_BUF;
1181 priv->rx_count++;
1182 schedule_work(&priv->rx_work);
1183 } else {
1184 priv->stats.rx_errors++;
1185 priv->stats.rx_over_errors++;
1186 }
1187 }
1188 }
1189 /* Get ready for new frame */
1190 if (priv->param.dma >= 0) {
1191 flags = claim_dma_lock();
1192 set_dma_addr(priv->param.dma, (int) priv->rx_buf[priv->rx_head]);
1193 set_dma_count(priv->param.dma, BUF_SIZE);
1194 release_dma_lock(flags);
1195 } else {
1196 priv->rx_ptr = 0;
1197 }
1198 }
1199 }
1200
1201
1202 static void rx_bh(void *arg) {
1203 struct scc_priv *priv = arg;
1204 int i = priv->rx_tail;
1205 int cb;
1206 unsigned long flags;
1207 struct sk_buff *skb;
1208 unsigned char *data;
1209
1210 spin_lock_irqsave(&priv->ring_lock, flags);
1211 while (priv->rx_count) {
1212 spin_unlock_irqrestore(&priv->ring_lock, flags);
1213 cb = priv->rx_len[i];
1214 /* Allocate buffer */
1215 skb = dev_alloc_skb(cb+1);
1216 if (skb == NULL) {
1217 /* Drop packet */
1218 priv->stats.rx_dropped++;
1219 } else {
1220 /* Fill buffer */
1221 data = skb_put(skb, cb+1);
1222 data[0] = 0;
1223 memcpy(&data[1], priv->rx_buf[i], cb);
1224 skb->dev = priv->dev;
1225 skb->protocol = ntohs(ETH_P_AX25);
1226 skb->mac.raw = skb->data;
1227 netif_rx(skb);
1228 priv->dev->last_rx = jiffies;
1229 priv->stats.rx_packets++;
1230 priv->stats.rx_bytes += cb;
1231 }
1232 spin_lock_irqsave(&priv->ring_lock, flags);
1233 /* Move tail */
1234 priv->rx_tail = i = (i + 1) % NUM_RX_BUF;
1235 priv->rx_count--;
1236 }
1237 spin_unlock_irqrestore(&priv->ring_lock, flags);
1238 }
1239
1240
1241 static void tx_isr(struct scc_priv *priv) {
1242 int i = priv->tx_tail, p = priv->tx_ptr;
1243
1244 /* Suspend TX interrupts if we don't want to send anything.
1245 See Figure 2-22. */
1246 if (p == priv->tx_len[i]) {
1247 write_scc(priv, R0, RES_Tx_P);
1248 return;
1249 }
1250
1251 /* Write characters */
1252 while ((read_scc(priv, R0) & Tx_BUF_EMP) && p < priv->tx_len[i]) {
1253 write_scc_data(priv, priv->tx_buf[i][p++], 0);
1254 }
1255
1256 /* Reset EOM latch of Z8530 */
1257 if (!priv->tx_ptr && p && priv->chip == Z8530)
1258 write_scc(priv, R0, RES_EOM_L);
1259
1260 priv->tx_ptr = p;
1261 }
1262
1263
1264 static void es_isr(struct scc_priv *priv) {
1265 int i, rr0, drr0, res;
1266 unsigned long flags;
1267
1268 /* Read status, reset interrupt bit (open latches) */
1269 rr0 = read_scc(priv, R0);
1270 write_scc(priv, R0, RES_EXT_INT);
1271 drr0 = priv->rr0 ^ rr0;
1272 priv->rr0 = rr0;
1273
1274 /* Transmit underrun (2.4.9.6). We can't check the TxEOM flag, since
1275 it might have already been cleared again by AUTOEOM. */
1276 if (priv->state == TX_DATA) {
1277 /* Get remaining bytes */
1278 i = priv->tx_tail;
1279 if (priv->param.dma >= 0) {
1280 disable_dma(priv->param.dma);
1281 flags = claim_dma_lock();
1282 res = get_dma_residue(priv->param.dma);
1283 release_dma_lock(flags);
1284 } else {
1285 res = priv->tx_len[i] - priv->tx_ptr;
1286 priv->tx_ptr = 0;
1287 }
1288 /* Disable DREQ / TX interrupt */
1289 if (priv->param.dma >= 0 && priv->type == TYPE_TWIN)
1290 outb(0, priv->card_base + TWIN_DMA_CFG);
1291 else
1292 write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN);
1293 if (res) {
1294 /* Update packet statistics */
1295 priv->stats.tx_errors++;
1296 priv->stats.tx_fifo_errors++;
1297 /* Other underrun interrupts may already be waiting */
1298 write_scc(priv, R0, RES_EXT_INT);
1299 write_scc(priv, R0, RES_EXT_INT);
1300 } else {
1301 /* Update packet statistics */
1302 priv->stats.tx_packets++;
1303 priv->stats.tx_bytes += priv->tx_len[i];
1304 /* Remove frame from FIFO */
1305 priv->tx_tail = (i + 1) % NUM_TX_BUF;
1306 priv->tx_count--;
1307 /* Inform upper layers */
1308 netif_wake_queue(priv->dev);
1309 }
1310 /* Switch state */
1311 write_scc(priv, R15, 0);
1312 if (priv->tx_count &&
1313 (jiffies - priv->tx_start) < priv->param.txtimeout) {
1314 priv->state = TX_PAUSE;
1315 start_timer(priv, priv->param.txpause, 0);
1316 } else {
1317 priv->state = TX_TAIL;
1318 start_timer(priv, priv->param.txtail, 0);
1319 }
1320 }
1321
1322 /* DCD transition */
1323 if (drr0 & DCD) {
1324 if (rr0 & DCD) {
1325 switch (priv->state) {
1326 case IDLE:
1327 case WAIT:
1328 priv->state = DCD_ON;
1329 write_scc(priv, R15, 0);
1330 start_timer(priv, priv->param.dcdon, 0);
1331 }
1332 } else {
1333 switch (priv->state) {
1334 case RX_ON:
1335 rx_off(priv);
1336 priv->state = DCD_OFF;
1337 write_scc(priv, R15, 0);
1338 start_timer(priv, priv->param.dcdoff, 0);
1339 }
1340 }
1341 }
1342
1343 /* CTS transition */
1344 if ((drr0 & CTS) && (~rr0 & CTS) && priv->type != TYPE_TWIN)
1345 tm_isr(priv);
1346
1347 }
1348
1349
1350 static void tm_isr(struct scc_priv *priv) {
1351 switch (priv->state) {
1352 case TX_HEAD:
1353 case TX_PAUSE:
1354 tx_on(priv);
1355 priv->state = TX_DATA;
1356 break;
1357 case TX_TAIL:
1358 write_scc(priv, R5, TxCRC_ENAB | Tx8);
1359 priv->state = RTS_OFF;
1360 if (priv->type != TYPE_TWIN) write_scc(priv, R15, 0);
1361 start_timer(priv, priv->param.rtsoff, 0);
1362 break;
1363 case RTS_OFF:
1364 write_scc(priv, R15, DCDIE);
1365 priv->rr0 = read_scc(priv, R0);
1366 if (priv->rr0 & DCD) {
1367 priv->stats.collisions++;
1368 rx_on(priv);
1369 priv->state = RX_ON;
1370 } else {
1371 priv->state = WAIT;
1372 start_timer(priv, priv->param.waittime, DCDIE);
1373 }
1374 break;
1375 case WAIT:
1376 if (priv->tx_count) {
1377 priv->state = TX_HEAD;
1378 priv->tx_start = jiffies;
1379 write_scc(priv, R5, TxCRC_ENAB | RTS | TxENAB | Tx8);
1380 write_scc(priv, R15, 0);
1381 start_timer(priv, priv->param.txdelay, 0);
1382 } else {
1383 priv->state = IDLE;
1384 if (priv->type != TYPE_TWIN) write_scc(priv, R15, DCDIE);
1385 }
1386 break;
1387 case DCD_ON:
1388 case DCD_OFF:
1389 write_scc(priv, R15, DCDIE);
1390 priv->rr0 = read_scc(priv, R0);
1391 if (priv->rr0 & DCD) {
1392 rx_on(priv);
1393 priv->state = RX_ON;
1394 } else {
1395 priv->state = WAIT;
1396 start_timer(priv,
1397 random()/priv->param.persist*priv->param.slottime,
1398 DCDIE);
1399 }
1400 break;
1401 }
1402 }
1403
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