1 /*
2 * drivers/net/gianfar_phy.h
3 *
4 * Gianfar Ethernet Driver -- PHY handling
5 * Driver for FEC on MPC8540 and TSEC on MPC8540/MPC8560
6 * Based on 8260_io/fcc_enet.c
7 *
8 * Author: Andy Fleming
9 * Maintainer: Kumar Gala (kumar.gala@freescale.com)
10 *
11 * Copyright (c) 2002-2004 Freescale Semiconductor, Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 */
19 #ifndef __GIANFAR_PHY_H
20 #define __GIANFAR_PHY_H
21
22 #define MII_end ((u32)-2)
23 #define MII_read ((u32)-1)
24
25 #define MIIMIND_BUSY 0x00000001
26 #define MIIMIND_NOTVALID 0x00000004
27
28 #define GFAR_AN_TIMEOUT 2000
29
30 /* 1000BT control (Marvell & BCM54xx at least) */
31 #define MII_1000BASETCONTROL 0x09
32 #define MII_1000BASETCONTROL_FULLDUPLEXCAP 0x0200
33 #define MII_1000BASETCONTROL_HALFDUPLEXCAP 0x0100
34
35 /* Cicada Extended Control Register 1 */
36 #define MII_CIS8201_EXT_CON1 0x17
37 #define MII_CIS8201_EXTCON1_INIT 0x0000
38
39 /* Cicada Interrupt Mask Register */
40 #define MII_CIS8201_IMASK 0x19
41 #define MII_CIS8201_IMASK_IEN 0x8000
42 #define MII_CIS8201_IMASK_SPEED 0x4000
43 #define MII_CIS8201_IMASK_LINK 0x2000
44 #define MII_CIS8201_IMASK_DUPLEX 0x1000
45 #define MII_CIS8201_IMASK_MASK 0xf000
46
47 /* Cicada Interrupt Status Register */
48 #define MII_CIS8201_ISTAT 0x1a
49 #define MII_CIS8201_ISTAT_STATUS 0x8000
50 #define MII_CIS8201_ISTAT_SPEED 0x4000
51 #define MII_CIS8201_ISTAT_LINK 0x2000
52 #define MII_CIS8201_ISTAT_DUPLEX 0x1000
53
54 /* Cicada Auxiliary Control/Status Register */
55 #define MII_CIS8201_AUX_CONSTAT 0x1c
56 #define MII_CIS8201_AUXCONSTAT_INIT 0x0004
57 #define MII_CIS8201_AUXCONSTAT_DUPLEX 0x0020
58 #define MII_CIS8201_AUXCONSTAT_SPEED 0x0018
59 #define MII_CIS8201_AUXCONSTAT_GBIT 0x0010
60 #define MII_CIS8201_AUXCONSTAT_100 0x0008
61
62 /* 88E1011 PHY Status Register */
63 #define MII_M1011_PHY_SPEC_STATUS 0x11
64 #define MII_M1011_PHY_SPEC_STATUS_1000 0x8000
65 #define MII_M1011_PHY_SPEC_STATUS_100 0x4000
66 #define MII_M1011_PHY_SPEC_STATUS_SPD_MASK 0xc000
67 #define MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX 0x2000
68 #define MII_M1011_PHY_SPEC_STATUS_RESOLVED 0x0800
69 #define MII_M1011_PHY_SPEC_STATUS_LINK 0x0400
70
71 #define MII_M1011_IEVENT 0x13
72 #define MII_M1011_IEVENT_CLEAR 0x0000
73
74 #define MII_M1011_IMASK 0x12
75 #define MII_M1011_IMASK_INIT 0x6400
76 #define MII_M1011_IMASK_CLEAR 0x0000
77
78 #define MII_DM9161_SCR 0x10
79 #define MII_DM9161_SCR_INIT 0x0610
80
81 /* DM9161 Specified Configuration and Status Register */
82 #define MII_DM9161_SCSR 0x11
83 #define MII_DM9161_SCSR_100F 0x8000
84 #define MII_DM9161_SCSR_100H 0x4000
85 #define MII_DM9161_SCSR_10F 0x2000
86 #define MII_DM9161_SCSR_10H 0x1000
87
88 /* DM9161 Interrupt Register */
89 #define MII_DM9161_INTR 0x15
90 #define MII_DM9161_INTR_PEND 0x8000
91 #define MII_DM9161_INTR_DPLX_MASK 0x0800
92 #define MII_DM9161_INTR_SPD_MASK 0x0400
93 #define MII_DM9161_INTR_LINK_MASK 0x0200
94 #define MII_DM9161_INTR_MASK 0x0100
95 #define MII_DM9161_INTR_DPLX_CHANGE 0x0010
96 #define MII_DM9161_INTR_SPD_CHANGE 0x0008
97 #define MII_DM9161_INTR_LINK_CHANGE 0x0004
98 #define MII_DM9161_INTR_INIT 0x0000
99 #define MII_DM9161_INTR_STOP \
100 (MII_DM9161_INTR_DPLX_MASK | MII_DM9161_INTR_SPD_MASK \
101 | MII_DM9161_INTR_LINK_MASK | MII_DM9161_INTR_MASK)
102
103 /* DM9161 10BT Configuration/Status */
104 #define MII_DM9161_10BTCSR 0x12
105 #define MII_DM9161_10BTCSR_INIT 0x7800
106
107 #define MII_BASIC_FEATURES (SUPPORTED_10baseT_Half | \
108 SUPPORTED_10baseT_Full | \
109 SUPPORTED_100baseT_Half | \
110 SUPPORTED_100baseT_Full | \
111 SUPPORTED_Autoneg | \
112 SUPPORTED_TP | \
113 SUPPORTED_MII)
114
115 #define MII_GBIT_FEATURES (MII_BASIC_FEATURES | \
116 SUPPORTED_1000baseT_Half | \
117 SUPPORTED_1000baseT_Full)
118
119 #define MII_READ_COMMAND 0x00000001
120
121 #define MII_INTERRUPT_DISABLED 0x0
122 #define MII_INTERRUPT_ENABLED 0x1
123 /* Taken from mii_if_info and sungem_phy.h */
124 struct gfar_mii_info {
125 /* Information about the PHY type */
126 /* And management functions */
127 struct phy_info *phyinfo;
128
129 /* forced speed & duplex (no autoneg)
130 * partner speed & duplex & pause (autoneg)
131 */
132 int speed;
133 int duplex;
134 int pause;
135
136 /* The most recently read link state */
137 int link;
138
139 /* Enabled Interrupts */
140 u32 interrupts;
141
142 u32 advertising;
143 int autoneg;
144 int mii_id;
145
146 /* private data pointer */
147 /* For use by PHYs to maintain extra state */
148 void *priv;
149
150 /* Provided by host chip */
151 struct net_device *dev;
152
153 /* A lock to ensure that only one thing can read/write
154 * the MDIO bus at a time */
155 spinlock_t mdio_lock;
156
157 /* Provided by ethernet driver */
158 int (*mdio_read) (struct net_device *dev, int mii_id, int reg);
159 void (*mdio_write) (struct net_device *dev, int mii_id, int reg, int val);
160 };
161
162 /* struct phy_info: a structure which defines attributes for a PHY
163 *
164 * id will contain a number which represents the PHY. During
165 * startup, the driver will poll the PHY to find out what its
166 * UID--as defined by registers 2 and 3--is. The 32-bit result
167 * gotten from the PHY will be ANDed with phy_id_mask to
168 * discard any bits which may change based on revision numbers
169 * unimportant to functionality
170 *
171 * There are 6 commands which take a gfar_mii_info structure.
172 * Each PHY must declare config_aneg, and read_status.
173 */
174 struct phy_info {
175 u32 phy_id;
176 char *name;
177 unsigned int phy_id_mask;
178 u32 features;
179
180 /* Called to initialize the PHY */
181 int (*init)(struct gfar_mii_info *mii_info);
182
183 /* Called to suspend the PHY for power */
184 int (*suspend)(struct gfar_mii_info *mii_info);
185
186 /* Reconfigures autonegotiation (or disables it) */
187 int (*config_aneg)(struct gfar_mii_info *mii_info);
188
189 /* Determines the negotiated speed and duplex */
190 int (*read_status)(struct gfar_mii_info *mii_info);
191
192 /* Clears any pending interrupts */
193 int (*ack_interrupt)(struct gfar_mii_info *mii_info);
194
195 /* Enables or disables interrupts */
196 int (*config_intr)(struct gfar_mii_info *mii_info);
197
198 /* Clears up any memory if needed */
199 void (*close)(struct gfar_mii_info *mii_info);
200 };
201
202 struct phy_info *get_phy_info(struct gfar_mii_info *mii_info);
203 int read_phy_reg(struct net_device *dev, int mii_id, int regnum);
204 void write_phy_reg(struct net_device *dev, int mii_id, int regnum, int value);
205 void mii_clear_phy_interrupt(struct gfar_mii_info *mii_info);
206 void mii_configure_phy_interrupt(struct gfar_mii_info *mii_info, u32 interrupts);
207
208 struct dm9161_private {
209 struct timer_list timer;
210 int resetdone;
211 };
212
213 #endif /* GIANFAR_PHY_H */
214
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