1 /*
2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
3 *
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey.
7 *
8 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
9 * trademarks of NVIDIA Corporation in the United States and other
10 * countries.
11 *
12 * Copyright (C) 2003,4,5 Manfred Spraul
13 * Copyright (C) 2004 Andrew de Quincey (wol support)
14 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
15 * IRQ rate fixes, bigendian fixes, cleanups, verification)
16 * Copyright (c) 2004,2005,2006,2007,2008 NVIDIA Corporation
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 *
32 * Changelog:
33 * 0.01: 05 Oct 2003: First release that compiles without warnings.
34 * 0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
35 * Check all PCI BARs for the register window.
36 * udelay added to mii_rw.
37 * 0.03: 06 Oct 2003: Initialize dev->irq.
38 * 0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
39 * 0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
40 * 0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
41 * irq mask updated
42 * 0.07: 14 Oct 2003: Further irq mask updates.
43 * 0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
44 * added into irq handler, NULL check for drain_ring.
45 * 0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
46 * requested interrupt sources.
47 * 0.10: 20 Oct 2003: First cleanup for release.
48 * 0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
49 * MAC Address init fix, set_multicast cleanup.
50 * 0.12: 23 Oct 2003: Cleanups for release.
51 * 0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
52 * Set link speed correctly. start rx before starting
53 * tx (nv_start_rx sets the link speed).
54 * 0.14: 25 Oct 2003: Nic dependant irq mask.
55 * 0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
56 * open.
57 * 0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
58 * increased to 1628 bytes.
59 * 0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
60 * the tx length.
61 * 0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
62 * 0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
63 * addresses, really stop rx if already running
64 * in nv_start_rx, clean up a bit.
65 * 0.20: 07 Dec 2003: alloc fixes
66 * 0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
67 * 0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
68 * on close.
69 * 0.23: 26 Jan 2004: various small cleanups
70 * 0.24: 27 Feb 2004: make driver even less anonymous in backtraces
71 * 0.25: 09 Mar 2004: wol support
72 * 0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
73 * 0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
74 * added CK804/MCP04 device IDs, code fixes
75 * for registers, link status and other minor fixes.
76 * 0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
77 * 0.29: 31 Aug 2004: Add backup timer for link change notification.
78 * 0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
79 * into nv_close, otherwise reenabling for wol can
80 * cause DMA to kfree'd memory.
81 * 0.31: 14 Nov 2004: ethtool support for getting/setting link
82 * capabilities.
83 * 0.32: 16 Apr 2005: RX_ERROR4 handling added.
84 * 0.33: 16 May 2005: Support for MCP51 added.
85 * 0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
86 * 0.35: 26 Jun 2005: Support for MCP55 added.
87 * 0.36: 28 Jun 2005: Add jumbo frame support.
88 * 0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
89 * 0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
90 * per-packet flags.
91 * 0.39: 18 Jul 2005: Add 64bit descriptor support.
92 * 0.40: 19 Jul 2005: Add support for mac address change.
93 * 0.41: 30 Jul 2005: Write back original MAC in nv_close instead
94 * of nv_remove
95 * 0.42: 06 Aug 2005: Fix lack of link speed initialization
96 * in the second (and later) nv_open call
97 * 0.43: 10 Aug 2005: Add support for tx checksum.
98 * 0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
99 * 0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
100 * 0.46: 20 Oct 2005: Add irq optimization modes.
101 * 0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
102 * 0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
103 * 0.49: 10 Dec 2005: Fix tso for large buffers.
104 * 0.50: 20 Jan 2006: Add 8021pq tagging support.
105 * 0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings.
106 * 0.52: 20 Jan 2006: Add MSI/MSIX support.
107 * 0.53: 19 Mar 2006: Fix init from low power mode and add hw reset.
108 * 0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup.
109 * 0.55: 22 Mar 2006: Add flow control (pause frame).
110 * 0.56: 22 Mar 2006: Additional ethtool config and moduleparam support.
111 * 0.57: 14 May 2006: Mac address set in probe/remove and order corrections.
112 * 0.58: 30 Oct 2006: Added support for sideband management unit.
113 * 0.59: 30 Oct 2006: Added support for recoverable error.
114 * 0.60: 20 Jan 2007: Code optimizations for rings, rx & tx data paths, and stats.
115 *
116 * Known bugs:
117 * We suspect that on some hardware no TX done interrupts are generated.
118 * This means recovery from netif_stop_queue only happens if the hw timer
119 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
120 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
121 * If your hardware reliably generates tx done interrupts, then you can remove
122 * DEV_NEED_TIMERIRQ from the driver_data flags.
123 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
124 * superfluous timer interrupts from the nic.
125 */
126 #ifdef CONFIG_FORCEDETH_NAPI
127 #define DRIVERNAPI "-NAPI"
128 #else
129 #define DRIVERNAPI
130 #endif
131 #define FORCEDETH_VERSION "0.61"
132 #define DRV_NAME "forcedeth"
133
134 #include <linux/module.h>
135 #include <linux/types.h>
136 #include <linux/pci.h>
137 #include <linux/interrupt.h>
138 #include <linux/netdevice.h>
139 #include <linux/etherdevice.h>
140 #include <linux/delay.h>
141 #include <linux/spinlock.h>
142 #include <linux/ethtool.h>
143 #include <linux/timer.h>
144 #include <linux/skbuff.h>
145 #include <linux/mii.h>
146 #include <linux/random.h>
147 #include <linux/init.h>
148 #include <linux/if_vlan.h>
149 #include <linux/dma-mapping.h>
150
151 #include <asm/irq.h>
152 #include <asm/io.h>
153 #include <asm/uaccess.h>
154 #include <asm/system.h>
155
156 #if 0
157 #define dprintk printk
158 #else
159 #define dprintk(x...) do { } while (0)
160 #endif
161
162 #define TX_WORK_PER_LOOP 64
163 #define RX_WORK_PER_LOOP 64
164
165 /*
166 * Hardware access:
167 */
168
169 #define DEV_NEED_TIMERIRQ 0x00001 /* set the timer irq flag in the irq mask */
170 #define DEV_NEED_LINKTIMER 0x00002 /* poll link settings. Relies on the timer irq */
171 #define DEV_HAS_LARGEDESC 0x00004 /* device supports jumbo frames and needs packet format 2 */
172 #define DEV_HAS_HIGH_DMA 0x00008 /* device supports 64bit dma */
173 #define DEV_HAS_CHECKSUM 0x00010 /* device supports tx and rx checksum offloads */
174 #define DEV_HAS_VLAN 0x00020 /* device supports vlan tagging and striping */
175 #define DEV_HAS_MSI 0x00040 /* device supports MSI */
176 #define DEV_HAS_MSI_X 0x00080 /* device supports MSI-X */
177 #define DEV_HAS_POWER_CNTRL 0x00100 /* device supports power savings */
178 #define DEV_HAS_STATISTICS_V1 0x00200 /* device supports hw statistics version 1 */
179 #define DEV_HAS_STATISTICS_V2 0x00400 /* device supports hw statistics version 2 */
180 #define DEV_HAS_TEST_EXTENDED 0x00800 /* device supports extended diagnostic test */
181 #define DEV_HAS_MGMT_UNIT 0x01000 /* device supports management unit */
182 #define DEV_HAS_CORRECT_MACADDR 0x02000 /* device supports correct mac address order */
183 #define DEV_HAS_COLLISION_FIX 0x04000 /* device supports tx collision fix */
184 #define DEV_HAS_PAUSEFRAME_TX_V1 0x08000 /* device supports tx pause frames version 1 */
185 #define DEV_HAS_PAUSEFRAME_TX_V2 0x10000 /* device supports tx pause frames version 2 */
186 #define DEV_HAS_PAUSEFRAME_TX_V3 0x20000 /* device supports tx pause frames version 3 */
187 #define DEV_NEED_TX_LIMIT 0x40000 /* device needs to limit tx */
188
189 enum {
190 NvRegIrqStatus = 0x000,
191 #define NVREG_IRQSTAT_MIIEVENT 0x040
192 #define NVREG_IRQSTAT_MASK 0x81ff
193 NvRegIrqMask = 0x004,
194 #define NVREG_IRQ_RX_ERROR 0x0001
195 #define NVREG_IRQ_RX 0x0002
196 #define NVREG_IRQ_RX_NOBUF 0x0004
197 #define NVREG_IRQ_TX_ERR 0x0008
198 #define NVREG_IRQ_TX_OK 0x0010
199 #define NVREG_IRQ_TIMER 0x0020
200 #define NVREG_IRQ_LINK 0x0040
201 #define NVREG_IRQ_RX_FORCED 0x0080
202 #define NVREG_IRQ_TX_FORCED 0x0100
203 #define NVREG_IRQ_RECOVER_ERROR 0x8000
204 #define NVREG_IRQMASK_THROUGHPUT 0x00df
205 #define NVREG_IRQMASK_CPU 0x0060
206 #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
207 #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
208 #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
209
210 #define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
211 NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
212 NVREG_IRQ_TX_FORCED|NVREG_IRQ_RECOVER_ERROR))
213
214 NvRegUnknownSetupReg6 = 0x008,
215 #define NVREG_UNKSETUP6_VAL 3
216
217 /*
218 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
219 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
220 */
221 NvRegPollingInterval = 0x00c,
222 #define NVREG_POLL_DEFAULT_THROUGHPUT 970 /* backup tx cleanup if loop max reached */
223 #define NVREG_POLL_DEFAULT_CPU 13
224 NvRegMSIMap0 = 0x020,
225 NvRegMSIMap1 = 0x024,
226 NvRegMSIIrqMask = 0x030,
227 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
228 NvRegMisc1 = 0x080,
229 #define NVREG_MISC1_PAUSE_TX 0x01
230 #define NVREG_MISC1_HD 0x02
231 #define NVREG_MISC1_FORCE 0x3b0f3c
232
233 NvRegMacReset = 0x34,
234 #define NVREG_MAC_RESET_ASSERT 0x0F3
235 NvRegTransmitterControl = 0x084,
236 #define NVREG_XMITCTL_START 0x01
237 #define NVREG_XMITCTL_MGMT_ST 0x40000000
238 #define NVREG_XMITCTL_SYNC_MASK 0x000f0000
239 #define NVREG_XMITCTL_SYNC_NOT_READY 0x0
240 #define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
241 #define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
242 #define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
243 #define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
244 #define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
245 #define NVREG_XMITCTL_HOST_LOADED 0x00004000
246 #define NVREG_XMITCTL_TX_PATH_EN 0x01000000
247 NvRegTransmitterStatus = 0x088,
248 #define NVREG_XMITSTAT_BUSY 0x01
249
250 NvRegPacketFilterFlags = 0x8c,
251 #define NVREG_PFF_PAUSE_RX 0x08
252 #define NVREG_PFF_ALWAYS 0x7F0000
253 #define NVREG_PFF_PROMISC 0x80
254 #define NVREG_PFF_MYADDR 0x20
255 #define NVREG_PFF_LOOPBACK 0x10
256
257 NvRegOffloadConfig = 0x90,
258 #define NVREG_OFFLOAD_HOMEPHY 0x601
259 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
260 NvRegReceiverControl = 0x094,
261 #define NVREG_RCVCTL_START 0x01
262 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
263 NvRegReceiverStatus = 0x98,
264 #define NVREG_RCVSTAT_BUSY 0x01
265
266 NvRegRandomSeed = 0x9c,
267 #define NVREG_RNDSEED_MASK 0x00ff
268 #define NVREG_RNDSEED_FORCE 0x7f00
269 #define NVREG_RNDSEED_FORCE2 0x2d00
270 #define NVREG_RNDSEED_FORCE3 0x7400
271
272 NvRegTxDeferral = 0xA0,
273 #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
274 #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
275 #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
276 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10 0x16190f
277 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f
278 #define NVREG_TX_DEFERRAL_MII_STRETCH 0x152000
279 NvRegRxDeferral = 0xA4,
280 #define NVREG_RX_DEFERRAL_DEFAULT 0x16
281 NvRegMacAddrA = 0xA8,
282 NvRegMacAddrB = 0xAC,
283 NvRegMulticastAddrA = 0xB0,
284 #define NVREG_MCASTADDRA_FORCE 0x01
285 NvRegMulticastAddrB = 0xB4,
286 NvRegMulticastMaskA = 0xB8,
287 #define NVREG_MCASTMASKA_NONE 0xffffffff
288 NvRegMulticastMaskB = 0xBC,
289 #define NVREG_MCASTMASKB_NONE 0xffff
290
291 NvRegPhyInterface = 0xC0,
292 #define PHY_RGMII 0x10000000
293
294 NvRegTxRingPhysAddr = 0x100,
295 NvRegRxRingPhysAddr = 0x104,
296 NvRegRingSizes = 0x108,
297 #define NVREG_RINGSZ_TXSHIFT 0
298 #define NVREG_RINGSZ_RXSHIFT 16
299 NvRegTransmitPoll = 0x10c,
300 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
301 NvRegLinkSpeed = 0x110,
302 #define NVREG_LINKSPEED_FORCE 0x10000
303 #define NVREG_LINKSPEED_10 1000
304 #define NVREG_LINKSPEED_100 100
305 #define NVREG_LINKSPEED_1000 50
306 #define NVREG_LINKSPEED_MASK (0xFFF)
307 NvRegUnknownSetupReg5 = 0x130,
308 #define NVREG_UNKSETUP5_BIT31 (1<<31)
309 NvRegTxWatermark = 0x13c,
310 #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
311 #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
312 #define NVREG_TX_WM_DESC2_3_1000 0xfe08000
313 NvRegTxRxControl = 0x144,
314 #define NVREG_TXRXCTL_KICK 0x0001
315 #define NVREG_TXRXCTL_BIT1 0x0002
316 #define NVREG_TXRXCTL_BIT2 0x0004
317 #define NVREG_TXRXCTL_IDLE 0x0008
318 #define NVREG_TXRXCTL_RESET 0x0010
319 #define NVREG_TXRXCTL_RXCHECK 0x0400
320 #define NVREG_TXRXCTL_DESC_1 0
321 #define NVREG_TXRXCTL_DESC_2 0x002100
322 #define NVREG_TXRXCTL_DESC_3 0xc02200
323 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
324 #define NVREG_TXRXCTL_VLANINS 0x00080
325 NvRegTxRingPhysAddrHigh = 0x148,
326 NvRegRxRingPhysAddrHigh = 0x14C,
327 NvRegTxPauseFrame = 0x170,
328 #define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080
329 #define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010
330 #define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0
331 #define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880
332 NvRegMIIStatus = 0x180,
333 #define NVREG_MIISTAT_ERROR 0x0001
334 #define NVREG_MIISTAT_LINKCHANGE 0x0008
335 #define NVREG_MIISTAT_MASK_RW 0x0007
336 #define NVREG_MIISTAT_MASK_ALL 0x000f
337 NvRegMIIMask = 0x184,
338 #define NVREG_MII_LINKCHANGE 0x0008
339
340 NvRegAdapterControl = 0x188,
341 #define NVREG_ADAPTCTL_START 0x02
342 #define NVREG_ADAPTCTL_LINKUP 0x04
343 #define NVREG_ADAPTCTL_PHYVALID 0x40000
344 #define NVREG_ADAPTCTL_RUNNING 0x100000
345 #define NVREG_ADAPTCTL_PHYSHIFT 24
346 NvRegMIISpeed = 0x18c,
347 #define NVREG_MIISPEED_BIT8 (1<<8)
348 #define NVREG_MIIDELAY 5
349 NvRegMIIControl = 0x190,
350 #define NVREG_MIICTL_INUSE 0x08000
351 #define NVREG_MIICTL_WRITE 0x00400
352 #define NVREG_MIICTL_ADDRSHIFT 5
353 NvRegMIIData = 0x194,
354 NvRegWakeUpFlags = 0x200,
355 #define NVREG_WAKEUPFLAGS_VAL 0x7770
356 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
357 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
358 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
359 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
360 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
361 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
362 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
363 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
364 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
365 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
366
367 NvRegPatternCRC = 0x204,
368 NvRegPatternMask = 0x208,
369 NvRegPowerCap = 0x268,
370 #define NVREG_POWERCAP_D3SUPP (1<<30)
371 #define NVREG_POWERCAP_D2SUPP (1<<26)
372 #define NVREG_POWERCAP_D1SUPP (1<<25)
373 NvRegPowerState = 0x26c,
374 #define NVREG_POWERSTATE_POWEREDUP 0x8000
375 #define NVREG_POWERSTATE_VALID 0x0100
376 #define NVREG_POWERSTATE_MASK 0x0003
377 #define NVREG_POWERSTATE_D0 0x0000
378 #define NVREG_POWERSTATE_D1 0x0001
379 #define NVREG_POWERSTATE_D2 0x0002
380 #define NVREG_POWERSTATE_D3 0x0003
381 NvRegTxCnt = 0x280,
382 NvRegTxZeroReXmt = 0x284,
383 NvRegTxOneReXmt = 0x288,
384 NvRegTxManyReXmt = 0x28c,
385 NvRegTxLateCol = 0x290,
386 NvRegTxUnderflow = 0x294,
387 NvRegTxLossCarrier = 0x298,
388 NvRegTxExcessDef = 0x29c,
389 NvRegTxRetryErr = 0x2a0,
390 NvRegRxFrameErr = 0x2a4,
391 NvRegRxExtraByte = 0x2a8,
392 NvRegRxLateCol = 0x2ac,
393 NvRegRxRunt = 0x2b0,
394 NvRegRxFrameTooLong = 0x2b4,
395 NvRegRxOverflow = 0x2b8,
396 NvRegRxFCSErr = 0x2bc,
397 NvRegRxFrameAlignErr = 0x2c0,
398 NvRegRxLenErr = 0x2c4,
399 NvRegRxUnicast = 0x2c8,
400 NvRegRxMulticast = 0x2cc,
401 NvRegRxBroadcast = 0x2d0,
402 NvRegTxDef = 0x2d4,
403 NvRegTxFrame = 0x2d8,
404 NvRegRxCnt = 0x2dc,
405 NvRegTxPause = 0x2e0,
406 NvRegRxPause = 0x2e4,
407 NvRegRxDropFrame = 0x2e8,
408 NvRegVlanControl = 0x300,
409 #define NVREG_VLANCONTROL_ENABLE 0x2000
410 NvRegMSIXMap0 = 0x3e0,
411 NvRegMSIXMap1 = 0x3e4,
412 NvRegMSIXIrqStatus = 0x3f0,
413
414 NvRegPowerState2 = 0x600,
415 #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F11
416 #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
417 };
418
419 /* Big endian: should work, but is untested */
420 struct ring_desc {
421 __le32 buf;
422 __le32 flaglen;
423 };
424
425 struct ring_desc_ex {
426 __le32 bufhigh;
427 __le32 buflow;
428 __le32 txvlan;
429 __le32 flaglen;
430 };
431
432 union ring_type {
433 struct ring_desc* orig;
434 struct ring_desc_ex* ex;
435 };
436
437 #define FLAG_MASK_V1 0xffff0000
438 #define FLAG_MASK_V2 0xffffc000
439 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
440 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
441
442 #define NV_TX_LASTPACKET (1<<16)
443 #define NV_TX_RETRYERROR (1<<19)
444 #define NV_TX_FORCED_INTERRUPT (1<<24)
445 #define NV_TX_DEFERRED (1<<26)
446 #define NV_TX_CARRIERLOST (1<<27)
447 #define NV_TX_LATECOLLISION (1<<28)
448 #define NV_TX_UNDERFLOW (1<<29)
449 #define NV_TX_ERROR (1<<30)
450 #define NV_TX_VALID (1<<31)
451
452 #define NV_TX2_LASTPACKET (1<<29)
453 #define NV_TX2_RETRYERROR (1<<18)
454 #define NV_TX2_FORCED_INTERRUPT (1<<30)
455 #define NV_TX2_DEFERRED (1<<25)
456 #define NV_TX2_CARRIERLOST (1<<26)
457 #define NV_TX2_LATECOLLISION (1<<27)
458 #define NV_TX2_UNDERFLOW (1<<28)
459 /* error and valid are the same for both */
460 #define NV_TX2_ERROR (1<<30)
461 #define NV_TX2_VALID (1<<31)
462 #define NV_TX2_TSO (1<<28)
463 #define NV_TX2_TSO_SHIFT 14
464 #define NV_TX2_TSO_MAX_SHIFT 14
465 #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
466 #define NV_TX2_CHECKSUM_L3 (1<<27)
467 #define NV_TX2_CHECKSUM_L4 (1<<26)
468
469 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
470
471 #define NV_RX_DESCRIPTORVALID (1<<16)
472 #define NV_RX_MISSEDFRAME (1<<17)
473 #define NV_RX_SUBSTRACT1 (1<<18)
474 #define NV_RX_ERROR1 (1<<23)
475 #define NV_RX_ERROR2 (1<<24)
476 #define NV_RX_ERROR3 (1<<25)
477 #define NV_RX_ERROR4 (1<<26)
478 #define NV_RX_CRCERR (1<<27)
479 #define NV_RX_OVERFLOW (1<<28)
480 #define NV_RX_FRAMINGERR (1<<29)
481 #define NV_RX_ERROR (1<<30)
482 #define NV_RX_AVAIL (1<<31)
483
484 #define NV_RX2_CHECKSUMMASK (0x1C000000)
485 #define NV_RX2_CHECKSUM_IP (0x10000000)
486 #define NV_RX2_CHECKSUM_IP_TCP (0x14000000)
487 #define NV_RX2_CHECKSUM_IP_UDP (0x18000000)
488 #define NV_RX2_DESCRIPTORVALID (1<<29)
489 #define NV_RX2_SUBSTRACT1 (1<<25)
490 #define NV_RX2_ERROR1 (1<<18)
491 #define NV_RX2_ERROR2 (1<<19)
492 #define NV_RX2_ERROR3 (1<<20)
493 #define NV_RX2_ERROR4 (1<<21)
494 #define NV_RX2_CRCERR (1<<22)
495 #define NV_RX2_OVERFLOW (1<<23)
496 #define NV_RX2_FRAMINGERR (1<<24)
497 /* error and avail are the same for both */
498 #define NV_RX2_ERROR (1<<30)
499 #define NV_RX2_AVAIL (1<<31)
500
501 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
502 #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
503
504 /* Miscelaneous hardware related defines: */
505 #define NV_PCI_REGSZ_VER1 0x270
506 #define NV_PCI_REGSZ_VER2 0x2d4
507 #define NV_PCI_REGSZ_VER3 0x604
508
509 /* various timeout delays: all in usec */
510 #define NV_TXRX_RESET_DELAY 4
511 #define NV_TXSTOP_DELAY1 10
512 #define NV_TXSTOP_DELAY1MAX 500000
513 #define NV_TXSTOP_DELAY2 100
514 #define NV_RXSTOP_DELAY1 10
515 #define NV_RXSTOP_DELAY1MAX 500000
516 #define NV_RXSTOP_DELAY2 100
517 #define NV_SETUP5_DELAY 5
518 #define NV_SETUP5_DELAYMAX 50000
519 #define NV_POWERUP_DELAY 5
520 #define NV_POWERUP_DELAYMAX 5000
521 #define NV_MIIBUSY_DELAY 50
522 #define NV_MIIPHY_DELAY 10
523 #define NV_MIIPHY_DELAYMAX 10000
524 #define NV_MAC_RESET_DELAY 64
525
526 #define NV_WAKEUPPATTERNS 5
527 #define NV_WAKEUPMASKENTRIES 4
528
529 /* General driver defaults */
530 #define NV_WATCHDOG_TIMEO (5*HZ)
531
532 #define RX_RING_DEFAULT 128
533 #define TX_RING_DEFAULT 256
534 #define RX_RING_MIN 128
535 #define TX_RING_MIN 64
536 #define RING_MAX_DESC_VER_1 1024
537 #define RING_MAX_DESC_VER_2_3 16384
538
539 /* rx/tx mac addr + type + vlan + align + slack*/
540 #define NV_RX_HEADERS (64)
541 /* even more slack. */
542 #define NV_RX_ALLOC_PAD (64)
543
544 /* maximum mtu size */
545 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
546 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
547
548 #define OOM_REFILL (1+HZ/20)
549 #define POLL_WAIT (1+HZ/100)
550 #define LINK_TIMEOUT (3*HZ)
551 #define STATS_INTERVAL (10*HZ)
552
553 /*
554 * desc_ver values:
555 * The nic supports three different descriptor types:
556 * - DESC_VER_1: Original
557 * - DESC_VER_2: support for jumbo frames.
558 * - DESC_VER_3: 64-bit format.
559 */
560 #define DESC_VER_1 1
561 #define DESC_VER_2 2
562 #define DESC_VER_3 3
563
564 /* PHY defines */
565 #define PHY_OUI_MARVELL 0x5043
566 #define PHY_OUI_CICADA 0x03f1
567 #define PHY_OUI_VITESSE 0x01c1
568 #define PHY_OUI_REALTEK 0x0732
569 #define PHYID1_OUI_MASK 0x03ff
570 #define PHYID1_OUI_SHFT 6
571 #define PHYID2_OUI_MASK 0xfc00
572 #define PHYID2_OUI_SHFT 10
573 #define PHYID2_MODEL_MASK 0x03f0
574 #define PHY_MODEL_MARVELL_E3016 0x220
575 #define PHY_MARVELL_E3016_INITMASK 0x0300
576 #define PHY_CICADA_INIT1 0x0f000
577 #define PHY_CICADA_INIT2 0x0e00
578 #define PHY_CICADA_INIT3 0x01000
579 #define PHY_CICADA_INIT4 0x0200
580 #define PHY_CICADA_INIT5 0x0004
581 #define PHY_CICADA_INIT6 0x02000
582 #define PHY_VITESSE_INIT_REG1 0x1f
583 #define PHY_VITESSE_INIT_REG2 0x10
584 #define PHY_VITESSE_INIT_REG3 0x11
585 #define PHY_VITESSE_INIT_REG4 0x12
586 #define PHY_VITESSE_INIT_MSK1 0xc
587 #define PHY_VITESSE_INIT_MSK2 0x0180
588 #define PHY_VITESSE_INIT1 0x52b5
589 #define PHY_VITESSE_INIT2 0xaf8a
590 #define PHY_VITESSE_INIT3 0x8
591 #define PHY_VITESSE_INIT4 0x8f8a
592 #define PHY_VITESSE_INIT5 0xaf86
593 #define PHY_VITESSE_INIT6 0x8f86
594 #define PHY_VITESSE_INIT7 0xaf82
595 #define PHY_VITESSE_INIT8 0x0100
596 #define PHY_VITESSE_INIT9 0x8f82
597 #define PHY_VITESSE_INIT10 0x0
598 #define PHY_REALTEK_INIT_REG1 0x1f
599 #define PHY_REALTEK_INIT_REG2 0x19
600 #define PHY_REALTEK_INIT_REG3 0x13
601 #define PHY_REALTEK_INIT1 0x0000
602 #define PHY_REALTEK_INIT2 0x8e00
603 #define PHY_REALTEK_INIT3 0x0001
604 #define PHY_REALTEK_INIT4 0xad17
605
606 #define PHY_GIGABIT 0x0100
607
608 #define PHY_TIMEOUT 0x1
609 #define PHY_ERROR 0x2
610
611 #define PHY_100 0x1
612 #define PHY_1000 0x2
613 #define PHY_HALF 0x100
614
615 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
616 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
617 #define NV_PAUSEFRAME_RX_ENABLE 0x0004
618 #define NV_PAUSEFRAME_TX_ENABLE 0x0008
619 #define NV_PAUSEFRAME_RX_REQ 0x0010
620 #define NV_PAUSEFRAME_TX_REQ 0x0020
621 #define NV_PAUSEFRAME_AUTONEG 0x0040
622
623 /* MSI/MSI-X defines */
624 #define NV_MSI_X_MAX_VECTORS 8
625 #define NV_MSI_X_VECTORS_MASK 0x000f
626 #define NV_MSI_CAPABLE 0x0010
627 #define NV_MSI_X_CAPABLE 0x0020
628 #define NV_MSI_ENABLED 0x0040
629 #define NV_MSI_X_ENABLED 0x0080
630
631 #define NV_MSI_X_VECTOR_ALL 0x0
632 #define NV_MSI_X_VECTOR_RX 0x0
633 #define NV_MSI_X_VECTOR_TX 0x1
634 #define NV_MSI_X_VECTOR_OTHER 0x2
635
636 #define NV_RESTART_TX 0x1
637 #define NV_RESTART_RX 0x2
638
639 #define NV_TX_LIMIT_COUNT 16
640
641 /* statistics */
642 struct nv_ethtool_str {
643 char name[ETH_GSTRING_LEN];
644 };
645
646 static const struct nv_ethtool_str nv_estats_str[] = {
647 { "tx_bytes" },
648 { "tx_zero_rexmt" },
649 { "tx_one_rexmt" },
650 { "tx_many_rexmt" },
651 { "tx_late_collision" },
652 { "tx_fifo_errors" },
653 { "tx_carrier_errors" },
654 { "tx_excess_deferral" },
655 { "tx_retry_error" },
656 { "rx_frame_error" },
657 { "rx_extra_byte" },
658 { "rx_late_collision" },
659 { "rx_runt" },
660 { "rx_frame_too_long" },
661 { "rx_over_errors" },
662 { "rx_crc_errors" },
663 { "rx_frame_align_error" },
664 { "rx_length_error" },
665 { "rx_unicast" },
666 { "rx_multicast" },
667 { "rx_broadcast" },
668 { "rx_packets" },
669 { "rx_errors_total" },
670 { "tx_errors_total" },
671
672 /* version 2 stats */
673 { "tx_deferral" },
674 { "tx_packets" },
675 { "rx_bytes" },
676 { "tx_pause" },
677 { "rx_pause" },
678 { "rx_drop_frame" }
679 };
680
681 struct nv_ethtool_stats {
682 u64 tx_bytes;
683 u64 tx_zero_rexmt;
684 u64 tx_one_rexmt;
685 u64 tx_many_rexmt;
686 u64 tx_late_collision;
687 u64 tx_fifo_errors;
688 u64 tx_carrier_errors;
689 u64 tx_excess_deferral;
690 u64 tx_retry_error;
691 u64 rx_frame_error;
692 u64 rx_extra_byte;
693 u64 rx_late_collision;
694 u64 rx_runt;
695 u64 rx_frame_too_long;
696 u64 rx_over_errors;
697 u64 rx_crc_errors;
698 u64 rx_frame_align_error;
699 u64 rx_length_error;
700 u64 rx_unicast;
701 u64 rx_multicast;
702 u64 rx_broadcast;
703 u64 rx_packets;
704 u64 rx_errors_total;
705 u64 tx_errors_total;
706
707 /* version 2 stats */
708 u64 tx_deferral;
709 u64 tx_packets;
710 u64 rx_bytes;
711 u64 tx_pause;
712 u64 rx_pause;
713 u64 rx_drop_frame;
714 };
715
716 #define NV_DEV_STATISTICS_V2_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
717 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
718
719 /* diagnostics */
720 #define NV_TEST_COUNT_BASE 3
721 #define NV_TEST_COUNT_EXTENDED 4
722
723 static const struct nv_ethtool_str nv_etests_str[] = {
724 { "link (online/offline)" },
725 { "register (offline) " },
726 { "interrupt (offline) " },
727 { "loopback (offline) " }
728 };
729
730 struct register_test {
731 __u32 reg;
732 __u32 mask;
733 };
734
735 static const struct register_test nv_registers_test[] = {
736 { NvRegUnknownSetupReg6, 0x01 },
737 { NvRegMisc1, 0x03c },
738 { NvRegOffloadConfig, 0x03ff },
739 { NvRegMulticastAddrA, 0xffffffff },
740 { NvRegTxWatermark, 0x0ff },
741 { NvRegWakeUpFlags, 0x07777 },
742 { 0,0 }
743 };
744
745 struct nv_skb_map {
746 struct sk_buff *skb;
747 dma_addr_t dma;
748 unsigned int dma_len;
749 struct ring_desc_ex *first_tx_desc;
750 struct nv_skb_map *next_tx_ctx;
751 };
752
753 /*
754 * SMP locking:
755 * All hardware access under dev->priv->lock, except the performance
756 * critical parts:
757 * - rx is (pseudo-) lockless: it relies on the single-threading provided
758 * by the arch code for interrupts.
759 * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
760 * needs dev->priv->lock :-(
761 * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
762 */
763
764 /* in dev: base, irq */
765 struct fe_priv {
766 spinlock_t lock;
767
768 struct net_device *dev;
769 struct napi_struct napi;
770
771 /* General data:
772 * Locking: spin_lock(&np->lock); */
773 struct nv_ethtool_stats estats;
774 int in_shutdown;
775 u32 linkspeed;
776 int duplex;
777 int autoneg;
778 int fixed_mode;
779 int phyaddr;
780 int wolenabled;
781 unsigned int phy_oui;
782 unsigned int phy_model;
783 u16 gigabit;
784 int intr_test;
785 int recover_error;
786
787 /* General data: RO fields */
788 dma_addr_t ring_addr;
789 struct pci_dev *pci_dev;
790 u32 orig_mac[2];
791 u32 irqmask;
792 u32 desc_ver;
793 u32 txrxctl_bits;
794 u32 vlanctl_bits;
795 u32 driver_data;
796 u32 register_size;
797 int rx_csum;
798 u32 mac_in_use;
799
800 void __iomem *base;
801
802 /* rx specific fields.
803 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
804 */
805 union ring_type get_rx, put_rx, first_rx, last_rx;
806 struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
807 struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
808 struct nv_skb_map *rx_skb;
809
810 union ring_type rx_ring;
811 unsigned int rx_buf_sz;
812 unsigned int pkt_limit;
813 struct timer_list oom_kick;
814 struct timer_list nic_poll;
815 struct timer_list stats_poll;
816 u32 nic_poll_irq;
817 int rx_ring_size;
818
819 /* media detection workaround.
820 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
821 */
822 int need_linktimer;
823 unsigned long link_timeout;
824 /*
825 * tx specific fields.
826 */
827 union ring_type get_tx, put_tx, first_tx, last_tx;
828 struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
829 struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
830 struct nv_skb_map *tx_skb;
831
832 union ring_type tx_ring;
833 u32 tx_flags;
834 int tx_ring_size;
835 int tx_limit;
836 u32 tx_pkts_in_progress;
837 struct nv_skb_map *tx_change_owner;
838 struct nv_skb_map *tx_end_flip;
839 int tx_stop;
840
841 /* vlan fields */
842 struct vlan_group *vlangrp;
843
844 /* msi/msi-x fields */
845 u32 msi_flags;
846 struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
847
848 /* flow control */
849 u32 pause_flags;
850 };
851
852 /*
853 * Maximum number of loops until we assume that a bit in the irq mask
854 * is stuck. Overridable with module param.
855 */
856 static int max_interrupt_work = 5;
857
858 /*
859 * Optimization can be either throuput mode or cpu mode
860 *
861 * Throughput Mode: Every tx and rx packet will generate an interrupt.
862 * CPU Mode: Interrupts are controlled by a timer.
863 */
864 enum {
865 NV_OPTIMIZATION_MODE_THROUGHPUT,
866 NV_OPTIMIZATION_MODE_CPU
867 };
868 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
869
870 /*
871 * Poll interval for timer irq
872 *
873 * This interval determines how frequent an interrupt is generated.
874 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
875 * Min = 0, and Max = 65535
876 */
877 static int poll_interval = -1;
878
879 /*
880 * MSI interrupts
881 */
882 enum {
883 NV_MSI_INT_DISABLED,
884 NV_MSI_INT_ENABLED
885 };
886 static int msi = NV_MSI_INT_ENABLED;
887
888 /*
889 * MSIX interrupts
890 */
891 enum {
892 NV_MSIX_INT_DISABLED,
893 NV_MSIX_INT_ENABLED
894 };
895 static int msix = NV_MSIX_INT_DISABLED;
896
897 /*
898 * DMA 64bit
899 */
900 enum {
901 NV_DMA_64BIT_DISABLED,
902 NV_DMA_64BIT_ENABLED
903 };
904 static int dma_64bit = NV_DMA_64BIT_ENABLED;
905
906 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
907 {
908 return netdev_priv(dev);
909 }
910
911 static inline u8 __iomem *get_hwbase(struct net_device *dev)
912 {
913 return ((struct fe_priv *)netdev_priv(dev))->base;
914 }
915
916 static inline void pci_push(u8 __iomem *base)
917 {
918 /* force out pending posted writes */
919 readl(base);
920 }
921
922 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
923 {
924 return le32_to_cpu(prd->flaglen)
925 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
926 }
927
928 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
929 {
930 return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
931 }
932
933 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
934 int delay, int delaymax, const char *msg)
935 {
936 u8 __iomem *base = get_hwbase(dev);
937
938 pci_push(base);
939 do {
940 udelay(delay);
941 delaymax -= delay;
942 if (delaymax < 0) {
943 if (msg)
944 printk(msg);
945 return 1;
946 }
947 } while ((readl(base + offset) & mask) != target);
948 return 0;
949 }
950
951 #define NV_SETUP_RX_RING 0x01
952 #define NV_SETUP_TX_RING 0x02
953
954 static inline u32 dma_low(dma_addr_t addr)
955 {
956 return addr;
957 }
958
959 static inline u32 dma_high(dma_addr_t addr)
960 {
961 return addr>>31>>1; /* 0 if 32bit, shift down by 32 if 64bit */
962 }
963
964 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
965 {
966 struct fe_priv *np = get_nvpriv(dev);
967 u8 __iomem *base = get_hwbase(dev);
968
969 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
970 if (rxtx_flags & NV_SETUP_RX_RING) {
971 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
972 }
973 if (rxtx_flags & NV_SETUP_TX_RING) {
974 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
975 }
976 } else {
977 if (rxtx_flags & NV_SETUP_RX_RING) {
978 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
979 writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
980 }
981 if (rxtx_flags & NV_SETUP_TX_RING) {
982 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
983 writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
984 }
985 }
986 }
987
988 static void free_rings(struct net_device *dev)
989 {
990 struct fe_priv *np = get_nvpriv(dev);
991
992 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
993 if (np->rx_ring.orig)
994 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
995 np->rx_ring.orig, np->ring_addr);
996 } else {
997 if (np->rx_ring.ex)
998 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
999 np->rx_ring.ex, np->ring_addr);
1000 }
1001 if (np->rx_skb)
1002 kfree(np->rx_skb);
1003 if (np->tx_skb)
1004 kfree(np->tx_skb);
1005 }
1006
1007 static int using_multi_irqs(struct net_device *dev)
1008 {
1009 struct fe_priv *np = get_nvpriv(dev);
1010
1011 if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
1012 ((np->msi_flags & NV_MSI_X_ENABLED) &&
1013 ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
1014 return 0;
1015 else
1016 return 1;
1017 }
1018
1019 static void nv_enable_irq(struct net_device *dev)
1020 {
1021 struct fe_priv *np = get_nvpriv(dev);
1022
1023 if (!using_multi_irqs(dev)) {
1024 if (np->msi_flags & NV_MSI_X_ENABLED)
1025 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1026 else
1027 enable_irq(np->pci_dev->irq);
1028 } else {
1029 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1030 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1031 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1032 }
1033 }
1034
1035 static void nv_disable_irq(struct net_device *dev)
1036 {
1037 struct fe_priv *np = get_nvpriv(dev);
1038
1039 if (!using_multi_irqs(dev)) {
1040 if (np->msi_flags & NV_MSI_X_ENABLED)
1041 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1042 else
1043 disable_irq(np->pci_dev->irq);
1044 } else {
1045 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1046 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1047 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1048 }
1049 }
1050
1051 /* In MSIX mode, a write to irqmask behaves as XOR */
1052 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1053 {
1054 u8 __iomem *base = get_hwbase(dev);
1055
1056 writel(mask, base + NvRegIrqMask);
1057 }
1058
1059 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1060 {
1061 struct fe_priv *np = get_nvpriv(dev);
1062 u8 __iomem *base = get_hwbase(dev);
1063
1064 if (np->msi_flags & NV_MSI_X_ENABLED) {
1065 writel(mask, base + NvRegIrqMask);
1066 } else {
1067 if (np->msi_flags & NV_MSI_ENABLED)
1068 writel(0, base + NvRegMSIIrqMask);
1069 writel(0, base + NvRegIrqMask);
1070 }
1071 }
1072
1073 #define MII_READ (-1)
1074 /* mii_rw: read/write a register on the PHY.
1075 *
1076 * Caller must guarantee serialization
1077 */
1078 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1079 {
1080 u8 __iomem *base = get_hwbase(dev);
1081 u32 reg;
1082 int retval;
1083
1084 writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
1085
1086 reg = readl(base + NvRegMIIControl);
1087 if (reg & NVREG_MIICTL_INUSE) {
1088 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1089 udelay(NV_MIIBUSY_DELAY);
1090 }
1091
1092 reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1093 if (value != MII_READ) {
1094 writel(value, base + NvRegMIIData);
1095 reg |= NVREG_MIICTL_WRITE;
1096 }
1097 writel(reg, base + NvRegMIIControl);
1098
1099 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1100 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1101 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1102 dev->name, miireg, addr);
1103 retval = -1;
1104 } else if (value != MII_READ) {
1105 /* it was a write operation - fewer failures are detectable */
1106 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1107 dev->name, value, miireg, addr);
1108 retval = 0;
1109 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1110 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1111 dev->name, miireg, addr);
1112 retval = -1;
1113 } else {
1114 retval = readl(base + NvRegMIIData);
1115 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1116 dev->name, miireg, addr, retval);
1117 }
1118
1119 return retval;
1120 }
1121
1122 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1123 {
1124 struct fe_priv *np = netdev_priv(dev);
1125 u32 miicontrol;
1126 unsigned int tries = 0;
1127
1128 miicontrol = BMCR_RESET | bmcr_setup;
1129 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1130 return -1;
1131 }
1132
1133 /* wait for 500ms */
1134 msleep(500);
1135
1136 /* must wait till reset is deasserted */
1137 while (miicontrol & BMCR_RESET) {
1138 msleep(10);
1139 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1140 /* FIXME: 100 tries seem excessive */
1141 if (tries++ > 100)
1142 return -1;
1143 }
1144 return 0;
1145 }
1146
1147 static int phy_init(struct net_device *dev)
1148 {
1149 struct fe_priv *np = get_nvpriv(dev);
1150 u8 __iomem *base = get_hwbase(dev);
1151 u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1152
1153 /* phy errata for E3016 phy */
1154 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1155 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1156 reg &= ~PHY_MARVELL_E3016_INITMASK;
1157 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1158 printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1159 return PHY_ERROR;
1160 }
1161 }
1162 if (np->phy_oui == PHY_OUI_REALTEK) {
1163 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1164 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1165 return PHY_ERROR;
1166 }
1167 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1168 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1169 return PHY_ERROR;
1170 }
1171 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1172 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1173 return PHY_ERROR;
1174 }
1175 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1176 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1177 return PHY_ERROR;
1178 }
1179 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1180 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1181 return PHY_ERROR;
1182 }
1183 }
1184
1185 /* set advertise register */
1186 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1187 reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1188 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1189 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1190 return PHY_ERROR;
1191 }
1192
1193 /* get phy interface type */
1194 phyinterface = readl(base + NvRegPhyInterface);
1195
1196 /* see if gigabit phy */
1197 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1198 if (mii_status & PHY_GIGABIT) {
1199 np->gigabit = PHY_GIGABIT;
1200 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1201 mii_control_1000 &= ~ADVERTISE_1000HALF;
1202 if (phyinterface & PHY_RGMII)
1203 mii_control_1000 |= ADVERTISE_1000FULL;
1204 else
1205 mii_control_1000 &= ~ADVERTISE_1000FULL;
1206
1207 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1208 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1209 return PHY_ERROR;
1210 }
1211 }
1212 else
1213 np->gigabit = 0;
1214
1215 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1216 mii_control |= BMCR_ANENABLE;
1217
1218 /* reset the phy
1219 * (certain phys need bmcr to be setup with reset)
1220 */
1221 if (phy_reset(dev, mii_control)) {
1222 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1223 return PHY_ERROR;
1224 }
1225
1226 /* phy vendor specific configuration */
1227 if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1228 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1229 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1230 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1231 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1232 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1233 return PHY_ERROR;
1234 }
1235 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1236 phy_reserved |= PHY_CICADA_INIT5;
1237 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1238 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1239 return PHY_ERROR;
1240 }
1241 }
1242 if (np->phy_oui == PHY_OUI_CICADA) {
1243 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1244 phy_reserved |= PHY_CICADA_INIT6;
1245 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1246 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1247 return PHY_ERROR;
1248 }
1249 }
1250 if (np->phy_oui == PHY_OUI_VITESSE) {
1251 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) {
1252 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1253 return PHY_ERROR;
1254 }
1255 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) {
1256 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1257 return PHY_ERROR;
1258 }
1259 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1260 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1261 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1262 return PHY_ERROR;
1263 }
1264 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1265 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1266 phy_reserved |= PHY_VITESSE_INIT3;
1267 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1268 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1269 return PHY_ERROR;
1270 }
1271 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) {
1272 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1273 return PHY_ERROR;
1274 }
1275 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) {
1276 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1277 return PHY_ERROR;
1278 }
1279 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1280 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1281 phy_reserved |= PHY_VITESSE_INIT3;
1282 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1283 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1284 return PHY_ERROR;
1285 }
1286 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1287 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1288 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1289 return PHY_ERROR;
1290 }
1291 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) {
1292 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1293 return PHY_ERROR;
1294 }
1295 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) {
1296 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1297 return PHY_ERROR;
1298 }
1299 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1300 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1301 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1302 return PHY_ERROR;
1303 }
1304 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1305 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1306 phy_reserved |= PHY_VITESSE_INIT8;
1307 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1308 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1309 return PHY_ERROR;
1310 }
1311 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) {
1312 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1313 return PHY_ERROR;
1314 }
1315 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) {
1316 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1317 return PHY_ERROR;
1318 }
1319 }
1320 if (np->phy_oui == PHY_OUI_REALTEK) {
1321 /* reset could have cleared these out, set them back */
1322 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1323 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1324 return PHY_ERROR;
1325 }
1326 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1327 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1328 return PHY_ERROR;
1329 }
1330 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1331 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1332 return PHY_ERROR;
1333 }
1334 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1335 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1336 return PHY_ERROR;
1337 }
1338 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1339 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1340 return PHY_ERROR;
1341 }
1342 }
1343
1344 /* some phys clear out pause advertisment on reset, set it back */
1345 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1346
1347 /* restart auto negotiation */
1348 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1349 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1350 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1351 return PHY_ERROR;
1352 }
1353
1354 return 0;
1355 }
1356
1357 static void nv_start_rx(struct net_device *dev)
1358 {
1359 struct fe_priv *np = netdev_priv(dev);
1360 u8 __iomem *base = get_hwbase(dev);
1361 u32 rx_ctrl = readl(base + NvRegReceiverControl);
1362
1363 dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1364 /* Already running? Stop it. */
1365 if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1366 rx_ctrl &= ~NVREG_RCVCTL_START;
1367 writel(rx_ctrl, base + NvRegReceiverControl);
1368 pci_push(base);
1369 }
1370 writel(np->linkspeed, base + NvRegLinkSpeed);
1371 pci_push(base);
1372 rx_ctrl |= NVREG_RCVCTL_START;
1373 if (np->mac_in_use)
1374 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1375 writel(rx_ctrl, base + NvRegReceiverControl);
1376 dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1377 dev->name, np->duplex, np->linkspeed);
1378 pci_push(base);
1379 }
1380
1381 static void nv_stop_rx(struct net_device *dev)
1382 {
1383 struct fe_priv *np = netdev_priv(dev);
1384 u8 __iomem *base = get_hwbase(dev);
1385 u32 rx_ctrl = readl(base + NvRegReceiverControl);
1386
1387 dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1388 if (!np->mac_in_use)
1389 rx_ctrl &= ~NVREG_RCVCTL_START;
1390 else
1391 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1392 writel(rx_ctrl, base + NvRegReceiverControl);
1393 reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1394 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1395 KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1396
1397 udelay(NV_RXSTOP_DELAY2);
1398 if (!np->mac_in_use)
1399 writel(0, base + NvRegLinkSpeed);
1400 }
1401
1402 static void nv_start_tx(struct net_device *dev)
1403 {
1404 struct fe_priv *np = netdev_priv(dev);
1405 u8 __iomem *base = get_hwbase(dev);
1406 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1407
1408 dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1409 tx_ctrl |= NVREG_XMITCTL_START;
1410 if (np->mac_in_use)
1411 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1412 writel(tx_ctrl, base + NvRegTransmitterControl);
1413 pci_push(base);
1414 }
1415
1416 static void nv_stop_tx(struct net_device *dev)
1417 {
1418 struct fe_priv *np = netdev_priv(dev);
1419 u8 __iomem *base = get_hwbase(dev);
1420 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1421
1422 dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1423 if (!np->mac_in_use)
1424 tx_ctrl &= ~NVREG_XMITCTL_START;
1425 else
1426 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1427 writel(tx_ctrl, base + NvRegTransmitterControl);
1428 reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1429 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1430 KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1431
1432 udelay(NV_TXSTOP_DELAY2);
1433 if (!np->mac_in_use)
1434 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1435 base + NvRegTransmitPoll);
1436 }
1437
1438 static void nv_txrx_reset(struct net_device *dev)
1439 {
1440 struct fe_priv *np = netdev_priv(dev);
1441 u8 __iomem *base = get_hwbase(dev);
1442
1443 dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1444 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1445 pci_push(base);
1446 udelay(NV_TXRX_RESET_DELAY);
1447 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1448 pci_push(base);
1449 }
1450
1451 static void nv_mac_reset(struct net_device *dev)
1452 {
1453 struct fe_priv *np = netdev_priv(dev);
1454 u8 __iomem *base = get_hwbase(dev);
1455 u32 temp1, temp2, temp3;
1456
1457 dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1458
1459 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1460 pci_push(base);
1461
1462 /* save registers since they will be cleared on reset */
1463 temp1 = readl(base + NvRegMacAddrA);
1464 temp2 = readl(base + NvRegMacAddrB);
1465 temp3 = readl(base + NvRegTransmitPoll);
1466
1467 writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1468 pci_push(base);
1469 udelay(NV_MAC_RESET_DELAY);
1470 writel(0, base + NvRegMacReset);
1471 pci_push(base);
1472 udelay(NV_MAC_RESET_DELAY);
1473
1474 /* restore saved registers */
1475 writel(temp1, base + NvRegMacAddrA);
1476 writel(temp2, base + NvRegMacAddrB);
1477 writel(temp3, base + NvRegTransmitPoll);
1478
1479 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1480 pci_push(base);
1481 }
1482
1483 static void nv_get_hw_stats(struct net_device *dev)
1484 {
1485 struct fe_priv *np = netdev_priv(dev);
1486 u8 __iomem *base = get_hwbase(dev);
1487
1488 np->estats.tx_bytes += readl(base + NvRegTxCnt);
1489 np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1490 np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1491 np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1492 np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1493 np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1494 np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1495 np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1496 np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1497 np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1498 np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1499 np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1500 np->estats.rx_runt += readl(base + NvRegRxRunt);
1501 np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1502 np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1503 np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1504 np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1505 np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1506 np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1507 np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1508 np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1509 np->estats.rx_packets =
1510 np->estats.rx_unicast +
1511 np->estats.rx_multicast +
1512 np->estats.rx_broadcast;
1513 np->estats.rx_errors_total =
1514 np->estats.rx_crc_errors +
1515 np->estats.rx_over_errors +
1516 np->estats.rx_frame_error +
1517 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1518 np->estats.rx_late_collision +
1519 np->estats.rx_runt +
1520 np->estats.rx_frame_too_long;
1521 np->estats.tx_errors_total =
1522 np->estats.tx_late_collision +
1523 np->estats.tx_fifo_errors +
1524 np->estats.tx_carrier_errors +
1525 np->estats.tx_excess_deferral +
1526 np->estats.tx_retry_error;
1527
1528 if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1529 np->estats.tx_deferral += readl(base + NvRegTxDef);
1530 np->estats.tx_packets += readl(base + NvRegTxFrame);
1531 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1532 np->estats.tx_pause += readl(base + NvRegTxPause);
1533 np->estats.rx_pause += readl(base + NvRegRxPause);
1534 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1535 }
1536 }
1537
1538 /*
1539 * nv_get_stats: dev->get_stats function
1540 * Get latest stats value from the nic.
1541 * Called with read_lock(&dev_base_lock) held for read -
1542 * only synchronized against unregister_netdevice.
1543 */
1544 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1545 {
1546 struct fe_priv *np = netdev_priv(dev);
1547
1548 /* If the nic supports hw counters then retrieve latest values */
1549 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2)) {
1550 nv_get_hw_stats(dev);
1551
1552 /* copy to net_device stats */
1553 dev->stats.tx_bytes = np->estats.tx_bytes;
1554 dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
1555 dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
1556 dev->stats.rx_crc_errors = np->estats.rx_crc_errors;
1557 dev->stats.rx_over_errors = np->estats.rx_over_errors;
1558 dev->stats.rx_errors = np->estats.rx_errors_total;
1559 dev->stats.tx_errors = np->estats.tx_errors_total;
1560 }
1561
1562 return &dev->stats;
1563 }
1564
1565 /*
1566 * nv_alloc_rx: fill rx ring entries.
1567 * Return 1 if the allocations for the skbs failed and the
1568 * rx engine is without Available descriptors
1569 */
1570 static int nv_alloc_rx(struct net_device *dev)
1571 {
1572 struct fe_priv *np = netdev_priv(dev);
1573 struct ring_desc* less_rx;
1574
1575 less_rx = np->get_rx.orig;
1576 if (less_rx-- == np->first_rx.orig)
1577 less_rx = np->last_rx.orig;
1578
1579 while (np->put_rx.orig != less_rx) {
1580 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1581 if (skb) {
1582 np->put_rx_ctx->skb = skb;
1583 np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1584 skb->data,
1585 skb_tailroom(skb),
1586 PCI_DMA_FROMDEVICE);
1587 np->put_rx_ctx->dma_len = skb_tailroom(skb);
1588 np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1589 wmb();
1590 np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1591 if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1592 np->put_rx.orig = np->first_rx.orig;
1593 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1594 np->put_rx_ctx = np->first_rx_ctx;
1595 } else {
1596 return 1;
1597 }
1598 }
1599 return 0;
1600 }
1601
1602 static int nv_alloc_rx_optimized(struct net_device *dev)
1603 {
1604 struct fe_priv *np = netdev_priv(dev);
1605 struct ring_desc_ex* less_rx;
1606
1607 less_rx = np->get_rx.ex;
1608 if (less_rx-- == np->first_rx.ex)
1609 less_rx = np->last_rx.ex;
1610
1611 while (np->put_rx.ex != less_rx) {
1612 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1613 if (skb) {
1614 np->put_rx_ctx->skb = skb;
1615 np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1616 skb->data,
1617 skb_tailroom(skb),
1618 PCI_DMA_FROMDEVICE);
1619 np->put_rx_ctx->dma_len = skb_tailroom(skb);
1620 np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1621 np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
1622 wmb();
1623 np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1624 if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1625 np->put_rx.ex = np->first_rx.ex;
1626 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1627 np->put_rx_ctx = np->first_rx_ctx;
1628 } else {
1629 return 1;
1630 }
1631 }
1632 return 0;
1633 }
1634
1635 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1636 #ifdef CONFIG_FORCEDETH_NAPI
1637 static void nv_do_rx_refill(unsigned long data)
1638 {
1639 struct net_device *dev = (struct net_device *) data;
1640 struct fe_priv *np = netdev_priv(dev);
1641
1642 /* Just reschedule NAPI rx processing */
1643 netif_rx_schedule(dev, &np->napi);
1644 }
1645 #else
1646 static void nv_do_rx_refill(unsigned long data)
1647 {
1648 struct net_device *dev = (struct net_device *) data;
1649 struct fe_priv *np = netdev_priv(dev);
1650 int retcode;
1651
1652 if (!using_multi_irqs(dev)) {
1653 if (np->msi_flags & NV_MSI_X_ENABLED)
1654 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1655 else
1656 disable_irq(np->pci_dev->irq);
1657 } else {
1658 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1659 }
1660 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1661 retcode = nv_alloc_rx(dev);
1662 else
1663 retcode = nv_alloc_rx_optimized(dev);
1664 if (retcode) {
1665 spin_lock_irq(&np->lock);
1666 if (!np->in_shutdown)
1667 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1668 spin_unlock_irq(&np->lock);
1669 }
1670 if (!using_multi_irqs(dev)) {
1671 if (np->msi_flags & NV_MSI_X_ENABLED)
1672 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1673 else
1674 enable_irq(np->pci_dev->irq);
1675 } else {
1676 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1677 }
1678 }
1679 #endif
1680
1681 static void nv_init_rx(struct net_device *dev)
1682 {
1683 struct fe_priv *np = netdev_priv(dev);
1684 int i;
1685 np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1686 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1687 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1688 else
1689 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1690 np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1691 np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1692
1693 for (i = 0; i < np->rx_ring_size; i++) {
1694 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1695 np->rx_ring.orig[i].flaglen = 0;
1696 np->rx_ring.orig[i].buf = 0;
1697 } else {
1698 np->rx_ring.ex[i].flaglen = 0;
1699 np->rx_ring.ex[i].txvlan = 0;
1700 np->rx_ring.ex[i].bufhigh = 0;
1701 np->rx_ring.ex[i].buflow = 0;
1702 }
1703 np->rx_skb[i].skb = NULL;
1704 np->rx_skb[i].dma = 0;
1705 }
1706 }
1707
1708 static void nv_init_tx(struct net_device *dev)
1709 {
1710 struct fe_priv *np = netdev_priv(dev);
1711 int i;
1712 np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1713 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1714 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1715 else
1716 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1717 np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1718 np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1719 np->tx_pkts_in_progress = 0;
1720 np->tx_change_owner = NULL;
1721 np->tx_end_flip = NULL;
1722
1723 for (i = 0; i < np->tx_ring_size; i++) {
1724 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1725 np->tx_ring.orig[i].flaglen = 0;
1726 np->tx_ring.orig[i].buf = 0;
1727 } else {
1728 np->tx_ring.ex[i].flaglen = 0;
1729 np->tx_ring.ex[i].txvlan = 0;
1730 np->tx_ring.ex[i].bufhigh = 0;
1731 np->tx_ring.ex[i].buflow = 0;
1732 }
1733 np->tx_skb[i].skb = NULL;
1734 np->tx_skb[i].dma = 0;
1735 np->tx_skb[i].dma_len = 0;
1736 np->tx_skb[i].first_tx_desc = NULL;
1737 np->tx_skb[i].next_tx_ctx = NULL;
1738 }
1739 }
1740
1741 static int nv_init_ring(struct net_device *dev)
1742 {
1743 struct fe_priv *np = netdev_priv(dev);
1744
1745 nv_init_tx(dev);
1746 nv_init_rx(dev);
1747 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1748 return nv_alloc_rx(dev);
1749 else
1750 return nv_alloc_rx_optimized(dev);
1751 }
1752
1753 static int nv_release_txskb(struct net_device *dev, struct nv_skb_map* tx_skb)
1754 {
1755 struct fe_priv *np = netdev_priv(dev);
1756
1757 if (tx_skb->dma) {
1758 pci_unmap_page(np->pci_dev, tx_skb->dma,
1759 tx_skb->dma_len,
1760 PCI_DMA_TODEVICE);
1761 tx_skb->dma = 0;
1762 }
1763 if (tx_skb->skb) {
1764 dev_kfree_skb_any(tx_skb->skb);
1765 tx_skb->skb = NULL;
1766 return 1;
1767 } else {
1768 return 0;
1769 }
1770 }
1771
1772 static void nv_drain_tx(struct net_device *dev)
1773 {
1774 struct fe_priv *np = netdev_priv(dev);
1775 unsigned int i;
1776
1777 for (i = 0; i < np->tx_ring_size; i++) {
1778 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1779 np->tx_ring.orig[i].flaglen = 0;
1780 np->tx_ring.orig[i].buf = 0;
1781 } else {
1782 np->tx_ring.ex[i].flaglen = 0;
1783 np->tx_ring.ex[i].txvlan = 0;
1784 np->tx_ring.ex[i].bufhigh = 0;
1785 np->tx_ring.ex[i].buflow = 0;
1786 }
1787 if (nv_release_txskb(dev, &np->tx_skb[i]))
1788 dev->stats.tx_dropped++;
1789 np->tx_skb[i].dma = 0;
1790 np->tx_skb[i].dma_len = 0;
1791 np->tx_skb[i].first_tx_desc = NULL;
1792 np->tx_skb[i].next_tx_ctx = NULL;
1793 }
1794 np->tx_pkts_in_progress = 0;
1795 np->tx_change_owner = NULL;
1796 np->tx_end_flip = NULL;
1797 }
1798
1799 static void nv_drain_rx(struct net_device *dev)
1800 {
1801 struct fe_priv *np = netdev_priv(dev);
1802 int i;
1803
1804 for (i = 0; i < np->rx_ring_size; i++) {
1805 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1806 np->rx_ring.orig[i].flaglen = 0;
1807 np->rx_ring.orig[i].buf = 0;
1808 } else {
1809 np->rx_ring.ex[i].flaglen = 0;
1810 np->rx_ring.ex[i].txvlan = 0;
1811 np->rx_ring.ex[i].bufhigh = 0;
1812 np->rx_ring.ex[i].buflow = 0;
1813 }
1814 wmb();
1815 if (np->rx_skb[i].skb) {
1816 pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
1817 (skb_end_pointer(np->rx_skb[i].skb) -
1818 np->rx_skb[i].skb->data),
1819 PCI_DMA_FROMDEVICE);
1820 dev_kfree_skb(np->rx_skb[i].skb);
1821 np->rx_skb[i].skb = NULL;
1822 }
1823 }
1824 }
1825
1826 static void drain_ring(struct net_device *dev)
1827 {
1828 nv_drain_tx(dev);
1829 nv_drain_rx(dev);
1830 }
1831
1832 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
1833 {
1834 return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
1835 }
1836
1837 /*
1838 * nv_start_xmit: dev->hard_start_xmit function
1839 * Called with netif_tx_lock held.
1840 */
1841 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1842 {
1843 struct fe_priv *np = netdev_priv(dev);
1844 u32 tx_flags = 0;
1845 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
1846 unsigned int fragments = skb_shinfo(skb)->nr_frags;
1847 unsigned int i;
1848 u32 offset = 0;
1849 u32 bcnt;
1850 u32 size = skb->len-skb->data_len;
1851 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1852 u32 empty_slots;
1853 struct ring_desc* put_tx;
1854 struct ring_desc* start_tx;
1855 struct ring_desc* prev_tx;
1856 struct nv_skb_map* prev_tx_ctx;
1857 unsigned long flags;
1858
1859 /* add fragments to entries count */
1860 for (i = 0; i < fragments; i++) {
1861 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1862 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1863 }
1864
1865 empty_slots = nv_get_empty_tx_slots(np);
1866 if (unlikely(empty_slots <= entries)) {
1867 spin_lock_irqsave(&np->lock, flags);
1868 netif_stop_queue(dev);
1869 np->tx_stop = 1;
1870 spin_unlock_irqrestore(&np->lock, flags);
1871 return NETDEV_TX_BUSY;
1872 }
1873
1874 start_tx = put_tx = np->put_tx.orig;
1875
1876 /* setup the header buffer */
1877 do {
1878 prev_tx = put_tx;
1879 prev_tx_ctx = np->put_tx_ctx;
1880 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1881 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1882 PCI_DMA_TODEVICE);
1883 np->put_tx_ctx->dma_len = bcnt;
1884 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
1885 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1886
1887 tx_flags = np->tx_flags;
1888 offset += bcnt;
1889 size -= bcnt;
1890 if (unlikely(put_tx++ == np->last_tx.orig))
1891 put_tx = np->first_tx.orig;
1892 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
1893 np->put_tx_ctx = np->first_tx_ctx;
1894 } while (size);
1895
1896 /* setup the fragments */
1897 for (i = 0; i < fragments; i++) {
1898 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1899 u32 size = frag->size;
1900 offset = 0;
1901
1902 do {
1903 prev_tx = put_tx;
1904 prev_tx_ctx = np->put_tx_ctx;
1905 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1906 np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
1907 PCI_DMA_TODEVICE);
1908 np->put_tx_ctx->dma_len = bcnt;
1909 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
1910 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1911
1912 offset += bcnt;
1913 size -= bcnt;
1914 if (unlikely(put_tx++ == np->last_tx.orig))
1915 put_tx = np->first_tx.orig;
1916 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
1917 np->put_tx_ctx = np->first_tx_ctx;
1918 } while (size);
1919 }
1920
1921 /* set last fragment flag */
1922 prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
1923
1924 /* save skb in this slot's context area */
1925 prev_tx_ctx->skb = skb;
1926
1927 if (skb_is_gso(skb))
1928 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
1929 else
1930 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
1931 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
1932
1933 spin_lock_irqsave(&np->lock, flags);
1934
1935 /* set tx flags */
1936 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
1937 np->put_tx.orig = put_tx;
1938
1939 spin_unlock_irqrestore(&np->lock, flags);
1940
1941 dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
1942 dev->name, entries, tx_flags_extra);
1943 {
1944 int j;
1945 for (j=0; j<64; j++) {
1946 if ((j%16) == 0)
1947 dprintk("\n%03x:", j);
1948 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1949 }
1950 dprintk("\n");
1951 }
1952
1953 dev->trans_start = jiffies;
1954 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1955 return NETDEV_TX_OK;
1956 }
1957
1958 static int nv_start_xmit_optimized(struct sk_buff *skb, struct net_device *dev)
1959 {
1960 struct fe_priv *np = netdev_priv(dev);
1961 u32 tx_flags = 0;
1962 u32 tx_flags_extra;
1963 unsigned int fragments = skb_shinfo(skb)->nr_frags;
1964 unsigned int i;
1965 u32 offset = 0;
1966 u32 bcnt;
1967 u32 size = skb->len-skb->data_len;
1968 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1969 u32 empty_slots;
1970 struct ring_desc_ex* put_tx;
1971 struct ring_desc_ex* start_tx;
1972 struct ring_desc_ex* prev_tx;
1973 struct nv_skb_map* prev_tx_ctx;
1974 struct nv_skb_map* start_tx_ctx;
1975 unsigned long flags;
1976
1977 /* add fragments to entries count */
1978 for (i = 0; i < fragments; i++) {
1979 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1980 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1981 }
1982
1983 empty_slots = nv_get_empty_tx_slots(np);
1984 if (unlikely(empty_slots <= entries)) {
1985 spin_lock_irqsave(&np->lock, flags);
1986 netif_stop_queue(dev);
1987 np->tx_stop = 1;
1988 spin_unlock_irqrestore(&np->lock, flags);
1989 return NETDEV_TX_BUSY;
1990 }
1991
1992 start_tx = put_tx = np->put_tx.ex;
1993 start_tx_ctx = np->put_tx_ctx;
1994
1995 /* setup the header buffer */
1996 do {
1997 prev_tx = put_tx;
1998 prev_tx_ctx = np->put_tx_ctx;
1999 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2000 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2001 PCI_DMA_TODEVICE);
2002 np->put_tx_ctx->dma_len = bcnt;
2003 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2004 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2005 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2006
2007 tx_flags = NV_TX2_VALID;
2008 offset += bcnt;
2009 size -= bcnt;
2010 if (unlikely(put_tx++ == np->last_tx.ex))
2011 put_tx = np->first_tx.ex;
2012 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2013 np->put_tx_ctx = np->first_tx_ctx;
2014 } while (size);
2015
2016 /* setup the fragments */
2017 for (i = 0; i < fragments; i++) {
2018 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2019 u32 size = frag->size;
2020 offset = 0;
2021
2022 do {
2023 prev_tx = put_tx;
2024 prev_tx_ctx = np->put_tx_ctx;
2025 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2026 np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2027 PCI_DMA_TODEVICE);
2028 np->put_tx_ctx->dma_len = bcnt;
2029 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2030 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2031 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2032
2033 offset += bcnt;
2034 size -= bcnt;
2035 if (unlikely(put_tx++ == np->last_tx.ex))
2036 put_tx = np->first_tx.ex;
2037 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2038 np->put_tx_ctx = np->first_tx_ctx;
2039 } while (size);
2040 }
2041
2042 /* set last fragment flag */
2043 prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
2044
2045 /* save skb in this slot's context area */
2046 prev_tx_ctx->skb = skb;
2047
2048 if (skb_is_gso(skb))
2049 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2050 else
2051 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2052 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2053
2054 /* vlan tag */
2055 if (likely(!np->vlangrp)) {
2056 start_tx->txvlan = 0;
2057 } else {
2058 if (vlan_tx_tag_present(skb))
2059 start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb));
2060 else
2061 start_tx->txvlan = 0;
2062 }
2063
2064 spin_lock_irqsave(&np->lock, flags);
2065
2066 if (np->tx_limit) {
2067 /* Limit the number of outstanding tx. Setup all fragments, but
2068 * do not set the VALID bit on the first descriptor. Save a pointer
2069 * to that descriptor and also for next skb_map element.
2070 */
2071
2072 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2073 if (!np->tx_change_owner)
2074 np->tx_change_owner = start_tx_ctx;
2075
2076 /* remove VALID bit */
2077 tx_flags &= ~NV_TX2_VALID;
2078 start_tx_ctx->first_tx_desc = start_tx;
2079 start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2080 np->tx_end_flip = np->put_tx_ctx;
2081 } else {
2082 np->tx_pkts_in_progress++;
2083 }
2084 }
2085
2086 /* set tx flags */
2087 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2088 np->put_tx.ex = put_tx;
2089
2090 spin_unlock_irqrestore(&np->lock, flags);
2091
2092 dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n",
2093 dev->name, entries, tx_flags_extra);
2094 {
2095 int j;
2096 for (j=0; j<64; j++) {
2097 if ((j%16) == 0)
2098 dprintk("\n%03x:", j);
2099 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2100 }
2101 dprintk("\n");
2102 }
2103
2104 dev->trans_start = jiffies;
2105 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2106 return NETDEV_TX_OK;
2107 }
2108
2109 static inline void nv_tx_flip_ownership(struct net_device *dev)
2110 {
2111 struct fe_priv *np = netdev_priv(dev);
2112
2113 np->tx_pkts_in_progress--;
2114 if (np->tx_change_owner) {
2115 np->tx_change_owner->first_tx_desc->flaglen |=
2116 cpu_to_le32(NV_TX2_VALID);
2117 np->tx_pkts_in_progress++;
2118
2119 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2120 if (np->tx_change_owner == np->tx_end_flip)
2121 np->tx_change_owner = NULL;
2122
2123 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2124 }
2125 }
2126
2127 /*
2128 * nv_tx_done: check for completed packets, release the skbs.
2129 *
2130 * Caller must own np->lock.
2131 */
2132 static void nv_tx_done(struct net_device *dev)
2133 {
2134 struct fe_priv *np = netdev_priv(dev);
2135 u32 flags;
2136 struct ring_desc* orig_get_tx = np->get_tx.orig;
2137
2138 while ((np->get_tx.orig != np->put_tx.orig) &&
2139 !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID)) {
2140
2141 dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n",
2142 dev->name, flags);
2143
2144 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
2145 np->get_tx_ctx->dma_len,
2146 PCI_DMA_TODEVICE);
2147 np->get_tx_ctx->dma = 0;
2148
2149 if (np->desc_ver == DESC_VER_1) {
2150 if (flags & NV_TX_LASTPACKET) {
2151 if (flags & NV_TX_ERROR) {
2152 if (flags & NV_TX_UNDERFLOW)
2153 dev->stats.tx_fifo_errors++;
2154 if (flags & NV_TX_CARRIERLOST)
2155 dev->stats.tx_carrier_errors++;
2156 dev->stats.tx_errors++;
2157 } else {
2158 dev->stats.tx_packets++;
2159 dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2160 }
2161 dev_kfree_skb_any(np->get_tx_ctx->skb);
2162 np->get_tx_ctx->skb = NULL;
2163 }
2164 } else {
2165 if (flags & NV_TX2_LASTPACKET) {
2166 if (flags & NV_TX2_ERROR) {
2167 if (flags & NV_TX2_UNDERFLOW)
2168 dev->stats.tx_fifo_errors++;
2169 if (flags & NV_TX2_CARRIERLOST)
2170 dev->stats.tx_carrier_errors++;
2171 dev->stats.tx_errors++;
2172 } else {
2173 dev->stats.tx_packets++;
2174 dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2175 }
2176 dev_kfree_skb_any(np->get_tx_ctx->skb);
2177 np->get_tx_ctx->skb = NULL;
2178 }
2179 }
2180 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
2181 np->get_tx.orig = np->first_tx.orig;
2182 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2183 np->get_tx_ctx = np->first_tx_ctx;
2184 }
2185 if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
2186 np->tx_stop = 0;
2187 netif_wake_queue(dev);
2188 }
2189 }
2190
2191 static void nv_tx_done_optimized(struct net_device *dev, int limit)
2192 {
2193 struct fe_priv *np = netdev_priv(dev);
2194 u32 flags;
2195 struct ring_desc_ex* orig_get_tx = np->get_tx.ex;
2196
2197 while ((np->get_tx.ex != np->put_tx.ex) &&
2198 !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX_VALID) &&
2199 (limit-- > 0)) {
2200
2201 dprintk(KERN_DEBUG "%s: nv_tx_done_optimized: flags 0x%x.\n",
2202 dev->name, flags);
2203
2204 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
2205 np->get_tx_ctx->dma_len,
2206 PCI_DMA_TODEVICE);
2207 np->get_tx_ctx->dma = 0;
2208
2209 if (flags & NV_TX2_LASTPACKET) {
2210 if (!(flags & NV_TX2_ERROR))
2211 dev->stats.tx_packets++;
2212 dev_kfree_skb_any(np->get_tx_ctx->skb);
2213 np->get_tx_ctx->skb = NULL;
2214
2215 if (np->tx_limit) {
2216 nv_tx_flip_ownership(dev);
2217 }
2218 }
2219 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
2220 np->get_tx.ex = np->first_tx.ex;
2221 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2222 np->get_tx_ctx = np->first_tx_ctx;
2223 }
2224 if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
2225 np->tx_stop = 0;
2226 netif_wake_queue(dev);
2227 }
2228 }
2229
2230 /*
2231 * nv_tx_timeout: dev->tx_timeout function
2232 * Called with netif_tx_lock held.
2233 */
2234 static void nv_tx_timeout(struct net_device *dev)
2235 {
2236 struct fe_priv *np = netdev_priv(dev);
2237 u8 __iomem *base = get_hwbase(dev);
2238 u32 status;
2239
2240 if (np->msi_flags & NV_MSI_X_ENABLED)
2241 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2242 else
2243 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2244
2245 printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
2246
2247 {
2248 int i;
2249
2250 printk(KERN_INFO "%s: Ring at %lx\n",
2251 dev->name, (unsigned long)np->ring_addr);
2252 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
2253 for (i=0;i<=np->register_size;i+= 32) {
2254 printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2255 i,
2256 readl(base + i + 0), readl(base + i + 4),
2257 readl(base + i + 8), readl(base + i + 12),
2258 readl(base + i + 16), readl(base + i + 20),
2259 readl(base + i + 24), readl(base + i + 28));
2260 }
2261 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
2262 for (i=0;i<np->tx_ring_size;i+= 4) {
2263 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
2264 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
2265 i,
2266 le32_to_cpu(np->tx_ring.orig[i].buf),
2267 le32_to_cpu(np->tx_ring.orig[i].flaglen),
2268 le32_to_cpu(np->tx_ring.orig[i+1].buf),
2269 le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2270 le32_to_cpu(np->tx_ring.orig[i+2].buf),
2271 le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2272 le32_to_cpu(np->tx_ring.orig[i+3].buf),
2273 le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2274 } else {
2275 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
2276 i,
2277 le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2278 le32_to_cpu(np->tx_ring.ex[i].buflow),
2279 le32_to_cpu(np->tx_ring.ex[i].flaglen),
2280 le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2281 le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2282 le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2283 le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2284 le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2285 le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2286 le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2287 le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2288 le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2289 }
2290 }
2291 }
2292
2293 spin_lock_irq(&np->lock);
2294
2295 /* 1) stop tx engine */
2296 nv_stop_tx(dev);
2297
2298 /* 2) check that the packets were not sent already: */
2299 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
2300 nv_tx_done(dev);
2301 else
2302 nv_tx_done_optimized(dev, np->tx_ring_size);
2303
2304 /* 3) if there are dead entries: clear everything */
2305 if (np->get_tx_ctx != np->put_tx_ctx) {
2306 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
2307 nv_drain_tx(dev);
2308 nv_init_tx(dev);
2309 setup_hw_rings(dev, NV_SETUP_TX_RING);
2310 }
2311
2312 netif_wake_queue(dev);
2313
2314 /* 4) restart tx engine */
2315 nv_start_tx(dev);
2316 spin_unlock_irq(&np->lock);
2317 }
2318
2319 /*
2320 * Called when the nic notices a mismatch between the actual data len on the
2321 * wire and the len indicated in the 802 header
2322 */
2323 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2324 {
2325 int hdrlen; /* length of the 802 header */
2326 int protolen; /* length as stored in the proto field */
2327
2328 /* 1) calculate len according to header */
2329 if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2330 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
2331 hdrlen = VLAN_HLEN;
2332 } else {
2333 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
2334 hdrlen = ETH_HLEN;
2335 }
2336 dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
2337 dev->name, datalen, protolen, hdrlen);
2338 if (protolen > ETH_DATA_LEN)
2339 return datalen; /* Value in proto field not a len, no checks possible */
2340
2341 protolen += hdrlen;
2342 /* consistency checks: */
2343 if (datalen > ETH_ZLEN) {
2344 if (datalen >= protolen) {
2345 /* more data on wire than in 802 header, trim of
2346 * additional data.
2347 */
2348 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2349 dev->name, protolen);
2350 return protolen;
2351 } else {
2352 /* less data on wire than mentioned in header.
2353 * Discard the packet.
2354 */
2355 dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
2356 dev->name);
2357 return -1;
2358 }
2359 } else {
2360 /* short packet. Accept only if 802 values are also short */
2361 if (protolen > ETH_ZLEN) {
2362 dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
2363 dev->name);
2364 return -1;
2365 }
2366 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2367 dev->name, datalen);
2368 return datalen;
2369 }
2370 }
2371
2372 static int nv_rx_process(struct net_device *dev, int limit)
2373 {
2374 struct fe_priv *np = netdev_priv(dev);
2375 u32 flags;
2376 int rx_work = 0;
2377 struct sk_buff *skb;
2378 int len;
2379
2380 while((np->get_rx.orig != np->put_rx.orig) &&
2381 !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2382 (rx_work < limit)) {
2383
2384 dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n",
2385 dev->name, flags);
2386
2387 /*
2388 * the packet is for us - immediately tear down the pci mapping.
2389 * TODO: check if a prefetch of the first cacheline improves
2390 * the performance.
2391 */
2392 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2393 np->get_rx_ctx->dma_len,
2394 PCI_DMA_FROMDEVICE);
2395 skb = np->get_rx_ctx->skb;
2396 np->get_rx_ctx->skb = NULL;
2397
2398 {
2399 int j;
2400 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2401 for (j=0; j<64; j++) {
2402 if ((j%16) == 0)
2403 dprintk("\n%03x:", j);
2404 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2405 }
2406 dprintk("\n");
2407 }
2408 /* look at what we actually got: */
2409 if (np->desc_ver == DESC_VER_1) {
2410 if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2411 len = flags & LEN_MASK_V1;
2412 if (unlikely(flags & NV_RX_ERROR)) {
2413 if (flags & NV_RX_ERROR4) {
2414 len = nv_getlen(dev, skb->data, len);
2415 if (len < 0) {
2416 dev->stats.rx_errors++;
2417 dev_kfree_skb(skb);
2418 goto next_pkt;
2419 }
2420 }
2421 /* framing errors are soft errors */
2422 else if (flags & NV_RX_FRAMINGERR) {
2423 if (flags & NV_RX_SUBSTRACT1) {
2424 len--;
2425 }
2426 }
2427 /* the rest are hard errors */
2428 else {
2429 if (flags & NV_RX_MISSEDFRAME)
2430 dev->stats.rx_missed_errors++;
2431 if (flags & NV_RX_CRCERR)
2432 dev->stats.rx_crc_errors++;
2433 if (flags & NV_RX_OVERFLOW)
2434 dev->stats.rx_over_errors++;
2435 dev->stats.rx_errors++;
2436 dev_kfree_skb(skb);
2437 goto next_pkt;
2438 }
2439 }
2440 } else {
2441 dev_kfree_skb(skb);
2442 goto next_pkt;
2443 }
2444 } else {
2445 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2446 len = flags & LEN_MASK_V2;
2447 if (unlikely(flags & NV_RX2_ERROR)) {
2448 if (flags & NV_RX2_ERROR4) {
2449 len = nv_getlen(dev, skb->data, len);
2450 if (len < 0) {
2451 dev->stats.rx_errors++;
2452 dev_kfree_skb(skb);
2453 goto next_pkt;
2454 }
2455 }
2456 /* framing errors are soft errors */
2457 else if (flags & NV_RX2_FRAMINGERR) {
2458 if (flags & NV_RX2_SUBSTRACT1) {
2459 len--;
2460 }
2461 }
2462 /* the rest are hard errors */
2463 else {
2464 if (flags & NV_RX2_CRCERR)
2465 dev->stats.rx_crc_errors++;
2466 if (flags & NV_RX2_OVERFLOW)
2467 dev->stats.rx_over_errors++;
2468 dev->stats.rx_errors++;
2469 dev_kfree_skb(skb);
2470 goto next_pkt;
2471 }
2472 }
2473 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2474 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
2475 skb->ip_summed = CHECKSUM_UNNECESSARY;
2476 } else {
2477 dev_kfree_skb(skb);
2478 goto next_pkt;
2479 }
2480 }
2481 /* got a valid packet - forward it to the network core */
2482 skb_put(skb, len);
2483 skb->protocol = eth_type_trans(skb, dev);
2484 dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n",
2485 dev->name, len, skb->protocol);
2486 #ifdef CONFIG_FORCEDETH_NAPI
2487 netif_receive_skb(skb);
2488 #else
2489 netif_rx(skb);
2490 #endif
2491 dev->last_rx = jiffies;
2492 dev->stats.rx_packets++;
2493 dev->stats.rx_bytes += len;
2494 next_pkt:
2495 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2496 np->get_rx.orig = np->first_rx.orig;
2497 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2498 np->get_rx_ctx = np->first_rx_ctx;
2499
2500 rx_work++;
2501 }
2502
2503 return rx_work;
2504 }
2505
2506 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2507 {
2508 struct fe_priv *np = netdev_priv(dev);
2509 u32 flags;
2510 u32 vlanflags = 0;
2511 int rx_work = 0;
2512 struct sk_buff *skb;
2513 int len;
2514
2515 while((np->get_rx.ex != np->put_rx.ex) &&
2516 !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2517 (rx_work < limit)) {
2518
2519 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: flags 0x%x.\n",
2520 dev->name, flags);
2521
2522 /*
2523 * the packet is for us - immediately tear down the pci mapping.
2524 * TODO: check if a prefetch of the first cacheline improves
2525 * the performance.
2526 */
2527 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2528 np->get_rx_ctx->dma_len,
2529 PCI_DMA_FROMDEVICE);
2530 skb = np->get_rx_ctx->skb;
2531 np->get_rx_ctx->skb = NULL;
2532
2533 {
2534 int j;
2535 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2536 for (j=0; j<64; j++) {
2537 if ((j%16) == 0)
2538 dprintk("\n%03x:", j);
2539 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2540 }
2541 dprintk("\n");
2542 }
2543 /* look at what we actually got: */
2544 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2545 len = flags & LEN_MASK_V2;
2546 if (unlikely(flags & NV_RX2_ERROR)) {
2547 if (flags & NV_RX2_ERROR4) {
2548 len = nv_getlen(dev, skb->data, len);
2549 if (len < 0) {
2550 dev_kfree_skb(skb);
2551 goto next_pkt;
2552 }
2553 }
2554 /* framing errors are soft errors */
2555 else if (flags & NV_RX2_FRAMINGERR) {
2556 if (flags & NV_RX2_SUBSTRACT1) {
2557 len--;
2558 }
2559 }
2560 /* the rest are hard errors */
2561 else {
2562 dev_kfree_skb(skb);
2563 goto next_pkt;
2564 }
2565 }
2566
2567 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2568 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
2569 skb->ip_summed = CHECKSUM_UNNECESSARY;
2570
2571 /* got a valid packet - forward it to the network core */
2572 skb_put(skb, len);
2573 skb->protocol = eth_type_trans(skb, dev);
2574 prefetch(skb->data);
2575
2576 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n",
2577 dev->name, len, skb->protocol);
2578
2579 if (likely(!np->vlangrp)) {
2580 #ifdef CONFIG_FORCEDETH_NAPI
2581 netif_receive_skb(skb);
2582 #else
2583 netif_rx(skb);
2584 #endif
2585 } else {
2586 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2587 if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2588 #ifdef CONFIG_FORCEDETH_NAPI
2589 vlan_hwaccel_receive_skb(skb, np->vlangrp,
2590 vlanflags & NV_RX3_VLAN_TAG_MASK);
2591 #else
2592 vlan_hwaccel_rx(skb, np->vlangrp,
2593 vlanflags & NV_RX3_VLAN_TAG_MASK);
2594 #endif
2595 } else {
2596 #ifdef CONFIG_FORCEDETH_NAPI
2597 netif_receive_skb(skb);
2598 #else
2599 netif_rx(skb);
2600 #endif
2601 }
2602 }
2603
2604 dev->last_rx = jiffies;
2605 dev->stats.rx_packets++;
2606 dev->stats.rx_bytes += len;
2607 } else {
2608 dev_kfree_skb(skb);
2609 }
2610 next_pkt:
2611 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
2612 np->get_rx.ex = np->first_rx.ex;
2613 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2614 np->get_rx_ctx = np->first_rx_ctx;
2615
2616 rx_work++;
2617 }
2618
2619 return rx_work;
2620 }
2621
2622 static void set_bufsize(struct net_device *dev)
2623 {
2624 struct fe_priv *np = netdev_priv(dev);
2625
2626 if (dev->mtu <= ETH_DATA_LEN)
2627 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2628 else
2629 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2630 }
2631
2632 /*
2633 * nv_change_mtu: dev->change_mtu function
2634 * Called with dev_base_lock held for read.
2635 */
2636 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2637 {
2638 struct fe_priv *np = netdev_priv(dev);
2639 int old_mtu;
2640
2641 if (new_mtu < 64 || new_mtu > np->pkt_limit)
2642 return -EINVAL;
2643
2644 old_mtu = dev->mtu;
2645 dev->mtu = new_mtu;
2646
2647 /* return early if the buffer sizes will not change */
2648 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2649 return 0;
2650 if (old_mtu == new_mtu)
2651 return 0;
2652
2653 /* synchronized against open : rtnl_lock() held by caller */
2654 if (netif_running(dev)) {
2655 u8 __iomem *base = get_hwbase(dev);
2656 /*
2657 * It seems that the nic preloads valid ring entries into an
2658 * internal buffer. The procedure for flushing everything is
2659 * guessed, there is probably a simpler approach.
2660 * Changing the MTU is a rare event, it shouldn't matter.
2661 */
2662 nv_disable_irq(dev);
2663 netif_tx_lock_bh(dev);
2664 spin_lock(&np->lock);
2665 /* stop engines */
2666 nv_stop_rx(dev);
2667 nv_stop_tx(dev);
2668 nv_txrx_reset(dev);
2669 /* drain rx queue */
2670 nv_drain_rx(dev);
2671 nv_drain_tx(dev);
2672 /* reinit driver view of the rx queue */
2673 set_bufsize(dev);
2674 if (nv_init_ring(dev)) {
2675 if (!np->in_shutdown)
2676 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2677 }
2678 /* reinit nic view of the rx queue */
2679 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2680 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2681 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2682 base + NvRegRingSizes);
2683 pci_push(base);
2684 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2685 pci_push(base);
2686
2687 /* restart rx engine */
2688 nv_start_rx(dev);
2689 nv_start_tx(dev);
2690 spin_unlock(&np->lock);
2691 netif_tx_unlock_bh(dev);
2692 nv_enable_irq(dev);
2693 }
2694 return 0;
2695 }
2696
2697 static void nv_copy_mac_to_hw(struct net_device *dev)
2698 {
2699 u8 __iomem *base = get_hwbase(dev);
2700 u32 mac[2];
2701
2702 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2703 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2704 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2705
2706 writel(mac[0], base + NvRegMacAddrA);
2707 writel(mac[1], base + NvRegMacAddrB);
2708 }
2709
2710 /*
2711 * nv_set_mac_address: dev->set_mac_address function
2712 * Called with rtnl_lock() held.
2713 */
2714 static int nv_set_mac_address(struct net_device *dev, void *addr)
2715 {
2716 struct fe_priv *np = netdev_priv(dev);
2717 struct sockaddr *macaddr = (struct sockaddr*)addr;
2718
2719 if (!is_valid_ether_addr(macaddr->sa_data))
2720 return -EADDRNOTAVAIL;
2721
2722 /* synchronized against open : rtnl_lock() held by caller */
2723 memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2724
2725 if (netif_running(dev)) {
2726 netif_tx_lock_bh(dev);
2727 spin_lock_irq(&np->lock);
2728
2729 /* stop rx engine */
2730 nv_stop_rx(dev);
2731
2732 /* set mac address */
2733 nv_copy_mac_to_hw(dev);
2734
2735 /* restart rx engine */
2736 nv_start_rx(dev);
2737 spin_unlock_irq(&np->lock);
2738 netif_tx_unlock_bh(dev);
2739 } else {
2740 nv_copy_mac_to_hw(dev);
2741 }
2742 return 0;
2743 }
2744
2745 /*
2746 * nv_set_multicast: dev->set_multicast function
2747 * Called with netif_tx_lock held.
2748 */
2749 static void nv_set_multicast(struct net_device *dev)
2750 {
2751 struct fe_priv *np = netdev_priv(dev);
2752 u8 __iomem *base = get_hwbase(dev);
2753 u32 addr[2];
2754 u32 mask[2];
2755 u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
2756
2757 memset(addr, 0, sizeof(addr));
2758 memset(mask, 0, sizeof(mask));
2759
2760 if (dev->flags & IFF_PROMISC) {
2761 pff |= NVREG_PFF_PROMISC;
2762 } else {
2763 pff |= NVREG_PFF_MYADDR;
2764
2765 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
2766 u32 alwaysOff[2];
2767 u32 alwaysOn[2];
2768
2769 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
2770 if (dev->flags & IFF_ALLMULTI) {
2771 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
2772 } else {
2773 struct dev_mc_list *walk;
2774
2775 walk = dev->mc_list;
2776 while (walk != NULL) {
2777 u32 a, b;
2778 a = le32_to_cpu(*(__le32 *) walk->dmi_addr);
2779 b = le16_to_cpu(*(__le16 *) (&walk->dmi_addr[4]));
2780 alwaysOn[0] &= a;
2781 alwaysOff[0] &= ~a;
2782 alwaysOn[1] &= b;
2783 alwaysOff[1] &= ~b;
2784 walk = walk->next;
2785 }
2786 }
2787 addr[0] = alwaysOn[0];
2788 addr[1] = alwaysOn[1];
2789 mask[0] = alwaysOn[0] | alwaysOff[0];
2790 mask[1] = alwaysOn[1] | alwaysOff[1];
2791 } else {
2792 mask[0] = NVREG_MCASTMASKA_NONE;
2793 mask[1] = NVREG_MCASTMASKB_NONE;
2794 }
2795 }
2796 addr[0] |= NVREG_MCASTADDRA_FORCE;
2797 pff |= NVREG_PFF_ALWAYS;
2798 spin_lock_irq(&np->lock);
2799 nv_stop_rx(dev);
2800 writel(addr[0], base + NvRegMulticastAddrA);
2801 writel(addr[1], base + NvRegMulticastAddrB);
2802 writel(mask[0], base + NvRegMulticastMaskA);
2803 writel(mask[1], base + NvRegMulticastMaskB);
2804 writel(pff, base + NvRegPacketFilterFlags);
2805 dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
2806 dev->name);
2807 nv_start_rx(dev);
2808 spin_unlock_irq(&np->lock);
2809 }
2810
2811 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
2812 {
2813 struct fe_priv *np = netdev_priv(dev);
2814 u8 __iomem *base = get_hwbase(dev);
2815
2816 np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
2817
2818 if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
2819 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
2820 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
2821 writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
2822 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2823 } else {
2824 writel(pff, base + NvRegPacketFilterFlags);
2825 }
2826 }
2827 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
2828 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
2829 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
2830 u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
2831 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
2832 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
2833 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)
2834 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
2835 writel(pause_enable, base + NvRegTxPauseFrame);
2836 writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
2837 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2838 } else {
2839 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
2840 writel(regmisc, base + NvRegMisc1);
2841 }
2842 }
2843 }
2844
2845 /**
2846 * nv_update_linkspeed: Setup the MAC according to the link partner
2847 * @dev: Network device to be configured
2848 *
2849 * The function queries the PHY and checks if there is a link partner.
2850 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
2851 * set to 10 MBit HD.
2852 *
2853 * The function returns 0 if there is no link partner and 1 if there is
2854 * a good link partner.
2855 */
2856 static int nv_update_linkspeed(struct net_device *dev)
2857 {
2858 struct fe_priv *np = netdev_priv(dev);
2859 u8 __iomem *base = get_hwbase(dev);
2860 int adv = 0;
2861 int lpa = 0;
2862 int adv_lpa, adv_pause, lpa_pause;
2863 int newls = np->linkspeed;
2864 int newdup = np->duplex;
2865 int mii_status;
2866 int retval = 0;
2867 u32 control_1000, status_1000, phyreg, pause_flags, txreg;
2868 u32 txrxFlags = 0;
2869 u32 phy_exp;
2870
2871 /* BMSR_LSTATUS is latched, read it twice:
2872 * we want the current value.
2873 */
2874 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2875 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2876
2877 if (!(mii_status & BMSR_LSTATUS)) {
2878 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
2879 dev->name);
2880 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2881 newdup = 0;
2882 retval = 0;
2883 goto set_speed;
2884 }
2885
2886 if (np->autoneg == 0) {
2887 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
2888 dev->name, np->fixed_mode);
2889 if (np->fixed_mode & LPA_100FULL) {
2890 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2891 newdup = 1;
2892 } else if (np->fixed_mode & LPA_100HALF) {
2893 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2894 newdup = 0;
2895 } else if (np->fixed_mode & LPA_10FULL) {
2896 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2897 newdup = 1;
2898 } else {
2899 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2900 newdup = 0;
2901 }
2902 retval = 1;
2903 goto set_speed;
2904 }
2905 /* check auto negotiation is complete */
2906 if (!(mii_status & BMSR_ANEGCOMPLETE)) {
2907 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
2908 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2909 newdup = 0;
2910 retval = 0;
2911 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
2912 goto set_speed;
2913 }
2914
2915 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2916 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
2917 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
2918 dev->name, adv, lpa);
2919
2920 retval = 1;
2921 if (np->gigabit == PHY_GIGABIT) {
2922 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
2923 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
2924
2925 if ((control_1000 & ADVERTISE_1000FULL) &&
2926 (status_1000 & LPA_1000FULL)) {
2927 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
2928 dev->name);
2929 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
2930 newdup = 1;
2931 goto set_speed;
2932 }
2933 }
2934
2935 /* FIXME: handle parallel detection properly */
2936 adv_lpa = lpa & adv;
2937 if (adv_lpa & LPA_100FULL) {
2938 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2939 newdup = 1;
2940 } else if (adv_lpa & LPA_100HALF) {
2941 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2942 newdup = 0;
2943 } else if (adv_lpa & LPA_10FULL) {
2944 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2945 newdup = 1;
2946 } else if (adv_lpa & LPA_10HALF) {
2947 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2948 newdup = 0;
2949 } else {
2950 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
2951 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2952 newdup = 0;
2953 }
2954
2955 set_speed:
2956 if (np->duplex == newdup && np->linkspeed == newls)
2957 return retval;
2958
2959 dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
2960 dev->name, np->linkspeed, np->duplex, newls, newdup);
2961
2962 np->duplex = newdup;
2963 np->linkspeed = newls;
2964
2965 /* The transmitter and receiver must be restarted for safe update */
2966 if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
2967 txrxFlags |= NV_RESTART_TX;
2968 nv_stop_tx(dev);
2969 }
2970 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
2971 txrxFlags |= NV_RESTART_RX;
2972 nv_stop_rx(dev);
2973 }
2974
2975 if (np->gigabit == PHY_GIGABIT) {
2976 phyreg = readl(base + NvRegRandomSeed);
2977 phyreg &= ~(0x3FF00);
2978 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
2979 phyreg |= NVREG_RNDSEED_FORCE3;
2980 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
2981 phyreg |= NVREG_RNDSEED_FORCE2;
2982 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
2983 phyreg |= NVREG_RNDSEED_FORCE;
2984 writel(phyreg, base + NvRegRandomSeed);
2985 }
2986
2987 phyreg = readl(base + NvRegPhyInterface);
2988 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
2989 if (np->duplex == 0)
2990 phyreg |= PHY_HALF;
2991 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
2992 phyreg |= PHY_100;
2993 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2994 phyreg |= PHY_1000;
2995 writel(phyreg, base + NvRegPhyInterface);
2996
2997 phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
2998 if (phyreg & PHY_RGMII) {
2999 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
3000 txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3001 } else {
3002 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3003 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3004 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3005 else
3006 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3007 } else {
3008 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3009 }
3010 }
3011 } else {
3012 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3013 txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3014 else
3015 txreg = NVREG_TX_DEFERRAL_DEFAULT;
3016 }
3017 writel(txreg, base + NvRegTxDeferral);
3018
3019 if (np->desc_ver == DESC_VER_1) {
3020 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3021 } else {
3022 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3023 txreg = NVREG_TX_WM_DESC2_3_1000;
3024 else
3025 txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3026 }
3027 writel(txreg, base + NvRegTxWatermark);
3028
3029 writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
3030 base + NvRegMisc1);
3031 pci_push(base);
3032 writel(np->linkspeed, base + NvRegLinkSpeed);
3033 pci_push(base);
3034
3035 pause_flags = 0;
3036 /* setup pause frame */
3037 if (np->duplex != 0) {
3038 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
3039 adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
3040 lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
3041
3042 switch (adv_pause) {
3043 case ADVERTISE_PAUSE_CAP:
3044 if (lpa_pause & LPA_PAUSE_CAP) {
3045 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3046 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3047 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3048 }
3049 break;
3050 case ADVERTISE_PAUSE_ASYM:
3051 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
3052 {
3053 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3054 }
3055 break;
3056 case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
3057 if (lpa_pause & LPA_PAUSE_CAP)
3058 {
3059 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3060 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3061 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3062 }
3063 if (lpa_pause == LPA_PAUSE_ASYM)
3064 {
3065 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3066 }
3067 break;
3068 }
3069 } else {
3070 pause_flags = np->pause_flags;
3071 }
3072 }
3073 nv_update_pause(dev, pause_flags);
3074
3075 if (txrxFlags & NV_RESTART_TX)
3076 nv_start_tx(dev);
3077 if (txrxFlags & NV_RESTART_RX)
3078 nv_start_rx(dev);
3079
3080 return retval;
3081 }
3082
3083 static void nv_linkchange(struct net_device *dev)
3084 {
3085 if (nv_update_linkspeed(dev)) {
3086 if (!netif_carrier_ok(dev)) {
3087 netif_carrier_on(dev);
3088 printk(KERN_INFO "%s: link up.\n", dev->name);
3089 nv_start_rx(dev);
3090 }
3091 } else {
3092 if (netif_carrier_ok(dev)) {
3093 netif_carrier_off(dev);
3094 printk(KERN_INFO "%s: link down.\n", dev->name);
3095 nv_stop_rx(dev);
3096 }
3097 }
3098 }
3099
3100 static void nv_link_irq(struct net_device *dev)
3101 {
3102 u8 __iomem *base = get_hwbase(dev);
3103 u32 miistat;
3104
3105 miistat = readl(base + NvRegMIIStatus);
3106 writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
3107 dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
3108
3109 if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3110 nv_linkchange(dev);
3111 dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
3112 }
3113
3114 static void nv_msi_workaround(struct fe_priv *np)
3115 {
3116
3117 /* Need to toggle the msi irq mask within the ethernet device,
3118 * otherwise, future interrupts will not be detected.
3119 */
3120 if (np->msi_flags & NV_MSI_ENABLED) {
3121 u8 __iomem *base = np->base;
3122
3123 writel(0, base + NvRegMSIIrqMask);
3124 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3125 }
3126 }
3127
3128 static irqreturn_t nv_nic_irq(int foo, void *data)
3129 {
3130 struct net_device *dev = (struct net_device *) data;
3131 struct fe_priv *np = netdev_priv(dev);
3132 u8 __iomem *base = get_hwbase(dev);
3133 u32 events;
3134 int i;
3135
3136 dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
3137
3138 for (i=0; ; i++) {
3139 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3140 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3141 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3142 } else {
3143 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3144 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3145 }
3146 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3147 if (!(events & np->irqmask))
3148 break;
3149
3150 nv_msi_workaround(np);
3151
3152 spin_lock(&np->lock);
3153 nv_tx_done(dev);
3154 spin_unlock(&np->lock);
3155
3156 #ifdef CONFIG_FORCEDETH_NAPI
3157 if (events & NVREG_IRQ_RX_ALL) {
3158 netif_rx_schedule(dev, &np->napi);
3159
3160 /* Disable furthur receive irq's */
3161 spin_lock(&np->lock);
3162 np->irqmask &= ~NVREG_IRQ_RX_ALL;
3163
3164 if (np->msi_flags & NV_MSI_X_ENABLED)
3165 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3166 else
3167 writel(np->irqmask, base + NvRegIrqMask);
3168 spin_unlock(&np->lock);
3169 }
3170 #else
3171 if (nv_rx_process(dev, RX_WORK_PER_LOOP)) {
3172 if (unlikely(nv_alloc_rx(dev))) {
3173 spin_lock(&np->lock);
3174 if (!np->in_shutdown)
3175 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3176 spin_unlock(&np->lock);
3177 }
3178 }
3179 #endif
3180 if (unlikely(events & NVREG_IRQ_LINK)) {
3181 spin_lock(&np->lock);
3182 nv_link_irq(dev);
3183 spin_unlock(&np->lock);
3184 }
3185 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3186 spin_lock(&np->lock);
3187 nv_linkchange(dev);
3188 spin_unlock(&np->lock);
3189 np->link_timeout = jiffies + LINK_TIMEOUT;
3190 }
3191 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3192 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3193 dev->name, events);
3194 }
3195 if (unlikely(events & (NVREG_IRQ_UNKNOWN))) {
3196 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3197 dev->name, events);
3198 }
3199 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
3200 spin_lock(&np->lock);
3201 /* disable interrupts on the nic */
3202 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3203 writel(0, base + NvRegIrqMask);
3204 else
3205 writel(np->irqmask, base + NvRegIrqMask);
3206 pci_push(base);
3207
3208 if (!np->in_shutdown) {
3209 np->nic_poll_irq = np->irqmask;
3210 np->recover_error = 1;
3211 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3212 }
3213 spin_unlock(&np->lock);
3214 break;
3215 }
3216 if (unlikely(i > max_interrupt_work)) {
3217 spin_lock(&np->lock);
3218 /* disable interrupts on the nic */
3219 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3220 writel(0, base + NvRegIrqMask);
3221 else
3222 writel(np->irqmask, base + NvRegIrqMask);
3223 pci_push(base);
3224
3225 if (!np->in_shutdown) {
3226 np->nic_poll_irq = np->irqmask;
3227 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3228 }
3229 spin_unlock(&np->lock);
3230 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
3231 break;
3232 }
3233
3234 }
3235 dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
3236
3237 return IRQ_RETVAL(i);
3238 }
3239
3240 /**
3241 * All _optimized functions are used to help increase performance
3242 * (reduce CPU and increase throughput). They use descripter version 3,
3243 * compiler directives, and reduce memory accesses.
3244 */
3245 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3246 {
3247 struct net_device *dev = (struct net_device *) data;
3248 struct fe_priv *np = netdev_priv(dev);
3249 u8 __iomem *base = get_hwbase(dev);
3250 u32 events;
3251 int i;
3252
3253 dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized\n", dev->name);
3254
3255 for (i=0; ; i++) {
3256 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3257 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3258 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3259 } else {
3260 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3261 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3262 }
3263 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3264 if (!(events & np->irqmask))
3265 break;
3266
3267 nv_msi_workaround(np);
3268
3269 spin_lock(&np->lock);
3270 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3271 spin_unlock(&np->lock);
3272
3273 #ifdef CONFIG_FORCEDETH_NAPI
3274 if (events & NVREG_IRQ_RX_ALL) {
3275 netif_rx_schedule(dev, &np->napi);
3276
3277 /* Disable furthur receive irq's */
3278 spin_lock(&np->lock);
3279 np->irqmask &= ~NVREG_IRQ_RX_ALL;
3280
3281 if (np->msi_flags & NV_MSI_X_ENABLED)
3282 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3283 else
3284 writel(np->irqmask, base + NvRegIrqMask);
3285 spin_unlock(&np->lock);
3286 }
3287 #else
3288 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3289 if (unlikely(nv_alloc_rx_optimized(dev))) {
3290 spin_lock(&np->lock);
3291 if (!np->in_shutdown)
3292 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3293 spin_unlock(&np->lock);
3294 }
3295 }
3296 #endif
3297 if (unlikely(events & NVREG_IRQ_LINK)) {
3298 spin_lock(&np->lock);
3299 nv_link_irq(dev);
3300 spin_unlock(&np->lock);
3301 }
3302 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3303 spin_lock(&np->lock);
3304 nv_linkchange(dev);
3305 spin_unlock(&np->lock);
3306 np->link_timeout = jiffies + LINK_TIMEOUT;
3307 }
3308 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3309 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3310 dev->name, events);
3311 }
3312 if (unlikely(events & (NVREG_IRQ_UNKNOWN))) {
3313 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3314 dev->name, events);
3315 }
3316 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
3317 spin_lock(&np->lock);
3318 /* disable interrupts on the nic */
3319 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3320 writel(0, base + NvRegIrqMask);
3321 else
3322 writel(np->irqmask, base + NvRegIrqMask);
3323 pci_push(base);
3324
3325 if (!np->in_shutdown) {
3326 np->nic_poll_irq = np->irqmask;
3327 np->recover_error = 1;
3328 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3329 }
3330 spin_unlock(&np->lock);
3331 break;
3332 }
3333
3334 if (unlikely(i > max_interrupt_work)) {
3335 spin_lock(&np->lock);
3336 /* disable interrupts on the nic */
3337 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3338 writel(0, base + NvRegIrqMask);
3339 else
3340 writel(np->irqmask, base + NvRegIrqMask);
3341 pci_push(base);
3342
3343 if (!np->in_shutdown) {
3344 np->nic_poll_irq = np->irqmask;
3345 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3346 }
3347 spin_unlock(&np->lock);
3348 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
3349 break;
3350 }
3351
3352 }
3353 dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized completed\n", dev->name);
3354
3355 return IRQ_RETVAL(i);
3356 }
3357
3358 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3359 {
3360 struct net_device *dev = (struct net_device *) data;
3361 struct fe_priv *np = netdev_priv(dev);
3362 u8 __iomem *base = get_hwbase(dev);
3363 u32 events;
3364 int i;
3365 unsigned long flags;
3366
3367 dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
3368
3369 for (i=0; ; i++) {
3370 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3371 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
3372 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
3373 if (!(events & np->irqmask))
3374 break;
3375
3376 spin_lock_irqsave(&np->lock, flags);
3377 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3378 spin_unlock_irqrestore(&np->lock, flags);
3379
3380 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3381 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3382 dev->name, events);
3383 }
3384 if (unlikely(i > max_interrupt_work)) {
3385 spin_lock_irqsave(&np->lock, flags);
3386 /* disable interrupts on the nic */
3387 writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3388 pci_push(base);
3389
3390 if (!np->in_shutdown) {
3391 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3392 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3393 }
3394 spin_unlock_irqrestore(&np->lock, flags);
3395 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
3396 break;
3397 }
3398
3399 }
3400 dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
3401
3402 return IRQ_RETVAL(i);
3403 }
3404
3405 #ifdef CONFIG_FORCEDETH_NAPI
3406 static int nv_napi_poll(struct napi_struct *napi, int budget)
3407 {
3408 struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3409 struct net_device *dev = np->dev;
3410 u8 __iomem *base = get_hwbase(dev);
3411 unsigned long flags;
3412 int pkts, retcode;
3413
3414 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3415 pkts = nv_rx_process(dev, budget);
3416 retcode = nv_alloc_rx(dev);
3417 } else {
3418 pkts = nv_rx_process_optimized(dev, budget);
3419 retcode = nv_alloc_rx_optimized(dev);
3420 }
3421
3422 if (retcode) {
3423 spin_lock_irqsave(&np->lock, flags);
3424 if (!np->in_shutdown)
3425 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3426 spin_unlock_irqrestore(&np->lock, flags);
3427 }
3428
3429 if (pkts < budget) {
3430 /* re-enable receive interrupts */
3431 spin_lock_irqsave(&np->lock, flags);
3432
3433 __netif_rx_complete(dev, napi);
3434
3435 np->irqmask |= NVREG_IRQ_RX_ALL;
3436 if (np->msi_flags & NV_MSI_X_ENABLED)
3437 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3438 else
3439 writel(np->irqmask, base + NvRegIrqMask);
3440
3441 spin_unlock_irqrestore(&np->lock, flags);
3442 }
3443 return pkts;
3444 }
3445 #endif
3446
3447 #ifdef CONFIG_FORCEDETH_NAPI
3448 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3449 {
3450 struct net_device *dev = (struct net_device *) data;
3451 struct fe_priv *np = netdev_priv(dev);
3452 u8 __iomem *base = get_hwbase(dev);
3453 u32 events;
3454
3455 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3456 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3457
3458 if (events) {
3459 netif_rx_schedule(dev, &np->napi);
3460 /* disable receive interrupts on the nic */
3461 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3462 pci_push(base);
3463 }
3464 return IRQ_HANDLED;
3465 }
3466 #else
3467 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3468 {
3469 struct net_device *dev = (struct net_device *) data;
3470 struct fe_priv *np = netdev_priv(dev);
3471 u8 __iomem *base = get_hwbase(dev);
3472 u32 events;
3473 int i;
3474 unsigned long flags;
3475
3476 dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
3477
3478 for (i=0; ; i++) {
3479 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3480 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3481 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
3482 if (!(events & np->irqmask))
3483 break;
3484
3485 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3486 if (unlikely(nv_alloc_rx_optimized(dev))) {
3487 spin_lock_irqsave(&np->lock, flags);
3488 if (!np->in_shutdown)
3489 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3490 spin_unlock_irqrestore(&np->lock, flags);
3491 }
3492 }
3493
3494 if (unlikely(i > max_interrupt_work)) {
3495 spin_lock_irqsave(&np->lock, flags);
3496 /* disable interrupts on the nic */
3497 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3498 pci_push(base);
3499
3500 if (!np->in_shutdown) {
3501 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3502 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3503 }
3504 spin_unlock_irqrestore(&np->lock, flags);
3505 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
3506 break;
3507 }
3508 }
3509 dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
3510
3511 return IRQ_RETVAL(i);
3512 }
3513 #endif
3514
3515 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3516 {
3517 struct net_device *dev = (struct net_device *) data;
3518 struct fe_priv *np = netdev_priv(dev);
3519 u8 __iomem *base = get_hwbase(dev);
3520 u32 events;
3521 int i;
3522 unsigned long flags;
3523
3524 dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
3525
3526 for (i=0; ; i++) {
3527 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3528 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
3529 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3530 if (!(events & np->irqmask))
3531 break;
3532
3533 /* check tx in case we reached max loop limit in tx isr */
3534 spin_lock_irqsave(&np->lock, flags);
3535 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3536 spin_unlock_irqrestore(&np->lock, flags);
3537
3538 if (events & NVREG_IRQ_LINK) {
3539 spin_lock_irqsave(&np->lock, flags);
3540 nv_link_irq(dev);
3541 spin_unlock_irqrestore(&np->lock, flags);
3542 }
3543 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3544 spin_lock_irqsave(&np->lock, flags);
3545 nv_linkchange(dev);
3546 spin_unlock_irqrestore(&np->lock, flags);
3547 np->link_timeout = jiffies + LINK_TIMEOUT;
3548 }
3549 if (events & NVREG_IRQ_RECOVER_ERROR) {
3550 spin_lock_irq(&np->lock);
3551 /* disable interrupts on the nic */
3552 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3553 pci_push(base);
3554
3555 if (!np->in_shutdown) {
3556 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3557 np->recover_error = 1;
3558 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3559 }
3560 spin_unlock_irq(&np->lock);
3561 break;
3562 }
3563 if (events & (NVREG_IRQ_UNKNOWN)) {
3564 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3565 dev->name, events);
3566 }
3567 if (unlikely(i > max_interrupt_work)) {
3568 spin_lock_irqsave(&np->lock, flags);
3569 /* disable interrupts on the nic */
3570 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3571 pci_push(base);
3572
3573 if (!np->in_shutdown) {
3574 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3575 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3576 }
3577 spin_unlock_irqrestore(&np->lock, flags);
3578 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
3579 break;
3580 }
3581
3582 }
3583 dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
3584
3585 return IRQ_RETVAL(i);
3586 }
3587
3588 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3589 {
3590 struct net_device *dev = (struct net_device *) data;
3591 struct fe_priv *np = netdev_priv(dev);
3592 u8 __iomem *base = get_hwbase(dev);
3593 u32 events;
3594
3595 dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
3596
3597 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3598 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3599 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3600 } else {
3601 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3602 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3603 }
3604 pci_push(base);
3605 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3606 if (!(events & NVREG_IRQ_TIMER))
3607 return IRQ_RETVAL(0);
3608
3609 nv_msi_workaround(np);
3610
3611 spin_lock(&np->lock);
3612 np->intr_test = 1;
3613 spin_unlock(&np->lock);
3614
3615 dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
3616
3617 return IRQ_RETVAL(1);
3618 }
3619
3620 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3621 {
3622 u8 __iomem *base = get_hwbase(dev);
3623 int i;
3624 u32 msixmap = 0;
3625
3626 /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3627 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3628 * the remaining 8 interrupts.
3629 */
3630 for (i = 0; i < 8; i++) {
3631 if ((irqmask >> i) & 0x1) {
3632 msixmap |= vector << (i << 2);
3633 }
3634 }
3635 writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3636
3637 msixmap = 0;
3638 for (i = 0; i < 8; i++) {
3639 if ((irqmask >> (i + 8)) & 0x1) {
3640 msixmap |= vector << (i << 2);
3641 }
3642 }
3643 writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3644 }
3645
3646 static int nv_request_irq(struct net_device *dev, int intr_test)
3647 {
3648 struct fe_priv *np = get_nvpriv(dev);
3649 u8 __iomem *base = get_hwbase(dev);
3650 int ret = 1;
3651 int i;
3652 irqreturn_t (*handler)(int foo, void *data);
3653
3654 if (intr_test) {
3655 handler = nv_nic_irq_test;
3656 } else {
3657 if (np->desc_ver == DESC_VER_3)
3658 handler = nv_nic_irq_optimized;
3659 else
3660 handler = nv_nic_irq;
3661 }
3662
3663 if (np->msi_flags & NV_MSI_X_CAPABLE) {
3664 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3665 np->msi_x_entry[i].entry = i;
3666 }
3667 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
3668 np->msi_flags |= NV_MSI_X_ENABLED;
3669 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
3670 /* Request irq for rx handling */
3671 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, IRQF_SHARED, dev->name, dev) != 0) {
3672 printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
3673 pci_disable_msix(np->pci_dev);
3674 np->msi_flags &= ~NV_MSI_X_ENABLED;
3675 goto out_err;
3676 }
3677 /* Request irq for tx handling */
3678 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, IRQF_SHARED, dev->name, dev) != 0) {
3679 printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
3680 pci_disable_msix(np->pci_dev);
3681 np->msi_flags &= ~NV_MSI_X_ENABLED;
3682 goto out_free_rx;
3683 }
3684 /* Request irq for link and timer handling */
3685 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, IRQF_SHARED, dev->name, dev) != 0) {
3686 printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
3687 pci_disable_msix(np->pci_dev);
3688 np->msi_flags &= ~NV_MSI_X_ENABLED;
3689 goto out_free_tx;
3690 }
3691 /* map interrupts to their respective vector */
3692 writel(0, base + NvRegMSIXMap0);
3693 writel(0, base + NvRegMSIXMap1);
3694 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3695 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3696 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3697 } else {
3698 /* Request irq for all interrupts */
3699 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
3700 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3701 pci_disable_msix(np->pci_dev);
3702 np->msi_flags &= ~NV_MSI_X_ENABLED;
3703 goto out_err;
3704 }
3705
3706 /* map interrupts to vector 0 */
3707 writel(0, base + NvRegMSIXMap0);
3708 writel(0, base + NvRegMSIXMap1);
3709 }
3710 }
3711 }
3712 if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
3713 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
3714 np->msi_flags |= NV_MSI_ENABLED;
3715 dev->irq = np->pci_dev->irq;
3716 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
3717 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3718 pci_disable_msi(np->pci_dev);
3719 np->msi_flags &= ~NV_MSI_ENABLED;
3720 dev->irq = np->pci_dev->irq;
3721 goto out_err;
3722 }
3723
3724 /* map interrupts to vector 0 */
3725 writel(0, base + NvRegMSIMap0);
3726 writel(0, base + NvRegMSIMap1);
3727 /* enable msi vector 0 */
3728 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3729 }
3730 }
3731 if (ret != 0) {
3732 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
3733 goto out_err;
3734
3735 }
3736
3737 return 0;
3738 out_free_tx:
3739 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
3740 out_free_rx:
3741 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
3742 out_err:
3743 return 1;
3744 }
3745
3746 static void nv_free_irq(struct net_device *dev)
3747 {
3748 struct fe_priv *np = get_nvpriv(dev);
3749 int i;
3750
3751 if (np->msi_flags & NV_MSI_X_ENABLED) {
3752 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3753 free_irq(np->msi_x_entry[i].vector, dev);
3754 }
3755 pci_disable_msix(np->pci_dev);
3756 np->msi_flags &= ~NV_MSI_X_ENABLED;
3757 } else {
3758 free_irq(np->pci_dev->irq, dev);
3759 if (np->msi_flags & NV_MSI_ENABLED) {
3760 pci_disable_msi(np->pci_dev);
3761 np->msi_flags &= ~NV_MSI_ENABLED;
3762 }
3763 }
3764 }
3765
3766 static void nv_do_nic_poll(unsigned long data)
3767 {
3768 struct net_device *dev = (struct net_device *) data;
3769 struct fe_priv *np = netdev_priv(dev);
3770 u8 __iomem *base = get_hwbase(dev);
3771 u32 mask = 0;
3772
3773 /*
3774 * First disable irq(s) and then
3775 * reenable interrupts on the nic, we have to do this before calling
3776 * nv_nic_irq because that may decide to do otherwise
3777 */
3778
3779 if (!using_multi_irqs(dev)) {
3780 if (np->msi_flags & NV_MSI_X_ENABLED)
3781 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3782 else
3783 disable_irq_lockdep(np->pci_dev->irq);
3784 mask = np->irqmask;
3785 } else {
3786 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3787 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3788 mask |= NVREG_IRQ_RX_ALL;
3789 }
3790 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3791 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3792 mask |= NVREG_IRQ_TX_ALL;
3793 }
3794 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3795 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3796 mask |= NVREG_IRQ_OTHER;
3797 }
3798 }
3799 np->nic_poll_irq = 0;
3800
3801 /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
3802
3803 if (np->recover_error) {
3804 np->recover_error = 0;
3805 printk(KERN_INFO "forcedeth: MAC in recoverable error state\n");
3806 if (netif_running(dev)) {
3807 netif_tx_lock_bh(dev);
3808 spin_lock(&np->lock);
3809 /* stop engines */
3810 nv_stop_rx(dev);
3811 nv_stop_tx(dev);
3812 nv_txrx_reset(dev);
3813 /* drain rx queue */
3814 nv_drain_rx(dev);
3815 nv_drain_tx(dev);
3816 /* reinit driver view of the rx queue */
3817 set_bufsize(dev);
3818 if (nv_init_ring(dev)) {
3819 if (!np->in_shutdown)
3820 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3821 }
3822 /* reinit nic view of the rx queue */
3823 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3824 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3825 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3826 base + NvRegRingSizes);
3827 pci_push(base);
3828 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3829 pci_push(base);
3830
3831 /* restart rx engine */
3832 nv_start_rx(dev);
3833 nv_start_tx(dev);
3834 spin_unlock(&np->lock);
3835 netif_tx_unlock_bh(dev);
3836 }
3837 }
3838
3839
3840 writel(mask, base + NvRegIrqMask);
3841 pci_push(base);
3842
3843 if (!using_multi_irqs(dev)) {
3844 if (np->desc_ver == DESC_VER_3)
3845 nv_nic_irq_optimized(0, dev);
3846 else
3847 nv_nic_irq(0, dev);
3848 if (np->msi_flags & NV_MSI_X_ENABLED)
3849 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3850 else
3851 enable_irq_lockdep(np->pci_dev->irq);
3852 } else {
3853 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3854 nv_nic_irq_rx(0, dev);
3855 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3856 }
3857 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3858 nv_nic_irq_tx(0, dev);
3859 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3860 }
3861 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3862 nv_nic_irq_other(0, dev);
3863 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3864 }
3865 }
3866 }
3867
3868 #ifdef CONFIG_NET_POLL_CONTROLLER
3869 static void nv_poll_controller(struct net_device *dev)
3870 {
3871 nv_do_nic_poll((unsigned long) dev);
3872 }
3873 #endif
3874
3875 static void nv_do_stats_poll(unsigned long data)
3876 {
3877 struct net_device *dev = (struct net_device *) data;
3878 struct fe_priv *np = netdev_priv(dev);
3879
3880 nv_get_hw_stats(dev);
3881
3882 if (!np->in_shutdown)
3883 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
3884 }
3885
3886 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
3887 {
3888 struct fe_priv *np = netdev_priv(dev);
3889 strcpy(info->driver, DRV_NAME);
3890 strcpy(info->version, FORCEDETH_VERSION);
3891 strcpy(info->bus_info, pci_name(np->pci_dev));
3892 }
3893
3894 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3895 {
3896 struct fe_priv *np = netdev_priv(dev);
3897 wolinfo->supported = WAKE_MAGIC;
3898
3899 spin_lock_irq(&np->lock);
3900 if (np->wolenabled)
3901 wolinfo->wolopts = WAKE_MAGIC;
3902 spin_unlock_irq(&np->lock);
3903 }
3904
3905 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3906 {
3907 struct fe_priv *np = netdev_priv(dev);
3908 u8 __iomem *base = get_hwbase(dev);
3909 u32 flags = 0;
3910
3911 if (wolinfo->wolopts == 0) {
3912 np->wolenabled = 0;
3913 } else if (wolinfo->wolopts & WAKE_MAGIC) {
3914 np->wolenabled = 1;
3915 flags = NVREG_WAKEUPFLAGS_ENABLE;
3916 }
3917 if (netif_running(dev)) {
3918 spin_lock_irq(&np->lock);
3919 writel(flags, base + NvRegWakeUpFlags);
3920 spin_unlock_irq(&np->lock);
3921 }
3922 return 0;
3923 }
3924
3925 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3926 {
3927 struct fe_priv *np = netdev_priv(dev);
3928 int adv;
3929
3930 spin_lock_irq(&np->lock);
3931 ecmd->port = PORT_MII;
3932 if (!netif_running(dev)) {
3933 /* We do not track link speed / duplex setting if the
3934 * interface is disabled. Force a link check */
3935 if (nv_update_linkspeed(dev)) {
3936 if (!netif_carrier_ok(dev))
3937 netif_carrier_on(dev);
3938 } else {
3939 if (netif_carrier_ok(dev))
3940 netif_carrier_off(dev);
3941 }
3942 }
3943
3944 if (netif_carrier_ok(dev)) {
3945 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
3946 case NVREG_LINKSPEED_10:
3947 ecmd->speed = SPEED_10;
3948 break;
3949 case NVREG_LINKSPEED_100:
3950 ecmd->speed = SPEED_100;
3951 break;
3952 case NVREG_LINKSPEED_1000:
3953 ecmd->speed = SPEED_1000;
3954 break;
3955 }
3956 ecmd->duplex = DUPLEX_HALF;
3957 if (np->duplex)
3958 ecmd->duplex = DUPLEX_FULL;
3959 } else {
3960 ecmd->speed = -1;
3961 ecmd->duplex = -1;
3962 }
3963
3964 ecmd->autoneg = np->autoneg;
3965
3966 ecmd->advertising = ADVERTISED_MII;
3967 if (np->autoneg) {
3968 ecmd->advertising |= ADVERTISED_Autoneg;
3969 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3970 if (adv & ADVERTISE_10HALF)
3971 ecmd->advertising |= ADVERTISED_10baseT_Half;
3972 if (adv & ADVERTISE_10FULL)
3973 ecmd->advertising |= ADVERTISED_10baseT_Full;
3974 if (adv & ADVERTISE_100HALF)
3975 ecmd->advertising |= ADVERTISED_100baseT_Half;
3976 if (adv & ADVERTISE_100FULL)
3977 ecmd->advertising |= ADVERTISED_100baseT_Full;
3978 if (np->gigabit == PHY_GIGABIT) {
3979 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3980 if (adv & ADVERTISE_1000FULL)
3981 ecmd->advertising |= ADVERTISED_1000baseT_Full;
3982 }
3983 }
3984 ecmd->supported = (SUPPORTED_Autoneg |
3985 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
3986 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
3987 SUPPORTED_MII);
3988 if (np->gigabit == PHY_GIGABIT)
3989 ecmd->supported |= SUPPORTED_1000baseT_Full;
3990
3991 ecmd->phy_address = np->phyaddr;
3992 ecmd->transceiver = XCVR_EXTERNAL;
3993
3994 /* ignore maxtxpkt, maxrxpkt for now */
3995 spin_unlock_irq(&np->lock);
3996 return 0;
3997 }
3998
3999 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4000 {
4001 struct fe_priv *np = netdev_priv(dev);
4002
4003 if (ecmd->port != PORT_MII)
4004 return -EINVAL;
4005 if (ecmd->transceiver != XCVR_EXTERNAL)
4006 return -EINVAL;
4007 if (ecmd->phy_address != np->phyaddr) {
4008 /* TODO: support switching between multiple phys. Should be
4009 * trivial, but not enabled due to lack of test hardware. */
4010 return -EINVAL;
4011 }
4012 if (ecmd->autoneg == AUTONEG_ENABLE) {
4013 u32 mask;
4014
4015 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4016 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4017 if (np->gigabit == PHY_GIGABIT)
4018 mask |= ADVERTISED_1000baseT_Full;
4019
4020 if ((ecmd->advertising & mask) == 0)
4021 return -EINVAL;
4022
4023 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
4024 /* Note: autonegotiation disable, speed 1000 intentionally
4025 * forbidden - noone should need that. */
4026
4027 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
4028 return -EINVAL;
4029 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
4030 return -EINVAL;
4031 } else {
4032 return -EINVAL;
4033 }
4034
4035 netif_carrier_off(dev);
4036 if (netif_running(dev)) {
4037 nv_disable_irq(dev);
4038 netif_tx_lock_bh(dev);
4039 spin_lock(&np->lock);
4040 /* stop engines */
4041 nv_stop_rx(dev);
4042 nv_stop_tx(dev);
4043 spin_unlock(&np->lock);
4044 netif_tx_unlock_bh(dev);
4045 }
4046
4047 if (ecmd->autoneg == AUTONEG_ENABLE) {
4048 int adv, bmcr;
4049
4050 np->autoneg = 1;
4051
4052 /* advertise only what has been requested */
4053 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4054 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4055 if (ecmd->advertising & ADVERTISED_10baseT_Half)
4056 adv |= ADVERTISE_10HALF;
4057 if (ecmd->advertising & ADVERTISED_10baseT_Full)
4058 adv |= ADVERTISE_10FULL;
4059 if (ecmd->advertising & ADVERTISED_100baseT_Half)
4060 adv |= ADVERTISE_100HALF;
4061 if (ecmd->advertising & ADVERTISED_100baseT_Full)
4062 adv |= ADVERTISE_100FULL;
4063 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4064 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4065 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4066 adv |= ADVERTISE_PAUSE_ASYM;
4067 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4068
4069 if (np->gigabit == PHY_GIGABIT) {
4070 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4071 adv &= ~ADVERTISE_1000FULL;
4072 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
4073 adv |= ADVERTISE_1000FULL;
4074 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4075 }
4076
4077 if (netif_running(dev))
4078 printk(KERN_INFO "%s: link down.\n", dev->name);
4079 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4080 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4081 bmcr |= BMCR_ANENABLE;
4082 /* reset the phy in order for settings to stick,
4083 * and cause autoneg to start */
4084 if (phy_reset(dev, bmcr)) {
4085 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4086 return -EINVAL;
4087 }
4088 } else {
4089 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4090 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4091 }
4092 } else {
4093 int adv, bmcr;
4094
4095 np->autoneg = 0;
4096
4097 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4098 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4099 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
4100 adv |= ADVERTISE_10HALF;
4101 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
4102 adv |= ADVERTISE_10FULL;
4103 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
4104 adv |= ADVERTISE_100HALF;
4105 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
4106 adv |= ADVERTISE_100FULL;
4107 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4108 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
4109 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4110 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4111 }
4112 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4113 adv |= ADVERTISE_PAUSE_ASYM;
4114 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4115 }
4116 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4117 np->fixed_mode = adv;
4118
4119 if (np->gigabit == PHY_GIGABIT) {
4120 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4121 adv &= ~ADVERTISE_1000FULL;
4122 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4123 }
4124
4125 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4126 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4127 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
4128 bmcr |= BMCR_FULLDPLX;
4129 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
4130 bmcr |= BMCR_SPEED100;
4131 if (np->phy_oui == PHY_OUI_MARVELL) {
4132 /* reset the phy in order for forced mode settings to stick */
4133 if (phy_reset(dev, bmcr)) {
4134 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4135 return -EINVAL;
4136 }
4137 } else {
4138 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4139 if (netif_running(dev)) {
4140 /* Wait a bit and then reconfigure the nic. */
4141 udelay(10);
4142 nv_linkchange(dev);
4143 }
4144 }
4145 }
4146
4147 if (netif_running(dev)) {
4148 nv_start_rx(dev);
4149 nv_start_tx(dev);
4150 nv_enable_irq(dev);
4151 }
4152
4153 return 0;
4154 }
4155
4156 #define FORCEDETH_REGS_VER 1
4157
4158 static int nv_get_regs_len(struct net_device *dev)
4159 {
4160 struct fe_priv *np = netdev_priv(dev);
4161 return np->register_size;
4162 }
4163
4164 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4165 {
4166 struct fe_priv *np = netdev_priv(dev);
4167 u8 __iomem *base = get_hwbase(dev);
4168 u32 *rbuf = buf;
4169 int i;
4170
4171 regs->version = FORCEDETH_REGS_VER;
4172 spin_lock_irq(&np->lock);
4173 for (i = 0;i <= np->register_size/sizeof(u32); i++)
4174 rbuf[i] = readl(base + i*sizeof(u32));
4175 spin_unlock_irq(&np->lock);
4176 }
4177
4178 static int nv_nway_reset(struct net_device *dev)
4179 {
4180 struct fe_priv *np = netdev_priv(dev);
4181 int ret;
4182
4183 if (np->autoneg) {
4184 int bmcr;
4185
4186 netif_carrier_off(dev);
4187 if (netif_running(dev)) {
4188 nv_disable_irq(dev);
4189 netif_tx_lock_bh(dev);
4190 spin_lock(&np->lock);
4191 /* stop engines */
4192 nv_stop_rx(dev);
4193 nv_stop_tx(dev);
4194 spin_unlock(&np->lock);
4195 netif_tx_unlock_bh(dev);
4196 printk(KERN_INFO "%s: link down.\n", dev->name);
4197 }
4198
4199 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4200 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4201 bmcr |= BMCR_ANENABLE;
4202 /* reset the phy in order for settings to stick*/
4203 if (phy_reset(dev, bmcr)) {
4204 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4205 return -EINVAL;
4206 }
4207 } else {
4208 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4209 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4210 }
4211
4212 if (netif_running(dev)) {
4213 nv_start_rx(dev);
4214 nv_start_tx(dev);
4215 nv_enable_irq(dev);
4216 }
4217 ret = 0;
4218 } else {
4219 ret = -EINVAL;
4220 }
4221
4222 return ret;
4223 }
4224
4225 static int nv_set_tso(struct net_device *dev, u32 value)
4226 {
4227 struct fe_priv *np = netdev_priv(dev);
4228
4229 if ((np->driver_data & DEV_HAS_CHECKSUM))
4230 return ethtool_op_set_tso(dev, value);
4231 else
4232 return -EOPNOTSUPP;
4233 }
4234
4235 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4236 {
4237 struct fe_priv *np = netdev_priv(dev);
4238
4239 ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4240 ring->rx_mini_max_pending = 0;
4241 ring->rx_jumbo_max_pending = 0;
4242 ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4243
4244 ring->rx_pending = np->rx_ring_size;
4245 ring->rx_mini_pending = 0;
4246 ring->rx_jumbo_pending = 0;
4247 ring->tx_pending = np->tx_ring_size;
4248 }
4249
4250 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4251 {
4252 struct fe_priv *np = netdev_priv(dev);
4253 u8 __iomem *base = get_hwbase(dev);
4254 u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
4255 dma_addr_t ring_addr;
4256
4257 if (ring->rx_pending < RX_RING_MIN ||
4258 ring->tx_pending < TX_RING_MIN ||
4259 ring->rx_mini_pending != 0 ||
4260 ring->rx_jumbo_pending != 0 ||
4261 (np->desc_ver == DESC_VER_1 &&
4262 (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4263 ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4264 (np->desc_ver != DESC_VER_1 &&
4265 (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4266 ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4267 return -EINVAL;
4268 }
4269
4270 /* allocate new rings */
4271 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4272 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4273 sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4274 &ring_addr);
4275 } else {
4276 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4277 sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4278 &ring_addr);
4279 }
4280 rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4281 tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4282 if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
4283 /* fall back to old rings */
4284 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4285 if (rxtx_ring)
4286 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4287 rxtx_ring, ring_addr);
4288 } else {
4289 if (rxtx_ring)
4290 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4291 rxtx_ring, ring_addr);
4292 }
4293 if (rx_skbuff)
4294 kfree(rx_skbuff);
4295 if (tx_skbuff)
4296 kfree(tx_skbuff);
4297 goto exit;
4298 }
4299
4300 if (netif_running(dev)) {
4301 nv_disable_irq(dev);
4302 netif_tx_lock_bh(dev);
4303 spin_lock(&np->lock);
4304 /* stop engines */
4305 nv_stop_rx(dev);
4306 nv_stop_tx(dev);
4307 nv_txrx_reset(dev);
4308 /* drain queues */
4309 nv_drain_rx(dev);
4310 nv_drain_tx(dev);
4311 /* delete queues */
4312 free_rings(dev);
4313 }
4314
4315 /* set new values */
4316 np->rx_ring_size = ring->rx_pending;
4317 np->tx_ring_size = ring->tx_pending;
4318 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4319 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
4320 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4321 } else {
4322 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
4323 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4324 }
4325 np->rx_skb = (struct nv_skb_map*)rx_skbuff;
4326 np->tx_skb = (struct nv_skb_map*)tx_skbuff;
4327 np->ring_addr = ring_addr;
4328
4329 memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4330 memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4331
4332 if (netif_running(dev)) {
4333 /* reinit driver view of the queues */
4334 set_bufsize(dev);
4335 if (nv_init_ring(dev)) {
4336 if (!np->in_shutdown)
4337 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4338 }
4339
4340 /* reinit nic view of the queues */
4341 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4342 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4343 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4344 base + NvRegRingSizes);
4345 pci_push(base);
4346 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4347 pci_push(base);
4348
4349 /* restart engines */
4350 nv_start_rx(dev);
4351 nv_start_tx(dev);
4352 spin_unlock(&np->lock);
4353 netif_tx_unlock_bh(dev);
4354 nv_enable_irq(dev);
4355 }
4356 return 0;
4357 exit:
4358 return -ENOMEM;
4359 }
4360
4361 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4362 {
4363 struct fe_priv *np = netdev_priv(dev);
4364
4365 pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4366 pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4367 pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4368 }
4369
4370 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4371 {
4372 struct fe_priv *np = netdev_priv(dev);
4373 int adv, bmcr;
4374
4375 if ((!np->autoneg && np->duplex == 0) ||
4376 (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4377 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
4378 dev->name);
4379 return -EINVAL;
4380 }
4381 if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4382 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
4383 return -EINVAL;
4384 }
4385
4386 netif_carrier_off(dev);
4387 if (netif_running(dev)) {
4388 nv_disable_irq(dev);
4389 netif_tx_lock_bh(dev);
4390 spin_lock(&np->lock);
4391 /* stop engines */
4392 nv_stop_rx(dev);
4393 nv_stop_tx(dev);
4394 spin_unlock(&np->lock);
4395 netif_tx_unlock_bh(dev);
4396 }
4397
4398 np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4399 if (pause->rx_pause)
4400 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4401 if (pause->tx_pause)
4402 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4403
4404 if (np->autoneg && pause->autoneg) {
4405 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4406
4407 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4408 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4409 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4410 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4411 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4412 adv |= ADVERTISE_PAUSE_ASYM;
4413 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4414
4415 if (netif_running(dev))
4416 printk(KERN_INFO "%s: link down.\n", dev->name);
4417 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4418 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4419 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4420 } else {
4421 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4422 if (pause->rx_pause)
4423 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4424 if (pause->tx_pause)
4425 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4426
4427 if (!netif_running(dev))
4428 nv_update_linkspeed(dev);
4429 else
4430 nv_update_pause(dev, np->pause_flags);
4431 }
4432
4433 if (netif_running(dev)) {
4434 nv_start_rx(dev);
4435 nv_start_tx(dev);
4436 nv_enable_irq(dev);
4437 }
4438 return 0;
4439 }
4440
4441 static u32 nv_get_rx_csum(struct net_device *dev)
4442 {
4443 struct fe_priv *np = netdev_priv(dev);
4444 return (np->rx_csum) != 0;
4445 }
4446
4447 static int nv_set_rx_csum(struct net_device *dev, u32 data)
4448 {
4449 struct fe_priv *np = netdev_priv(dev);
4450 u8 __iomem *base = get_hwbase(dev);
4451 int retcode = 0;
4452
4453 if (np->driver_data & DEV_HAS_CHECKSUM) {
4454 if (data) {
4455 np->rx_csum = 1;
4456 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4457 } else {
4458 np->rx_csum = 0;
4459 /* vlan is dependent on rx checksum offload */
4460 if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
4461 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4462 }
4463 if (netif_running(dev)) {
4464 spin_lock_irq(&np->lock);
4465 writel(np->txrxctl_bits, base + NvRegTxRxControl);
4466 spin_unlock_irq(&np->lock);
4467 }
4468 } else {
4469 return -EINVAL;
4470 }
4471
4472 return retcode;
4473 }
4474
4475 static int nv_set_tx_csum(struct net_device *dev, u32 data)
4476 {
4477 struct fe_priv *np = netdev_priv(dev);
4478
4479 if (np->driver_data & DEV_HAS_CHECKSUM)
4480 return ethtool_op_set_tx_hw_csum(dev, data);
4481 else
4482 return -EOPNOTSUPP;
4483 }
4484
4485 static int nv_set_sg(struct net_device *dev, u32 data)
4486 {
4487 struct fe_priv *np = netdev_priv(dev);
4488
4489 if (np->driver_data & DEV_HAS_CHECKSUM)
4490 return ethtool_op_set_sg(dev, data);
4491 else
4492 return -EOPNOTSUPP;
4493 }
4494
4495 static int nv_get_sset_count(struct net_device *dev, int sset)
4496 {
4497 struct fe_priv *np = netdev_priv(dev);
4498
4499 switch (sset) {
4500 case ETH_SS_TEST:
4501 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4502 return NV_TEST_COUNT_EXTENDED;
4503 else
4504 return NV_TEST_COUNT_BASE;
4505 case ETH_SS_STATS:
4506 if (np->driver_data & DEV_HAS_STATISTICS_V1)
4507 return NV_DEV_STATISTICS_V1_COUNT;
4508 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4509 return NV_DEV_STATISTICS_V2_COUNT;
4510 else
4511 return 0;
4512 default:
4513 return -EOPNOTSUPP;
4514 }
4515 }
4516
4517 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
4518 {
4519 struct fe_priv *np = netdev_priv(dev);
4520
4521 /* update stats */
4522 nv_do_stats_poll((unsigned long)dev);
4523
4524 memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
4525 }
4526
4527 static int nv_link_test(struct net_device *dev)
4528 {
4529 struct fe_priv *np = netdev_priv(dev);
4530 int mii_status;
4531
4532 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4533 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4534
4535 /* check phy link status */
4536 if (!(mii_status & BMSR_LSTATUS))
4537 return 0;
4538 else
4539 return 1;
4540 }
4541
4542 static int nv_register_test(struct net_device *dev)
4543 {
4544 u8 __iomem *base = get_hwbase(dev);
4545 int i = 0;
4546 u32 orig_read, new_read;
4547
4548 do {
4549 orig_read = readl(base + nv_registers_test[i].reg);
4550
4551 /* xor with mask to toggle bits */
4552 orig_read ^= nv_registers_test[i].mask;
4553
4554 writel(orig_read, base + nv_registers_test[i].reg);
4555
4556 new_read = readl(base + nv_registers_test[i].reg);
4557
4558 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4559 return 0;
4560
4561 /* restore original value */
4562 orig_read ^= nv_registers_test[i].mask;
4563 writel(orig_read, base + nv_registers_test[i].reg);
4564
4565 } while (nv_registers_test[++i].reg != 0);
4566
4567 return 1;
4568 }
4569
4570 static int nv_interrupt_test(struct net_device *dev)
4571 {
4572 struct fe_priv *np = netdev_priv(dev);
4573 u8 __iomem *base = get_hwbase(dev);
4574 int ret = 1;
4575 int testcnt;
4576 u32 save_msi_flags, save_poll_interval = 0;
4577
4578 if (netif_running(dev)) {
4579 /* free current irq */
4580 nv_free_irq(dev);
4581 save_poll_interval = readl(base+NvRegPollingInterval);
4582 }
4583
4584 /* flag to test interrupt handler */
4585 np->intr_test = 0;
4586
4587 /* setup test irq */
4588 save_msi_flags = np->msi_flags;
4589 np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4590 np->msi_flags |= 0x001; /* setup 1 vector */
4591 if (nv_request_irq(dev, 1))
4592 return 0;
4593
4594 /* setup timer interrupt */
4595 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4596 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4597
4598 nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4599
4600 /* wait for at least one interrupt */
4601 msleep(100);
4602
4603 spin_lock_irq(&np->lock);
4604
4605 /* flag should be set within ISR */
4606 testcnt = np->intr_test;
4607 if (!testcnt)
4608 ret = 2;
4609
4610 nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4611 if (!(np->msi_flags & NV_MSI_X_ENABLED))
4612 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4613 else
4614 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4615
4616 spin_unlock_irq(&np->lock);
4617
4618 nv_free_irq(dev);
4619
4620 np->msi_flags = save_msi_flags;
4621
4622 if (netif_running(dev)) {
4623 writel(save_poll_interval, base + NvRegPollingInterval);
4624 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4625 /* restore original irq */
4626 if (nv_request_irq(dev, 0))
4627 return 0;
4628 }
4629
4630 return ret;
4631 }
4632
4633 static int nv_loopback_test(struct net_device *dev)
4634 {
4635 struct fe_priv *np = netdev_priv(dev);
4636 u8 __iomem *base = get_hwbase(dev);
4637 struct sk_buff *tx_skb, *rx_skb;
4638 dma_addr_t test_dma_addr;
4639 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
4640 u32 flags;
4641 int len, i, pkt_len;
4642 u8 *pkt_data;
4643 u32 filter_flags = 0;
4644 u32 misc1_flags = 0;
4645 int ret = 1;
4646
4647 if (netif_running(dev)) {
4648 nv_disable_irq(dev);
4649 filter_flags = readl(base + NvRegPacketFilterFlags);
4650 misc1_flags = readl(base + NvRegMisc1);
4651 } else {
4652 nv_txrx_reset(dev);
4653 }
4654
4655 /* reinit driver view of the rx queue */
4656 set_bufsize(dev);
4657 nv_init_ring(dev);
4658
4659 /* setup hardware for loopback */
4660 writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
4661 writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
4662
4663 /* reinit nic view of the rx queue */
4664 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4665 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4666 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4667 base + NvRegRingSizes);
4668 pci_push(base);
4669
4670 /* restart rx engine */
4671 nv_start_rx(dev);
4672 nv_start_tx(dev);
4673
4674 /* setup packet for tx */
4675 pkt_len = ETH_DATA_LEN;
4676 tx_skb = dev_alloc_skb(pkt_len);
4677 if (!tx_skb) {
4678 printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
4679 " of %s\n", dev->name);
4680 ret = 0;
4681 goto out;
4682 }
4683 test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
4684 skb_tailroom(tx_skb),
4685 PCI_DMA_FROMDEVICE);
4686 pkt_data = skb_put(tx_skb, pkt_len);
4687 for (i = 0; i < pkt_len; i++)
4688 pkt_data[i] = (u8)(i & 0xff);
4689
4690 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4691 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
4692 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4693 } else {
4694 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
4695 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
4696 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4697 }
4698 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4699 pci_push(get_hwbase(dev));
4700
4701 msleep(500);
4702
4703 /* check for rx of the packet */
4704 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4705 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
4706 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
4707
4708 } else {
4709 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
4710 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
4711 }
4712
4713 if (flags & NV_RX_AVAIL) {
4714 ret = 0;
4715 } else if (np->desc_ver == DESC_VER_1) {
4716 if (flags & NV_RX_ERROR)
4717 ret = 0;
4718 } else {
4719 if (flags & NV_RX2_ERROR) {
4720 ret = 0;
4721 }
4722 }
4723
4724 if (ret) {
4725 if (len != pkt_len) {
4726 ret = 0;
4727 dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
4728 dev->name, len, pkt_len);
4729 } else {
4730 rx_skb = np->rx_skb[0].skb;
4731 for (i = 0; i < pkt_len; i++) {
4732 if (rx_skb->data[i] != (u8)(i & 0xff)) {
4733 ret = 0;
4734 dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
4735 dev->name, i);
4736 break;
4737 }
4738 }
4739 }
4740 } else {
4741 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
4742 }
4743
4744 pci_unmap_page(np->pci_dev, test_dma_addr,
4745 (skb_end_pointer(tx_skb) - tx_skb->data),
4746 PCI_DMA_TODEVICE);
4747 dev_kfree_skb_any(tx_skb);
4748 out:
4749 /* stop engines */
4750 nv_stop_rx(dev);
4751 nv_stop_tx(dev);
4752 nv_txrx_reset(dev);
4753 /* drain rx queue */
4754 nv_drain_rx(dev);
4755 nv_drain_tx(dev);
4756
4757 if (netif_running(dev)) {
4758 writel(misc1_flags, base + NvRegMisc1);
4759 writel(filter_flags, base + NvRegPacketFilterFlags);
4760 nv_enable_irq(dev);
4761 }
4762
4763 return ret;
4764 }
4765
4766 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
4767 {
4768 struct fe_priv *np = netdev_priv(dev);
4769 u8 __iomem *base = get_hwbase(dev);
4770 int result;
4771 memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
4772
4773 if (!nv_link_test(dev)) {
4774 test->flags |= ETH_TEST_FL_FAILED;
4775 buffer[0] = 1;
4776 }
4777
4778 if (test->flags & ETH_TEST_FL_OFFLINE) {
4779 if (netif_running(dev)) {
4780 netif_stop_queue(dev);
4781 #ifdef CONFIG_FORCEDETH_NAPI
4782 napi_disable(&np->napi);
4783 #endif
4784 netif_tx_lock_bh(dev);
4785 spin_lock_irq(&np->lock);
4786 nv_disable_hw_interrupts(dev, np->irqmask);
4787 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
4788 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4789 } else {
4790 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4791 }
4792 /* stop engines */
4793 nv_stop_rx(dev);
4794 nv_stop_tx(dev);
4795 nv_txrx_reset(dev);
4796 /* drain rx queue */
4797 nv_drain_rx(dev);
4798 nv_drain_tx(dev);
4799 spin_unlock_irq(&np->lock);
4800 netif_tx_unlock_bh(dev);
4801 }
4802
4803 if (!nv_register_test(dev)) {
4804 test->flags |= ETH_TEST_FL_FAILED;
4805 buffer[1] = 1;
4806 }
4807
4808 result = nv_interrupt_test(dev);
4809 if (result != 1) {
4810 test->flags |= ETH_TEST_FL_FAILED;
4811 buffer[2] = 1;
4812 }
4813 if (result == 0) {
4814 /* bail out */
4815 return;
4816 }
4817
4818 if (!nv_loopback_test(dev)) {
4819 test->flags |= ETH_TEST_FL_FAILED;
4820 buffer[3] = 1;
4821 }
4822
4823 if (netif_running(dev)) {
4824 /* reinit driver view of the rx queue */
4825 set_bufsize(dev);
4826 if (nv_init_ring(dev)) {
4827 if (!np->in_shutdown)
4828 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4829 }
4830 /* reinit nic view of the rx queue */
4831 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4832 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4833 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4834 base + NvRegRingSizes);
4835 pci_push(base);
4836 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4837 pci_push(base);
4838 /* restart rx engine */
4839 nv_start_rx(dev);
4840 nv_start_tx(dev);
4841 netif_start_queue(dev);
4842 #ifdef CONFIG_FORCEDETH_NAPI
4843 napi_enable(&np->napi);
4844 #endif
4845 nv_enable_hw_interrupts(dev, np->irqmask);
4846 }
4847 }
4848 }
4849
4850 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
4851 {
4852 switch (stringset) {
4853 case ETH_SS_STATS:
4854 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
4855 break;
4856 case ETH_SS_TEST:
4857 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
4858 break;
4859 }
4860 }
4861
4862 static const struct ethtool_ops ops = {
4863 .get_drvinfo = nv_get_drvinfo,
4864 .get_link = ethtool_op_get_link,
4865 .get_wol = nv_get_wol,
4866 .set_wol = nv_set_wol,
4867 .get_settings = nv_get_settings,
4868 .set_settings = nv_set_settings,
4869 .get_regs_len = nv_get_regs_len,
4870 .get_regs = nv_get_regs,
4871 .nway_reset = nv_nway_reset,
4872 .set_tso = nv_set_tso,
4873 .get_ringparam = nv_get_ringparam,
4874 .set_ringparam = nv_set_ringparam,
4875 .get_pauseparam = nv_get_pauseparam,
4876 .set_pauseparam = nv_set_pauseparam,
4877 .get_rx_csum = nv_get_rx_csum,
4878 .set_rx_csum = nv_set_rx_csum,
4879 .set_tx_csum = nv_set_tx_csum,
4880 .set_sg = nv_set_sg,
4881 .get_strings = nv_get_strings,
4882 .get_ethtool_stats = nv_get_ethtool_stats,
4883 .get_sset_count = nv_get_sset_count,
4884 .self_test = nv_self_test,
4885 };
4886
4887 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
4888 {
4889 struct fe_priv *np = get_nvpriv(dev);
4890
4891 spin_lock_irq(&np->lock);
4892
4893 /* save vlan group */
4894 np->vlangrp = grp;
4895
4896 if (grp) {
4897 /* enable vlan on MAC */
4898 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
4899 } else {
4900 /* disable vlan on MAC */
4901 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
4902 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
4903 }
4904
4905 writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4906
4907 spin_unlock_irq(&np->lock);
4908 }
4909
4910 /* The mgmt unit and driver use a semaphore to access the phy during init */
4911 static int nv_mgmt_acquire_sema(struct net_device *dev)
4912 {
4913 u8 __iomem *base = get_hwbase(dev);
4914 int i;
4915 u32 tx_ctrl, mgmt_sema;
4916
4917 for (i = 0; i < 10; i++) {
4918 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
4919 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
4920 break;
4921 msleep(500);
4922 }
4923
4924 if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
4925 return 0;
4926
4927 for (i = 0; i < 2; i++) {
4928 tx_ctrl = readl(base + NvRegTransmitterControl);
4929 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
4930 writel(tx_ctrl, base + NvRegTransmitterControl);
4931
4932 /* verify that semaphore was acquired */
4933 tx_ctrl = readl(base + NvRegTransmitterControl);
4934 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
4935 ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE))
4936 return 1;
4937 else
4938 udelay(50);
4939 }
4940
4941 return 0;
4942 }
4943
4944 static int nv_open(struct net_device *dev)
4945 {
4946 struct fe_priv *np = netdev_priv(dev);
4947 u8 __iomem *base = get_hwbase(dev);
4948 int ret = 1;
4949 int oom, i;
4950
4951 dprintk(KERN_DEBUG "nv_open: begin\n");
4952
4953 /* erase previous misconfiguration */
4954 if (np->driver_data & DEV_HAS_POWER_CNTRL)
4955 nv_mac_reset(dev);
4956 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
4957 writel(0, base + NvRegMulticastAddrB);
4958 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
4959 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
4960 writel(0, base + NvRegPacketFilterFlags);
4961
4962 writel(0, base + NvRegTransmitterControl);
4963 writel(0, base + NvRegReceiverControl);
4964
4965 writel(0, base + NvRegAdapterControl);
4966
4967 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
4968 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
4969
4970 /* initialize descriptor rings */
4971 set_bufsize(dev);
4972 oom = nv_init_ring(dev);
4973
4974 writel(0, base + NvRegLinkSpeed);
4975 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
4976 nv_txrx_reset(dev);
4977 writel(0, base + NvRegUnknownSetupReg6);
4978
4979 np->in_shutdown = 0;
4980
4981 /* give hw rings */
4982 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4983 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4984 base + NvRegRingSizes);
4985
4986 writel(np->linkspeed, base + NvRegLinkSpeed);
4987 if (np->desc_ver == DESC_VER_1)
4988 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
4989 else
4990 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
4991 writel(np->txrxctl_bits, base + NvRegTxRxControl);
4992 writel(np->vlanctl_bits, base + NvRegVlanControl);
4993 pci_push(base);
4994 writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
4995 reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
4996 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
4997 KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
4998
4999 writel(0, base + NvRegMIIMask);
5000 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5001 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5002
5003 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5004 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5005 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
5006 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5007
5008 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
5009 get_random_bytes(&i, sizeof(i));
5010 writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
5011 writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5012 writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
5013 if (poll_interval == -1) {
5014 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
5015 writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5016 else
5017 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5018 }
5019 else
5020 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
5021 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5022 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5023 base + NvRegAdapterControl);
5024 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
5025 writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
5026 if (np->wolenabled)
5027 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
5028
5029 i = readl(base + NvRegPowerState);
5030 if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
5031 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5032
5033 pci_push(base);
5034 udelay(10);
5035 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5036
5037 nv_disable_hw_interrupts(dev, np->irqmask);
5038 pci_push(base);
5039 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5040 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5041 pci_push(base);
5042
5043 if (nv_request_irq(dev, 0)) {
5044 goto out_drain;
5045 }
5046
5047 /* ask for interrupts */
5048 nv_enable_hw_interrupts(dev, np->irqmask);
5049
5050 spin_lock_irq(&np->lock);
5051 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5052 writel(0, base + NvRegMulticastAddrB);
5053 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5054 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5055 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5056 /* One manual link speed update: Interrupts are enabled, future link
5057 * speed changes cause interrupts and are handled by nv_link_irq().
5058 */
5059 {
5060 u32 miistat;
5061 miistat = readl(base + NvRegMIIStatus);
5062 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5063 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
5064 }
5065 /* set linkspeed to invalid value, thus force nv_update_linkspeed
5066 * to init hw */
5067 np->linkspeed = 0;
5068 ret = nv_update_linkspeed(dev);
5069 nv_start_rx(dev);
5070 nv_start_tx(dev);
5071 netif_start_queue(dev);
5072 #ifdef CONFIG_FORCEDETH_NAPI
5073 napi_enable(&np->napi);
5074 #endif
5075
5076 if (ret) {
5077 netif_carrier_on(dev);
5078 } else {
5079 printk(KERN_INFO "%s: no link during initialization.\n", dev->name);
5080 netif_carrier_off(dev);
5081 }
5082 if (oom)
5083 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5084
5085 /* start statistics timer */
5086 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2))
5087 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
5088
5089 spin_unlock_irq(&np->lock);
5090
5091 return 0;
5092 out_drain:
5093 drain_ring(dev);
5094 return ret;
5095 }
5096
5097 static int nv_close(struct net_device *dev)
5098 {
5099 struct fe_priv *np = netdev_priv(dev);
5100 u8 __iomem *base;
5101
5102 spin_lock_irq(&np->lock);
5103 np->in_shutdown = 1;
5104 spin_unlock_irq(&np->lock);
5105 #ifdef CONFIG_FORCEDETH_NAPI
5106 napi_disable(&np->napi);
5107 #endif
5108 synchronize_irq(np->pci_dev->irq);
5109
5110 del_timer_sync(&np->oom_kick);
5111 del_timer_sync(&np->nic_poll);
5112 del_timer_sync(&np->stats_poll);
5113
5114 netif_stop_queue(dev);
5115 spin_lock_irq(&np->lock);
5116 nv_stop_tx(dev);
5117 nv_stop_rx(dev);
5118 nv_txrx_reset(dev);
5119
5120 /* disable interrupts on the nic or we will lock up */
5121 base = get_hwbase(dev);
5122 nv_disable_hw_interrupts(dev, np->irqmask);
5123 pci_push(base);
5124 dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
5125
5126 spin_unlock_irq(&np->lock);
5127
5128 nv_free_irq(dev);
5129
5130 drain_ring(dev);
5131
5132 if (np->wolenabled) {
5133 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5134 nv_start_rx(dev);
5135 }
5136
5137 /* FIXME: power down nic */
5138
5139 return 0;
5140 }
5141
5142 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5143 {
5144 struct net_device *dev;
5145 struct fe_priv *np;
5146 unsigned long addr;
5147 u8 __iomem *base;
5148 int err, i;
5149 u32 powerstate, txreg;
5150 u32 phystate_orig = 0, phystate;
5151 int phyinitialized = 0;
5152 DECLARE_MAC_BUF(mac);
5153 static int printed_version;
5154
5155 if (!printed_version++)
5156 printk(KERN_INFO "%s: Reverse Engineered nForce ethernet"
5157 " driver. Version %s.\n", DRV_NAME, FORCEDETH_VERSION);
5158
5159 dev = alloc_etherdev(sizeof(struct fe_priv));
5160 err = -ENOMEM;
5161 if (!dev)
5162 goto out;
5163
5164 np = netdev_priv(dev);
5165 np->dev = dev;
5166 np->pci_dev = pci_dev;
5167 spin_lock_init(&np->lock);
5168 SET_NETDEV_DEV(dev, &pci_dev->dev);
5169
5170 init_timer(&np->oom_kick);
5171 np->oom_kick.data = (unsigned long) dev;
5172 np->oom_kick.function = &nv_do_rx_refill; /* timer handler */
5173 init_timer(&np->nic_poll);
5174 np->nic_poll.data = (unsigned long) dev;
5175 np->nic_poll.function = &nv_do_nic_poll; /* timer handler */
5176 init_timer(&np->stats_poll);
5177 np->stats_poll.data = (unsigned long) dev;
5178 np->stats_poll.function = &nv_do_stats_poll; /* timer handler */
5179
5180 err = pci_enable_device(pci_dev);
5181 if (err)
5182 goto out_free;
5183
5184 pci_set_master(pci_dev);
5185
5186 err = pci_request_regions(pci_dev, DRV_NAME);
5187 if (err < 0)
5188 goto out_disable;
5189
5190 if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2))
5191 np->register_size = NV_PCI_REGSZ_VER3;
5192 else if (id->driver_data & DEV_HAS_STATISTICS_V1)
5193 np->register_size = NV_PCI_REGSZ_VER2;
5194 else
5195 np->register_size = NV_PCI_REGSZ_VER1;
5196
5197 err = -EINVAL;
5198 addr = 0;
5199 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5200 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
5201 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
5202 pci_resource_len(pci_dev, i),
5203 pci_resource_flags(pci_dev, i));
5204 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
5205 pci_resource_len(pci_dev, i) >= np->register_size) {
5206 addr = pci_resource_start(pci_dev, i);
5207 break;
5208 }
5209 }
5210 if (i == DEVICE_COUNT_RESOURCE) {
5211 dev_printk(KERN_INFO, &pci_dev->dev,
5212 "Couldn't find register window\n");
5213 goto out_relreg;
5214 }
5215
5216 /* copy of driver data */
5217 np->driver_data = id->driver_data;
5218
5219 /* handle different descriptor versions */
5220 if (id->driver_data & DEV_HAS_HIGH_DMA) {
5221 /* packet format 3: supports 40-bit addressing */
5222 np->desc_ver = DESC_VER_3;
5223 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
5224 if (dma_64bit) {
5225 if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK))
5226 dev_printk(KERN_INFO, &pci_dev->dev,
5227 "64-bit DMA failed, using 32-bit addressing\n");
5228 else
5229 dev->features |= NETIF_F_HIGHDMA;
5230 if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) {
5231 dev_printk(KERN_INFO, &pci_dev->dev,
5232 "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
5233 }
5234 }
5235 } else if (id->driver_data & DEV_HAS_LARGEDESC) {
5236 /* packet format 2: supports jumbo frames */
5237 np->desc_ver = DESC_VER_2;
5238 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
5239 } else {
5240 /* original packet format */
5241 np->desc_ver = DESC_VER_1;
5242 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
5243 }
5244
5245 np->pkt_limit = NV_PKTLIMIT_1;
5246 if (id->driver_data & DEV_HAS_LARGEDESC)
5247 np->pkt_limit = NV_PKTLIMIT_2;
5248
5249 if (id->driver_data & DEV_HAS_CHECKSUM) {
5250 np->rx_csum = 1;
5251 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
5252 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
5253 dev->features |= NETIF_F_TSO;
5254 }
5255
5256 np->vlanctl_bits = 0;
5257 if (id->driver_data & DEV_HAS_VLAN) {
5258 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
5259 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
5260 dev->vlan_rx_register = nv_vlan_rx_register;
5261 }
5262
5263 np->msi_flags = 0;
5264 if ((id->driver_data & DEV_HAS_MSI) && msi) {
5265 np->msi_flags |= NV_MSI_CAPABLE;
5266 }
5267 if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
5268 np->msi_flags |= NV_MSI_X_CAPABLE;
5269 }
5270
5271 np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
5272 if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
5273 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
5274 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
5275 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
5276 }
5277
5278
5279 err = -ENOMEM;
5280 np->base = ioremap(addr, np->register_size);
5281 if (!np->base)
5282 goto out_relreg;
5283 dev->base_addr = (unsigned long)np->base;
5284
5285 dev->irq = pci_dev->irq;
5286
5287 np->rx_ring_size = RX_RING_DEFAULT;
5288 np->tx_ring_size = TX_RING_DEFAULT;
5289
5290 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
5291 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
5292 sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
5293 &np->ring_addr);
5294 if (!np->rx_ring.orig)
5295 goto out_unmap;
5296 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
5297 } else {
5298 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
5299 sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
5300 &np->ring_addr);
5301 if (!np->rx_ring.ex)
5302 goto out_unmap;
5303 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
5304 }
5305 np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5306 np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5307 if (!np->rx_skb || !np->tx_skb)
5308 goto out_freering;
5309
5310 dev->open = nv_open;
5311 dev->stop = nv_close;
5312 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
5313 dev->hard_start_xmit = nv_start_xmit;
5314 else
5315 dev->hard_start_xmit = nv_start_xmit_optimized;
5316 dev->get_stats = nv_get_stats;
5317 dev->change_mtu = nv_change_mtu;
5318 dev->set_mac_address = nv_set_mac_address;
5319 dev->set_multicast_list = nv_set_multicast;
5320 #ifdef CONFIG_NET_POLL_CONTROLLER
5321 dev->poll_controller = nv_poll_controller;
5322 #endif
5323 #ifdef CONFIG_FORCEDETH_NAPI
5324 netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
5325 #endif
5326 SET_ETHTOOL_OPS(dev, &ops);
5327 dev->tx_timeout = nv_tx_timeout;
5328 dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5329
5330 pci_set_drvdata(pci_dev, dev);
5331
5332 /* read the mac address */
5333 base = get_hwbase(dev);
5334 np->orig_mac[0] = readl(base + NvRegMacAddrA);
5335 np->orig_mac[1] = readl(base + NvRegMacAddrB);
5336
5337 /* check the workaround bit for correct mac address order */
5338 txreg = readl(base + NvRegTransmitPoll);
5339 if (id->driver_data & DEV_HAS_CORRECT_MACADDR) {
5340 /* mac address is already in correct order */
5341 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5342 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5343 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5344 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5345 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5346 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
5347 } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5348 /* mac address is already in correct order */
5349 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5350 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5351 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5352 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5353 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5354 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
5355 /*
5356 * Set orig mac address back to the reversed version.
5357 * This flag will be cleared during low power transition.
5358 * Therefore, we should always put back the reversed address.
5359 */
5360 np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) +
5361 (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24);
5362 np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8);
5363 } else {
5364 /* need to reverse mac address to correct order */
5365 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
5366 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
5367 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5368 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5369 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
5370 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
5371 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5372 }
5373 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
5374
5375 if (!is_valid_ether_addr(dev->perm_addr)) {
5376 /*
5377 * Bad mac address. At least one bios sets the mac address
5378 * to 01:23:45:67:89:ab
5379 */
5380 dev_printk(KERN_ERR, &pci_dev->dev,
5381 "Invalid Mac address detected: %s\n",
5382 print_mac(mac, dev->dev_addr));
5383 dev_printk(KERN_ERR, &pci_dev->dev,
5384 "Please complain to your hardware vendor. Switching to a random MAC.\n");
5385 dev->dev_addr[0] = 0x00;
5386 dev->dev_addr[1] = 0x00;
5387 dev->dev_addr[2] = 0x6c;
5388 get_random_bytes(&dev->dev_addr[3], 3);
5389 }
5390
5391 dprintk(KERN_DEBUG "%s: MAC Address %s\n",
5392 pci_name(pci_dev), print_mac(mac, dev->dev_addr));
5393
5394 /* set mac address */
5395 nv_copy_mac_to_hw(dev);
5396
5397 /* disable WOL */
5398 writel(0, base + NvRegWakeUpFlags);
5399 np->wolenabled = 0;
5400
5401 if (id->driver_data & DEV_HAS_POWER_CNTRL) {
5402
5403 /* take phy and nic out of low power mode */
5404 powerstate = readl(base + NvRegPowerState2);
5405 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5406 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
5407 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) &&
5408 pci_dev->revision >= 0xA3)
5409 powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5410 writel(powerstate, base + NvRegPowerState2);
5411 }
5412
5413 if (np->desc_ver == DESC_VER_1) {
5414 np->tx_flags = NV_TX_VALID;
5415 } else {
5416 np->tx_flags = NV_TX2_VALID;
5417 }
5418 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) {
5419 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5420 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5421 np->msi_flags |= 0x0003;
5422 } else {
5423 np->irqmask = NVREG_IRQMASK_CPU;
5424 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5425 np->msi_flags |= 0x0001;
5426 }
5427
5428 if (id->driver_data & DEV_NEED_TIMERIRQ)
5429 np->irqmask |= NVREG_IRQ_TIMER;
5430 if (id->driver_data & DEV_NEED_LINKTIMER) {
5431 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
5432 np->need_linktimer = 1;
5433 np->link_timeout = jiffies + LINK_TIMEOUT;
5434 } else {
5435 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
5436 np->need_linktimer = 0;
5437 }
5438
5439 /* Limit the number of tx's outstanding for hw bug */
5440 if (id->driver_data & DEV_NEED_TX_LIMIT) {
5441 np->tx_limit = 1;
5442 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_32 ||
5443 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
5444 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
5445 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
5446 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
5447 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
5448 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
5449 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_39) &&
5450 pci_dev->revision >= 0xA2)
5451 np->tx_limit = 0;
5452 }
5453
5454 /* clear phy state and temporarily halt phy interrupts */
5455 writel(0, base + NvRegMIIMask);
5456 phystate = readl(base + NvRegAdapterControl);
5457 if (phystate & NVREG_ADAPTCTL_RUNNING) {
5458 phystate_orig = 1;
5459 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5460 writel(phystate, base + NvRegAdapterControl);
5461 }
5462 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5463
5464 if (id->driver_data & DEV_HAS_MGMT_UNIT) {
5465 /* management unit running on the mac? */
5466 if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) {
5467 np->mac_in_use = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST;
5468 dprintk(KERN_INFO "%s: mgmt unit is running. mac in use %x.\n", pci_name(pci_dev), np->mac_in_use);
5469 if (nv_mgmt_acquire_sema(dev)) {
5470 /* management unit setup the phy already? */
5471 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5472 NVREG_XMITCTL_SYNC_PHY_INIT) {
5473 /* phy is inited by mgmt unit */
5474 phyinitialized = 1;
5475 dprintk(KERN_INFO "%s: Phy already initialized by mgmt unit.\n", pci_name(pci_dev));
5476 } else {
5477 /* we need to init the phy */
5478 }
5479 }
5480 }
5481 }
5482
5483 /* find a suitable phy */
5484 for (i = 1; i <= 32; i++) {
5485 int id1, id2;
5486 int phyaddr = i & 0x1F;
5487
5488 spin_lock_irq(&np->lock);
5489 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
5490 spin_unlock_irq(&np->lock);
5491 if (id1 < 0 || id1 == 0xffff)
5492 continue;
5493 spin_lock_irq(&np->lock);
5494 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
5495 spin_unlock_irq(&np->lock);
5496 if (id2 < 0 || id2 == 0xffff)
5497 continue;
5498
5499 np->phy_model = id2 & PHYID2_MODEL_MASK;
5500 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5501 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
5502 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
5503 pci_name(pci_dev), id1, id2, phyaddr);
5504 np->phyaddr = phyaddr;
5505 np->phy_oui = id1 | id2;
5506 break;
5507 }
5508 if (i == 33) {
5509 dev_printk(KERN_INFO, &pci_dev->dev,
5510 "open: Could not find a valid PHY.\n");
5511 goto out_error;
5512 }
5513
5514 if (!phyinitialized) {
5515 /* reset it */
5516 phy_init(dev);
5517 } else {
5518 /* see if it is a gigabit phy */
5519 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5520 if (mii_status & PHY_GIGABIT) {
5521 np->gigabit = PHY_GIGABIT;
5522 }
5523 }
5524
5525 /* set default link speed settings */
5526 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5527 np->duplex = 0;
5528 np->autoneg = 1;
5529
5530 err = register_netdev(dev);
5531 if (err) {
5532 dev_printk(KERN_INFO, &pci_dev->dev,
5533 "unable to register netdev: %d\n", err);
5534 goto out_error;
5535 }
5536
5537 dev_printk(KERN_INFO, &pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, "
5538 "addr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
5539 dev->name,
5540 np->phy_oui,
5541 np->phyaddr,
5542 dev->dev_addr[0],
5543 dev->dev_addr[1],
5544 dev->dev_addr[2],
5545 dev->dev_addr[3],
5546 dev->dev_addr[4],
5547 dev->dev_addr[5]);
5548
5549 dev_printk(KERN_INFO, &pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
5550 dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
5551 dev->features & (NETIF_F_HW_CSUM | NETIF_F_SG) ?
5552 "csum " : "",
5553 dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ?
5554 "vlan " : "",
5555 id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
5556 id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
5557 id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
5558 np->gigabit == PHY_GIGABIT ? "gbit " : "",
5559 np->need_linktimer ? "lnktim " : "",
5560 np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
5561 np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
5562 np->desc_ver);
5563
5564 return 0;
5565
5566 out_error:
5567 if (phystate_orig)
5568 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
5569 pci_set_drvdata(pci_dev, NULL);
5570 out_freering:
5571 free_rings(dev);
5572 out_unmap:
5573 iounmap(get_hwbase(dev));
5574 out_relreg:
5575 pci_release_regions(pci_dev);
5576 out_disable:
5577 pci_disable_device(pci_dev);
5578 out_free:
5579 free_netdev(dev);
5580 out:
5581 return err;
5582 }
5583
5584 static void __devexit nv_remove(struct pci_dev *pci_dev)
5585 {
5586 struct net_device *dev = pci_get_drvdata(pci_dev);
5587 struct fe_priv *np = netdev_priv(dev);
5588 u8 __iomem *base = get_hwbase(dev);
5589
5590 unregister_netdev(dev);
5591
5592 /* special op: write back the misordered MAC address - otherwise
5593 * the next nv_probe would see a wrong address.
5594 */
5595 writel(np->orig_mac[0], base + NvRegMacAddrA);
5596 writel(np->orig_mac[1], base + NvRegMacAddrB);
5597 writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
5598 base + NvRegTransmitPoll);
5599
5600 /* free all structures */
5601 free_rings(dev);
5602 iounmap(get_hwbase(dev));
5603 pci_release_regions(pci_dev);
5604 pci_disable_device(pci_dev);
5605 free_netdev(dev);
5606 pci_set_drvdata(pci_dev, NULL);
5607 }
5608
5609 #ifdef CONFIG_PM
5610 static int nv_suspend(struct pci_dev *pdev, pm_message_t state)
5611 {
5612 struct net_device *dev = pci_get_drvdata(pdev);
5613 struct fe_priv *np = netdev_priv(dev);
5614
5615 if (!netif_running(dev))
5616 goto out;
5617
5618 netif_device_detach(dev);
5619
5620 // Gross.
5621 nv_close(dev);
5622
5623 pci_save_state(pdev);
5624 pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled);
5625 pci_set_power_state(pdev, pci_choose_state(pdev, state));
5626 out:
5627 return 0;
5628 }
5629
5630 static int nv_resume(struct pci_dev *pdev)
5631 {
5632 struct net_device *dev = pci_get_drvdata(pdev);
5633 u8 __iomem *base = get_hwbase(dev);
5634 int rc = 0;
5635 u32 txreg;
5636
5637 if (!netif_running(dev))
5638 goto out;
5639
5640 netif_device_attach(dev);
5641
5642 pci_set_power_state(pdev, PCI_D0);
5643 pci_restore_state(pdev);
5644 pci_enable_wake(pdev, PCI_D0, 0);
5645
5646 /* restore mac address reverse flag */
5647 txreg = readl(base + NvRegTransmitPoll);
5648 txreg |= NVREG_TRANSMITPOLL_MAC_ADDR_REV;
5649 writel(txreg, base + NvRegTransmitPoll);
5650
5651 rc = nv_open(dev);
5652 out:
5653 return rc;
5654 }
5655 #else
5656 #define nv_suspend NULL
5657 #define nv_resume NULL
5658 #endif /* CONFIG_PM */
5659
5660 static struct pci_device_id pci_tbl[] = {
5661 { /* nForce Ethernet Controller */
5662 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
5663 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5664 },
5665 { /* nForce2 Ethernet Controller */
5666 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
5667 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5668 },
5669 { /* nForce3 Ethernet Controller */
5670 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
5671 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5672 },
5673 { /* nForce3 Ethernet Controller */
5674 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
5675 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5676 },
5677 { /* nForce3 Ethernet Controller */
5678 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
5679 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5680 },
5681 { /* nForce3 Ethernet Controller */
5682 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
5683 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5684 },
5685 { /* nForce3 Ethernet Controller */
5686 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
5687 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5688 },
5689 { /* CK804 Ethernet Controller */
5690 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
5691 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
5692 },
5693 { /* CK804 Ethernet Controller */
5694 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
5695 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
5696 },
5697 { /* MCP04 Ethernet Controller */
5698 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
5699 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
5700 },
5701 { /* MCP04 Ethernet Controller */
5702 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
5703 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
5704 },
5705 { /* MCP51 Ethernet Controller */
5706 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
5707 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1,
5708 },
5709 { /* MCP51 Ethernet Controller */
5710 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
5711 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1,
5712 },
5713 { /* MCP55 Ethernet Controller */
5714 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
5715 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT,
5716 },
5717 { /* MCP55 Ethernet Controller */
5718 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
5719 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT,
5720 },
5721 { /* MCP61 Ethernet Controller */
5722 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16),
5723 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5724 },
5725 { /* MCP61 Ethernet Controller */
5726 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17),
5727 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5728 },
5729 { /* MCP61 Ethernet Controller */
5730 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18),
5731 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5732 },
5733 { /* MCP61 Ethernet Controller */
5734 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19),
5735 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5736 },
5737 { /* MCP65 Ethernet Controller */
5738 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20),
5739 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_NEED_TX_LIMIT,
5740 },
5741 { /* MCP65 Ethernet Controller */
5742 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21),
5743 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT,
5744 },
5745 { /* MCP65 Ethernet Controller */
5746 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22),
5747 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT,
5748 },
5749 { /* MCP65 Ethernet Controller */
5750 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23),
5751 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT,
5752 },
5753 { /* MCP67 Ethernet Controller */
5754 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_24),
5755 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5756 },
5757 { /* MCP67 Ethernet Controller */
5758 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_25),
5759 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5760 },
5761 { /* MCP67 Ethernet Controller */
5762 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_26),
5763 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5764 },
5765 { /* MCP67 Ethernet Controller */
5766 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_27),
5767 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5768 },
5769 { /* MCP73 Ethernet Controller */
5770 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_28),
5771 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX,
5772 },
5773 { /* MCP73 Ethernet Controller */
5774 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_29),
5775 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX,
5776 },
5777 { /* MCP73 Ethernet Controller */
5778 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_30),
5779 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX,
5780 },
5781 { /* MCP73 Ethernet Controller */
5782 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_31),
5783 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_