1 /* epic100.c: A SMC 83c170 EPIC/100 Fast Ethernet driver for Linux. */
2 /*
3 Written/copyright 1997-2001 by Donald Becker.
4
5 This software may be used and distributed according to the terms of
6 the GNU General Public License (GPL), incorporated herein by reference.
7 Drivers based on or derived from this code fall under the GPL and must
8 retain the authorship, copyright and license notice. This file is not
9 a complete program and may only be used when the entire operating
10 system is licensed under the GPL.
11
12 This driver is for the SMC83c170/175 "EPIC" series, as used on the
13 SMC EtherPower II 9432 PCI adapter, and several CardBus cards.
14
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
18 Annapolis MD 21403
19
20 Information and updates available at
21 http://www.scyld.com/network/epic100.html
22
23 ---------------------------------------------------------------------
24
25 Linux kernel-specific changes:
26
27 LK1.1.2 (jgarzik):
28 * Merge becker version 1.09 (4/08/2000)
29
30 LK1.1.3:
31 * Major bugfix to 1.09 driver (Francis Romieu)
32
33 LK1.1.4 (jgarzik):
34 * Merge becker test version 1.09 (5/29/2000)
35
36 LK1.1.5:
37 * Fix locking (jgarzik)
38 * Limit 83c175 probe to ethernet-class PCI devices (rgooch)
39
40 LK1.1.6:
41 * Merge becker version 1.11
42 * Move pci_enable_device before any PCI BAR len checks
43
44 LK1.1.7:
45 * { fill me in }
46
47 LK1.1.8:
48 * ethtool driver info support (jgarzik)
49
50 LK1.1.9:
51 * ethtool media get/set support (jgarzik)
52
53 LK1.1.10:
54 * revert MII transceiver init change (jgarzik)
55
56 LK1.1.11:
57 * implement ETHTOOL_[GS]SET, _NWAY_RST, _[GS]MSGLVL, _GLINK (jgarzik)
58 * replace some MII-related magic numbers with constants
59
60 LK1.1.12:
61 * fix power-up sequence
62
63 LK1.1.13:
64 * revert version 1.1.12, power-up sequence "fix"
65
66 LK1.1.14 (Kryzsztof Halasa):
67 * fix spurious bad initializations
68 * pound phy a la SMSC's app note on the subject
69
70 AC1.1.14ac
71 * fix power up/down for ethtool that broke in 1.11
72
73 */
74
75 #define DRV_NAME "epic100"
76 #define DRV_VERSION "1.11+LK1.1.14+AC1.1.14"
77 #define DRV_RELDATE "June 2, 2004"
78
79 /* The user-configurable values.
80 These may be modified when a driver module is loaded.*/
81
82 static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
83
84 /* Used to pass the full-duplex flag, etc. */
85 #define MAX_UNITS 8 /* More are supported, limit only on options */
86 static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
87 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
88
89 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
90 Setting to > 1518 effectively disables this feature. */
91 static int rx_copybreak;
92
93 /* Operational parameters that are set at compile time. */
94
95 /* Keep the ring sizes a power of two for operational efficiency.
96 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
97 Making the Tx ring too large decreases the effectiveness of channel
98 bonding and packet priority.
99 There are no ill effects from too-large receive rings. */
100 #define TX_RING_SIZE 256
101 #define TX_QUEUE_LEN 240 /* Limit ring entries actually used. */
102 #define RX_RING_SIZE 256
103 #define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct epic_tx_desc)
104 #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct epic_rx_desc)
105
106 /* Operational parameters that usually are not changed. */
107 /* Time in jiffies before concluding the transmitter is hung. */
108 #define TX_TIMEOUT (2*HZ)
109
110 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
111
112 /* Bytes transferred to chip before transmission starts. */
113 /* Initial threshold, increased on underflow, rounded down to 4 byte units. */
114 #define TX_FIFO_THRESH 256
115 #define RX_FIFO_THRESH 1 /* 0-3, 0==32, 64,96, or 3==128 bytes */
116
117 #include <linux/config.h>
118 #include <linux/module.h>
119 #include <linux/kernel.h>
120 #include <linux/string.h>
121 #include <linux/timer.h>
122 #include <linux/errno.h>
123 #include <linux/ioport.h>
124 #include <linux/slab.h>
125 #include <linux/interrupt.h>
126 #include <linux/pci.h>
127 #include <linux/delay.h>
128 #include <linux/netdevice.h>
129 #include <linux/etherdevice.h>
130 #include <linux/skbuff.h>
131 #include <linux/init.h>
132 #include <linux/spinlock.h>
133 #include <linux/ethtool.h>
134 #include <linux/mii.h>
135 #include <linux/crc32.h>
136 #include <linux/bitops.h>
137 #include <asm/io.h>
138 #include <asm/uaccess.h>
139
140 /* These identify the driver base version and may not be removed. */
141 static char version[] __devinitdata =
142 DRV_NAME ".c:v1.11 1/7/2001 Written by Donald Becker <becker@scyld.com>\n";
143 static char version2[] __devinitdata =
144 " http://www.scyld.com/network/epic100.html\n";
145 static char version3[] __devinitdata =
146 " (unofficial 2.4.x kernel port, version " DRV_VERSION ", " DRV_RELDATE ")\n";
147
148 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
149 MODULE_DESCRIPTION("SMC 83c170 EPIC series Ethernet driver");
150 MODULE_LICENSE("GPL");
151
152 module_param(debug, int, 0);
153 module_param(rx_copybreak, int, 0);
154 module_param_array(options, int, NULL, 0);
155 module_param_array(full_duplex, int, NULL, 0);
156 MODULE_PARM_DESC(debug, "EPIC/100 debug level (0-5)");
157 MODULE_PARM_DESC(options, "EPIC/100: Bits 0-3: media type, bit 4: full duplex");
158 MODULE_PARM_DESC(rx_copybreak, "EPIC/100 copy breakpoint for copy-only-tiny-frames");
159 MODULE_PARM_DESC(full_duplex, "EPIC/100 full duplex setting(s) (1)");
160
161 /*
162 Theory of Operation
163
164 I. Board Compatibility
165
166 This device driver is designed for the SMC "EPIC/100", the SMC
167 single-chip Ethernet controllers for PCI. This chip is used on
168 the SMC EtherPower II boards.
169
170 II. Board-specific settings
171
172 PCI bus devices are configured by the system at boot time, so no jumpers
173 need to be set on the board. The system BIOS will assign the
174 PCI INTA signal to a (preferably otherwise unused) system IRQ line.
175 Note: Kernel versions earlier than 1.3.73 do not support shared PCI
176 interrupt lines.
177
178 III. Driver operation
179
180 IIIa. Ring buffers
181
182 IVb. References
183
184 http://www.smsc.com/main/datasheets/83c171.pdf
185 http://www.smsc.com/main/datasheets/83c175.pdf
186 http://scyld.com/expert/NWay.html
187 http://www.national.com/pf/DP/DP83840A.html
188
189 IVc. Errata
190
191 */
192
193
194 enum pci_id_flags_bits {
195 /* Set PCI command register bits before calling probe1(). */
196 PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4,
197 /* Read and map the single following PCI BAR. */
198 PCI_ADDR0=0<<4, PCI_ADDR1=1<<4, PCI_ADDR2=2<<4, PCI_ADDR3=3<<4,
199 PCI_ADDR_64BITS=0x100, PCI_NO_ACPI_WAKE=0x200, PCI_NO_MIN_LATENCY=0x400,
200 };
201
202 enum chip_capability_flags { MII_PWRDWN=1, TYPE2_INTR=2, NO_MII=4 };
203
204 #define EPIC_TOTAL_SIZE 0x100
205 #define USE_IO_OPS 1
206 #ifdef USE_IO_OPS
207 #define EPIC_IOTYPE PCI_USES_MASTER|PCI_USES_IO|PCI_ADDR0
208 #else
209 #define EPIC_IOTYPE PCI_USES_MASTER|PCI_USES_MEM|PCI_ADDR1
210 #endif
211
212 typedef enum {
213 SMSC_83C170_0,
214 SMSC_83C170,
215 SMSC_83C175,
216 } chip_t;
217
218
219 struct epic_chip_info {
220 const char *name;
221 enum pci_id_flags_bits pci_flags;
222 int io_size; /* Needed for I/O region check or ioremap(). */
223 int drv_flags; /* Driver use, intended as capability flags. */
224 };
225
226
227 /* indexed by chip_t */
228 static struct epic_chip_info pci_id_tbl[] = {
229 { "SMSC EPIC/100 83c170",
230 EPIC_IOTYPE, EPIC_TOTAL_SIZE, TYPE2_INTR | NO_MII | MII_PWRDWN },
231 { "SMSC EPIC/100 83c170",
232 EPIC_IOTYPE, EPIC_TOTAL_SIZE, TYPE2_INTR },
233 { "SMSC EPIC/C 83c175",
234 EPIC_IOTYPE, EPIC_TOTAL_SIZE, TYPE2_INTR | MII_PWRDWN },
235 };
236
237
238 static struct pci_device_id epic_pci_tbl[] = {
239 { 0x10B8, 0x0005, 0x1092, 0x0AB4, 0, 0, SMSC_83C170_0 },
240 { 0x10B8, 0x0005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, SMSC_83C170 },
241 { 0x10B8, 0x0006, PCI_ANY_ID, PCI_ANY_ID,
242 PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, SMSC_83C175 },
243 { 0,}
244 };
245 MODULE_DEVICE_TABLE (pci, epic_pci_tbl);
246
247
248 #ifndef USE_IO_OPS
249 #undef inb
250 #undef inw
251 #undef inl
252 #undef outb
253 #undef outw
254 #undef outl
255 #define inb readb
256 #define inw readw
257 #define inl readl
258 #define outb writeb
259 #define outw writew
260 #define outl writel
261 #endif
262
263 /* Offsets to registers, using the (ugh) SMC names. */
264 enum epic_registers {
265 COMMAND=0, INTSTAT=4, INTMASK=8, GENCTL=0x0C, NVCTL=0x10, EECTL=0x14,
266 PCIBurstCnt=0x18,
267 TEST1=0x1C, CRCCNT=0x20, ALICNT=0x24, MPCNT=0x28, /* Rx error counters. */
268 MIICtrl=0x30, MIIData=0x34, MIICfg=0x38,
269 LAN0=64, /* MAC address. */
270 MC0=80, /* Multicast filter table. */
271 RxCtrl=96, TxCtrl=112, TxSTAT=0x74,
272 PRxCDAR=0x84, RxSTAT=0xA4, EarlyRx=0xB0, PTxCDAR=0xC4, TxThresh=0xDC,
273 };
274
275 /* Interrupt register bits, using my own meaningful names. */
276 enum IntrStatus {
277 TxIdle=0x40000, RxIdle=0x20000, IntrSummary=0x010000,
278 PCIBusErr170=0x7000, PCIBusErr175=0x1000, PhyEvent175=0x8000,
279 RxStarted=0x0800, RxEarlyWarn=0x0400, CntFull=0x0200, TxUnderrun=0x0100,
280 TxEmpty=0x0080, TxDone=0x0020, RxError=0x0010,
281 RxOverflow=0x0008, RxFull=0x0004, RxHeader=0x0002, RxDone=0x0001,
282 };
283 enum CommandBits {
284 StopRx=1, StartRx=2, TxQueued=4, RxQueued=8,
285 StopTxDMA=0x20, StopRxDMA=0x40, RestartTx=0x80,
286 };
287
288 #define EpicRemoved 0xffffffff /* Chip failed or removed (CardBus) */
289
290 #define EpicNapiEvent (TxEmpty | TxDone | \
291 RxDone | RxStarted | RxEarlyWarn | RxOverflow | RxFull)
292 #define EpicNormalEvent (0x0000ffff & ~EpicNapiEvent)
293
294 static u16 media2miictl[16] = {
295 0, 0x0C00, 0x0C00, 0x2000, 0x0100, 0x2100, 0, 0,
296 0, 0, 0, 0, 0, 0, 0, 0 };
297
298 /* The EPIC100 Rx and Tx buffer descriptors. */
299
300 struct epic_tx_desc {
301 u32 txstatus;
302 u32 bufaddr;
303 u32 buflength;
304 u32 next;
305 };
306
307 struct epic_rx_desc {
308 u32 rxstatus;
309 u32 bufaddr;
310 u32 buflength;
311 u32 next;
312 };
313
314 enum desc_status_bits {
315 DescOwn=0x8000,
316 };
317
318 #define PRIV_ALIGN 15 /* Required alignment mask */
319 struct epic_private {
320 struct epic_rx_desc *rx_ring;
321 struct epic_tx_desc *tx_ring;
322 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
323 struct sk_buff* tx_skbuff[TX_RING_SIZE];
324 /* The addresses of receive-in-place skbuffs. */
325 struct sk_buff* rx_skbuff[RX_RING_SIZE];
326
327 dma_addr_t tx_ring_dma;
328 dma_addr_t rx_ring_dma;
329
330 /* Ring pointers. */
331 spinlock_t lock; /* Group with Tx control cache line. */
332 spinlock_t napi_lock;
333 unsigned int reschedule_in_poll;
334 unsigned int cur_tx, dirty_tx;
335
336 unsigned int cur_rx, dirty_rx;
337 u32 irq_mask;
338 unsigned int rx_buf_sz; /* Based on MTU+slack. */
339
340 struct pci_dev *pci_dev; /* PCI bus location. */
341 int chip_id, chip_flags;
342
343 struct net_device_stats stats;
344 struct timer_list timer; /* Media selection timer. */
345 int tx_threshold;
346 unsigned char mc_filter[8];
347 signed char phys[4]; /* MII device addresses. */
348 u16 advertising; /* NWay media advertisement */
349 int mii_phy_cnt;
350 struct mii_if_info mii;
351 unsigned int tx_full:1; /* The Tx queue is full. */
352 unsigned int default_port:4; /* Last dev->if_port value. */
353 };
354
355 static int epic_open(struct net_device *dev);
356 static int read_eeprom(long ioaddr, int location);
357 static int mdio_read(struct net_device *dev, int phy_id, int location);
358 static void mdio_write(struct net_device *dev, int phy_id, int loc, int val);
359 static void epic_restart(struct net_device *dev);
360 static void epic_timer(unsigned long data);
361 static void epic_tx_timeout(struct net_device *dev);
362 static void epic_init_ring(struct net_device *dev);
363 static int epic_start_xmit(struct sk_buff *skb, struct net_device *dev);
364 static int epic_rx(struct net_device *dev, int budget);
365 static int epic_poll(struct net_device *dev, int *budget);
366 static irqreturn_t epic_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
367 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
368 static struct ethtool_ops netdev_ethtool_ops;
369 static int epic_close(struct net_device *dev);
370 static struct net_device_stats *epic_get_stats(struct net_device *dev);
371 static void set_rx_mode(struct net_device *dev);
372
373
374
375 static int __devinit epic_init_one (struct pci_dev *pdev,
376 const struct pci_device_id *ent)
377 {
378 static int card_idx = -1;
379 long ioaddr;
380 int chip_idx = (int) ent->driver_data;
381 int irq;
382 struct net_device *dev;
383 struct epic_private *ep;
384 int i, ret, option = 0, duplex = 0;
385 void *ring_space;
386 dma_addr_t ring_dma;
387
388 /* when built into the kernel, we only print version if device is found */
389 #ifndef MODULE
390 static int printed_version;
391 if (!printed_version++)
392 printk (KERN_INFO "%s" KERN_INFO "%s" KERN_INFO "%s",
393 version, version2, version3);
394 #endif
395
396 card_idx++;
397
398 ret = pci_enable_device(pdev);
399 if (ret)
400 goto out;
401 irq = pdev->irq;
402
403 if (pci_resource_len(pdev, 0) < pci_id_tbl[chip_idx].io_size) {
404 printk (KERN_ERR "card %d: no PCI region space\n", card_idx);
405 ret = -ENODEV;
406 goto err_out_disable;
407 }
408
409 pci_set_master(pdev);
410
411 ret = pci_request_regions(pdev, DRV_NAME);
412 if (ret < 0)
413 goto err_out_disable;
414
415 ret = -ENOMEM;
416
417 dev = alloc_etherdev(sizeof (*ep));
418 if (!dev) {
419 printk (KERN_ERR "card %d: no memory for eth device\n", card_idx);
420 goto err_out_free_res;
421 }
422 SET_MODULE_OWNER(dev);
423 SET_NETDEV_DEV(dev, &pdev->dev);
424
425 #ifdef USE_IO_OPS
426 ioaddr = pci_resource_start (pdev, 0);
427 #else
428 ioaddr = pci_resource_start (pdev, 1);
429 ioaddr = (long) ioremap (ioaddr, pci_resource_len (pdev, 1));
430 if (!ioaddr) {
431 printk (KERN_ERR DRV_NAME " %d: ioremap failed\n", card_idx);
432 goto err_out_free_netdev;
433 }
434 #endif
435
436 pci_set_drvdata(pdev, dev);
437 ep = dev->priv;
438 ep->mii.dev = dev;
439 ep->mii.mdio_read = mdio_read;
440 ep->mii.mdio_write = mdio_write;
441 ep->mii.phy_id_mask = 0x1f;
442 ep->mii.reg_num_mask = 0x1f;
443
444 ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
445 if (!ring_space)
446 goto err_out_iounmap;
447 ep->tx_ring = (struct epic_tx_desc *)ring_space;
448 ep->tx_ring_dma = ring_dma;
449
450 ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
451 if (!ring_space)
452 goto err_out_unmap_tx;
453 ep->rx_ring = (struct epic_rx_desc *)ring_space;
454 ep->rx_ring_dma = ring_dma;
455
456 if (dev->mem_start) {
457 option = dev->mem_start;
458 duplex = (dev->mem_start & 16) ? 1 : 0;
459 } else if (card_idx >= 0 && card_idx < MAX_UNITS) {
460 if (options[card_idx] >= 0)
461 option = options[card_idx];
462 if (full_duplex[card_idx] >= 0)
463 duplex = full_duplex[card_idx];
464 }
465
466 dev->base_addr = ioaddr;
467 dev->irq = irq;
468
469 spin_lock_init(&ep->lock);
470 spin_lock_init(&ep->napi_lock);
471 ep->reschedule_in_poll = 0;
472
473 /* Bring the chip out of low-power mode. */
474 outl(0x4200, ioaddr + GENCTL);
475 /* Magic?! If we don't set this bit the MII interface won't work. */
476 /* This magic is documented in SMSC app note 7.15 */
477 for (i = 16; i > 0; i--)
478 outl(0x0008, ioaddr + TEST1);
479
480 /* Turn on the MII transceiver. */
481 outl(0x12, ioaddr + MIICfg);
482 if (chip_idx == 1)
483 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
484 outl(0x0200, ioaddr + GENCTL);
485
486 /* Note: the '175 does not have a serial EEPROM. */
487 for (i = 0; i < 3; i++)
488 ((u16 *)dev->dev_addr)[i] = le16_to_cpu(inw(ioaddr + LAN0 + i*4));
489
490 if (debug > 2) {
491 printk(KERN_DEBUG DRV_NAME "(%s): EEPROM contents\n",
492 pci_name(pdev));
493 for (i = 0; i < 64; i++)
494 printk(" %4.4x%s", read_eeprom(ioaddr, i),
495 i % 16 == 15 ? "\n" : "");
496 }
497
498 ep->pci_dev = pdev;
499 ep->chip_id = chip_idx;
500 ep->chip_flags = pci_id_tbl[chip_idx].drv_flags;
501 ep->irq_mask =
502 (ep->chip_flags & TYPE2_INTR ? PCIBusErr175 : PCIBusErr170)
503 | CntFull | TxUnderrun | EpicNapiEvent;
504
505 /* Find the connected MII xcvrs.
506 Doing this in open() would allow detecting external xcvrs later, but
507 takes much time and no cards have external MII. */
508 {
509 int phy, phy_idx = 0;
510 for (phy = 1; phy < 32 && phy_idx < sizeof(ep->phys); phy++) {
511 int mii_status = mdio_read(dev, phy, MII_BMSR);
512 if (mii_status != 0xffff && mii_status != 0x0000) {
513 ep->phys[phy_idx++] = phy;
514 printk(KERN_INFO DRV_NAME "(%s): MII transceiver #%d control "
515 "%4.4x status %4.4x.\n",
516 pci_name(pdev), phy, mdio_read(dev, phy, 0), mii_status);
517 }
518 }
519 ep->mii_phy_cnt = phy_idx;
520 if (phy_idx != 0) {
521 phy = ep->phys[0];
522 ep->mii.advertising = mdio_read(dev, phy, MII_ADVERTISE);
523 printk(KERN_INFO DRV_NAME "(%s): Autonegotiation advertising %4.4x link "
524 "partner %4.4x.\n",
525 pci_name(pdev), ep->mii.advertising, mdio_read(dev, phy, 5));
526 } else if ( ! (ep->chip_flags & NO_MII)) {
527 printk(KERN_WARNING DRV_NAME "(%s): ***WARNING***: No MII transceiver found!\n",
528 pci_name(pdev));
529 /* Use the known PHY address of the EPII. */
530 ep->phys[0] = 3;
531 }
532 ep->mii.phy_id = ep->phys[0];
533 }
534
535 /* Turn off the MII xcvr (175 only!), leave the chip in low-power mode. */
536 if (ep->chip_flags & MII_PWRDWN)
537 outl(inl(ioaddr + NVCTL) & ~0x483C, ioaddr + NVCTL);
538 outl(0x0008, ioaddr + GENCTL);
539
540 /* The lower four bits are the media type. */
541 if (duplex) {
542 ep->mii.force_media = ep->mii.full_duplex = 1;
543 printk(KERN_INFO DRV_NAME "(%s): Forced full duplex operation requested.\n",
544 pci_name(pdev));
545 }
546 dev->if_port = ep->default_port = option;
547
548 /* The Epic-specific entries in the device structure. */
549 dev->open = &epic_open;
550 dev->hard_start_xmit = &epic_start_xmit;
551 dev->stop = &epic_close;
552 dev->get_stats = &epic_get_stats;
553 dev->set_multicast_list = &set_rx_mode;
554 dev->do_ioctl = &netdev_ioctl;
555 dev->ethtool_ops = &netdev_ethtool_ops;
556 dev->watchdog_timeo = TX_TIMEOUT;
557 dev->tx_timeout = &epic_tx_timeout;
558 dev->poll = epic_poll;
559 dev->weight = 64;
560
561 ret = register_netdev(dev);
562 if (ret < 0)
563 goto err_out_unmap_rx;
564
565 printk(KERN_INFO "%s: %s at %#lx, IRQ %d, ",
566 dev->name, pci_id_tbl[chip_idx].name, ioaddr, dev->irq);
567 for (i = 0; i < 5; i++)
568 printk("%2.2x:", dev->dev_addr[i]);
569 printk("%2.2x.\n", dev->dev_addr[i]);
570
571 out:
572 return ret;
573
574 err_out_unmap_rx:
575 pci_free_consistent(pdev, RX_TOTAL_SIZE, ep->rx_ring, ep->rx_ring_dma);
576 err_out_unmap_tx:
577 pci_free_consistent(pdev, TX_TOTAL_SIZE, ep->tx_ring, ep->tx_ring_dma);
578 err_out_iounmap:
579 #ifndef USE_IO_OPS
580 iounmap(ioaddr);
581 err_out_free_netdev:
582 #endif
583 free_netdev(dev);
584 err_out_free_res:
585 pci_release_regions(pdev);
586 err_out_disable:
587 pci_disable_device(pdev);
588 goto out;
589 }
590
591 /* Serial EEPROM section. */
592
593 /* EEPROM_Ctrl bits. */
594 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
595 #define EE_CS 0x02 /* EEPROM chip select. */
596 #define EE_DATA_WRITE 0x08 /* EEPROM chip data in. */
597 #define EE_WRITE_0 0x01
598 #define EE_WRITE_1 0x09
599 #define EE_DATA_READ 0x10 /* EEPROM chip data out. */
600 #define EE_ENB (0x0001 | EE_CS)
601
602 /* Delay between EEPROM clock transitions.
603 This serves to flush the operation to the PCI bus.
604 */
605
606 #define eeprom_delay() inl(ee_addr)
607
608 /* The EEPROM commands include the alway-set leading bit. */
609 #define EE_WRITE_CMD (5 << 6)
610 #define EE_READ64_CMD (6 << 6)
611 #define EE_READ256_CMD (6 << 8)
612 #define EE_ERASE_CMD (7 << 6)
613
614 static void epic_disable_int(struct net_device *dev, struct epic_private *ep)
615 {
616 long ioaddr = dev->base_addr;
617
618 outl(0x00000000, ioaddr + INTMASK);
619 }
620
621 static inline void __epic_pci_commit(long ioaddr)
622 {
623 #ifndef USE_IO_OPS
624 inl(ioaddr + INTMASK);
625 #endif
626 }
627
628 static inline void epic_napi_irq_off(struct net_device *dev,
629 struct epic_private *ep)
630 {
631 long ioaddr = dev->base_addr;
632
633 outl(ep->irq_mask & ~EpicNapiEvent, ioaddr + INTMASK);
634 __epic_pci_commit(ioaddr);
635 }
636
637 static inline void epic_napi_irq_on(struct net_device *dev,
638 struct epic_private *ep)
639 {
640 long ioaddr = dev->base_addr;
641
642 /* No need to commit possible posted write */
643 outl(ep->irq_mask | EpicNapiEvent, ioaddr + INTMASK);
644 }
645
646 static int __devinit read_eeprom(long ioaddr, int location)
647 {
648 int i;
649 int retval = 0;
650 long ee_addr = ioaddr + EECTL;
651 int read_cmd = location |
652 (inl(ee_addr) & 0x40 ? EE_READ64_CMD : EE_READ256_CMD);
653
654 outl(EE_ENB & ~EE_CS, ee_addr);
655 outl(EE_ENB, ee_addr);
656
657 /* Shift the read command bits out. */
658 for (i = 12; i >= 0; i--) {
659 short dataval = (read_cmd & (1 << i)) ? EE_WRITE_1 : EE_WRITE_0;
660 outl(EE_ENB | dataval, ee_addr);
661 eeprom_delay();
662 outl(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
663 eeprom_delay();
664 }
665 outl(EE_ENB, ee_addr);
666
667 for (i = 16; i > 0; i--) {
668 outl(EE_ENB | EE_SHIFT_CLK, ee_addr);
669 eeprom_delay();
670 retval = (retval << 1) | ((inl(ee_addr) & EE_DATA_READ) ? 1 : 0);
671 outl(EE_ENB, ee_addr);
672 eeprom_delay();
673 }
674
675 /* Terminate the EEPROM access. */
676 outl(EE_ENB & ~EE_CS, ee_addr);
677 return retval;
678 }
679
680 #define MII_READOP 1
681 #define MII_WRITEOP 2
682 static int mdio_read(struct net_device *dev, int phy_id, int location)
683 {
684 long ioaddr = dev->base_addr;
685 int read_cmd = (phy_id << 9) | (location << 4) | MII_READOP;
686 int i;
687
688 outl(read_cmd, ioaddr + MIICtrl);
689 /* Typical operation takes 25 loops. */
690 for (i = 400; i > 0; i--) {
691 barrier();
692 if ((inl(ioaddr + MIICtrl) & MII_READOP) == 0) {
693 /* Work around read failure bug. */
694 if (phy_id == 1 && location < 6
695 && inw(ioaddr + MIIData) == 0xffff) {
696 outl(read_cmd, ioaddr + MIICtrl);
697 continue;
698 }
699 return inw(ioaddr + MIIData);
700 }
701 }
702 return 0xffff;
703 }
704
705 static void mdio_write(struct net_device *dev, int phy_id, int loc, int value)
706 {
707 long ioaddr = dev->base_addr;
708 int i;
709
710 outw(value, ioaddr + MIIData);
711 outl((phy_id << 9) | (loc << 4) | MII_WRITEOP, ioaddr + MIICtrl);
712 for (i = 10000; i > 0; i--) {
713 barrier();
714 if ((inl(ioaddr + MIICtrl) & MII_WRITEOP) == 0)
715 break;
716 }
717 return;
718 }
719
720
721 static int epic_open(struct net_device *dev)
722 {
723 struct epic_private *ep = dev->priv;
724 long ioaddr = dev->base_addr;
725 int i;
726 int retval;
727
728 /* Soft reset the chip. */
729 outl(0x4001, ioaddr + GENCTL);
730
731 if ((retval = request_irq(dev->irq, &epic_interrupt, SA_SHIRQ, dev->name, dev)))
732 return retval;
733
734 epic_init_ring(dev);
735
736 outl(0x4000, ioaddr + GENCTL);
737 /* This magic is documented in SMSC app note 7.15 */
738 for (i = 16; i > 0; i--)
739 outl(0x0008, ioaddr + TEST1);
740
741 /* Pull the chip out of low-power mode, enable interrupts, and set for
742 PCI read multiple. The MIIcfg setting and strange write order are
743 required by the details of which bits are reset and the transceiver
744 wiring on the Ositech CardBus card.
745 */
746 #if 0
747 outl(dev->if_port == 1 ? 0x13 : 0x12, ioaddr + MIICfg);
748 #endif
749 if (ep->chip_flags & MII_PWRDWN)
750 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
751
752 #if defined(__powerpc__) || defined(__sparc__) /* Big endian */
753 outl(0x4432 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
754 inl(ioaddr + GENCTL);
755 outl(0x0432 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
756 #else
757 outl(0x4412 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
758 inl(ioaddr + GENCTL);
759 outl(0x0412 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
760 #endif
761
762 udelay(20); /* Looks like EPII needs that if you want reliable RX init. FIXME: pci posting bug? */
763
764 for (i = 0; i < 3; i++)
765 outl(cpu_to_le16(((u16*)dev->dev_addr)[i]), ioaddr + LAN0 + i*4);
766
767 ep->tx_threshold = TX_FIFO_THRESH;
768 outl(ep->tx_threshold, ioaddr + TxThresh);
769
770 if (media2miictl[dev->if_port & 15]) {
771 if (ep->mii_phy_cnt)
772 mdio_write(dev, ep->phys[0], MII_BMCR, media2miictl[dev->if_port&15]);
773 if (dev->if_port == 1) {
774 if (debug > 1)
775 printk(KERN_INFO "%s: Using the 10base2 transceiver, MII "
776 "status %4.4x.\n",
777 dev->name, mdio_read(dev, ep->phys[0], MII_BMSR));
778 }
779 } else {
780 int mii_lpa = mdio_read(dev, ep->phys[0], MII_LPA);
781 if (mii_lpa != 0xffff) {
782 if ((mii_lpa & LPA_100FULL) || (mii_lpa & 0x01C0) == LPA_10FULL)
783 ep->mii.full_duplex = 1;
784 else if (! (mii_lpa & LPA_LPACK))
785 mdio_write(dev, ep->phys[0], MII_BMCR, BMCR_ANENABLE|BMCR_ANRESTART);
786 if (debug > 1)
787 printk(KERN_INFO "%s: Setting %s-duplex based on MII xcvr %d"
788 " register read of %4.4x.\n", dev->name,
789 ep->mii.full_duplex ? "full" : "half",
790 ep->phys[0], mii_lpa);
791 }
792 }
793
794 outl(ep->mii.full_duplex ? 0x7F : 0x79, ioaddr + TxCtrl);
795 outl(ep->rx_ring_dma, ioaddr + PRxCDAR);
796 outl(ep->tx_ring_dma, ioaddr + PTxCDAR);
797
798 /* Start the chip's Rx process. */
799 set_rx_mode(dev);
800 outl(StartRx | RxQueued, ioaddr + COMMAND);
801
802 netif_start_queue(dev);
803
804 /* Enable interrupts by setting the interrupt mask. */
805 outl((ep->chip_flags & TYPE2_INTR ? PCIBusErr175 : PCIBusErr170)
806 | CntFull | TxUnderrun
807 | RxError | RxHeader | EpicNapiEvent, ioaddr + INTMASK);
808
809 if (debug > 1)
810 printk(KERN_DEBUG "%s: epic_open() ioaddr %lx IRQ %d status %4.4x "
811 "%s-duplex.\n",
812 dev->name, ioaddr, dev->irq, (int)inl(ioaddr + GENCTL),
813 ep->mii.full_duplex ? "full" : "half");
814
815 /* Set the timer to switch to check for link beat and perhaps switch
816 to an alternate media type. */
817 init_timer(&ep->timer);
818 ep->timer.expires = jiffies + 3*HZ;
819 ep->timer.data = (unsigned long)dev;
820 ep->timer.function = &epic_timer; /* timer handler */
821 add_timer(&ep->timer);
822
823 return 0;
824 }
825
826 /* Reset the chip to recover from a PCI transaction error.
827 This may occur at interrupt time. */
828 static void epic_pause(struct net_device *dev)
829 {
830 long ioaddr = dev->base_addr;
831 struct epic_private *ep = dev->priv;
832
833 netif_stop_queue (dev);
834
835 /* Disable interrupts by clearing the interrupt mask. */
836 outl(0x00000000, ioaddr + INTMASK);
837 /* Stop the chip's Tx and Rx DMA processes. */
838 outw(StopRx | StopTxDMA | StopRxDMA, ioaddr + COMMAND);
839
840 /* Update the error counts. */
841 if (inw(ioaddr + COMMAND) != 0xffff) {
842 ep->stats.rx_missed_errors += inb(ioaddr + MPCNT);
843 ep->stats.rx_frame_errors += inb(ioaddr + ALICNT);
844 ep->stats.rx_crc_errors += inb(ioaddr + CRCCNT);
845 }
846
847 /* Remove the packets on the Rx queue. */
848 epic_rx(dev, RX_RING_SIZE);
849 }
850
851 static void epic_restart(struct net_device *dev)
852 {
853 long ioaddr = dev->base_addr;
854 struct epic_private *ep = dev->priv;
855 int i;
856
857 /* Soft reset the chip. */
858 outl(0x4001, ioaddr + GENCTL);
859
860 printk(KERN_DEBUG "%s: Restarting the EPIC chip, Rx %d/%d Tx %d/%d.\n",
861 dev->name, ep->cur_rx, ep->dirty_rx, ep->dirty_tx, ep->cur_tx);
862 udelay(1);
863
864 /* This magic is documented in SMSC app note 7.15 */
865 for (i = 16; i > 0; i--)
866 outl(0x0008, ioaddr + TEST1);
867
868 #if defined(__powerpc__) || defined(__sparc__) /* Big endian */
869 outl(0x0432 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
870 #else
871 outl(0x0412 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
872 #endif
873 outl(dev->if_port == 1 ? 0x13 : 0x12, ioaddr + MIICfg);
874 if (ep->chip_flags & MII_PWRDWN)
875 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
876
877 for (i = 0; i < 3; i++)
878 outl(cpu_to_le16(((u16*)dev->dev_addr)[i]), ioaddr + LAN0 + i*4);
879
880 ep->tx_threshold = TX_FIFO_THRESH;
881 outl(ep->tx_threshold, ioaddr + TxThresh);
882 outl(ep->mii.full_duplex ? 0x7F : 0x79, ioaddr + TxCtrl);
883 outl(ep->rx_ring_dma + (ep->cur_rx%RX_RING_SIZE)*
884 sizeof(struct epic_rx_desc), ioaddr + PRxCDAR);
885 outl(ep->tx_ring_dma + (ep->dirty_tx%TX_RING_SIZE)*
886 sizeof(struct epic_tx_desc), ioaddr + PTxCDAR);
887
888 /* Start the chip's Rx process. */
889 set_rx_mode(dev);
890 outl(StartRx | RxQueued, ioaddr + COMMAND);
891
892 /* Enable interrupts by setting the interrupt mask. */
893 outl((ep->chip_flags & TYPE2_INTR ? PCIBusErr175 : PCIBusErr170)
894 | CntFull | TxUnderrun
895 | RxError | RxHeader | EpicNapiEvent, ioaddr + INTMASK);
896
897 printk(KERN_DEBUG "%s: epic_restart() done, cmd status %4.4x, ctl %4.4x"
898 " interrupt %4.4x.\n",
899 dev->name, (int)inl(ioaddr + COMMAND), (int)inl(ioaddr + GENCTL),
900 (int)inl(ioaddr + INTSTAT));
901 return;
902 }
903
904 static void check_media(struct net_device *dev)
905 {
906 struct epic_private *ep = dev->priv;
907 long ioaddr = dev->base_addr;
908 int mii_lpa = ep->mii_phy_cnt ? mdio_read(dev, ep->phys[0], MII_LPA) : 0;
909 int negotiated = mii_lpa & ep->mii.advertising;
910 int duplex = (negotiated & 0x0100) || (negotiated & 0x01C0) == 0x0040;
911
912 if (ep->mii.force_media)
913 return;
914 if (mii_lpa == 0xffff) /* Bogus read */
915 return;
916 if (ep->mii.full_duplex != duplex) {
917 ep->mii.full_duplex = duplex;
918 printk(KERN_INFO "%s: Setting %s-duplex based on MII #%d link"
919 " partner capability of %4.4x.\n", dev->name,
920 ep->mii.full_duplex ? "full" : "half", ep->phys[0], mii_lpa);
921 outl(ep->mii.full_duplex ? 0x7F : 0x79, ioaddr + TxCtrl);
922 }
923 }
924
925 static void epic_timer(unsigned long data)
926 {
927 struct net_device *dev = (struct net_device *)data;
928 struct epic_private *ep = dev->priv;
929 long ioaddr = dev->base_addr;
930 int next_tick = 5*HZ;
931
932 if (debug > 3) {
933 printk(KERN_DEBUG "%s: Media monitor tick, Tx status %8.8x.\n",
934 dev->name, (int)inl(ioaddr + TxSTAT));
935 printk(KERN_DEBUG "%s: Other registers are IntMask %4.4x "
936 "IntStatus %4.4x RxStatus %4.4x.\n",
937 dev->name, (int)inl(ioaddr + INTMASK),
938 (int)inl(ioaddr + INTSTAT), (int)inl(ioaddr + RxSTAT));
939 }
940
941 check_media(dev);
942
943 ep->timer.expires = jiffies + next_tick;
944 add_timer(&ep->timer);
945 }
946
947 static void epic_tx_timeout(struct net_device *dev)
948 {
949 struct epic_private *ep = dev->priv;
950 long ioaddr = dev->base_addr;
951
952 if (debug > 0) {
953 printk(KERN_WARNING "%s: Transmit timeout using MII device, "
954 "Tx status %4.4x.\n",
955 dev->name, (int)inw(ioaddr + TxSTAT));
956 if (debug > 1) {
957 printk(KERN_DEBUG "%s: Tx indices: dirty_tx %d, cur_tx %d.\n",
958 dev->name, ep->dirty_tx, ep->cur_tx);
959 }
960 }
961 if (inw(ioaddr + TxSTAT) & 0x10) { /* Tx FIFO underflow. */
962 ep->stats.tx_fifo_errors++;
963 outl(RestartTx, ioaddr + COMMAND);
964 } else {
965 epic_restart(dev);
966 outl(TxQueued, dev->base_addr + COMMAND);
967 }
968
969 dev->trans_start = jiffies;
970 ep->stats.tx_errors++;
971 if (!ep->tx_full)
972 netif_wake_queue(dev);
973 }
974
975 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
976 static void epic_init_ring(struct net_device *dev)
977 {
978 struct epic_private *ep = dev->priv;
979 int i;
980
981 ep->tx_full = 0;
982 ep->dirty_tx = ep->cur_tx = 0;
983 ep->cur_rx = ep->dirty_rx = 0;
984 ep->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
985
986 /* Initialize all Rx descriptors. */
987 for (i = 0; i < RX_RING_SIZE; i++) {
988 ep->rx_ring[i].rxstatus = 0;
989 ep->rx_ring[i].buflength = cpu_to_le32(ep->rx_buf_sz);
990 ep->rx_ring[i].next = ep->rx_ring_dma +
991 (i+1)*sizeof(struct epic_rx_desc);
992 ep->rx_skbuff[i] = NULL;
993 }
994 /* Mark the last entry as wrapping the ring. */
995 ep->rx_ring[i-1].next = ep->rx_ring_dma;
996
997 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
998 for (i = 0; i < RX_RING_SIZE; i++) {
999 struct sk_buff *skb = dev_alloc_skb(ep->rx_buf_sz);
1000 ep->rx_skbuff[i] = skb;
1001 if (skb == NULL)
1002 break;
1003 skb->dev = dev; /* Mark as being used by this device. */
1004 skb_reserve(skb, 2); /* 16 byte align the IP header. */
1005 ep->rx_ring[i].bufaddr = pci_map_single(ep->pci_dev,
1006 skb->tail, ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
1007 ep->rx_ring[i].rxstatus = cpu_to_le32(DescOwn);
1008 }
1009 ep->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
1010
1011 /* The Tx buffer descriptor is filled in as needed, but we
1012 do need to clear the ownership bit. */
1013 for (i = 0; i < TX_RING_SIZE; i++) {
1014 ep->tx_skbuff[i] = NULL;
1015 ep->tx_ring[i].txstatus = 0x0000;
1016 ep->tx_ring[i].next = ep->tx_ring_dma +
1017 (i+1)*sizeof(struct epic_tx_desc);
1018 }
1019 ep->tx_ring[i-1].next = ep->tx_ring_dma;
1020 return;
1021 }
1022
1023 static int epic_start_xmit(struct sk_buff *skb, struct net_device *dev)
1024 {
1025 struct epic_private *ep = dev->priv;
1026 int entry, free_count;
1027 u32 ctrl_word;
1028 unsigned long flags;
1029
1030 if (skb->len < ETH_ZLEN) {
1031 skb = skb_padto(skb, ETH_ZLEN);
1032 if (skb == NULL)
1033 return 0;
1034 }
1035
1036 /* Caution: the write order is important here, set the field with the
1037 "ownership" bit last. */
1038
1039 /* Calculate the next Tx descriptor entry. */
1040 spin_lock_irqsave(&ep->lock, flags);
1041 free_count = ep->cur_tx - ep->dirty_tx;
1042 entry = ep->cur_tx % TX_RING_SIZE;
1043
1044 ep->tx_skbuff[entry] = skb;
1045 ep->tx_ring[entry].bufaddr = pci_map_single(ep->pci_dev, skb->data,
1046 skb->len, PCI_DMA_TODEVICE);
1047 if (free_count < TX_QUEUE_LEN/2) {/* Typical path */
1048 ctrl_word = cpu_to_le32(0x100000); /* No interrupt */
1049 } else if (free_count == TX_QUEUE_LEN/2) {
1050 ctrl_word = cpu_to_le32(0x140000); /* Tx-done intr. */
1051 } else if (free_count < TX_QUEUE_LEN - 1) {
1052 ctrl_word = cpu_to_le32(0x100000); /* No Tx-done intr. */
1053 } else {
1054 /* Leave room for an additional entry. */
1055 ctrl_word = cpu_to_le32(0x140000); /* Tx-done intr. */
1056 ep->tx_full = 1;
1057 }
1058 ep->tx_ring[entry].buflength = ctrl_word | cpu_to_le32(skb->len);
1059 ep->tx_ring[entry].txstatus =
1060 ((skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN) << 16)
1061 | cpu_to_le32(DescOwn);
1062
1063 ep->cur_tx++;
1064 if (ep->tx_full)
1065 netif_stop_queue(dev);
1066
1067 spin_unlock_irqrestore(&ep->lock, flags);
1068 /* Trigger an immediate transmit demand. */
1069 outl(TxQueued, dev->base_addr + COMMAND);
1070
1071 dev->trans_start = jiffies;
1072 if (debug > 4)
1073 printk(KERN_DEBUG "%s: Queued Tx packet size %d to slot %d, "
1074 "flag %2.2x Tx status %8.8x.\n",
1075 dev->name, (int)skb->len, entry, ctrl_word,
1076 (int)inl(dev->base_addr + TxSTAT));
1077
1078 return 0;
1079 }
1080
1081 static void epic_tx_error(struct net_device *dev, struct epic_private *ep,
1082 int status)
1083 {
1084 struct net_device_stats *stats = &ep->stats;
1085
1086 #ifndef final_version
1087 /* There was an major error, log it. */
1088 if (debug > 1)
1089 printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n",
1090 dev->name, status);
1091 #endif
1092 stats->tx_errors++;
1093 if (status & 0x1050)
1094 stats->tx_aborted_errors++;
1095 if (status & 0x0008)
1096 stats->tx_carrier_errors++;
1097 if (status & 0x0040)
1098 stats->tx_window_errors++;
1099 if (status & 0x0010)
1100 stats->tx_fifo_errors++;
1101 }
1102
1103 static void epic_tx(struct net_device *dev, struct epic_private *ep)
1104 {
1105 unsigned int dirty_tx, cur_tx;
1106
1107 /*
1108 * Note: if this lock becomes a problem we can narrow the locked
1109 * region at the cost of occasionally grabbing the lock more times.
1110 */
1111 cur_tx = ep->cur_tx;
1112 for (dirty_tx = ep->dirty_tx; cur_tx - dirty_tx > 0; dirty_tx++) {
1113 struct sk_buff *skb;
1114 int entry = dirty_tx % TX_RING_SIZE;
1115 int txstatus = le32_to_cpu(ep->tx_ring[entry].txstatus);
1116
1117 if (txstatus & DescOwn)
1118 break; /* It still hasn't been Txed */
1119
1120 if (likely(txstatus & 0x0001)) {
1121 ep->stats.collisions += (txstatus >> 8) & 15;
1122 ep->stats.tx_packets++;
1123 ep->stats.tx_bytes += ep->tx_skbuff[entry]->len;
1124 } else
1125 epic_tx_error(dev, ep, txstatus);
1126
1127 /* Free the original skb. */
1128 skb = ep->tx_skbuff[entry];
1129 pci_unmap_single(ep->pci_dev, ep->tx_ring[entry].bufaddr,
1130 skb->len, PCI_DMA_TODEVICE);
1131 dev_kfree_skb_irq(skb);
1132 ep->tx_skbuff[entry] = NULL;
1133 }
1134
1135 #ifndef final_version
1136 if (cur_tx - dirty_tx > TX_RING_SIZE) {
1137 printk(KERN_WARNING
1138 "%s: Out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1139 dev->name, dirty_tx, cur_tx, ep->tx_full);
1140 dirty_tx += TX_RING_SIZE;
1141 }
1142 #endif
1143 ep->dirty_tx = dirty_tx;
1144 if (ep->tx_full && cur_tx - dirty_tx < TX_QUEUE_LEN - 4) {
1145 /* The ring is no longer full, allow new TX entries. */
1146 ep->tx_full = 0;
1147 netif_wake_queue(dev);
1148 }
1149 }
1150
1151 /* The interrupt handler does all of the Rx thread work and cleans up
1152 after the Tx thread. */
1153 static irqreturn_t epic_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
1154 {
1155 struct net_device *dev = dev_instance;
1156 struct epic_private *ep = dev->priv;
1157 long ioaddr = dev->base_addr;
1158 unsigned int handled = 0;
1159 int status;
1160
1161 status = inl(ioaddr + INTSTAT);
1162 /* Acknowledge all of the current interrupt sources ASAP. */
1163 outl(status & EpicNormalEvent, ioaddr + INTSTAT);
1164
1165 if (debug > 4) {
1166 printk(KERN_DEBUG "%s: Interrupt, status=%#8.8x new "
1167 "intstat=%#8.8x.\n", dev->name, status,
1168 (int)inl(ioaddr + INTSTAT));
1169 }
1170
1171 if ((status & IntrSummary) == 0)
1172 goto out;
1173
1174 handled = 1;
1175
1176 if ((status & EpicNapiEvent) && !ep->reschedule_in_poll) {
1177 spin_lock(&ep->napi_lock);
1178 if (netif_rx_schedule_prep(dev)) {
1179 epic_napi_irq_off(dev, ep);
1180 __netif_rx_schedule(dev);
1181 } else
1182 ep->reschedule_in_poll++;
1183 spin_unlock(&ep->napi_lock);
1184 }
1185 status &= ~EpicNapiEvent;
1186
1187 /* Check uncommon events all at once. */
1188 if (status & (CntFull | TxUnderrun | PCIBusErr170 | PCIBusErr175)) {
1189 if (status == EpicRemoved)
1190 goto out;
1191
1192 /* Always update the error counts to avoid overhead later. */
1193 ep->stats.rx_missed_errors += inb(ioaddr + MPCNT);
1194 ep->stats.rx_frame_errors += inb(ioaddr + ALICNT);
1195 ep->stats.rx_crc_errors += inb(ioaddr + CRCCNT);
1196
1197 if (status & TxUnderrun) { /* Tx FIFO underflow. */
1198 ep->stats.tx_fifo_errors++;
1199 outl(ep->tx_threshold += 128, ioaddr + TxThresh);
1200 /* Restart the transmit process. */
1201 outl(RestartTx, ioaddr + COMMAND);
1202 }
1203 if (status & PCIBusErr170) {
1204 printk(KERN_ERR "%s: PCI Bus Error! status %4.4x.\n",
1205 dev->name, status);
1206 epic_pause(dev);
1207 epic_restart(dev);
1208 }
1209 /* Clear all error sources. */
1210 outl(status & 0x7f18, ioaddr + INTSTAT);
1211 }
1212
1213 out:
1214 if (debug > 3) {
1215 printk(KERN_DEBUG "%s: exit interrupt, intr_status=%#4.4x.\n",
1216 dev->name, status);
1217 }
1218
1219 return IRQ_RETVAL(handled);
1220 }
1221
1222 static int epic_rx(struct net_device *dev, int budget)
1223 {
1224 struct epic_private *ep = dev->priv;
1225 int entry = ep->cur_rx % RX_RING_SIZE;
1226 int rx_work_limit = ep->dirty_rx + RX_RING_SIZE - ep->cur_rx;
1227 int work_done = 0;
1228
1229 if (debug > 4)
1230 printk(KERN_DEBUG " In epic_rx(), entry %d %8.8x.\n", entry,
1231 ep->rx_ring[entry].rxstatus);
1232
1233 if (rx_work_limit > budget)
1234 rx_work_limit = budget;
1235
1236 /* If we own the next entry, it's a new packet. Send it up. */
1237 while ((ep->rx_ring[entry].rxstatus & cpu_to_le32(DescOwn)) == 0) {
1238 int status = le32_to_cpu(ep->rx_ring[entry].rxstatus);
1239
1240 if (debug > 4)
1241 printk(KERN_DEBUG " epic_rx() status was %8.8x.\n", status);
1242 if (--rx_work_limit < 0)
1243 break;
1244 if (status & 0x2006) {
1245 if (debug > 2)
1246 printk(KERN_DEBUG "%s: epic_rx() error status was %8.8x.\n",
1247 dev->name, status);
1248 if (status & 0x2000) {
1249 printk(KERN_WARNING "%s: Oversized Ethernet frame spanned "
1250 "multiple buffers, status %4.4x!\n", dev->name, status);
1251 ep->stats.rx_length_errors++;
1252 } else if (status & 0x0006)
1253 /* Rx Frame errors are counted in hardware. */
1254 ep->stats.rx_errors++;
1255 } else {
1256 /* Malloc up new buffer, compatible with net-2e. */
1257 /* Omit the four octet CRC from the length. */
1258 short pkt_len = (status >> 16) - 4;
1259 struct sk_buff *skb;
1260
1261 if (pkt_len > PKT_BUF_SZ - 4) {
1262 printk(KERN_ERR "%s: Oversized Ethernet frame, status %x "
1263 "%d bytes.\n",
1264 dev->name, status, pkt_len);
1265 pkt_len = 1514;
1266 }
1267 /* Check if the packet is long enough to accept without copying
1268 to a minimally-sized skbuff. */
1269 if (pkt_len < rx_copybreak
1270 && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1271 skb->dev = dev;
1272 skb_reserve(skb, 2); /* 16 byte align the IP header */
1273 pci_dma_sync_single_for_cpu(ep->pci_dev,
1274 ep->rx_ring[entry].bufaddr,
1275 ep->rx_buf_sz,
1276 PCI_DMA_FROMDEVICE);
1277 eth_copy_and_sum(skb, ep->rx_skbuff[entry]->tail, pkt_len, 0);
1278 skb_put(skb, pkt_len);
1279 pci_dma_sync_single_for_device(ep->pci_dev,
1280 ep->rx_ring[entry].bufaddr,
1281 ep->rx_buf_sz,
1282 PCI_DMA_FROMDEVICE);
1283 } else {
1284 pci_unmap_single(ep->pci_dev,
1285 ep->rx_ring[entry].bufaddr,
1286 ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
1287 skb_put(skb = ep->rx_skbuff[entry], pkt_len);
1288 ep->rx_skbuff[entry] = NULL;
1289 }
1290 skb->protocol = eth_type_trans(skb, dev);
1291 netif_receive_skb(skb);
1292 dev->last_rx = jiffies;
1293 ep->stats.rx_packets++;
1294 ep->stats.rx_bytes += pkt_len;
1295 }
1296 work_done++;
1297 entry = (++ep->cur_rx) % RX_RING_SIZE;
1298 }
1299
1300 /* Refill the Rx ring buffers. */
1301 for (; ep->cur_rx - ep->dirty_rx > 0; ep->dirty_rx++) {
1302 entry = ep->dirty_rx % RX_RING_SIZE;
1303 if (ep->rx_skbuff[entry] == NULL) {
1304 struct sk_buff *skb;
1305 skb = ep->rx_skbuff[entry] = dev_alloc_skb(ep->rx_buf_sz);
1306 if (skb == NULL)
1307 break;
1308 skb->dev = dev; /* Mark as being used by this device. */
1309 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1310 ep->rx_ring[entry].bufaddr = pci_map_single(ep->pci_dev,
1311 skb->tail, ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
1312 work_done++;
1313 }
1314 ep->rx_ring[entry].rxstatus = cpu_to_le32(DescOwn);
1315 }
1316 return work_done;
1317 }
1318
1319 static void epic_rx_err(struct net_device *dev, struct epic_private *ep)
1320 {
1321 long ioaddr = dev->base_addr;
1322 int status;
1323
1324 status = inl(ioaddr + INTSTAT);
1325
1326 if (status == EpicRemoved)
1327 return;
1328 if (status & RxOverflow) /* Missed a Rx frame. */
1329 ep->stats.rx_errors++;
1330 if (status & (RxOverflow | RxFull))
1331 outw(RxQueued, ioaddr + COMMAND);
1332 }
1333
1334 static int epic_poll(struct net_device *dev, int *budget)
1335 {
1336 struct epic_private *ep = dev->priv;
1337 int work_done, orig_budget;
1338 long ioaddr = dev->base_addr;
1339
1340 orig_budget = (*budget > dev->quota) ? dev->quota : *budget;
1341
1342 rx_action:
1343
1344 epic_tx(dev, ep);
1345
1346 work_done = epic_rx(dev, *budget);
1347
1348 epic_rx_err(dev, ep);
1349
1350 *budget -= work_done;
1351 dev->quota -= work_done;
1352
1353 if (netif_running(dev) && (work_done < orig_budget)) {
1354 unsigned long flags;
1355 int more;
1356
1357 /* A bit baroque but it avoids a (space hungry) spin_unlock */
1358
1359 spin_lock_irqsave(&ep->napi_lock, flags);
1360
1361 more = ep->reschedule_in_poll;
1362 if (!more) {
1363 __netif_rx_complete(dev);
1364 outl(EpicNapiEvent, ioaddr + INTSTAT);
1365 epic_napi_irq_on(dev, ep);
1366 } else
1367 ep->reschedule_in_poll--;
1368
1369 spin_unlock_irqrestore(&ep->napi_lock, flags);
1370
1371 if (more)
1372 goto rx_action;
1373 }
1374
1375 return (work_done >= orig_budget);
1376 }
1377
1378 static int epic_close(struct net_device *dev)
1379 {
1380 long ioaddr = dev->base_addr;
1381 struct epic_private *ep = dev->priv;
1382 struct sk_buff *skb;
1383 int i;
1384
1385 netif_stop_queue(dev);
1386
1387 if (debug > 1)
1388 printk(KERN_DEBUG "%s: Shutting down ethercard, status was %2.2x.\n",
1389 dev->name, (int)inl(ioaddr + INTSTAT));
1390
1391 del_timer_sync(&ep->timer);
1392
1393 epic_disable_int(dev, ep);
1394
1395 free_irq(dev->irq, dev);
1396
1397 epic_pause(dev);
1398
1399 /* Free all the skbuffs in the Rx queue. */
1400 for (i = 0; i < RX_RING_SIZE; i++) {
1401 skb = ep->rx_skbuff[i];
1402 ep->rx_skbuff[i] = NULL;
1403 ep->rx_ring[i].rxstatus = 0; /* Not owned by Epic chip. */
1404 ep->rx_ring[i].buflength = 0;
1405 if (skb) {
1406 pci_unmap_single(ep->pci_dev, ep->rx_ring[i].bufaddr,
1407 ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
1408 dev_kfree_skb(skb);
1409 }
1410 ep->rx_ring[i].bufaddr = 0xBADF00D0; /* An invalid address. */
1411 }
1412 for (i = 0; i < TX_RING_SIZE; i++) {
1413 skb = ep->tx_skbuff[i];
1414 ep->tx_skbuff[i] = NULL;
1415 if (!skb)
1416 continue;
1417 pci_unmap_single(ep->pci_dev, ep->tx_ring[i].bufaddr,
1418 skb->len, PCI_DMA_TODEVICE);
1419 dev_kfree_skb(skb);
1420 }
1421
1422 /* Green! Leave the chip in low-power mode. */
1423 outl(0x0008, ioaddr + GENCTL);
1424
1425 return 0;
1426 }
1427
1428 static struct net_device_stats *epic_get_stats(struct net_device *dev)
1429 {
1430 struct epic_private *ep = dev->priv;
1431 long ioaddr = dev->base_addr;
1432
1433 if (netif_running(dev)) {
1434 /* Update the error counts. */
1435 ep->stats.rx_missed_errors += inb(ioaddr + MPCNT);
1436 ep->stats.rx_frame_errors += inb(ioaddr + ALICNT);
1437 ep->stats.rx_crc_errors += inb(ioaddr + CRCCNT);
1438 }
1439
1440 return &ep->stats;
1441 }
1442
1443 /* Set or clear the multicast filter for this adaptor.
1444 Note that we only use exclusion around actually queueing the
1445 new frame, not around filling ep->setup_frame. This is non-deterministic
1446 when re-entered but still correct. */
1447
1448 static void set_rx_mode(struct net_device *dev)
1449 {
1450 long ioaddr = dev->base_addr;
1451 struct epic_private *ep = dev->priv;
1452 unsigned char mc_filter[8]; /* Multicast hash filter */
1453 int i;
1454
1455 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1456 outl(0x002C, ioaddr + RxCtrl);
1457 /* Unconditionally log net taps. */
1458 printk(KERN_INFO "%s: Promiscuous mode enabled.\n", dev->name);
1459 memset(mc_filter, 0xff, sizeof(mc_filter));
1460 } else if ((dev->mc_count > 0) || (dev->flags & IFF_ALLMULTI)) {
1461 /* There is apparently a chip bug, so the multicast filter
1462 is never enabled. */
1463 /* Too many to filter perfectly -- accept all multicasts. */
1464 memset(mc_filter, 0xff, sizeof(mc_filter));
1465 outl(0x000C, ioaddr + RxCtrl);
1466 } else if (dev->mc_count == 0) {
1467 outl(0x0004, ioaddr + RxCtrl);
1468 return;
1469 } else { /* Never executed, for now. */
1470 struct dev_mc_list *mclist;
1471
1472 memset(mc_filter, 0, sizeof(mc_filter));
1473 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1474 i++, mclist = mclist->next) {
1475 unsigned int bit_nr =
1476 ether_crc_le(ETH_ALEN, mclist->dmi_addr) & 0x3f;
1477 mc_filter[bit_nr >> 3] |= (1 << bit_nr);
1478 }
1479 }
1480 /* ToDo: perhaps we need to stop the Tx and Rx process here? */
1481 if (memcmp(mc_filter, ep->mc_filter, sizeof(mc_filter))) {
1482 for (i = 0; i < 4; i++)
1483 outw(((u16 *)mc_filter)[i], ioaddr + MC0 + i*4);
1484 memcpy(ep->mc_filter, mc_filter, sizeof(mc_filter));
1485 }
1486 return;
1487 }
1488
1489 static void netdev_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1490 {
1491 struct epic_private *np = dev->priv;
1492
1493 strcpy (info->driver, DRV_NAME);
1494 strcpy (info->version, DRV_VERSION);
1495 strcpy (info->bus_info, pci_name(np->pci_dev));
1496 }
1497
1498 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1499 {
1500 struct epic_private *np = dev->priv;
1501 int rc;
1502
1503 spin_lock_irq(&np->lock);
1504 rc = mii_ethtool_gset(&np->mii, cmd);
1505 spin_unlock_irq(&np->lock);
1506
1507 return rc;
1508 }
1509
1510 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1511 {
1512 struct epic_private *np = dev->priv;
1513 int rc;
1514
1515 spin_lock_irq(&np->lock);
1516 rc = mii_ethtool_sset(&np->mii, cmd);
1517 spin_unlock_irq(&np->lock);
1518
1519 return rc;
1520 }
1521
1522 static int netdev_nway_reset(struct net_device *dev)
1523 {
1524 struct epic_private *np = dev->priv;
1525 return mii_nway_restart(&np->mii);
1526 }
1527
1528 static u32 netdev_get_link(struct net_device *dev)
1529 {
1530 struct epic_private *np = dev->priv;
1531 return mii_link_ok(&np->mii);
1532 }
1533
1534 static u32 netdev_get_msglevel(struct net_device *dev)
1535 {
1536 return debug;
1537 }
1538
1539 static void netdev_set_msglevel(struct net_device *dev, u32 value)
1540 {
1541 debug = value;
1542 }
1543
1544 static int ethtool_begin(struct net_device *dev)
1545 {
1546 unsigned long ioaddr = dev->base_addr;
1547 /* power-up, if interface is down */
1548 if (! netif_running(dev)) {
1549 outl(0x0200, ioaddr + GENCTL);
1550 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
1551 }
1552 return 0;
1553 }
1554
1555 static void ethtool_complete(struct net_device *dev)
1556 {
1557 unsigned long ioaddr = dev->base_addr;
1558 /* power-down, if interface is down */
1559 if (! netif_running(dev)) {
1560 outl(0x0008, ioaddr + GENCTL);
1561 outl((inl(ioaddr + NVCTL) & ~0x483C) | 0x0000, ioaddr + NVCTL);
1562 }
1563 }
1564
1565 static struct ethtool_ops netdev_ethtool_ops = {
1566 .get_drvinfo = netdev_get_drvinfo,
1567 .get_settings = netdev_get_settings,
1568 .set_settings = netdev_set_settings,
1569 .nway_reset = netdev_nway_reset,
1570 .get_link = netdev_get_link,
1571 .get_msglevel = netdev_get_msglevel,
1572 .set_msglevel = netdev_set_msglevel,
1573 .get_sg = ethtool_op_get_sg,
1574 .get_tx_csum = ethtool_op_get_tx_csum,
1575 .begin = ethtool_begin,
1576 .complete = ethtool_complete
1577 };
1578
1579 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1580 {
1581 struct epic_private *np = dev->priv;
1582 long ioaddr = dev->base_addr;
1583 struct mii_ioctl_data *data = if_mii(rq);
1584 int rc;
1585
1586 /* power-up, if interface is down */
1587 if (! netif_running(dev)) {
1588 outl(0x0200, ioaddr + GENCTL);
1589 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
1590 }
1591
1592 /* all non-ethtool ioctls (the SIOC[GS]MIIxxx ioctls) */
1593 spin_lock_irq(&np->lock);
1594 rc = generic_mii_ioctl(&np->mii, data, cmd, NULL);
1595 spin_unlock_irq(&np->lock);
1596
1597 /* power-down, if interface is down */
1598 if (! netif_running(dev)) {
1599 outl(0x0008, ioaddr + GENCTL);
1600 outl((inl(ioaddr + NVCTL) & ~0x483C) | 0x0000, ioaddr + NVCTL);
1601 }
1602 return rc;
1603 }
1604
1605
1606 static void __devexit epic_remove_one (struct pci_dev *pdev)
1607 {
1608 struct net_device *dev = pci_get_drvdata(pdev);
1609 struct epic_private *ep = dev->priv;
1610
1611 pci_free_consistent(pdev, TX_TOTAL_SIZE, ep->tx_ring, ep->tx_ring_dma);
1612 pci_free_consistent(pdev, RX_TOTAL_SIZE, ep->rx_ring, ep->rx_ring_dma);
1613 unregister_netdev(dev);
1614 #ifndef USE_IO_OPS
1615 iounmap((void*) dev->base_addr);
1616 #endif
1617 pci_release_regions(pdev);
1618 free_netdev(dev);
1619 pci_disable_device(pdev);
1620 pci_set_drvdata(pdev, NULL);
1621 /* pci_power_off(pdev, -1); */
1622 }
1623
1624
1625 #ifdef CONFIG_PM
1626
1627 static int epic_suspend (struct pci_dev *pdev, u32 state)
1628 {
1629 struct net_device *dev = pci_get_drvdata(pdev);
1630 long ioaddr = dev->base_addr;
1631
1632 if (!netif_running(dev))
1633 return 0;
1634 epic_pause(dev);
1635 /* Put the chip into low-power mode. */
1636 outl(0x0008, ioaddr + GENCTL);
1637 /* pci_power_off(pdev, -1); */
1638 return 0;
1639 }
1640
1641
1642 static int epic_resume (struct pci_dev *pdev)
1643 {
1644 struct net_device *dev = pci_get_drvdata(pdev);
1645
1646 if (!netif_running(dev))
1647 return 0;
1648 epic_restart(dev);
1649 /* pci_power_on(pdev); */
1650 return 0;
1651 }
1652
1653 #endif /* CONFIG_PM */
1654
1655
1656 static struct pci_driver epic_driver = {
1657 .name = DRV_NAME,
1658 .id_table = epic_pci_tbl,
1659 .probe = epic_init_one,
1660 .remove = __devexit_p(epic_remove_one),
1661 #ifdef CONFIG_PM
1662 .suspend = epic_suspend,
1663 .resume = epic_resume,
1664 #endif /* CONFIG_PM */
1665 };
1666
1667
1668 static int __init epic_init (void)
1669 {
1670 /* when a module, this is printed whether or not devices are found in probe */
1671 #ifdef MODULE
1672 printk (KERN_INFO "%s" KERN_INFO "%s" KERN_INFO "%s",
1673 version, version2, version3);
1674 #endif
1675
1676 return pci_module_init (&epic_driver);
1677 }
1678
1679
1680 static void __exit epic_cleanup (void)
1681 {
1682 pci_unregister_driver (&epic_driver);
1683 }
1684
1685
1686 module_init(epic_init);
1687 module_exit(epic_cleanup);
1688
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