1 /*******************************************************************************
2
3
4 Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
9 any later version.
10
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19
20 The full GNU General Public License is included in this distribution in the
21 file called LICENSE.
22
23 Contact Information:
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29
30 /* glue for the OS independent part of e1000
31 * includes register access macros
32 */
33
34 #ifndef _E1000_OSDEP_H_
35 #define _E1000_OSDEP_H_
36
37 #include <linux/types.h>
38 #include <linux/pci.h>
39 #include <linux/delay.h>
40 #include <asm/io.h>
41 #include <linux/interrupt.h>
42 #include <linux/sched.h>
43
44 #ifndef msec_delay
45 #define msec_delay(x) msleep(x)
46
47 /* Some workarounds require millisecond delays and are run during interrupt
48 * context. Most notably, when establishing link, the phy may need tweaking
49 * but cannot process phy register reads/writes faster than millisecond
50 * intervals...and we establish link due to a "link status change" interrupt.
51 */
52 #define msec_delay_irq(x) mdelay(x)
53 #endif
54
55 #define PCI_COMMAND_REGISTER PCI_COMMAND
56 #define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE
57
58 typedef enum {
59 #undef FALSE
60 FALSE = 0,
61 #undef TRUE
62 TRUE = 1
63 } boolean_t;
64
65 #define MSGOUT(S, A, B) printk(KERN_DEBUG S "\n", A, B)
66
67 #ifdef DBG
68 #define DEBUGOUT(S) printk(KERN_DEBUG S "\n")
69 #define DEBUGOUT1(S, A...) printk(KERN_DEBUG S "\n", A)
70 #else
71 #define DEBUGOUT(S)
72 #define DEBUGOUT1(S, A...)
73 #endif
74
75 #define DEBUGFUNC(F) DEBUGOUT(F)
76 #define DEBUGOUT2 DEBUGOUT1
77 #define DEBUGOUT3 DEBUGOUT2
78 #define DEBUGOUT7 DEBUGOUT3
79
80
81 #define E1000_WRITE_REG(a, reg, value) ( \
82 writel((value), ((a)->hw_addr + \
83 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg))))
84
85 #define E1000_READ_REG(a, reg) ( \
86 readl((a)->hw_addr + \
87 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg)))
88
89 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \
90 writel((value), ((a)->hw_addr + \
91 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
92 ((offset) << 2))))
93
94 #define E1000_READ_REG_ARRAY(a, reg, offset) ( \
95 readl((a)->hw_addr + \
96 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
97 ((offset) << 2)))
98
99 #define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, STATUS)
100
101 #endif /* _E1000_OSDEP_H_ */
102
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