1 /*******************************************************************************
2
3 Intel PRO/100 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /*
30 * e100.c: Intel(R) PRO/100 ethernet driver
31 *
32 * (Re)written 2003 by scott.feldman@intel.com. Based loosely on
33 * original e100 driver, but better described as a munging of
34 * e100, e1000, eepro100, tg3, 8139cp, and other drivers.
35 *
36 * References:
37 * Intel 8255x 10/100 Mbps Ethernet Controller Family,
38 * Open Source Software Developers Manual,
39 * http://sourceforge.net/projects/e1000
40 *
41 *
42 * Theory of Operation
43 *
44 * I. General
45 *
46 * The driver supports Intel(R) 10/100 Mbps PCI Fast Ethernet
47 * controller family, which includes the 82557, 82558, 82559, 82550,
48 * 82551, and 82562 devices. 82558 and greater controllers
49 * integrate the Intel 82555 PHY. The controllers are used in
50 * server and client network interface cards, as well as in
51 * LAN-On-Motherboard (LOM), CardBus, MiniPCI, and ICHx
52 * configurations. 8255x supports a 32-bit linear addressing
53 * mode and operates at 33Mhz PCI clock rate.
54 *
55 * II. Driver Operation
56 *
57 * Memory-mapped mode is used exclusively to access the device's
58 * shared-memory structure, the Control/Status Registers (CSR). All
59 * setup, configuration, and control of the device, including queuing
60 * of Tx, Rx, and configuration commands is through the CSR.
61 * cmd_lock serializes accesses to the CSR command register. cb_lock
62 * protects the shared Command Block List (CBL).
63 *
64 * 8255x is highly MII-compliant and all access to the PHY go
65 * through the Management Data Interface (MDI). Consequently, the
66 * driver leverages the mii.c library shared with other MII-compliant
67 * devices.
68 *
69 * Big- and Little-Endian byte order as well as 32- and 64-bit
70 * archs are supported. Weak-ordered memory and non-cache-coherent
71 * archs are supported.
72 *
73 * III. Transmit
74 *
75 * A Tx skb is mapped and hangs off of a TCB. TCBs are linked
76 * together in a fixed-size ring (CBL) thus forming the flexible mode
77 * memory structure. A TCB marked with the suspend-bit indicates
78 * the end of the ring. The last TCB processed suspends the
79 * controller, and the controller can be restarted by issue a CU
80 * resume command to continue from the suspend point, or a CU start
81 * command to start at a given position in the ring.
82 *
83 * Non-Tx commands (config, multicast setup, etc) are linked
84 * into the CBL ring along with Tx commands. The common structure
85 * used for both Tx and non-Tx commands is the Command Block (CB).
86 *
87 * cb_to_use is the next CB to use for queuing a command; cb_to_clean
88 * is the next CB to check for completion; cb_to_send is the first
89 * CB to start on in case of a previous failure to resume. CB clean
90 * up happens in interrupt context in response to a CU interrupt.
91 * cbs_avail keeps track of number of free CB resources available.
92 *
93 * Hardware padding of short packets to minimum packet size is
94 * enabled. 82557 pads with 7Eh, while the later controllers pad
95 * with 00h.
96 *
97 * IV. Receive
98 *
99 * The Receive Frame Area (RFA) comprises a ring of Receive Frame
100 * Descriptors (RFD) + data buffer, thus forming the simplified mode
101 * memory structure. Rx skbs are allocated to contain both the RFD
102 * and the data buffer, but the RFD is pulled off before the skb is
103 * indicated. The data buffer is aligned such that encapsulated
104 * protocol headers are u32-aligned. Since the RFD is part of the
105 * mapped shared memory, and completion status is contained within
106 * the RFD, the RFD must be dma_sync'ed to maintain a consistent
107 * view from software and hardware.
108 *
109 * In order to keep updates to the RFD link field from colliding with
110 * hardware writes to mark packets complete, we use the feature that
111 * hardware will not write to a size 0 descriptor and mark the previous
112 * packet as end-of-list (EL). After updating the link, we remove EL
113 * and only then restore the size such that hardware may use the
114 * previous-to-end RFD.
115 *
116 * Under typical operation, the receive unit (RU) is start once,
117 * and the controller happily fills RFDs as frames arrive. If
118 * replacement RFDs cannot be allocated, or the RU goes non-active,
119 * the RU must be restarted. Frame arrival generates an interrupt,
120 * and Rx indication and re-allocation happen in the same context,
121 * therefore no locking is required. A software-generated interrupt
122 * is generated from the watchdog to recover from a failed allocation
123 * scenario where all Rx resources have been indicated and none re-
124 * placed.
125 *
126 * V. Miscellaneous
127 *
128 * VLAN offloading of tagging, stripping and filtering is not
129 * supported, but driver will accommodate the extra 4-byte VLAN tag
130 * for processing by upper layers. Tx/Rx Checksum offloading is not
131 * supported. Tx Scatter/Gather is not supported. Jumbo Frames is
132 * not supported (hardware limitation).
133 *
134 * MagicPacket(tm) WoL support is enabled/disabled via ethtool.
135 *
136 * Thanks to JC (jchapman@katalix.com) for helping with
137 * testing/troubleshooting the development driver.
138 *
139 * TODO:
140 * o several entry points race with dev->close
141 * o check for tx-no-resources/stop Q races with tx clean/wake Q
142 *
143 * FIXES:
144 * 2005/12/02 - Michael O'Donnell <Michael.ODonnell at stratus dot com>
145 * - Stratus87247: protect MDI control register manipulations
146 * 2009/06/01 - Andreas Mohr <andi at lisas dot de>
147 * - add clean lowlevel I/O emulation for cards with MII-lacking PHYs
148 */
149
150 #include <linux/module.h>
151 #include <linux/moduleparam.h>
152 #include <linux/kernel.h>
153 #include <linux/types.h>
154 #include <linux/slab.h>
155 #include <linux/delay.h>
156 #include <linux/init.h>
157 #include <linux/pci.h>
158 #include <linux/dma-mapping.h>
159 #include <linux/dmapool.h>
160 #include <linux/netdevice.h>
161 #include <linux/etherdevice.h>
162 #include <linux/mii.h>
163 #include <linux/if_vlan.h>
164 #include <linux/skbuff.h>
165 #include <linux/ethtool.h>
166 #include <linux/string.h>
167 #include <linux/firmware.h>
168 #include <asm/unaligned.h>
169
170
171 #define DRV_NAME "e100"
172 #define DRV_EXT "-NAPI"
173 #define DRV_VERSION "3.5.24-k2"DRV_EXT
174 #define DRV_DESCRIPTION "Intel(R) PRO/100 Network Driver"
175 #define DRV_COPYRIGHT "Copyright(c) 1999-2006 Intel Corporation"
176 #define PFX DRV_NAME ": "
177
178 #define E100_WATCHDOG_PERIOD (2 * HZ)
179 #define E100_NAPI_WEIGHT 16
180
181 #define FIRMWARE_D101M "e100/d101m_ucode.bin"
182 #define FIRMWARE_D101S "e100/d101s_ucode.bin"
183 #define FIRMWARE_D102E "e100/d102e_ucode.bin"
184
185 MODULE_DESCRIPTION(DRV_DESCRIPTION);
186 MODULE_AUTHOR(DRV_COPYRIGHT);
187 MODULE_LICENSE("GPL");
188 MODULE_VERSION(DRV_VERSION);
189 MODULE_FIRMWARE(FIRMWARE_D101M);
190 MODULE_FIRMWARE(FIRMWARE_D101S);
191 MODULE_FIRMWARE(FIRMWARE_D102E);
192
193 static int debug = 3;
194 static int eeprom_bad_csum_allow = 0;
195 static int use_io = 0;
196 module_param(debug, int, 0);
197 module_param(eeprom_bad_csum_allow, int, 0);
198 module_param(use_io, int, 0);
199 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
200 MODULE_PARM_DESC(eeprom_bad_csum_allow, "Allow bad eeprom checksums");
201 MODULE_PARM_DESC(use_io, "Force use of i/o access mode");
202 #define DPRINTK(nlevel, klevel, fmt, args...) \
203 (void)((NETIF_MSG_##nlevel & nic->msg_enable) && \
204 printk(KERN_##klevel PFX "%s: %s: " fmt, nic->netdev->name, \
205 __func__ , ## args))
206
207 #define INTEL_8255X_ETHERNET_DEVICE(device_id, ich) {\
208 PCI_VENDOR_ID_INTEL, device_id, PCI_ANY_ID, PCI_ANY_ID, \
209 PCI_CLASS_NETWORK_ETHERNET << 8, 0xFFFF00, ich }
210 static struct pci_device_id e100_id_table[] = {
211 INTEL_8255X_ETHERNET_DEVICE(0x1029, 0),
212 INTEL_8255X_ETHERNET_DEVICE(0x1030, 0),
213 INTEL_8255X_ETHERNET_DEVICE(0x1031, 3),
214 INTEL_8255X_ETHERNET_DEVICE(0x1032, 3),
215 INTEL_8255X_ETHERNET_DEVICE(0x1033, 3),
216 INTEL_8255X_ETHERNET_DEVICE(0x1034, 3),
217 INTEL_8255X_ETHERNET_DEVICE(0x1038, 3),
218 INTEL_8255X_ETHERNET_DEVICE(0x1039, 4),
219 INTEL_8255X_ETHERNET_DEVICE(0x103A, 4),
220 INTEL_8255X_ETHERNET_DEVICE(0x103B, 4),
221 INTEL_8255X_ETHERNET_DEVICE(0x103C, 4),
222 INTEL_8255X_ETHERNET_DEVICE(0x103D, 4),
223 INTEL_8255X_ETHERNET_DEVICE(0x103E, 4),
224 INTEL_8255X_ETHERNET_DEVICE(0x1050, 5),
225 INTEL_8255X_ETHERNET_DEVICE(0x1051, 5),
226 INTEL_8255X_ETHERNET_DEVICE(0x1052, 5),
227 INTEL_8255X_ETHERNET_DEVICE(0x1053, 5),
228 INTEL_8255X_ETHERNET_DEVICE(0x1054, 5),
229 INTEL_8255X_ETHERNET_DEVICE(0x1055, 5),
230 INTEL_8255X_ETHERNET_DEVICE(0x1056, 5),
231 INTEL_8255X_ETHERNET_DEVICE(0x1057, 5),
232 INTEL_8255X_ETHERNET_DEVICE(0x1059, 0),
233 INTEL_8255X_ETHERNET_DEVICE(0x1064, 6),
234 INTEL_8255X_ETHERNET_DEVICE(0x1065, 6),
235 INTEL_8255X_ETHERNET_DEVICE(0x1066, 6),
236 INTEL_8255X_ETHERNET_DEVICE(0x1067, 6),
237 INTEL_8255X_ETHERNET_DEVICE(0x1068, 6),
238 INTEL_8255X_ETHERNET_DEVICE(0x1069, 6),
239 INTEL_8255X_ETHERNET_DEVICE(0x106A, 6),
240 INTEL_8255X_ETHERNET_DEVICE(0x106B, 6),
241 INTEL_8255X_ETHERNET_DEVICE(0x1091, 7),
242 INTEL_8255X_ETHERNET_DEVICE(0x1092, 7),
243 INTEL_8255X_ETHERNET_DEVICE(0x1093, 7),
244 INTEL_8255X_ETHERNET_DEVICE(0x1094, 7),
245 INTEL_8255X_ETHERNET_DEVICE(0x1095, 7),
246 INTEL_8255X_ETHERNET_DEVICE(0x10fe, 7),
247 INTEL_8255X_ETHERNET_DEVICE(0x1209, 0),
248 INTEL_8255X_ETHERNET_DEVICE(0x1229, 0),
249 INTEL_8255X_ETHERNET_DEVICE(0x2449, 2),
250 INTEL_8255X_ETHERNET_DEVICE(0x2459, 2),
251 INTEL_8255X_ETHERNET_DEVICE(0x245D, 2),
252 INTEL_8255X_ETHERNET_DEVICE(0x27DC, 7),
253 { 0, }
254 };
255 MODULE_DEVICE_TABLE(pci, e100_id_table);
256
257 enum mac {
258 mac_82557_D100_A = 0,
259 mac_82557_D100_B = 1,
260 mac_82557_D100_C = 2,
261 mac_82558_D101_A4 = 4,
262 mac_82558_D101_B0 = 5,
263 mac_82559_D101M = 8,
264 mac_82559_D101S = 9,
265 mac_82550_D102 = 12,
266 mac_82550_D102_C = 13,
267 mac_82551_E = 14,
268 mac_82551_F = 15,
269 mac_82551_10 = 16,
270 mac_unknown = 0xFF,
271 };
272
273 enum phy {
274 phy_100a = 0x000003E0,
275 phy_100c = 0x035002A8,
276 phy_82555_tx = 0x015002A8,
277 phy_nsc_tx = 0x5C002000,
278 phy_82562_et = 0x033002A8,
279 phy_82562_em = 0x032002A8,
280 phy_82562_ek = 0x031002A8,
281 phy_82562_eh = 0x017002A8,
282 phy_82552_v = 0xd061004d,
283 phy_unknown = 0xFFFFFFFF,
284 };
285
286 /* CSR (Control/Status Registers) */
287 struct csr {
288 struct {
289 u8 status;
290 u8 stat_ack;
291 u8 cmd_lo;
292 u8 cmd_hi;
293 u32 gen_ptr;
294 } scb;
295 u32 port;
296 u16 flash_ctrl;
297 u8 eeprom_ctrl_lo;
298 u8 eeprom_ctrl_hi;
299 u32 mdi_ctrl;
300 u32 rx_dma_count;
301 };
302
303 enum scb_status {
304 rus_no_res = 0x08,
305 rus_ready = 0x10,
306 rus_mask = 0x3C,
307 };
308
309 enum ru_state {
310 RU_SUSPENDED = 0,
311 RU_RUNNING = 1,
312 RU_UNINITIALIZED = -1,
313 };
314
315 enum scb_stat_ack {
316 stat_ack_not_ours = 0x00,
317 stat_ack_sw_gen = 0x04,
318 stat_ack_rnr = 0x10,
319 stat_ack_cu_idle = 0x20,
320 stat_ack_frame_rx = 0x40,
321 stat_ack_cu_cmd_done = 0x80,
322 stat_ack_not_present = 0xFF,
323 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
324 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
325 };
326
327 enum scb_cmd_hi {
328 irq_mask_none = 0x00,
329 irq_mask_all = 0x01,
330 irq_sw_gen = 0x02,
331 };
332
333 enum scb_cmd_lo {
334 cuc_nop = 0x00,
335 ruc_start = 0x01,
336 ruc_load_base = 0x06,
337 cuc_start = 0x10,
338 cuc_resume = 0x20,
339 cuc_dump_addr = 0x40,
340 cuc_dump_stats = 0x50,
341 cuc_load_base = 0x60,
342 cuc_dump_reset = 0x70,
343 };
344
345 enum cuc_dump {
346 cuc_dump_complete = 0x0000A005,
347 cuc_dump_reset_complete = 0x0000A007,
348 };
349
350 enum port {
351 software_reset = 0x0000,
352 selftest = 0x0001,
353 selective_reset = 0x0002,
354 };
355
356 enum eeprom_ctrl_lo {
357 eesk = 0x01,
358 eecs = 0x02,
359 eedi = 0x04,
360 eedo = 0x08,
361 };
362
363 enum mdi_ctrl {
364 mdi_write = 0x04000000,
365 mdi_read = 0x08000000,
366 mdi_ready = 0x10000000,
367 };
368
369 enum eeprom_op {
370 op_write = 0x05,
371 op_read = 0x06,
372 op_ewds = 0x10,
373 op_ewen = 0x13,
374 };
375
376 enum eeprom_offsets {
377 eeprom_cnfg_mdix = 0x03,
378 eeprom_phy_iface = 0x06,
379 eeprom_id = 0x0A,
380 eeprom_config_asf = 0x0D,
381 eeprom_smbus_addr = 0x90,
382 };
383
384 enum eeprom_cnfg_mdix {
385 eeprom_mdix_enabled = 0x0080,
386 };
387
388 enum eeprom_phy_iface {
389 NoSuchPhy = 0,
390 I82553AB,
391 I82553C,
392 I82503,
393 DP83840,
394 S80C240,
395 S80C24,
396 I82555,
397 DP83840A = 10,
398 };
399
400 enum eeprom_id {
401 eeprom_id_wol = 0x0020,
402 };
403
404 enum eeprom_config_asf {
405 eeprom_asf = 0x8000,
406 eeprom_gcl = 0x4000,
407 };
408
409 enum cb_status {
410 cb_complete = 0x8000,
411 cb_ok = 0x2000,
412 };
413
414 enum cb_command {
415 cb_nop = 0x0000,
416 cb_iaaddr = 0x0001,
417 cb_config = 0x0002,
418 cb_multi = 0x0003,
419 cb_tx = 0x0004,
420 cb_ucode = 0x0005,
421 cb_dump = 0x0006,
422 cb_tx_sf = 0x0008,
423 cb_cid = 0x1f00,
424 cb_i = 0x2000,
425 cb_s = 0x4000,
426 cb_el = 0x8000,
427 };
428
429 struct rfd {
430 __le16 status;
431 __le16 command;
432 __le32 link;
433 __le32 rbd;
434 __le16 actual_size;
435 __le16 size;
436 };
437
438 struct rx {
439 struct rx *next, *prev;
440 struct sk_buff *skb;
441 dma_addr_t dma_addr;
442 };
443
444 #if defined(__BIG_ENDIAN_BITFIELD)
445 #define X(a,b) b,a
446 #else
447 #define X(a,b) a,b
448 #endif
449 struct config {
450 /**/ u8 X(byte_count:6, pad0:2);
451 /*1*/ u8 X(X(rx_fifo_limit:4, tx_fifo_limit:3), pad1:1);
452 /*2*/ u8 adaptive_ifs;
453 /*3*/ u8 X(X(X(X(mwi_enable:1, type_enable:1), read_align_enable:1),
454 term_write_cache_line:1), pad3:4);
455 /*4*/ u8 X(rx_dma_max_count:7, pad4:1);
456 /*5*/ u8 X(tx_dma_max_count:7, dma_max_count_enable:1);
457 /*6*/ u8 X(X(X(X(X(X(X(late_scb_update:1, direct_rx_dma:1),
458 tno_intr:1), cna_intr:1), standard_tcb:1), standard_stat_counter:1),
459 rx_discard_overruns:1), rx_save_bad_frames:1);
460 /*7*/ u8 X(X(X(X(X(rx_discard_short_frames:1, tx_underrun_retry:2),
461 pad7:2), rx_extended_rfd:1), tx_two_frames_in_fifo:1),
462 tx_dynamic_tbd:1);
463 /*8*/ u8 X(X(mii_mode:1, pad8:6), csma_disabled:1);
464 /*9*/ u8 X(X(X(X(X(rx_tcpudp_checksum:1, pad9:3), vlan_arp_tco:1),
465 link_status_wake:1), arp_wake:1), mcmatch_wake:1);
466 /*10*/ u8 X(X(X(pad10:3, no_source_addr_insertion:1), preamble_length:2),
467 loopback:2);
468 /*11*/ u8 X(linear_priority:3, pad11:5);
469 /*12*/ u8 X(X(linear_priority_mode:1, pad12:3), ifs:4);
470 /*13*/ u8 ip_addr_lo;
471 /*14*/ u8 ip_addr_hi;
472 /*15*/ u8 X(X(X(X(X(X(X(promiscuous_mode:1, broadcast_disabled:1),
473 wait_after_win:1), pad15_1:1), ignore_ul_bit:1), crc_16_bit:1),
474 pad15_2:1), crs_or_cdt:1);
475 /*16*/ u8 fc_delay_lo;
476 /*17*/ u8 fc_delay_hi;
477 /*18*/ u8 X(X(X(X(X(rx_stripping:1, tx_padding:1), rx_crc_transfer:1),
478 rx_long_ok:1), fc_priority_threshold:3), pad18:1);
479 /*19*/ u8 X(X(X(X(X(X(X(addr_wake:1, magic_packet_disable:1),
480 fc_disable:1), fc_restop:1), fc_restart:1), fc_reject:1),
481 full_duplex_force:1), full_duplex_pin:1);
482 /*20*/ u8 X(X(X(pad20_1:5, fc_priority_location:1), multi_ia:1), pad20_2:1);
483 /*21*/ u8 X(X(pad21_1:3, multicast_all:1), pad21_2:4);
484 /*22*/ u8 X(X(rx_d102_mode:1, rx_vlan_drop:1), pad22:6);
485 u8 pad_d102[9];
486 };
487
488 #define E100_MAX_MULTICAST_ADDRS 64
489 struct multi {
490 __le16 count;
491 u8 addr[E100_MAX_MULTICAST_ADDRS * ETH_ALEN + 2/*pad*/];
492 };
493
494 /* Important: keep total struct u32-aligned */
495 #define UCODE_SIZE 134
496 struct cb {
497 __le16 status;
498 __le16 command;
499 __le32 link;
500 union {
501 u8 iaaddr[ETH_ALEN];
502 __le32 ucode[UCODE_SIZE];
503 struct config config;
504 struct multi multi;
505 struct {
506 u32 tbd_array;
507 u16 tcb_byte_count;
508 u8 threshold;
509 u8 tbd_count;
510 struct {
511 __le32 buf_addr;
512 __le16 size;
513 u16 eol;
514 } tbd;
515 } tcb;
516 __le32 dump_buffer_addr;
517 } u;
518 struct cb *next, *prev;
519 dma_addr_t dma_addr;
520 struct sk_buff *skb;
521 };
522
523 enum loopback {
524 lb_none = 0, lb_mac = 1, lb_phy = 3,
525 };
526
527 struct stats {
528 __le32 tx_good_frames, tx_max_collisions, tx_late_collisions,
529 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
530 tx_multiple_collisions, tx_total_collisions;
531 __le32 rx_good_frames, rx_crc_errors, rx_alignment_errors,
532 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
533 rx_short_frame_errors;
534 __le32 fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
535 __le16 xmt_tco_frames, rcv_tco_frames;
536 __le32 complete;
537 };
538
539 struct mem {
540 struct {
541 u32 signature;
542 u32 result;
543 } selftest;
544 struct stats stats;
545 u8 dump_buf[596];
546 };
547
548 struct param_range {
549 u32 min;
550 u32 max;
551 u32 count;
552 };
553
554 struct params {
555 struct param_range rfds;
556 struct param_range cbs;
557 };
558
559 struct nic {
560 /* Begin: frequently used values: keep adjacent for cache effect */
561 u32 msg_enable ____cacheline_aligned;
562 struct net_device *netdev;
563 struct pci_dev *pdev;
564 u16 (*mdio_ctrl)(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data);
565
566 struct rx *rxs ____cacheline_aligned;
567 struct rx *rx_to_use;
568 struct rx *rx_to_clean;
569 struct rfd blank_rfd;
570 enum ru_state ru_running;
571
572 spinlock_t cb_lock ____cacheline_aligned;
573 spinlock_t cmd_lock;
574 struct csr __iomem *csr;
575 enum scb_cmd_lo cuc_cmd;
576 unsigned int cbs_avail;
577 struct napi_struct napi;
578 struct cb *cbs;
579 struct cb *cb_to_use;
580 struct cb *cb_to_send;
581 struct cb *cb_to_clean;
582 __le16 tx_command;
583 /* End: frequently used values: keep adjacent for cache effect */
584
585 enum {
586 ich = (1 << 0),
587 promiscuous = (1 << 1),
588 multicast_all = (1 << 2),
589 wol_magic = (1 << 3),
590 ich_10h_workaround = (1 << 4),
591 } flags ____cacheline_aligned;
592
593 enum mac mac;
594 enum phy phy;
595 struct params params;
596 struct timer_list watchdog;
597 struct timer_list blink_timer;
598 struct mii_if_info mii;
599 struct work_struct tx_timeout_task;
600 enum loopback loopback;
601
602 struct mem *mem;
603 dma_addr_t dma_addr;
604
605 struct pci_pool *cbs_pool;
606 dma_addr_t cbs_dma_addr;
607 u8 adaptive_ifs;
608 u8 tx_threshold;
609 u32 tx_frames;
610 u32 tx_collisions;
611 u32 tx_deferred;
612 u32 tx_single_collisions;
613 u32 tx_multiple_collisions;
614 u32 tx_fc_pause;
615 u32 tx_tco_frames;
616
617 u32 rx_fc_pause;
618 u32 rx_fc_unsupported;
619 u32 rx_tco_frames;
620 u32 rx_over_length_errors;
621
622 u16 leds;
623 u16 eeprom_wc;
624 __le16 eeprom[256];
625 spinlock_t mdio_lock;
626 };
627
628 static inline void e100_write_flush(struct nic *nic)
629 {
630 /* Flush previous PCI writes through intermediate bridges
631 * by doing a benign read */
632 (void)ioread8(&nic->csr->scb.status);
633 }
634
635 static void e100_enable_irq(struct nic *nic)
636 {
637 unsigned long flags;
638
639 spin_lock_irqsave(&nic->cmd_lock, flags);
640 iowrite8(irq_mask_none, &nic->csr->scb.cmd_hi);
641 e100_write_flush(nic);
642 spin_unlock_irqrestore(&nic->cmd_lock, flags);
643 }
644
645 static void e100_disable_irq(struct nic *nic)
646 {
647 unsigned long flags;
648
649 spin_lock_irqsave(&nic->cmd_lock, flags);
650 iowrite8(irq_mask_all, &nic->csr->scb.cmd_hi);
651 e100_write_flush(nic);
652 spin_unlock_irqrestore(&nic->cmd_lock, flags);
653 }
654
655 static void e100_hw_reset(struct nic *nic)
656 {
657 /* Put CU and RU into idle with a selective reset to get
658 * device off of PCI bus */
659 iowrite32(selective_reset, &nic->csr->port);
660 e100_write_flush(nic); udelay(20);
661
662 /* Now fully reset device */
663 iowrite32(software_reset, &nic->csr->port);
664 e100_write_flush(nic); udelay(20);
665
666 /* Mask off our interrupt line - it's unmasked after reset */
667 e100_disable_irq(nic);
668 }
669
670 static int e100_self_test(struct nic *nic)
671 {
672 u32 dma_addr = nic->dma_addr + offsetof(struct mem, selftest);
673
674 /* Passing the self-test is a pretty good indication
675 * that the device can DMA to/from host memory */
676
677 nic->mem->selftest.signature = 0;
678 nic->mem->selftest.result = 0xFFFFFFFF;
679
680 iowrite32(selftest | dma_addr, &nic->csr->port);
681 e100_write_flush(nic);
682 /* Wait 10 msec for self-test to complete */
683 msleep(10);
684
685 /* Interrupts are enabled after self-test */
686 e100_disable_irq(nic);
687
688 /* Check results of self-test */
689 if (nic->mem->selftest.result != 0) {
690 DPRINTK(HW, ERR, "Self-test failed: result=0x%08X\n",
691 nic->mem->selftest.result);
692 return -ETIMEDOUT;
693 }
694 if (nic->mem->selftest.signature == 0) {
695 DPRINTK(HW, ERR, "Self-test failed: timed out\n");
696 return -ETIMEDOUT;
697 }
698
699 return 0;
700 }
701
702 static void e100_eeprom_write(struct nic *nic, u16 addr_len, u16 addr, __le16 data)
703 {
704 u32 cmd_addr_data[3];
705 u8 ctrl;
706 int i, j;
707
708 /* Three cmds: write/erase enable, write data, write/erase disable */
709 cmd_addr_data[0] = op_ewen << (addr_len - 2);
710 cmd_addr_data[1] = (((op_write << addr_len) | addr) << 16) |
711 le16_to_cpu(data);
712 cmd_addr_data[2] = op_ewds << (addr_len - 2);
713
714 /* Bit-bang cmds to write word to eeprom */
715 for (j = 0; j < 3; j++) {
716
717 /* Chip select */
718 iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
719 e100_write_flush(nic); udelay(4);
720
721 for (i = 31; i >= 0; i--) {
722 ctrl = (cmd_addr_data[j] & (1 << i)) ?
723 eecs | eedi : eecs;
724 iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo);
725 e100_write_flush(nic); udelay(4);
726
727 iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
728 e100_write_flush(nic); udelay(4);
729 }
730 /* Wait 10 msec for cmd to complete */
731 msleep(10);
732
733 /* Chip deselect */
734 iowrite8(0, &nic->csr->eeprom_ctrl_lo);
735 e100_write_flush(nic); udelay(4);
736 }
737 };
738
739 /* General technique stolen from the eepro100 driver - very clever */
740 static __le16 e100_eeprom_read(struct nic *nic, u16 *addr_len, u16 addr)
741 {
742 u32 cmd_addr_data;
743 u16 data = 0;
744 u8 ctrl;
745 int i;
746
747 cmd_addr_data = ((op_read << *addr_len) | addr) << 16;
748
749 /* Chip select */
750 iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
751 e100_write_flush(nic); udelay(4);
752
753 /* Bit-bang to read word from eeprom */
754 for (i = 31; i >= 0; i--) {
755 ctrl = (cmd_addr_data & (1 << i)) ? eecs | eedi : eecs;
756 iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo);
757 e100_write_flush(nic); udelay(4);
758
759 iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
760 e100_write_flush(nic); udelay(4);
761
762 /* Eeprom drives a dummy zero to EEDO after receiving
763 * complete address. Use this to adjust addr_len. */
764 ctrl = ioread8(&nic->csr->eeprom_ctrl_lo);
765 if (!(ctrl & eedo) && i > 16) {
766 *addr_len -= (i - 16);
767 i = 17;
768 }
769
770 data = (data << 1) | (ctrl & eedo ? 1 : 0);
771 }
772
773 /* Chip deselect */
774 iowrite8(0, &nic->csr->eeprom_ctrl_lo);
775 e100_write_flush(nic); udelay(4);
776
777 return cpu_to_le16(data);
778 };
779
780 /* Load entire EEPROM image into driver cache and validate checksum */
781 static int e100_eeprom_load(struct nic *nic)
782 {
783 u16 addr, addr_len = 8, checksum = 0;
784
785 /* Try reading with an 8-bit addr len to discover actual addr len */
786 e100_eeprom_read(nic, &addr_len, 0);
787 nic->eeprom_wc = 1 << addr_len;
788
789 for (addr = 0; addr < nic->eeprom_wc; addr++) {
790 nic->eeprom[addr] = e100_eeprom_read(nic, &addr_len, addr);
791 if (addr < nic->eeprom_wc - 1)
792 checksum += le16_to_cpu(nic->eeprom[addr]);
793 }
794
795 /* The checksum, stored in the last word, is calculated such that
796 * the sum of words should be 0xBABA */
797 if (cpu_to_le16(0xBABA - checksum) != nic->eeprom[nic->eeprom_wc - 1]) {
798 DPRINTK(PROBE, ERR, "EEPROM corrupted\n");
799 if (!eeprom_bad_csum_allow)
800 return -EAGAIN;
801 }
802
803 return 0;
804 }
805
806 /* Save (portion of) driver EEPROM cache to device and update checksum */
807 static int e100_eeprom_save(struct nic *nic, u16 start, u16 count)
808 {
809 u16 addr, addr_len = 8, checksum = 0;
810
811 /* Try reading with an 8-bit addr len to discover actual addr len */
812 e100_eeprom_read(nic, &addr_len, 0);
813 nic->eeprom_wc = 1 << addr_len;
814
815 if (start + count >= nic->eeprom_wc)
816 return -EINVAL;
817
818 for (addr = start; addr < start + count; addr++)
819 e100_eeprom_write(nic, addr_len, addr, nic->eeprom[addr]);
820
821 /* The checksum, stored in the last word, is calculated such that
822 * the sum of words should be 0xBABA */
823 for (addr = 0; addr < nic->eeprom_wc - 1; addr++)
824 checksum += le16_to_cpu(nic->eeprom[addr]);
825 nic->eeprom[nic->eeprom_wc - 1] = cpu_to_le16(0xBABA - checksum);
826 e100_eeprom_write(nic, addr_len, nic->eeprom_wc - 1,
827 nic->eeprom[nic->eeprom_wc - 1]);
828
829 return 0;
830 }
831
832 #define E100_WAIT_SCB_TIMEOUT 20000 /* we might have to wait 100ms!!! */
833 #define E100_WAIT_SCB_FAST 20 /* delay like the old code */
834 static int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr)
835 {
836 unsigned long flags;
837 unsigned int i;
838 int err = 0;
839
840 spin_lock_irqsave(&nic->cmd_lock, flags);
841
842 /* Previous command is accepted when SCB clears */
843 for (i = 0; i < E100_WAIT_SCB_TIMEOUT; i++) {
844 if (likely(!ioread8(&nic->csr->scb.cmd_lo)))
845 break;
846 cpu_relax();
847 if (unlikely(i > E100_WAIT_SCB_FAST))
848 udelay(5);
849 }
850 if (unlikely(i == E100_WAIT_SCB_TIMEOUT)) {
851 err = -EAGAIN;
852 goto err_unlock;
853 }
854
855 if (unlikely(cmd != cuc_resume))
856 iowrite32(dma_addr, &nic->csr->scb.gen_ptr);
857 iowrite8(cmd, &nic->csr->scb.cmd_lo);
858
859 err_unlock:
860 spin_unlock_irqrestore(&nic->cmd_lock, flags);
861
862 return err;
863 }
864
865 static int e100_exec_cb(struct nic *nic, struct sk_buff *skb,
866 void (*cb_prepare)(struct nic *, struct cb *, struct sk_buff *))
867 {
868 struct cb *cb;
869 unsigned long flags;
870 int err = 0;
871
872 spin_lock_irqsave(&nic->cb_lock, flags);
873
874 if (unlikely(!nic->cbs_avail)) {
875 err = -ENOMEM;
876 goto err_unlock;
877 }
878
879 cb = nic->cb_to_use;
880 nic->cb_to_use = cb->next;
881 nic->cbs_avail--;
882 cb->skb = skb;
883
884 if (unlikely(!nic->cbs_avail))
885 err = -ENOSPC;
886
887 cb_prepare(nic, cb, skb);
888
889 /* Order is important otherwise we'll be in a race with h/w:
890 * set S-bit in current first, then clear S-bit in previous. */
891 cb->command |= cpu_to_le16(cb_s);
892 wmb();
893 cb->prev->command &= cpu_to_le16(~cb_s);
894
895 while (nic->cb_to_send != nic->cb_to_use) {
896 if (unlikely(e100_exec_cmd(nic, nic->cuc_cmd,
897 nic->cb_to_send->dma_addr))) {
898 /* Ok, here's where things get sticky. It's
899 * possible that we can't schedule the command
900 * because the controller is too busy, so
901 * let's just queue the command and try again
902 * when another command is scheduled. */
903 if (err == -ENOSPC) {
904 //request a reset
905 schedule_work(&nic->tx_timeout_task);
906 }
907 break;
908 } else {
909 nic->cuc_cmd = cuc_resume;
910 nic->cb_to_send = nic->cb_to_send->next;
911 }
912 }
913
914 err_unlock:
915 spin_unlock_irqrestore(&nic->cb_lock, flags);
916
917 return err;
918 }
919
920 static int mdio_read(struct net_device *netdev, int addr, int reg)
921 {
922 struct nic *nic = netdev_priv(netdev);
923 return nic->mdio_ctrl(nic, addr, mdi_read, reg, 0);
924 }
925
926 static void mdio_write(struct net_device *netdev, int addr, int reg, int data)
927 {
928 struct nic *nic = netdev_priv(netdev);
929
930 nic->mdio_ctrl(nic, addr, mdi_write, reg, data);
931 }
932
933 /* the standard mdio_ctrl() function for usual MII-compliant hardware */
934 static u16 mdio_ctrl_hw(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data)
935 {
936 u32 data_out = 0;
937 unsigned int i;
938 unsigned long flags;
939
940
941 /*
942 * Stratus87247: we shouldn't be writing the MDI control
943 * register until the Ready bit shows True. Also, since
944 * manipulation of the MDI control registers is a multi-step
945 * procedure it should be done under lock.
946 */
947 spin_lock_irqsave(&nic->mdio_lock, flags);
948 for (i = 100; i; --i) {
949 if (ioread32(&nic->csr->mdi_ctrl) & mdi_ready)
950 break;
951 udelay(20);
952 }
953 if (unlikely(!i)) {
954 printk("e100.mdio_ctrl(%s) won't go Ready\n",
955 nic->netdev->name );
956 spin_unlock_irqrestore(&nic->mdio_lock, flags);
957 return 0; /* No way to indicate timeout error */
958 }
959 iowrite32((reg << 16) | (addr << 21) | dir | data, &nic->csr->mdi_ctrl);
960
961 for (i = 0; i < 100; i++) {
962 udelay(20);
963 if ((data_out = ioread32(&nic->csr->mdi_ctrl)) & mdi_ready)
964 break;
965 }
966 spin_unlock_irqrestore(&nic->mdio_lock, flags);
967 DPRINTK(HW, DEBUG,
968 "%s:addr=%d, reg=%d, data_in=0x%04X, data_out=0x%04X\n",
969 dir == mdi_read ? "READ" : "WRITE", addr, reg, data, data_out);
970 return (u16)data_out;
971 }
972
973 /* slightly tweaked mdio_ctrl() function for phy_82552_v specifics */
974 static u16 mdio_ctrl_phy_82552_v(struct nic *nic,
975 u32 addr,
976 u32 dir,
977 u32 reg,
978 u16 data)
979 {
980 if ((reg == MII_BMCR) && (dir == mdi_write)) {
981 if (data & (BMCR_ANRESTART | BMCR_ANENABLE)) {
982 u16 advert = mdio_read(nic->netdev, nic->mii.phy_id,
983 MII_ADVERTISE);
984
985 /*
986 * Workaround Si issue where sometimes the part will not
987 * autoneg to 100Mbps even when advertised.
988 */
989 if (advert & ADVERTISE_100FULL)
990 data |= BMCR_SPEED100 | BMCR_FULLDPLX;
991 else if (advert & ADVERTISE_100HALF)
992 data |= BMCR_SPEED100;
993 }
994 }
995 return mdio_ctrl_hw(nic, addr, dir, reg, data);
996 }
997
998 /* Fully software-emulated mdio_ctrl() function for cards without
999 * MII-compliant PHYs.
1000 * For now, this is mainly geared towards 80c24 support; in case of further
1001 * requirements for other types (i82503, ...?) either extend this mechanism
1002 * or split it, whichever is cleaner.
1003 */
1004 static u16 mdio_ctrl_phy_mii_emulated(struct nic *nic,
1005 u32 addr,
1006 u32 dir,
1007 u32 reg,
1008 u16 data)
1009 {
1010 /* might need to allocate a netdev_priv'ed register array eventually
1011 * to be able to record state changes, but for now
1012 * some fully hardcoded register handling ought to be ok I guess. */
1013
1014 if (dir == mdi_read) {
1015 switch (reg) {
1016 case MII_BMCR:
1017 /* Auto-negotiation, right? */
1018 return BMCR_ANENABLE |
1019 BMCR_FULLDPLX;
1020 case MII_BMSR:
1021 return BMSR_LSTATUS /* for mii_link_ok() */ |
1022 BMSR_ANEGCAPABLE |
1023 BMSR_10FULL;
1024 case MII_ADVERTISE:
1025 /* 80c24 is a "combo card" PHY, right? */
1026 return ADVERTISE_10HALF |
1027 ADVERTISE_10FULL;
1028 default:
1029 DPRINTK(HW, DEBUG,
1030 "%s:addr=%d, reg=%d, data=0x%04X: unimplemented emulation!\n",
1031 dir == mdi_read ? "READ" : "WRITE", addr, reg, data);
1032 return 0xFFFF;
1033 }
1034 } else {
1035 switch (reg) {
1036 default:
1037 DPRINTK(HW, DEBUG,
1038 "%s:addr=%d, reg=%d, data=0x%04X: unimplemented emulation!\n",
1039 dir == mdi_read ? "READ" : "WRITE", addr, reg, data);
1040 return 0xFFFF;
1041 }
1042 }
1043 }
1044 static inline int e100_phy_supports_mii(struct nic *nic)
1045 {
1046 /* for now, just check it by comparing whether we
1047 are using MII software emulation.
1048 */
1049 return (nic->mdio_ctrl != mdio_ctrl_phy_mii_emulated);
1050 }
1051
1052 static void e100_get_defaults(struct nic *nic)
1053 {
1054 struct param_range rfds = { .min = 16, .max = 256, .count = 256 };
1055 struct param_range cbs = { .min = 64, .max = 256, .count = 128 };
1056
1057 /* MAC type is encoded as rev ID; exception: ICH is treated as 82559 */
1058 nic->mac = (nic->flags & ich) ? mac_82559_D101M : nic->pdev->revision;
1059 if (nic->mac == mac_unknown)
1060 nic->mac = mac_82557_D100_A;
1061
1062 nic->params.rfds = rfds;
1063 nic->params.cbs = cbs;
1064
1065 /* Quadwords to DMA into FIFO before starting frame transmit */
1066 nic->tx_threshold = 0xE0;
1067
1068 /* no interrupt for every tx completion, delay = 256us if not 557 */
1069 nic->tx_command = cpu_to_le16(cb_tx | cb_tx_sf |
1070 ((nic->mac >= mac_82558_D101_A4) ? cb_cid : cb_i));
1071
1072 /* Template for a freshly allocated RFD */
1073 nic->blank_rfd.command = 0;
1074 nic->blank_rfd.rbd = cpu_to_le32(0xFFFFFFFF);
1075 nic->blank_rfd.size = cpu_to_le16(VLAN_ETH_FRAME_LEN);
1076
1077 /* MII setup */
1078 nic->mii.phy_id_mask = 0x1F;
1079 nic->mii.reg_num_mask = 0x1F;
1080 nic->mii.dev = nic->netdev;
1081 nic->mii.mdio_read = mdio_read;
1082 nic->mii.mdio_write = mdio_write;
1083 }
1084
1085 static void e100_configure(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1086 {
1087 struct config *config = &cb->u.config;
1088 u8 *c = (u8 *)config;
1089
1090 cb->command = cpu_to_le16(cb_config);
1091
1092 memset(config, 0, sizeof(struct config));
1093
1094 config->byte_count = 0x16; /* bytes in this struct */
1095 config->rx_fifo_limit = 0x8; /* bytes in FIFO before DMA */
1096 config->direct_rx_dma = 0x1; /* reserved */
1097 config->standard_tcb = 0x1; /* 1=standard, 0=extended */
1098 config->standard_stat_counter = 0x1; /* 1=standard, 0=extended */
1099 config->rx_discard_short_frames = 0x1; /* 1=discard, 0=pass */
1100 config->tx_underrun_retry = 0x3; /* # of underrun retries */
1101 if (e100_phy_supports_mii(nic))
1102 config->mii_mode = 1; /* 1=MII mode, 0=i82503 mode */
1103 config->pad10 = 0x6;
1104 config->no_source_addr_insertion = 0x1; /* 1=no, 0=yes */
1105 config->preamble_length = 0x2; /* 0=1, 1=3, 2=7, 3=15 bytes */
1106 config->ifs = 0x6; /* x16 = inter frame spacing */
1107 config->ip_addr_hi = 0xF2; /* ARP IP filter - not used */
1108 config->pad15_1 = 0x1;
1109 config->pad15_2 = 0x1;
1110 config->crs_or_cdt = 0x0; /* 0=CRS only, 1=CRS or CDT */
1111 config->fc_delay_hi = 0x40; /* time delay for fc frame */
1112 config->tx_padding = 0x1; /* 1=pad short frames */
1113 config->fc_priority_threshold = 0x7; /* 7=priority fc disabled */
1114 config->pad18 = 0x1;
1115 config->full_duplex_pin = 0x1; /* 1=examine FDX# pin */
1116 config->pad20_1 = 0x1F;
1117 config->fc_priority_location = 0x1; /* 1=byte#31, 0=byte#19 */
1118 config->pad21_1 = 0x5;
1119
1120 config->adaptive_ifs = nic->adaptive_ifs;
1121 config->loopback = nic->loopback;
1122
1123 if (nic->mii.force_media && nic->mii.full_duplex)
1124 config->full_duplex_force = 0x1; /* 1=force, 0=auto */
1125
1126 if (nic->flags & promiscuous || nic->loopback) {
1127 config->rx_save_bad_frames = 0x1; /* 1=save, 0=discard */
1128 config->rx_discard_short_frames = 0x0; /* 1=discard, 0=save */
1129 config->promiscuous_mode = 0x1; /* 1=on, 0=off */
1130 }
1131
1132 if (nic->flags & multicast_all)
1133 config->multicast_all = 0x1; /* 1=accept, 0=no */
1134
1135 /* disable WoL when up */
1136 if (netif_running(nic->netdev) || !(nic->flags & wol_magic))
1137 config->magic_packet_disable = 0x1; /* 1=off, 0=on */
1138
1139 if (nic->mac >= mac_82558_D101_A4) {
1140 config->fc_disable = 0x1; /* 1=Tx fc off, 0=Tx fc on */
1141 config->mwi_enable = 0x1; /* 1=enable, 0=disable */
1142 config->standard_tcb = 0x0; /* 1=standard, 0=extended */
1143 config->rx_long_ok = 0x1; /* 1=VLANs ok, 0=standard */
1144 if (nic->mac >= mac_82559_D101M) {
1145 config->tno_intr = 0x1; /* TCO stats enable */
1146 /* Enable TCO in extended config */
1147 if (nic->mac >= mac_82551_10) {
1148 config->byte_count = 0x20; /* extended bytes */
1149 config->rx_d102_mode = 0x1; /* GMRC for TCO */
1150 }
1151 } else {
1152 config->standard_stat_counter = 0x0;
1153 }
1154 }
1155
1156 DPRINTK(HW, DEBUG, "[00-07]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1157 c[0], c[1], c[2], c[3], c[4], c[5], c[6], c[7]);
1158 DPRINTK(HW, DEBUG, "[08-15]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1159 c[8], c[9], c[10], c[11], c[12], c[13], c[14], c[15]);
1160 DPRINTK(HW, DEBUG, "[16-23]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1161 c[16], c[17], c[18], c[19], c[20], c[21], c[22], c[23]);
1162 }
1163
1164 /*************************************************************************
1165 * CPUSaver parameters
1166 *
1167 * All CPUSaver parameters are 16-bit literals that are part of a
1168 * "move immediate value" instruction. By changing the value of
1169 * the literal in the instruction before the code is loaded, the
1170 * driver can change the algorithm.
1171 *
1172 * INTDELAY - This loads the dead-man timer with its initial value.
1173 * When this timer expires the interrupt is asserted, and the
1174 * timer is reset each time a new packet is received. (see
1175 * BUNDLEMAX below to set the limit on number of chained packets)
1176 * The current default is 0x600 or 1536. Experiments show that
1177 * the value should probably stay within the 0x200 - 0x1000.
1178 *
1179 * BUNDLEMAX -
1180 * This sets the maximum number of frames that will be bundled. In
1181 * some situations, such as the TCP windowing algorithm, it may be
1182 * better to limit the growth of the bundle size than let it go as
1183 * high as it can, because that could cause too much added latency.
1184 * The default is six, because this is the number of packets in the
1185 * default TCP window size. A value of 1 would make CPUSaver indicate
1186 * an interrupt for every frame received. If you do not want to put
1187 * a limit on the bundle size, set this value to xFFFF.
1188 *
1189 * BUNDLESMALL -
1190 * This contains a bit-mask describing the minimum size frame that
1191 * will be bundled. The default masks the lower 7 bits, which means
1192 * that any frame less than 128 bytes in length will not be bundled,
1193 * but will instead immediately generate an interrupt. This does
1194 * not affect the current bundle in any way. Any frame that is 128
1195 * bytes or large will be bundled normally. This feature is meant
1196 * to provide immediate indication of ACK frames in a TCP environment.
1197 * Customers were seeing poor performance when a machine with CPUSaver
1198 * enabled was sending but not receiving. The delay introduced when
1199 * the ACKs were received was enough to reduce total throughput, because
1200 * the sender would sit idle until the ACK was finally seen.
1201 *
1202 * The current default is 0xFF80, which masks out the lower 7 bits.
1203 * This means that any frame which is x7F (127) bytes or smaller
1204 * will cause an immediate interrupt. Because this value must be a
1205 * bit mask, there are only a few valid values that can be used. To
1206 * turn this feature off, the driver can write the value xFFFF to the
1207 * lower word of this instruction (in the same way that the other
1208 * parameters are used). Likewise, a value of 0xF800 (2047) would
1209 * cause an interrupt to be generated for every frame, because all
1210 * standard Ethernet frames are <= 2047 bytes in length.
1211 *************************************************************************/
1212
1213 /* if you wish to disable the ucode functionality, while maintaining the
1214 * workarounds it provides, set the following defines to:
1215 * BUNDLESMALL 0
1216 * BUNDLEMAX 1
1217 * INTDELAY 1
1218 */
1219 #define BUNDLESMALL 1
1220 #define BUNDLEMAX (u16)6
1221 #define INTDELAY (u16)1536 /* 0x600 */
1222
1223 /* Initialize firmware */
1224 static const struct firmware *e100_request_firmware(struct nic *nic)
1225 {
1226 const char *fw_name;
1227 const struct firmware *fw;
1228 u8 timer, bundle, min_size;
1229 int err;
1230
1231 /* do not load u-code for ICH devices */
1232 if (nic->flags & ich)
1233 return NULL;
1234
1235 /* Search for ucode match against h/w revision */
1236 if (nic->mac == mac_82559_D101M)
1237 fw_name = FIRMWARE_D101M;
1238 else if (nic->mac == mac_82559_D101S)
1239 fw_name = FIRMWARE_D101S;
1240 else if (nic->mac == mac_82551_F || nic->mac == mac_82551_10)
1241 fw_name = FIRMWARE_D102E;
1242 else /* No ucode on other devices */
1243 return NULL;
1244
1245 err = request_firmware(&fw, fw_name, &nic->pdev->dev);
1246 if (err) {
1247 DPRINTK(PROBE, ERR, "Failed to load firmware \"%s\": %d\n",
1248 fw_name, err);
1249 return ERR_PTR(err);
1250 }
1251 /* Firmware should be precisely UCODE_SIZE (words) plus three bytes
1252 indicating the offsets for BUNDLESMALL, BUNDLEMAX, INTDELAY */
1253 if (fw->size != UCODE_SIZE * 4 + 3) {
1254 DPRINTK(PROBE, ERR, "Firmware \"%s\" has wrong size %zu\n",
1255 fw_name, fw->size);
1256 release_firmware(fw);
1257 return ERR_PTR(-EINVAL);
1258 }
1259
1260 /* Read timer, bundle and min_size from end of firmware blob */
1261 timer = fw->data[UCODE_SIZE * 4];
1262 bundle = fw->data[UCODE_SIZE * 4 + 1];
1263 min_size = fw->data[UCODE_SIZE * 4 + 2];
1264
1265 if (timer >= UCODE_SIZE || bundle >= UCODE_SIZE ||
1266 min_size >= UCODE_SIZE) {
1267 DPRINTK(PROBE, ERR,
1268 "\"%s\" has bogus offset values (0x%x,0x%x,0x%x)\n",
1269 fw_name, timer, bundle, min_size);
1270 release_firmware(fw);
1271 return ERR_PTR(-EINVAL);
1272 }
1273 /* OK, firmware is validated and ready to use... */
1274 return fw;
1275 }
1276
1277 static void e100_setup_ucode(struct nic *nic, struct cb *cb,
1278 struct sk_buff *skb)
1279 {
1280 const struct firmware *fw = (void *)skb;
1281 u8 timer, bundle, min_size;
1282
1283 /* It's not a real skb; we just abused the fact that e100_exec_cb
1284 will pass it through to here... */
1285 cb->skb = NULL;
1286
1287 /* firmware is stored as little endian already */
1288 memcpy(cb->u.ucode, fw->data, UCODE_SIZE * 4);
1289
1290 /* Read timer, bundle and min_size from end of firmware blob */
1291 timer = fw->data[UCODE_SIZE * 4];
1292 bundle = fw->data[UCODE_SIZE * 4 + 1];
1293 min_size = fw->data[UCODE_SIZE * 4 + 2];
1294
1295 /* Insert user-tunable settings in cb->u.ucode */
1296 cb->u.ucode[timer] &= cpu_to_le32(0xFFFF0000);
1297 cb->u.ucode[timer] |= cpu_to_le32(INTDELAY);
1298 cb->u.ucode[bundle] &= cpu_to_le32(0xFFFF0000);
1299 cb->u.ucode[bundle] |= cpu_to_le32(BUNDLEMAX);
1300 cb->u.ucode[min_size] &= cpu_to_le32(0xFFFF0000);
1301 cb->u.ucode[min_size] |= cpu_to_le32((BUNDLESMALL) ? 0xFFFF : 0xFF80);
1302
1303 cb->command = cpu_to_le16(cb_ucode | cb_el);
1304 }
1305
1306 static inline int e100_load_ucode_wait(struct nic *nic)
1307 {
1308 const struct firmware *fw;
1309 int err = 0, counter = 50;
1310 struct cb *cb = nic->cb_to_clean;
1311
1312 fw = e100_request_firmware(nic);
1313 /* If it's NULL, then no ucode is required */
1314 if (!fw || IS_ERR(fw))
1315 return PTR_ERR(fw);
1316
1317 if ((err = e100_exec_cb(nic, (void *)fw, e100_setup_ucode)))
1318 DPRINTK(PROBE,ERR, "ucode cmd failed with error %d\n", err);
1319
1320 /* must restart cuc */
1321 nic->cuc_cmd = cuc_start;
1322
1323 /* wait for completion */
1324 e100_write_flush(nic);
1325 udelay(10);
1326
1327 /* wait for possibly (ouch) 500ms */
1328 while (!(cb->status & cpu_to_le16(cb_complete))) {
1329 msleep(10);
1330 if (!--counter) break;
1331 }
1332
1333 /* ack any interrupts, something could have been set */
1334 iowrite8(~0, &nic->csr->scb.stat_ack);
1335
1336 /* if the command failed, or is not OK, notify and return */
1337 if (!counter || !(cb->status & cpu_to_le16(cb_ok))) {
1338 DPRINTK(PROBE,ERR, "ucode load failed\n");
1339 err = -EPERM;
1340 }
1341
1342 return err;
1343 }
1344
1345 static void e100_setup_iaaddr(struct nic *nic, struct cb *cb,
1346 struct sk_buff *skb)
1347 {
1348 cb->command = cpu_to_le16(cb_iaaddr);
1349 memcpy(cb->u.iaaddr, nic->netdev->dev_addr, ETH_ALEN);
1350 }
1351
1352 static void e100_dump(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1353 {
1354 cb->command = cpu_to_le16(cb_dump);
1355 cb->u.dump_buffer_addr = cpu_to_le32(nic->dma_addr +
1356 offsetof(struct mem, dump_buf));
1357 }
1358
1359 static int e100_phy_check_without_mii(struct nic *nic)
1360 {
1361 u8 phy_type;
1362 int without_mii;
1363
1364 phy_type = (nic->eeprom[eeprom_phy_iface] >> 8) & 0x0f;
1365
1366 switch (phy_type) {
1367 case NoSuchPhy: /* Non-MII PHY; UNTESTED! */
1368 case I82503: /* Non-MII PHY; UNTESTED! */
1369 case S80C24: /* Non-MII PHY; tested and working */
1370 /* paragraph from the FreeBSD driver, "FXP_PHY_80C24":
1371 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
1372 * doesn't have a programming interface of any sort. The
1373 * media is sensed automatically based on how the link partner
1374 * is configured. This is, in essence, manual configuration.
1375 */
1376 DPRINTK(PROBE, INFO,
1377 "found MII-less i82503 or 80c24 or other PHY\n");
1378
1379 nic->mdio_ctrl = mdio_ctrl_phy_mii_emulated;
1380 nic->mii.phy_id = 0; /* is this ok for an MII-less PHY? */
1381
1382 /* these might be needed for certain MII-less cards...
1383 * nic->flags |= ich;
1384 * nic->flags |= ich_10h_workaround; */
1385
1386 without_mii = 1;
1387 break;
1388 default:
1389 without_mii = 0;
1390 break;
1391 }
1392 return without_mii;
1393 }
1394
1395 #define NCONFIG_AUTO_SWITCH 0x0080
1396 #define MII_NSC_CONG MII_RESV1
1397 #define NSC_CONG_ENABLE 0x0100
1398 #define NSC_CONG_TXREADY 0x0400
1399 #define ADVERTISE_FC_SUPPORTED 0x0400
1400 static int e100_phy_init(struct nic *nic)
1401 {
1402 struct net_device *netdev = nic->netdev;
1403 u32 addr;
1404 u16 bmcr, stat, id_lo, id_hi, cong;
1405
1406 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
1407 for (addr = 0; addr < 32; addr++) {
1408 nic->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
1409 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR);
1410 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1411 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1412 if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
1413 break;
1414 }
1415 if (addr == 32) {
1416 /* uhoh, no PHY detected: check whether we seem to be some
1417 * weird, rare variant which is *known* to not have any MII.
1418 * But do this AFTER MII checking only, since this does
1419 * lookup of EEPROM values which may easily be unreliable. */
1420 if (e100_phy_check_without_mii(nic))
1421 return 0; /* simply return and hope for the best */
1422 else {
1423 /* for unknown cases log a fatal error */
1424 DPRINTK(HW, ERR,
1425 "Failed to locate any known PHY, aborting.\n");
1426 return -EAGAIN;
1427 }
1428 } else
1429 DPRINTK(HW, DEBUG, "phy_addr = %d\n", nic->mii.phy_id);
1430
1431 /* Isolate all the PHY ids */
1432 for (addr = 0; addr < 32; addr++)
1433 mdio_write(netdev, addr, MII_BMCR, BMCR_ISOLATE);
1434 /* Select the discovered PHY */
1435 bmcr &= ~BMCR_ISOLATE;
1436 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, bmcr);
1437
1438 /* Get phy ID */
1439 id_lo = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID1);
1440 id_hi = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID2);
1441 nic->phy = (u32)id_hi << 16 | (u32)id_lo;
1442 DPRINTK(HW, DEBUG, "phy ID = 0x%08X\n", nic->phy);
1443
1444 /* Handle National tx phys */
1445 #define NCS_PHY_MODEL_MASK 0xFFF0FFFF
1446 if ((nic->phy & NCS_PHY_MODEL_MASK) == phy_nsc_tx) {
1447 /* Disable congestion control */
1448 cong = mdio_read(netdev, nic->mii.phy_id, MII_NSC_CONG);
1449 cong |= NSC_CONG_TXREADY;
1450 cong &= ~NSC_CONG_ENABLE;
1451 mdio_write(netdev, nic->mii.phy_id, MII_NSC_CONG, cong);
1452 }
1453
1454 if (nic->phy == phy_82552_v) {
1455 u16 advert = mdio_read(netdev, nic->mii.phy_id, MII_ADVERTISE);
1456
1457 /* assign special tweaked mdio_ctrl() function */
1458 nic->mdio_ctrl = mdio_ctrl_phy_82552_v;
1459
1460 /* Workaround Si not advertising flow-control during autoneg */
1461 advert |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1462 mdio_write(netdev, nic->mii.phy_id, MII_ADVERTISE, advert);
1463
1464 /* Reset for the above changes to take effect */
1465 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR);
1466 bmcr |= BMCR_RESET;
1467 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, bmcr);
1468 } else if ((nic->mac >= mac_82550_D102) || ((nic->flags & ich) &&
1469 (mdio_read(netdev, nic->mii.phy_id, MII_TPISTATUS) & 0x8000) &&
1470 !(nic->eeprom[eeprom_cnfg_mdix] & eeprom_mdix_enabled))) {
1471 /* enable/disable MDI/MDI-X auto-switching. */
1472 mdio_write(netdev, nic->mii.phy_id, MII_NCONFIG,
1473 nic->mii.force_media ? 0 : NCONFIG_AUTO_SWITCH);
1474 }
1475
1476 return 0;
1477 }
1478
1479 static int e100_hw_init(struct nic *nic)
1480 {
1481 int err;
1482
1483 e100_hw_reset(nic);
1484
1485 DPRINTK(HW, ERR, "e100_hw_init\n");
1486 if (!in_interrupt() && (err = e100_self_test(nic)))
1487 return err;
1488
1489 if ((err = e100_phy_init(nic)))
1490 return err;
1491 if ((err = e100_exec_cmd(nic, cuc_load_base, 0)))
1492 return err;
1493 if ((err = e100_exec_cmd(nic, ruc_load_base, 0)))
1494 return err;
1495 if ((err = e100_load_ucode_wait(nic)))
1496 return err;
1497 if ((err = e100_exec_cb(nic, NULL, e100_configure)))
1498 return err;
1499 if ((err = e100_exec_cb(nic, NULL, e100_setup_iaaddr)))
1500 return err;
1501 if ((err = e100_exec_cmd(nic, cuc_dump_addr,
1502 nic->dma_addr + offsetof(struct mem, stats))))
1503 return err;
1504 if ((err = e100_exec_cmd(nic, cuc_dump_reset, 0)))
1505 return err;
1506
1507 e100_disable_irq(nic);
1508
1509 return 0;
1510 }
1511
1512 static void e100_multi(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1513 {
1514 struct net_device *netdev = nic->netdev;
1515 struct dev_mc_list *list = netdev->mc_list;
1516 u16 i, count = min(netdev->mc_count, E100_MAX_MULTICAST_ADDRS);
1517
1518 cb->command = cpu_to_le16(cb_multi);
1519 cb->u.multi.count = cpu_to_le16(count * ETH_ALEN);
1520 for (i = 0; list && i < count; i++, list = list->next)
1521 memcpy(&cb->u.multi.addr[i*ETH_ALEN], &list->dmi_addr,
1522 ETH_ALEN);
1523 }
1524
1525 static void e100_set_multicast_list(struct net_device *netdev)
1526 {
1527 struct nic *nic = netdev_priv(netdev);
1528
1529 DPRINTK(HW, DEBUG, "mc_count=%d, flags=0x%04X\n",
1530 netdev->mc_count, netdev->flags);
1531
1532 if (netdev->flags & IFF_PROMISC)
1533 nic->flags |= promiscuous;
1534 else
1535 nic->flags &= ~promiscuous;
1536
1537 if (netdev->flags & IFF_ALLMULTI ||
1538 netdev->mc_count > E100_MAX_MULTICAST_ADDRS)
1539 nic->flags |= multicast_all;
1540 else
1541 nic->flags &= ~multicast_all;
1542
1543 e100_exec_cb(nic, NULL, e100_configure);
1544 e100_exec_cb(nic, NULL, e100_multi);
1545 }
1546
1547 static void e100_update_stats(struct nic *nic)
1548 {
1549 struct net_device *dev = nic->netdev;
1550 struct net_device_stats *ns = &dev->stats;
1551 struct stats *s = &nic->mem->stats;
1552 __le32 *complete = (nic->mac < mac_82558_D101_A4) ? &s->fc_xmt_pause :
1553 (nic->mac < mac_82559_D101M) ? (__le32 *)&s->xmt_tco_frames :
1554 &s->complete;
1555
1556 /* Device's stats reporting may take several microseconds to
1557 * complete, so we're always waiting for results of the
1558 * previous command. */
1559
1560 if (*complete == cpu_to_le32(cuc_dump_reset_complete)) {
1561 *complete = 0;
1562 nic->tx_frames = le32_to_cpu(s->tx_good_frames);
1563 nic->tx_collisions = le32_to_cpu(s->tx_total_collisions);
1564 ns->tx_aborted_errors += le32_to_cpu(s->tx_max_collisions);
1565 ns->tx_window_errors += le32_to_cpu(s->tx_late_collisions);
1566 ns->tx_carrier_errors += le32_to_cpu(s->tx_lost_crs);
1567 ns->tx_fifo_errors += le32_to_cpu(s->tx_underruns);
1568 ns->collisions += nic->tx_collisions;
1569 ns->tx_errors += le32_to_cpu(s->tx_max_collisions) +
1570 le32_to_cpu(s->tx_lost_crs);
1571 ns->rx_length_errors += le32_to_cpu(s->rx_short_frame_errors) +
1572 nic->rx_over_length_errors;
1573 ns->rx_crc_errors += le32_to_cpu(s->rx_crc_errors);
1574 ns->rx_frame_errors += le32_to_cpu(s->rx_alignment_errors);
1575 ns->rx_over_errors += le32_to_cpu(s->rx_overrun_errors);
1576 ns->rx_fifo_errors += le32_to_cpu(s->rx_overrun_errors);
1577 ns->rx_missed_errors += le32_to_cpu(s->rx_resource_errors);
1578 ns->rx_errors += le32_to_cpu(s->rx_crc_errors) +
1579 le32_to_cpu(s->rx_alignment_errors) +
1580 le32_to_cpu(s->rx_short_frame_errors) +
1581 le32_to_cpu(s->rx_cdt_errors);
1582 nic->tx_deferred += le32_to_cpu(s->tx_deferred);
1583 nic->tx_single_collisions +=
1584 le32_to_cpu(s->tx_single_collisions);
1585 nic->tx_multiple_collisions +=
1586 le32_to_cpu(s->tx_multiple_collisions);
1587 if (nic->mac >= mac_82558_D101_A4) {
1588 nic->tx_fc_pause += le32_to_cpu(s->fc_xmt_pause);
1589 nic->rx_fc_pause += le32_to_cpu(s->fc_rcv_pause);
1590 nic->rx_fc_unsupported +=
1591 le32_to_cpu(s->fc_rcv_unsupported);
1592 if (nic->mac >= mac_82559_D101M) {
1593 nic->tx_tco_frames +=
1594 le16_to_cpu(s->xmt_tco_frames);
1595 nic->rx_tco_frames +=
1596 le16_to_cpu(s->rcv_tco_frames);
1597 }
1598 }
1599 }
1600
1601
1602 if (e100_exec_cmd(nic, cuc_dump_reset, 0))
1603 DPRINTK(TX_ERR, DEBUG, "exec cuc_dump_reset failed\n");
1604 }
1605
1606 static void e100_adjust_adaptive_ifs(struct nic *nic, int speed, int duplex)
1607 {
1608 /* Adjust inter-frame-spacing (IFS) between two transmits if
1609 * we're getting collisions on a half-duplex connection. */
1610
1611 if (duplex == DUPLEX_HALF) {
1612 u32 prev = nic->adaptive_ifs;
1613 u32 min_frames = (speed == SPEED_100) ? 1000 : 100;
1614
1615 if ((nic->tx_frames / 32 < nic->tx_collisions) &&
1616 (nic->tx_frames > min_frames)) {
1617 if (nic->adaptive_ifs < 60)
1618 nic->adaptive_ifs += 5;
1619 } else if (nic->tx_frames < min_frames) {
1620 if (nic->adaptive_ifs >= 5)
1621 nic->adaptive_ifs -= 5;
1622 }
1623 if (nic->adaptive_ifs != prev)
1624 e100_exec_cb(nic, NULL, e100_configure);
1625 }
1626 }
1627
1628 static void e100_watchdog(unsigned long data)
1629 {
1630 struct nic *nic = (struct nic *)data;
1631 struct ethtool_cmd cmd;
1632
1633 DPRINTK(TIMER, DEBUG, "right now = %ld\n", jiffies);
1634
1635 /* mii library handles link maintenance tasks */
1636
1637 mii_ethtool_gset(&nic->mii, &cmd);
1638
1639 if (mii_link_ok(&nic->mii) && !netif_carrier_ok(nic->netdev)) {
1640 printk(KERN_INFO "e100: %s NIC Link is Up %s Mbps %s Duplex\n",
1641 nic->netdev->name,
1642 cmd.speed == SPEED_100 ? "100" : "10",
1643 cmd.duplex == DUPLEX_FULL ? "Full" : "Half");
1644 } else if (!mii_link_ok(&nic->mii) && netif_carrier_ok(nic->netdev)) {
1645 printk(KERN_INFO "e100: %s NIC Link is Down\n",
1646 nic->netdev->name);
1647 }
1648
1649 mii_check_link(&nic->mii);
1650
1651 /* Software generated interrupt to recover from (rare) Rx
1652 * allocation failure.
1653 * Unfortunately have to use a spinlock to not re-enable interrupts
1654 * accidentally, due to hardware that shares a register between the
1655 * interrupt mask bit and the SW Interrupt generation bit */
1656 spin_lock_irq(&nic->cmd_lock);
1657 iowrite8(ioread8(&nic->csr->scb.cmd_hi) | irq_sw_gen,&nic->csr->scb.cmd_hi);
1658 e100_write_flush(nic);
1659 spin_unlock_irq(&nic->cmd_lock);
1660
1661 e100_update_stats(nic);
1662 e100_adjust_adaptive_ifs(nic, cmd.speed, cmd.duplex);
1663
1664 if (nic->mac <= mac_82557_D100_C)
1665 /* Issue a multicast command to workaround a 557 lock up */
1666 e100_set_multicast_list(nic->netdev);
1667
1668 if (nic->flags & ich && cmd.speed==SPEED_10 && cmd.duplex==DUPLEX_HALF)
1669 /* Need SW workaround for ICH[x] 10Mbps/half duplex Tx hang. */
1670 nic->flags |= ich_10h_workaround;
1671 else
1672 nic->flags &= ~ich_10h_workaround;
1673
1674 mod_timer(&nic->watchdog,
1675 round_jiffies(jiffies + E100_WATCHDOG_PERIOD));
1676 }
1677
1678 static void e100_xmit_prepare(struct nic *nic, struct cb *cb,
1679 struct sk_buff *skb)
1680 {
1681 cb->command = nic->tx_command;
1682 /* interrupt every 16 packets regardless of delay */
1683 if ((nic->cbs_avail & ~15) == nic->cbs_avail)
1684 cb->command |= cpu_to_le16(cb_i);
1685 cb->u.tcb.tbd_array = cb->dma_addr + offsetof(struct cb, u.tcb.tbd);
1686 cb->u.tcb.tcb_byte_count = 0;
1687 cb->u.tcb.threshold = nic->tx_threshold;
1688 cb->u.tcb.tbd_count = 1;
1689 cb->u.tcb.tbd.buf_addr = cpu_to_le32(pci_map_single(nic->pdev,
1690 skb->data, skb->len, PCI_DMA_TODEVICE));
1691 /* check for mapping failure? */
1692 cb->u.tcb.tbd.size = cpu_to_le16(skb->len);
1693 }
1694
1695 static int e100_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1696 {
1697 struct nic *nic = netdev_priv(netdev);
1698 int err;
1699
1700 if (nic->flags & ich_10h_workaround) {
1701 /* SW workaround for ICH[x] 10Mbps/half duplex Tx hang.
1702 Issue a NOP command followed by a 1us delay before
1703 issuing the Tx command. */
1704 if (e100_exec_cmd(nic, cuc_nop, 0))
1705 DPRINTK(TX_ERR, DEBUG, "exec cuc_nop failed\n");
1706 udelay(1);
1707 }
1708
1709 err = e100_exec_cb(nic, skb, e100_xmit_prepare);
1710
1711 switch (err) {
1712 case -ENOSPC:
1713 /* We queued the skb, but now we're out of space. */
1714 DPRINTK(TX_ERR, DEBUG, "No space for CB\n");
1715 netif_stop_queue(netdev);
1716 break;
1717 case -ENOMEM:
1718 /* This is a hard error - log it. */
1719 DPRINTK(TX_ERR, DEBUG, "Out of Tx resources, returning skb\n");
1720 netif_stop_queue(netdev);
1721 return NETDEV_TX_BUSY;
1722 }
1723
1724 netdev->trans_start = jiffies;
1725 return 0;
1726 }
1727
1728 static int e100_tx_clean(struct nic *nic)
1729 {
1730 struct net_device *dev = nic->netdev;
1731 struct cb *cb;
1732 int tx_cleaned = 0;
1733
1734 spin_lock(&nic->cb_lock);
1735
1736 /* Clean CBs marked complete */
1737 for (cb = nic->cb_to_clean;
1738 cb->status & cpu_to_le16(cb_complete);
1739 cb = nic->cb_to_clean = cb->next) {
1740 DPRINTK(TX_DONE, DEBUG, "cb[%d]->status = 0x%04X\n",
1741 (int)(((void*)cb - (void*)nic->cbs)/sizeof(struct cb)),
1742 cb->status);
1743
1744 if (likely(cb->skb != NULL)) {
1745 dev->stats.tx_packets++;
1746 dev->stats.tx_bytes += cb->skb->len;
1747
1748 pci_unmap_single(nic->pdev,
1749 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1750 le16_to_cpu(cb->u.tcb.tbd.size),
1751 PCI_DMA_TODEVICE);
1752 dev_kfree_skb_any(cb->skb);
1753 cb->skb = NULL;
1754 tx_cleaned = 1;
1755 }
1756 cb->status = 0;
1757 nic->cbs_avail++;
1758 }
1759
1760 spin_unlock(&nic->cb_lock);
1761
1762 /* Recover from running out of Tx resources in xmit_frame */
1763 if (unlikely(tx_cleaned && netif_queue_stopped(nic->netdev)))
1764 netif_wake_queue(nic->netdev);
1765
1766 return tx_cleaned;
1767 }
1768
1769 static void e100_clean_cbs(struct nic *nic)
1770 {
1771 if (nic->cbs) {
1772 while (nic->cbs_avail != nic->params.cbs.count) {
1773 struct cb *cb = nic->cb_to_clean;
1774 if (cb->skb) {
1775 pci_unmap_single(nic->pdev,
1776 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1777 le16_to_cpu(cb->u.tcb.tbd.size),
1778 PCI_DMA_TODEVICE);
1779 dev_kfree_skb(cb->skb);
1780 }
1781 nic->cb_to_clean = nic->cb_to_clean->next;
1782 nic->cbs_avail++;
1783 }
1784 pci_pool_free(nic->cbs_pool, nic->cbs, nic->cbs_dma_addr);
1785 nic->cbs = NULL;
1786 nic->cbs_avail = 0;
1787 }
1788 nic->cuc_cmd = cuc_start;
1789 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean =
1790 nic->cbs;
1791 }
1792
1793 static int e100_alloc_cbs(struct nic *nic)
1794 {
1795 struct cb *cb;
1796 unsigned int i, count = nic->params.cbs.count;
1797
1798 nic->cuc_cmd = cuc_start;
1799 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = NULL;
1800 nic->cbs_avail = 0;
1801
1802 nic->cbs = pci_pool_alloc(nic->cbs_pool, GFP_KERNEL,
1803 &nic->cbs_dma_addr);
1804 if (!nic->cbs)
1805 return -ENOMEM;
1806 memset(nic->cbs, 0, count * sizeof(struct cb));
1807
1808 for (cb = nic->cbs, i = 0; i < count; cb++, i++) {
1809 cb->next = (i + 1 < count) ? cb + 1 : nic->cbs;
1810 cb->prev = (i == 0) ? nic->cbs + count - 1 : cb - 1;
1811
1812 cb->dma_addr = nic->cbs_dma_addr + i * sizeof(struct cb);
1813 cb->link = cpu_to_le32(nic->cbs_dma_addr +
1814 ((i+1) % count) * sizeof(struct cb));
1815 }
1816
1817 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = nic->cbs;
1818 nic->cbs_avail = count;
1819
1820 return 0;
1821 }
1822
1823 static inline void e100_start_receiver(struct nic *nic, struct rx *rx)
1824 {
1825 if (!nic->rxs) return;
1826 if (RU_SUSPENDED != nic->ru_running) return;
1827
1828 /* handle init time starts */
1829 if (!rx) rx = nic->rxs;
1830
1831 /* (Re)start RU if suspended or idle and RFA is non-NULL */
1832 if (rx->skb) {
1833 e100_exec_cmd(nic, ruc_start, rx->dma_addr);
1834 nic->ru_running = RU_RUNNING;
1835 }
1836 }
1837
1838 #define RFD_BUF_LEN (sizeof(struct rfd) + VLAN_ETH_FRAME_LEN)
1839 static int e100_rx_alloc_skb(struct nic *nic, struct rx *rx)
1840 {
1841 if (!(rx->skb = netdev_alloc_skb(nic->netdev, RFD_BUF_LEN + NET_IP_ALIGN)))
1842 return -ENOMEM;
1843
1844 /* Align, init, and map the RFD. */
1845 skb_reserve(rx->skb, NET_IP_ALIGN);
1846 skb_copy_to_linear_data(rx->skb, &nic->blank_rfd, sizeof(struct rfd));
1847 rx->dma_addr = pci_map_single(nic->pdev, rx->skb->data,
1848 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
1849
1850 if (pci_dma_mapping_error(nic->pdev, rx->dma_addr)) {
1851 dev_kfree_skb_any(rx->skb);
1852 rx->skb = NULL;
1853 rx->dma_addr = 0;
1854 return -ENOMEM;
1855 }
1856
1857 /* Link the RFD to end of RFA by linking previous RFD to
1858 * this one. We are safe to touch the previous RFD because
1859 * it is protected by the before last buffer's el bit being set */
1860 if (rx->prev->skb) {
1861 struct rfd *prev_rfd = (struct rfd *)rx->prev->skb->data;
1862 put_unaligned_le32(rx->dma_addr, &prev_rfd->link);
1863 pci_dma_sync_single_for_device(nic->pdev, rx->prev->dma_addr,
1864 sizeof(struct rfd), PCI_DMA_BIDIRECTIONAL);
1865 }
1866
1867 return 0;
1868 }
1869
1870 static int e100_rx_indicate(struct nic *nic, struct rx *rx,
1871 unsigned int *work_done, unsigned int work_to_do)
1872 {
1873 struct net_device *dev = nic->netdev;
1874 struct sk_buff *skb = rx->skb;
1875 struct rfd *rfd = (struct rfd *)skb->data;
1876 u16 rfd_status, actual_size;
1877
1878 if (unlikely(work_done && *work_done >= work_to_do))
1879 return -EAGAIN;
1880
1881 /* Need to sync before taking a peek at cb_complete bit */
1882 pci_dma_sync_single_for_cpu(nic->pdev, rx->dma_addr,
1883 sizeof(struct rfd), PCI_DMA_BIDIRECTIONAL);
1884 rfd_status = le16_to_cpu(rfd->status);
1885
1886 DPRINTK(RX_STATUS, DEBUG, "status=0x%04X\n", rfd_status);
1887
1888 /* If data isn't ready, nothing to indicate */
1889 if (unlikely(!(rfd_status & cb_complete))) {
1890 /* If the next buffer has the el bit, but we think the receiver
1891 * is still running, check to see if it really stopped while
1892 * we had interrupts off.
1893 * This allows for a fast restart without re-enabling
1894 * interrupts */
1895 if ((le16_to_cpu(rfd->command) & cb_el) &&
1896 (RU_RUNNING == nic->ru_running))
1897
1898 if (ioread8(&nic->csr->scb.status) & rus_no_res)
1899 nic->ru_running = RU_SUSPENDED;
1900 pci_dma_sync_single_for_device(nic->pdev, rx->dma_addr,
1901 sizeof(struct rfd),
1902 PCI_DMA_FROMDEVICE);
1903 return -ENODATA;
1904 }
1905
1906 /* Get actual data size */
1907 actual_size = le16_to_cpu(rfd->actual_size) & 0x3FFF;
1908 if (unlikely(actual_size > RFD_BUF_LEN - sizeof(struct rfd)))
1909 actual_size = RFD_BUF_LEN - sizeof(struct rfd);
1910
1911 /* Get data */
1912 pci_unmap_single(nic->pdev, rx->dma_addr,
1913 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
1914
1915 /* If this buffer has the el bit, but we think the receiver
1916 * is still running, check to see if it really stopped while
1917 * we had interrupts off.
1918 * This allows for a fast restart without re-enabling interrupts.
1919 * This can happen when the RU sees the size change but also sees
1920 * the el bit set. */
1921 if ((le16_to_cpu(rfd->command) & cb_el) &&
1922 (RU_RUNNING == nic->ru_running)) {
1923
1924 if (ioread8(&nic->csr->scb.status) & rus_no_res)
1925 nic->ru_running = RU_SUSPENDED;
1926 }
1927
1928 /* Pull off the RFD and put the actual data (minus eth hdr) */
1929 skb_reserve(skb, sizeof(struct rfd));
1930 skb_put(skb, actual_size);
1931 skb->protocol = eth_type_trans(skb, nic->netdev);
1932
1933 if (unlikely(!(rfd_status & cb_ok))) {
1934 /* Don't indicate if hardware indicates errors */
1935 dev_kfree_skb_any(skb);
1936 } else if (actual_size > ETH_DATA_LEN + VLAN_ETH_HLEN) {
1937 /* Don't indicate oversized frames */
1938 nic->rx_over_length_errors++;
1939 dev_kfree_skb_any(skb);
1940 } else {
1941 dev->stats.rx_packets++;
1942 dev->stats.rx_bytes += actual_size;
1943 netif_receive_skb(skb);
1944 if (work_done)
1945 (*work_done)++;
1946 }
1947
1948 rx->skb = NULL;
1949
1950 return 0;
1951 }
1952
1953 static void e100_rx_clean(struct nic *nic, unsigned int *work_done,
1954 unsigned int work_to_do)
1955 {
1956 struct rx *rx;
1957 int restart_required = 0, err = 0;
1958 struct rx *old_before_last_rx, *new_before_last_rx;
1959 struct rfd *old_before_last_rfd, *new_before_last_rfd;
1960
1961 /* Indicate newly arrived packets */
1962 for (rx = nic->rx_to_clean; rx->skb; rx = nic->rx_to_clean = rx->next) {
1963 err = e100_rx_indicate(nic, rx, work_done, work_to_do);
1964 /* Hit quota or no more to clean */
1965 if (-EAGAIN == err || -ENODATA == err)
1966 break;
1967 }
1968
1969
1970 /* On EAGAIN, hit quota so have more work to do, restart once
1971 * cleanup is complete.
1972 * Else, are we already rnr? then pay attention!!! this ensures that
1973 * the state machine progression never allows a start with a
1974 * partially cleaned list, avoiding a race between hardware
1975 * and rx_to_clean when in NAPI mode */
1976 if (-EAGAIN != err && RU_SUSPENDED == nic->ru_running)
1977 restart_required = 1;
1978
1979 old_before_last_rx = nic->rx_to_use->prev->prev;
1980 old_before_last_rfd = (struct rfd *)old_before_last_rx->skb->data;
1981
1982 /* Alloc new skbs to refill list */
1983 for (rx = nic->rx_to_use; !rx->skb; rx = nic->rx_to_use = rx->next) {
1984 if (unlikely(e100_rx_alloc_skb(nic, rx)))
1985 break; /* Better luck next time (see watchdog) */
1986 }
1987
1988 new_before_last_rx = nic->rx_to_use->prev->prev;
1989 if (new_before_last_rx != old_before_last_rx) {
1990 /* Set the el-bit on the buffer that is before the last buffer.
1991 * This lets us update the next pointer on the last buffer
1992 * without worrying about hardware touching it.
1993 * We set the size to 0 to prevent hardware from touching this
1994 * buffer.
1995 * When the hardware hits the before last buffer with el-bit
1996 * and size of 0, it will RNR interrupt, the RUS will go into
1997 * the No Resources state. It will not complete nor write to
1998 * this buffer. */
1999 new_before_last_rfd =
2000 (struct rfd *)new_before_last_rx->skb->data;
2001 new_before_last_rfd->size = 0;
2002 new_before_last_rfd->command |= cpu_to_le16(cb_el);
2003 pci_dma_sync_single_for_device(nic->pdev,
2004 new_before_last_rx->dma_addr, sizeof(struct rfd),
2005 PCI_DMA_BIDIRECTIONAL);
2006
2007 /* Now that we have a new stopping point, we can clear the old
2008 * stopping point. We must sync twice to get the proper
2009 * ordering on the hardware side of things. */
2010 old_before_last_rfd->command &= ~cpu_to_le16(cb_el);
2011 pci_dma_sync_single_for_device(nic->pdev,
2012 old_before_last_rx->dma_addr, sizeof(struct rfd),
2013 PCI_DMA_BIDIRECTIONAL);
2014 old_before_last_rfd->size = cpu_to_le16(VLAN_ETH_FRAME_LEN);
2015 pci_dma_sync_single_for_device(nic->pdev,
2016 old_before_last_rx->dma_addr, sizeof(struct rfd),
2017 PCI_DMA_BIDIRECTIONAL);
2018 }
2019
2020 if (restart_required) {
2021 // ack the rnr?
2022 iowrite8(stat_ack_rnr, &nic->csr->scb.stat_ack);
2023 e100_start_receiver(nic, nic->rx_to_clean);
2024 if (work_done)
2025 (*work_done)++;
2026 }
2027 }
2028
2029 static void e100_rx_clean_list(struct nic *nic)
2030 {
2031 struct rx *rx;
2032 unsigned int i, count = nic->params.rfds.count;
2033
2034 nic->ru_running = RU_UNINITIALIZED;
2035
2036 if (nic->rxs) {
2037 for (rx = nic->rxs, i = 0; i < count; rx++, i++) {
2038 if (rx->skb) {
2039 pci_unmap_single(nic->pdev, rx->dma_addr,
2040 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
2041 dev_kfree_skb(rx->skb);
2042 }
2043 }
2044 kfree(nic->rxs);
2045 nic->rxs = NULL;
2046 }
2047
2048 nic->rx_to_use = nic->rx_to_clean = NULL;
2049 }
2050
2051 static int e100_rx_alloc_list(struct nic *nic)
2052 {
2053 struct rx *rx;
2054 unsigned int i, count = nic->params.rfds.count;
2055 struct rfd *before_last;
2056
2057 nic->rx_to_use = nic->rx_to_clean = NULL;
2058 nic->ru_running = RU_UNINITIALIZED;
2059
2060 if (!(nic->rxs = kcalloc(count, sizeof(struct rx), GFP_ATOMIC)))
2061 return -ENOMEM;
2062
2063 for (rx = nic->rxs, i = 0; i < count; rx++, i++) {
2064 rx->next = (i + 1 < count) ? rx + 1 : nic->rxs;
2065 rx->prev = (i == 0) ? nic->rxs + count - 1 : rx - 1;
2066 if (e100_rx_alloc_skb(nic, rx)) {
2067 e100_rx_clean_list(nic);
2068 return -ENOMEM;
2069 }
2070 }
2071 /* Set the el-bit on the buffer that is before the last buffer.
2072 * This lets us update the next pointer on the last buffer without
2073 * worrying about hardware touching it.
2074 * We set the size to 0 to prevent hardware from touching this buffer.
2075 * When the hardware hits the before last buffer with el-bit and size
2076 * of 0, it will RNR interrupt, the RU will go into the No Resources
2077 * state. It will not complete nor write to this buffer. */
2078 rx = nic->rxs->prev->prev;
2079 before_last = (struct rfd *)rx->skb->data;
2080 before_last->command |= cpu_to_le16(cb_el);
2081 before_last->size = 0;
2082 pci_dma_sync_single_for_device(nic->pdev, rx->dma_addr,
2083 sizeof(struct rfd), PCI_DMA_BIDIRECTIONAL);
2084
2085 nic->rx_to_use = nic->rx_to_clean = nic->rxs;
2086 nic->ru_running = RU_SUSPENDED;
2087
2088 return 0;
2089 }
2090
2091 static irqreturn_t e100_intr(int irq, void *dev_id)
2092 {
2093 struct net_device *netdev = dev_id;
2094 struct nic *nic = netdev_priv(netdev);
2095 u8 stat_ack = ioread8(&nic->csr->scb.stat_ack);
2096
2097 DPRINTK(INTR, DEBUG, "stat_ack = 0x%02X\n", stat_ack);
2098
2099 if (stat_ack == stat_ack_not_ours || /* Not our interrupt */
2100 stat_ack == stat_ack_not_present) /* Hardware is ejected */
2101 return IRQ_NONE;
2102
2103 /* Ack interrupt(s) */
2104 iowrite8(stat_ack, &nic->csr->scb.stat_ack);
2105
2106 /* We hit Receive No Resource (RNR); restart RU after cleaning */
2107 if (stat_ack & stat_ack_rnr)
2108 nic->ru_running = RU_SUSPENDED;
2109
2110 if (likely(napi_schedule_prep(&nic->napi))) {
2111 e100_disable_irq(nic);
2112 __napi_schedule(&nic->napi);
2113 }
2114
2115 return IRQ_HANDLED;
2116 }
2117
2118 static int e100_poll(struct napi_struct *napi, int budget)
2119 {
2120 struct nic *nic = container_of(napi, struct nic, napi);
2121 unsigned int work_done = 0;
2122
2123 e100_rx_clean(nic, &work_done, budget);
2124 e100_tx_clean(nic);
2125
2126 /* If budget not fully consumed, exit the polling mode */
2127 if (work_done < budget) {
2128 napi_complete(napi);
2129 e100_enable_irq(nic);
2130 }
2131
2132 return work_done;
2133 }
2134
2135 #ifdef CONFIG_NET_POLL_CONTROLLER
2136 static void e100_netpoll(struct net_device *netdev)
2137 {
2138 struct nic *nic = netdev_priv(netdev);
2139
2140 e100_disable_irq(nic);
2141 e100_intr(nic->pdev->irq, netdev);
2142 e100_tx_clean(nic);
2143 e100_enable_irq(nic);
2144 }
2145 #endif
2146
2147 static int e100_set_mac_address(struct net_device *netdev, void *p)
2148 {
2149 struct nic *nic = netdev_priv(netdev);
2150 struct sockaddr *addr = p;
2151
2152 if (!is_valid_ether_addr(addr->sa_data))
2153 return -EADDRNOTAVAIL;
2154
2155 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2156 e100_exec_cb(nic, NULL, e100_setup_iaaddr);
2157
2158 return 0;
2159 }
2160
2161 static int e100_change_mtu(struct net_device *netdev, int new_mtu)
2162 {
2163 if (new_mtu < ETH_ZLEN || new_mtu > ETH_DATA_LEN)
2164 return -EINVAL;
2165 netdev->mtu = new_mtu;
2166 return 0;
2167 }
2168
2169 static int e100_asf(struct nic *nic)
2170 {
2171 /* ASF can be enabled from eeprom */
2172 return((nic->pdev->device >= 0x1050) && (nic->pdev->device <= 0x1057) &&
2173 (nic->eeprom[eeprom_config_asf] & eeprom_asf) &&
2174 !(nic->eeprom[eeprom_config_asf] & eeprom_gcl) &&
2175 ((nic->eeprom[eeprom_smbus_addr] & 0xFF) != 0xFE));
2176 }
2177
2178 static int e100_up(struct nic *nic)
2179 {
2180 int err;
2181
2182 if ((err = e100_rx_alloc_list(nic)))
2183 return err;
2184 if ((err = e100_alloc_cbs(nic)))
2185 goto err_rx_clean_list;
2186 if ((err = e100_hw_init(nic)))
2187 goto err_clean_cbs;
2188 e100_set_multicast_list(nic->netdev);
2189 e100_start_receiver(nic, NULL);
2190 mod_timer(&nic->watchdog, jiffies);
2191 if ((err = request_irq(nic->pdev->irq, e100_intr, IRQF_SHARED,
2192 nic->netdev->name, nic->netdev)))
2193 goto err_no_irq;
2194 netif_wake_queue(nic->netdev);
2195 napi_enable(&nic->napi);
2196 /* enable ints _after_ enabling poll, preventing a race between
2197 * disable ints+schedule */
2198 e100_enable_irq(nic);
2199 return 0;
2200
2201 err_no_irq:
2202 del_timer_sync(&nic->watchdog);
2203 err_clean_cbs:
2204 e100_clean_cbs(nic);
2205 err_rx_clean_list:
2206 e100_rx_clean_list(nic);
2207 return err;
2208 }
2209
2210 static void e100_down(struct nic *nic)
2211 {
2212 /* wait here for poll to complete */
2213 napi_disable(&nic->napi);
2214 netif_stop_queue(nic->netdev);
2215 e100_hw_reset(nic);
2216 free_irq(nic->pdev->irq, nic->netdev);
2217 del_timer_sync(&nic->watchdog);
2218 netif_carrier_off(nic->netdev);
2219 e100_clean_cbs(nic);
2220 e100_rx_clean_list(nic);
2221 }
2222
2223 static void e100_tx_timeout(struct net_device *netdev)
2224 {
2225 struct nic *nic = netdev_priv(netdev);
2226
2227 /* Reset outside of interrupt context, to avoid request_irq
2228 * in interrupt context */
2229 schedule_work(&nic->tx_timeout_task);
2230 }
2231
2232 static void e100_tx_timeout_task(struct work_struct *work)
2233 {
2234 struct nic *nic = container_of(work, struct nic, tx_timeout_task);
2235 struct net_device *netdev = nic->netdev;
2236
2237 DPRINTK(TX_ERR, DEBUG, "scb.status=0x%02X\n",
2238 ioread8(&nic->csr->scb.status));
2239 e100_down(netdev_priv(netdev));
2240 e100_up(netdev_priv(netdev));
2241 }
2242
2243 static int e100_loopback_test(struct nic *nic, enum loopback loopback_mode)
2244 {
2245 int err;
2246 struct sk_buff *skb;
2247
2248 /* Use driver resources to perform internal MAC or PHY
2249 * loopback test. A single packet is prepared and transmitted
2250 * in loopback mode, and the test passes if the received
2251 * packet compares byte-for-byte to the transmitted packet. */
2252
2253 if ((err = e100_rx_alloc_list(nic)))
2254 return err;
2255 if ((err = e100_alloc_cbs(nic)))
2256 goto err_clean_rx;
2257
2258 /* ICH PHY loopback is broken so do MAC loopback instead */
2259 if (nic->flags & ich && loopback_mode == lb_phy)
2260 loopback_mode = lb_mac;
2261
2262 nic->loopback = loopback_mode;
2263 if ((err = e100_hw_init(nic)))
2264 goto err_loopback_none;
2265
2266 if (loopback_mode == lb_phy)
2267 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR,
2268 BMCR_LOOPBACK);
2269
2270 e100_start_receiver(nic, NULL);
2271
2272 if (!(skb = netdev_alloc_skb(nic->netdev, ETH_DATA_LEN))) {
2273 err = -ENOMEM;
2274 goto err_loopback_none;
2275 }
2276 skb_put(skb, ETH_DATA_LEN);
2277 memset(skb->data, 0xFF, ETH_DATA_LEN);
2278 e100_xmit_frame(skb, nic->netdev);
2279
2280 msleep(10);
2281
2282 pci_dma_sync_single_for_cpu(nic->pdev, nic->rx_to_clean->dma_addr,
2283 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
2284
2285 if (memcmp(nic->rx_to_clean->skb->data + sizeof(struct rfd),
2286 skb->data, ETH_DATA_LEN))
2287 err = -EAGAIN;
2288
2289 err_loopback_none:
2290 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR, 0);
2291 nic->loopback = lb_none;
2292 e100_clean_cbs(nic);
2293 e100_hw_reset(nic);
2294 err_clean_rx:
2295 e100_rx_clean_list(nic);
2296 return err;
2297 }
2298
2299 #define MII_LED_CONTROL 0x1B
2300 #define E100_82552_LED_OVERRIDE 0x19
2301 #define E100_82552_LED_ON 0x000F /* LEDTX and LED_RX both on */
2302 #define E100_82552_LED_OFF 0x000A /* LEDTX and LED_RX both off */
2303 static void e100_blink_led(unsigned long data)
2304 {
2305 struct nic *nic = (struct nic *)data;
2306 enum led_state {
2307 led_on = 0x01,
2308 led_off = 0x04,
2309 led_on_559 = 0x05,
2310 led_on_557 = 0x07,
2311 };
2312 u16 led_reg = MII_LED_CONTROL;
2313
2314 if (nic->phy == phy_82552_v) {
2315 led_reg = E100_82552_LED_OVERRIDE;
2316
2317 nic->leds = (nic->leds == E100_82552_LED_ON) ?
2318 E100_82552_LED_OFF : E100_82552_LED_ON;
2319 } else {
2320 nic->leds = (nic->leds & led_on) ? led_off :
2321 (nic->mac < mac_82559_D101M) ? led_on_557 :
2322 led_on_559;
2323 }
2324 mdio_write(nic->netdev, nic->mii.phy_id, led_reg, nic->leds);
2325 mod_timer(&nic->blink_timer, jiffies + HZ / 4);
2326 }
2327
2328 static int e100_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
2329 {
2330 struct nic *nic = netdev_priv(netdev);
2331 return mii_ethtool_gset(&nic->mii, cmd);
2332 }
2333
2334 static int e100_set_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
2335 {
2336 struct nic *nic = netdev_priv(netdev);
2337 int err;
2338
2339 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, BMCR_RESET);
2340 err = mii_ethtool_sset(&nic->mii, cmd);
2341 e100_exec_cb(nic, NULL, e100_configure);
2342
2343 return err;
2344 }
2345
2346 static void e100_get_drvinfo(struct net_device *netdev,
2347 struct ethtool_drvinfo *info)
2348 {
2349 struct nic *nic = netdev_priv(netdev);
2350 strcpy(info->driver, DRV_NAME);
2351 strcpy(info->version, DRV_VERSION);
2352 strcpy(info->fw_version, "N/A");
2353 strcpy(info->bus_info, pci_name(nic->pdev));
2354 }
2355
2356 #define E100_PHY_REGS 0x1C
2357 static int e100_get_regs_len(struct net_device *netdev)
2358 {
2359 struct nic *nic = netdev_priv(netdev);
2360 return 1 + E100_PHY_REGS + sizeof(nic->mem->dump_buf);
2361 }
2362
2363 static void e100_get_regs(struct net_device *netdev,
2364 struct ethtool_regs *regs, void *p)
2365 {
2366 struct nic *nic = netdev_priv(netdev);
2367 u32 *buff = p;
2368 int i;
2369
2370 regs->version = (1 << 24) | nic->pdev->revision;
2371 buff[0] = ioread8(&nic->csr->scb.cmd_hi) << 24 |
2372 ioread8(&nic->csr->scb.cmd_lo) << 16 |
2373 ioread16(&nic->csr->scb.status);
2374 for (i = E100_PHY_REGS; i >= 0; i--)
2375 buff[1 + E100_PHY_REGS - i] =
2376 mdio_read(netdev, nic->mii.phy_id, i);
2377 memset(nic->mem->dump_buf, 0, sizeof(nic->mem->dump_buf));
2378 e100_exec_cb(nic, NULL, e100_dump);
2379 msleep(10);
2380 memcpy(&buff[2 + E100_PHY_REGS], nic->mem->dump_buf,
2381 sizeof(nic->mem->dump_buf));
2382 }
2383
2384 static void e100_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2385 {
2386 struct nic *nic = netdev_priv(netdev);
2387 wol->supported = (nic->mac >= mac_82558_D101_A4) ? WAKE_MAGIC : 0;
2388 wol->wolopts = (nic->flags & wol_magic) ? WAKE_MAGIC : 0;
2389 }
2390
2391 static int e100_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2392 {
2393 struct nic *nic = netdev_priv(netdev);
2394
2395 if ((wol->wolopts && wol->wolopts != WAKE_MAGIC) ||
2396 !device_can_wakeup(&nic->pdev->dev))
2397 return -EOPNOTSUPP;
2398
2399 if (wol->wolopts)
2400 nic->flags |= wol_magic;
2401 else
2402 nic->flags &= ~wol_magic;
2403
2404 device_set_wakeup_enable(&nic->pdev->dev, wol->wolopts);
2405
2406 e100_exec_cb(nic, NULL, e100_configure);
2407
2408 return 0;
2409 }
2410
2411 static u32 e100_get_msglevel(struct net_device *netdev)
2412 {
2413 struct nic *nic = netdev_priv(netdev);
2414 return nic->msg_enable;
2415 }
2416
2417 static void e100_set_msglevel(struct net_device *netdev, u32 value)
2418 {
2419 struct nic *nic = netdev_priv(netdev);
2420 nic->msg_enable = value;
2421 }
2422
2423 static int e100_nway_reset(struct net_device *netdev)
2424 {
2425 struct nic *nic = netdev_priv(netdev);
2426 return mii_nway_restart(&nic->mii);
2427 }
2428
2429 static u32 e100_get_link(struct net_device *netdev)
2430 {
2431 struct nic *nic = netdev_priv(netdev);
2432 return mii_link_ok(&nic->mii);
2433 }
2434
2435 static int e100_get_eeprom_len(struct net_device *netdev)
2436 {
2437 struct nic *nic = netdev_priv(netdev);
2438 return nic->eeprom_wc << 1;
2439 }
2440
2441 #define E100_EEPROM_MAGIC 0x1234
2442 static int e100_get_eeprom(struct net_device *netdev,
2443 struct ethtool_eeprom *eeprom, u8 *bytes)
2444 {
2445 struct nic *nic = netdev_priv(netdev);
2446
2447 eeprom->magic = E100_EEPROM_MAGIC;
2448 memcpy(bytes, &((u8 *)nic->eeprom)[eeprom->offset], eeprom->len);
2449
2450 return 0;
2451 }
2452
2453 static int e100_set_eeprom(struct net_device *netdev,
2454 struct ethtool_eeprom *eeprom, u8 *bytes)
2455 {
2456 struct nic *nic = netdev_priv(netdev);
2457
2458 if (eeprom->magic != E100_EEPROM_MAGIC)
2459 return -EINVAL;
2460
2461 memcpy(&((u8 *)nic->eeprom)[eeprom->offset], bytes, eeprom->len);
2462
2463 return e100_eeprom_save(nic, eeprom->offset >> 1,
2464 (eeprom->len >> 1) + 1);
2465 }
2466
2467 static void e100_get_ringparam(struct net_device *netdev,
2468 struct ethtool_ringparam *ring)
2469 {
2470 struct nic *nic = netdev_priv(netdev);
2471 struct param_range *rfds = &nic->params.rfds;
2472 struct param_range *cbs = &nic->params.cbs;
2473
2474 ring->rx_max_pending = rfds->max;
2475 ring->tx_max_pending = cbs->max;
2476 ring->rx_mini_max_pending = 0;
2477 ring->rx_jumbo_max_pending = 0;
2478 ring->rx_pending = rfds->count;
2479 ring->tx_pending = cbs->count;
2480 ring->rx_mini_pending = 0;
2481 ring->rx_jumbo_pending = 0;
2482 }
2483
2484 static int e100_set_ringparam(struct net_device *netdev,
2485 struct ethtool_ringparam *ring)
2486 {
2487 struct nic *nic = netdev_priv(netdev);
2488 struct param_range *rfds = &nic->params.rfds;
2489 struct param_range *cbs = &nic->params.cbs;
2490
2491 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
2492 return -EINVAL;
2493
2494 if (netif_running(netdev))
2495 e100_down(nic);
2496 rfds->count = max(ring->rx_pending, rfds->min);
2497 rfds->count = min(rfds->count, rfds->max);
2498 cbs->count = max(ring->tx_pending, cbs->min);
2499 cbs->count = min(cbs->count, cbs->max);
2500 DPRINTK(DRV, INFO, "Ring Param settings: rx: %d, tx %d\n",
2501 rfds->count, cbs->count);
2502 if (netif_running(netdev))
2503 e100_up(nic);
2504
2505 return 0;
2506 }
2507
2508 static const char e100_gstrings_test[][ETH_GSTRING_LEN] = {
2509 "Link test (on/offline)",
2510 "Eeprom test (on/offline)",
2511 "Self test (offline)",
2512 "Mac loopback (offline)",
2513 "Phy loopback (offline)",
2514 };
2515 #define E100_TEST_LEN ARRAY_SIZE(e100_gstrings_test)
2516
2517 static void e100_diag_test(struct net_device *netdev,
2518 struct ethtool_test *test, u64 *data)
2519 {
2520 struct ethtool_cmd cmd;
2521 struct nic *nic = netdev_priv(netdev);
2522 int i, err;
2523
2524 memset(data, 0, E100_TEST_LEN * sizeof(u64));
2525 data[0] = !mii_link_ok(&nic->mii);
2526 data[1] = e100_eeprom_load(nic);
2527 if (test->flags & ETH_TEST_FL_OFFLINE) {
2528
2529 /* save speed, duplex & autoneg settings */
2530 err = mii_ethtool_gset(&nic->mii, &cmd);
2531
2532 if (netif_running(netdev))
2533 e100_down(nic);
2534 data[2] = e100_self_test(nic);
2535 data[3] = e100_loopback_test(nic, lb_mac);
2536 data[4] = e100_loopback_test(nic, lb_phy);
2537
2538 /* restore speed, duplex & autoneg settings */
2539 err = mii_ethtool_sset(&nic->mii, &cmd);
2540
2541 if (netif_running(netdev))
2542 e100_up(nic);
2543 }
2544 for (i = 0; i < E100_TEST_LEN; i++)
2545 test->flags |= data[i] ? ETH_TEST_FL_FAILED : 0;
2546
2547 msleep_interruptible(4 * 1000);
2548 }
2549
2550 static int e100_phys_id(struct net_device *netdev, u32 data)
2551 {
2552 struct nic *nic = netdev_priv(netdev);
2553 u16 led_reg = (nic->phy == phy_82552_v) ? E100_82552_LED_OVERRIDE :
2554 MII_LED_CONTROL;
2555
2556 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
2557 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
2558 mod_timer(&nic->blink_timer, jiffies);
2559 msleep_interruptible(data * 1000);
2560 del_timer_sync(&nic->blink_timer);
2561 mdio_write(netdev, nic->mii.phy_id, led_reg, 0);
2562
2563 return 0;
2564 }
2565
2566 static const char e100_gstrings_stats[][ETH_GSTRING_LEN] = {
2567 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
2568 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
2569 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
2570 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
2571 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
2572 "tx_heartbeat_errors", "tx_window_errors",
2573 /* device-specific stats */
2574 "tx_deferred", "tx_single_collisions", "tx_multi_collisions",
2575 "tx_flow_control_pause", "rx_flow_control_pause",
2576 "rx_flow_control_unsupported", "tx_tco_packets", "rx_tco_packets",
2577 };
2578 #define E100_NET_STATS_LEN 21
2579 #define E100_STATS_LEN ARRAY_SIZE(e100_gstrings_stats)
2580
2581 static int e100_get_sset_count(struct net_device *netdev, int sset)
2582 {
2583 switch (sset) {
2584 case ETH_SS_TEST:
2585 return E100_TEST_LEN;
2586 case ETH_SS_STATS:
2587 return E100_STATS_LEN;
2588 default:
2589 return -EOPNOTSUPP;
2590 }
2591 }
2592
2593 static void e100_get_ethtool_stats(struct net_device *netdev,
2594 struct ethtool_stats *stats, u64 *data)
2595 {
2596 struct nic *nic = netdev_priv(netdev);
2597 int i;
2598
2599 for (i = 0; i < E100_NET_STATS_LEN; i++)
2600 data[i] = ((unsigned long *)&netdev->stats)[i];
2601
2602 data[i++] = nic->tx_deferred;
2603 data[i++] = nic->tx_single_collisions;
2604 data[i++] = nic->tx_multiple_collisions;
2605 data[i++] = nic->tx_fc_pause;
2606 data[i++] = nic->rx_fc_pause;
2607 data[i++] = nic->rx_fc_unsupported;
2608 data[i++] = nic->tx_tco_frames;
2609 data[i++] = nic->rx_tco_frames;
2610 }
2611
2612 static void e100_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2613 {
2614 switch (stringset) {
2615 case ETH_SS_TEST:
2616 memcpy(data, *e100_gstrings_test, sizeof(e100_gstrings_test));
2617 break;
2618 case ETH_SS_STATS:
2619 memcpy(data, *e100_gstrings_stats, sizeof(e100_gstrings_stats));
2620 break;
2621 }
2622 }
2623
2624 static const struct ethtool_ops e100_ethtool_ops = {
2625 .get_settings = e100_get_settings,
2626 .set_settings = e100_set_settings,
2627 .get_drvinfo = e100_get_drvinfo,
2628 .get_regs_len = e100_get_regs_len,
2629 .get_regs = e100_get_regs,
2630 .get_wol = e100_get_wol,
2631 .set_wol = e100_set_wol,
2632 .get_msglevel = e100_get_msglevel,
2633 .set_msglevel = e100_set_msglevel,
2634 .nway_reset = e100_nway_reset,
2635 .get_link = e100_get_link,
2636 .get_eeprom_len = e100_get_eeprom_len,
2637 .get_eeprom = e100_get_eeprom,
2638 .set_eeprom = e100_set_eeprom,
2639 .get_ringparam = e100_get_ringparam,
2640 .set_ringparam = e100_set_ringparam,
2641 .self_test = e100_diag_test,
2642 .get_strings = e100_get_strings,
2643 .phys_id = e100_phys_id,
2644 .get_ethtool_stats = e100_get_ethtool_stats,
2645 .get_sset_count = e100_get_sset_count,
2646 };
2647
2648 static int e100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2649 {
2650 struct nic *nic = netdev_priv(netdev);
2651
2652 return generic_mii_ioctl(&nic->mii, if_mii(ifr), cmd, NULL);
2653 }
2654
2655 static int e100_alloc(struct nic *nic)
2656 {
2657 nic->mem = pci_alloc_consistent(nic->pdev, sizeof(struct mem),
2658 &nic->dma_addr);
2659 return nic->mem ? 0 : -ENOMEM;
2660 }
2661
2662 static void e100_free(struct nic *nic)
2663 {
2664 if (nic->mem) {
2665 pci_free_consistent(nic->pdev, sizeof(struct mem),
2666 nic->mem, nic->dma_addr);
2667 nic->mem = NULL;
2668 }
2669 }
2670
2671 static int e100_open(struct net_device *netdev)
2672 {
2673 struct nic *nic = netdev_priv(netdev);
2674 int err = 0;
2675
2676 netif_carrier_off(netdev);
2677 if ((err = e100_up(nic)))
2678 DPRINTK(IFUP, ERR, "Cannot open interface, aborting.\n");
2679 return err;
2680 }
2681
2682 static int e100_close(struct net_device *netdev)
2683 {
2684 e100_down(netdev_priv(netdev));
2685 return 0;
2686 }
2687
2688 static const struct net_device_ops e100_netdev_ops = {
2689 .ndo_open = e100_open,
2690 .ndo_stop = e100_close,
2691 .ndo_start_xmit = e100_xmit_frame,
2692 .ndo_validate_addr = eth_validate_addr,
2693 .ndo_set_multicast_list = e100_set_multicast_list,
2694 .ndo_set_mac_address = e100_set_mac_address,
2695 .ndo_change_mtu = e100_change_mtu,
2696 .ndo_do_ioctl = e100_do_ioctl,
2697 .ndo_tx_timeout = e100_tx_timeout,
2698 #ifdef CONFIG_NET_POLL_CONTROLLER
2699 .ndo_poll_controller = e100_netpoll,
2700 #endif
2701 };
2702
2703 static int __devinit e100_probe(struct pci_dev *pdev,
2704 const struct pci_device_id *ent)
2705 {
2706 struct net_device *netdev;
2707 struct nic *nic;
2708 int err;
2709
2710 if (!(netdev = alloc_etherdev(sizeof(struct nic)))) {
2711 if (((1 << debug) - 1) & NETIF_MSG_PROBE)
2712 printk(KERN_ERR PFX "Etherdev alloc failed, abort.\n");
2713 return -ENOMEM;
2714 }
2715
2716 netdev->netdev_ops = &e100_netdev_ops;
2717 SET_ETHTOOL_OPS(netdev, &e100_ethtool_ops);
2718 netdev->watchdog_timeo = E100_WATCHDOG_PERIOD;
2719 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2720
2721 nic = netdev_priv(netdev);
2722 netif_napi_add(netdev, &nic->napi, e100_poll, E100_NAPI_WEIGHT);
2723 nic->netdev = netdev;
2724 nic->pdev = pdev;
2725 nic->msg_enable = (1 << debug) - 1;
2726 nic->mdio_ctrl = mdio_ctrl_hw;
2727 pci_set_drvdata(pdev, netdev);
2728
2729 if ((err = pci_enable_device(pdev))) {
2730 DPRINTK(PROBE, ERR, "Cannot enable PCI device, aborting.\n");
2731 goto err_out_free_dev;
2732 }
2733
2734 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2735 DPRINTK(PROBE, ERR, "Cannot find proper PCI device "
2736 "base address, aborting.\n");
2737 err = -ENODEV;
2738 goto err_out_disable_pdev;
2739 }
2740
2741 if ((err = pci_request_regions(pdev, DRV_NAME))) {
2742 DPRINTK(PROBE, ERR, "Cannot obtain PCI resources, aborting.\n");
2743 goto err_out_disable_pdev;
2744 }
2745
2746 if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))) {
2747 DPRINTK(PROBE, ERR, "No usable DMA configuration, aborting.\n");
2748 goto err_out_free_res;
2749 }
2750
2751 SET_NETDEV_DEV(netdev, &pdev->dev);
2752
2753 if (use_io)
2754 DPRINTK(PROBE, INFO, "using i/o access mode\n");
2755
2756 nic->csr = pci_iomap(pdev, (use_io ? 1 : 0), sizeof(struct csr));
2757 if (!nic->csr) {
2758 DPRINTK(PROBE, ERR, "Cannot map device registers, aborting.\n");
2759 err = -ENOMEM;
2760 goto err_out_free_res;
2761 }
2762
2763 if (ent->driver_data)
2764 nic->flags |= ich;
2765 else
2766 nic->flags &= ~ich;
2767
2768 e100_get_defaults(nic);
2769
2770 /* locks must be initialized before calling hw_reset */
2771 spin_lock_init(&nic->cb_lock);
2772 spin_lock_init(&nic->cmd_lock);
2773 spin_lock_init(&nic->mdio_lock);
2774
2775 /* Reset the device before pci_set_master() in case device is in some
2776 * funky state and has an interrupt pending - hint: we don't have the
2777 * interrupt handler registered yet. */
2778 e100_hw_reset(nic);
2779
2780 pci_set_master(pdev);
2781
2782 init_timer(&nic->watchdog);
2783 nic->watchdog.function = e100_watchdog;
2784 nic->watchdog.data = (unsigned long)nic;
2785 init_timer(&nic->blink_timer);
2786 nic->blink_timer.function = e100_blink_led;
2787 nic->blink_timer.data = (unsigned long)nic;
2788
2789 INIT_WORK(&nic->tx_timeout_task, e100_tx_timeout_task);
2790
2791 if ((err = e100_alloc(nic))) {
2792 DPRINTK(PROBE, ERR, "Cannot alloc driver memory, aborting.\n");
2793 goto err_out_iounmap;
2794 }
2795
2796 if ((err = e100_eeprom_load(nic)))
2797 goto err_out_free;
2798
2799 e100_phy_init(nic);
2800
2801 memcpy(netdev->dev_addr, nic->eeprom, ETH_ALEN);
2802 memcpy(netdev->perm_addr, nic->eeprom, ETH_ALEN);
2803 if (!is_valid_ether_addr(netdev->perm_addr)) {
2804 if (!eeprom_bad_csum_allow) {
2805 DPRINTK(PROBE, ERR, "Invalid MAC address from "
2806 "EEPROM, aborting.\n");
2807 err = -EAGAIN;
2808 goto err_out_free;
2809 } else {
2810 DPRINTK(PROBE, ERR, "Invalid MAC address from EEPROM, "
2811 "you MUST configure one.\n");
2812 }
2813 }
2814
2815 /* Wol magic packet can be enabled from eeprom */
2816 if ((nic->mac >= mac_82558_D101_A4) &&
2817 (nic->eeprom[eeprom_id] & eeprom_id_wol)) {
2818 nic->flags |= wol_magic;
2819 device_set_wakeup_enable(&pdev->dev, true);
2820 }
2821
2822 /* ack any pending wake events, disable PME */
2823 pci_pme_active(pdev, false);
2824
2825 strcpy(netdev->name, "eth%d");
2826 if ((err = register_netdev(netdev))) {
2827 DPRINTK(PROBE, ERR, "Cannot register net device, aborting.\n");
2828 goto err_out_free;
2829 }
2830 nic->cbs_pool = pci_pool_create(netdev->name,
2831 nic->pdev,
2832 nic->params.cbs.count * sizeof(struct cb),
2833 sizeof(u32),
2834 0);
2835 DPRINTK(PROBE, INFO, "addr 0x%llx, irq %d, MAC addr %pM\n",
2836 (unsigned long long)pci_resource_start(pdev, use_io ? 1 : 0),
2837 pdev->irq, netdev->dev_addr);
2838
2839 return 0;
2840
2841 err_out_free:
2842 e100_free(nic);
2843 err_out_iounmap:
2844 pci_iounmap(pdev, nic->csr);
2845 err_out_free_res:
2846 pci_release_regions(pdev);
2847 err_out_disable_pdev:
2848 pci_disable_device(pdev);
2849 err_out_free_dev:
2850 pci_set_drvdata(pdev, NULL);
2851 free_netdev(netdev);
2852 return err;
2853 }
2854
2855 static void __devexit e100_remove(struct pci_dev *pdev)
2856 {
2857 struct net_device *netdev = pci_get_drvdata(pdev);
2858
2859 if (netdev) {
2860 struct nic *nic = netdev_priv(netdev);
2861 unregister_netdev(netdev);
2862 e100_free(nic);
2863 pci_iounmap(pdev, nic->csr);
2864 pci_pool_destroy(nic->cbs_pool);
2865 free_netdev(netdev);
2866 pci_release_regions(pdev);
2867 pci_disable_device(pdev);
2868 pci_set_drvdata(pdev, NULL);
2869 }
2870 }
2871
2872 #define E100_82552_SMARTSPEED 0x14 /* SmartSpeed Ctrl register */
2873 #define E100_82552_REV_ANEG 0x0200 /* Reverse auto-negotiation */
2874 #define E100_82552_ANEG_NOW 0x0400 /* Auto-negotiate now */
2875 static void __e100_shutdown(struct pci_dev *pdev, bool *enable_wake)
2876 {
2877 struct net_device *netdev = pci_get_drvdata(pdev);
2878 struct nic *nic = netdev_priv(netdev);
2879
2880 if (netif_running(netdev))
2881 e100_down(nic);
2882 netif_device_detach(netdev);
2883
2884 pci_save_state(pdev);
2885
2886 if ((nic->flags & wol_magic) | e100_asf(nic)) {
2887 /* enable reverse auto-negotiation */
2888 if (nic->phy == phy_82552_v) {
2889 u16 smartspeed = mdio_read(netdev, nic->mii.phy_id,
2890 E100_82552_SMARTSPEED);
2891
2892 mdio_write(netdev, nic->mii.phy_id,
2893 E100_82552_SMARTSPEED, smartspeed |
2894 E100_82552_REV_ANEG | E100_82552_ANEG_NOW);
2895 }
2896 *enable_wake = true;
2897 } else {
2898 *enable_wake = false;
2899 }
2900
2901 pci_disable_device(pdev);
2902 }
2903
2904 static int __e100_power_off(struct pci_dev *pdev, bool wake)
2905 {
2906 if (wake)
2907 return pci_prepare_to_sleep(pdev);
2908
2909 pci_wake_from_d3(pdev, false);
2910 pci_set_power_state(pdev, PCI_D3hot);
2911
2912 return 0;
2913 }
2914
2915 #ifdef CONFIG_PM
2916 static int e100_suspend(struct pci_dev *pdev, pm_message_t state)
2917 {
2918 bool wake;
2919 __e100_shutdown(pdev, &wake);
2920 return __e100_power_off(pdev, wake);
2921 }
2922
2923 static int e100_resume(struct pci_dev *pdev)
2924 {
2925 struct net_device *netdev = pci_get_drvdata(pdev);
2926 struct nic *nic = netdev_priv(netdev);
2927
2928 pci_set_power_state(pdev, PCI_D0);
2929 pci_restore_state(pdev);
2930 /* ack any pending wake events, disable PME */
2931 pci_enable_wake(pdev, 0, 0);
2932
2933 /* disable reverse auto-negotiation */
2934 if (nic->phy == phy_82552_v) {
2935 u16 smartspeed = mdio_read(netdev, nic->mii.phy_id,
2936 E100_82552_SMARTSPEED);
2937
2938 mdio_write(netdev, nic->mii.phy_id,
2939 E100_82552_SMARTSPEED,
2940 smartspeed & ~(E100_82552_REV_ANEG));
2941 }
2942
2943 netif_device_attach(netdev);
2944 if (netif_running(netdev))
2945 e100_up(nic);
2946
2947 return 0;
2948 }
2949 #endif /* CONFIG_PM */
2950
2951 static void e100_shutdown(struct pci_dev *pdev)
2952 {
2953 bool wake;
2954 __e100_shutdown(pdev, &wake);
2955 if (system_state == SYSTEM_POWER_OFF)
2956 __e100_power_off(pdev, wake);
2957 }
2958
2959 /* ------------------ PCI Error Recovery infrastructure -------------- */
2960 /**
2961 * e100_io_error_detected - called when PCI error is detected.
2962 * @pdev: Pointer to PCI device
2963 * @state: The current pci connection state
2964 */
2965 static pci_ers_result_t e100_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
2966 {
2967 struct net_device *netdev = pci_get_drvdata(pdev);
2968 struct nic *nic = netdev_priv(netdev);
2969
2970 netif_device_detach(netdev);
2971
2972 if (state == pci_channel_io_perm_failure)
2973 return PCI_ERS_RESULT_DISCONNECT;
2974
2975 if (netif_running(netdev))
2976 e100_down(nic);
2977 pci_disable_device(pdev);
2978
2979 /* Request a slot reset. */
2980 return PCI_ERS_RESULT_NEED_RESET;
2981 }
2982
2983 /**
2984 * e100_io_slot_reset - called after the pci bus has been reset.
2985 * @pdev: Pointer to PCI device
2986 *
2987 * Restart the card from scratch.
2988 */
2989 static pci_ers_result_t e100_io_slot_reset(struct pci_dev *pdev)
2990 {
2991 struct net_device *netdev = pci_get_drvdata(pdev);
2992 struct nic *nic = netdev_priv(netdev);
2993
2994 if (pci_enable_device(pdev)) {
2995 printk(KERN_ERR "e100: Cannot re-enable PCI device after reset.\n");
2996 return PCI_ERS_RESULT_DISCONNECT;
2997 }
2998 pci_set_master(pdev);
2999
3000 /* Only one device per card can do a reset */
3001 if (0 != PCI_FUNC(pdev->devfn))
3002 return PCI_ERS_RESULT_RECOVERED;
3003 e100_hw_reset(nic);
3004 e100_phy_init(nic);
3005
3006 return PCI_ERS_RESULT_RECOVERED;
3007 }
3008
3009 /**
3010 * e100_io_resume - resume normal operations
3011 * @pdev: Pointer to PCI device
3012 *
3013 * Resume normal operations after an error recovery
3014 * sequence has been completed.
3015 */
3016 static void e100_io_resume(struct pci_dev *pdev)
3017 {
3018 struct net_device *netdev = pci_get_drvdata(pdev);
3019 struct nic *nic = netdev_priv(netdev);
3020
3021 /* ack any pending wake events, disable PME */
3022 pci_enable_wake(pdev, 0, 0);
3023
3024 netif_device_attach(netdev);
3025 if (netif_running(netdev)) {
3026 e100_open(netdev);
3027 mod_timer(&nic->watchdog, jiffies);
3028 }
3029 }
3030
3031 static struct pci_error_handlers e100_err_handler = {
3032 .error_detected = e100_io_error_detected,
3033 .slot_reset = e100_io_slot_reset,
3034 .resume = e100_io_resume,
3035 };
3036
3037 static struct pci_driver e100_driver = {
3038 .name = DRV_NAME,
3039 .id_table = e100_id_table,
3040 .probe = e100_probe,
3041 .remove = __devexit_p(e100_remove),
3042 #ifdef CONFIG_PM
3043 /* Power Management hooks */
3044 .suspend = e100_suspend,
3045 .resume = e100_resume,
3046 #endif
3047 .shutdown = e100_shutdown,
3048 .err_handler = &e100_err_handler,
3049 };
3050
3051 static int __init e100_init_module(void)
3052 {
3053 if (((1 << debug) - 1) & NETIF_MSG_DRV) {
3054 printk(KERN_INFO PFX "%s, %s\n", DRV_DESCRIPTION, DRV_VERSION);
3055 printk(KERN_INFO PFX "%s\n", DRV_COPYRIGHT);
3056 }
3057 return pci_register_driver(&e100_driver);
3058 }
3059
3060 static void __exit e100_cleanup_module(void)
3061 {
3062 pci_unregister_driver(&e100_driver);
3063 }
3064
3065 module_init(e100_init_module);
3066 module_exit(e100_cleanup_module);
3067
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