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1 #define A_SG_CONTROL 0x0 2 3 #define S_CONGMODE 29 4 #define V_CONGMODE(x) ((x) << S_CONGMODE) 5 #define F_CONGMODE V_CONGMODE(1U) 6 7 #define S_TNLFLMODE 28 8 #define V_TNLFLMODE(x) ((x) << S_TNLFLMODE) 9 #define F_TNLFLMODE V_TNLFLMODE(1U) 10 11 #define S_FATLPERREN 27 12 #define V_FATLPERREN(x) ((x) << S_FATLPERREN) 13 #define F_FATLPERREN V_FATLPERREN(1U) 14 15 #define S_DROPPKT 20 16 #define V_DROPPKT(x) ((x) << S_DROPPKT) 17 #define F_DROPPKT V_DROPPKT(1U) 18 19 #define S_EGRGENCTRL 19 20 #define V_EGRGENCTRL(x) ((x) << S_EGRGENCTRL) 21 #define F_EGRGENCTRL V_EGRGENCTRL(1U) 22 23 #define S_USERSPACESIZE 14 24 #define M_USERSPACESIZE 0x1f 25 #define V_USERSPACESIZE(x) ((x) << S_USERSPACESIZE) 26 27 #define S_HOSTPAGESIZE 11 28 #define M_HOSTPAGESIZE 0x7 29 #define V_HOSTPAGESIZE(x) ((x) << S_HOSTPAGESIZE) 30 31 #define S_FLMODE 9 32 #define V_FLMODE(x) ((x) << S_FLMODE) 33 #define F_FLMODE V_FLMODE(1U) 34 35 #define S_PKTSHIFT 6 36 #define M_PKTSHIFT 0x7 37 #define V_PKTSHIFT(x) ((x) << S_PKTSHIFT) 38 39 #define S_ONEINTMULTQ 5 40 #define V_ONEINTMULTQ(x) ((x) << S_ONEINTMULTQ) 41 #define F_ONEINTMULTQ V_ONEINTMULTQ(1U) 42 43 #define S_BIGENDIANINGRESS 2 44 #define V_BIGENDIANINGRESS(x) ((x) << S_BIGENDIANINGRESS) 45 #define F_BIGENDIANINGRESS V_BIGENDIANINGRESS(1U) 46 47 #define S_ISCSICOALESCING 1 48 #define V_ISCSICOALESCING(x) ((x) << S_ISCSICOALESCING) 49 #define F_ISCSICOALESCING V_ISCSICOALESCING(1U) 50 51 #define S_GLOBALENABLE 0 52 #define V_GLOBALENABLE(x) ((x) << S_GLOBALENABLE) 53 #define F_GLOBALENABLE V_GLOBALENABLE(1U) 54 55 #define S_AVOIDCQOVFL 24 56 #define V_AVOIDCQOVFL(x) ((x) << S_AVOIDCQOVFL) 57 #define F_AVOIDCQOVFL V_AVOIDCQOVFL(1U) 58 59 #define S_OPTONEINTMULTQ 23 60 #define V_OPTONEINTMULTQ(x) ((x) << S_OPTONEINTMULTQ) 61 #define F_OPTONEINTMULTQ V_OPTONEINTMULTQ(1U) 62 63 #define S_CQCRDTCTRL 22 64 #define V_CQCRDTCTRL(x) ((x) << S_CQCRDTCTRL) 65 #define F_CQCRDTCTRL V_CQCRDTCTRL(1U) 66 67 #define A_SG_KDOORBELL 0x4 68 69 #define S_SELEGRCNTX 31 70 #define V_SELEGRCNTX(x) ((x) << S_SELEGRCNTX) 71 #define F_SELEGRCNTX V_SELEGRCNTX(1U) 72 73 #define S_EGRCNTX 0 74 #define M_EGRCNTX 0xffff 75 #define V_EGRCNTX(x) ((x) << S_EGRCNTX) 76 77 #define A_SG_GTS 0x8 78 79 #define S_RSPQ 29 80 #define M_RSPQ 0x7 81 #define V_RSPQ(x) ((x) << S_RSPQ) 82 #define G_RSPQ(x) (((x) >> S_RSPQ) & M_RSPQ) 83 84 #define S_NEWTIMER 16 85 #define M_NEWTIMER 0x1fff 86 #define V_NEWTIMER(x) ((x) << S_NEWTIMER) 87 88 #define S_NEWINDEX 0 89 #define M_NEWINDEX 0xffff 90 #define V_NEWINDEX(x) ((x) << S_NEWINDEX) 91 92 #define A_SG_CONTEXT_CMD 0xc 93 94 #define S_CONTEXT_CMD_OPCODE 28 95 #define M_CONTEXT_CMD_OPCODE 0xf 96 #define V_CONTEXT_CMD_OPCODE(x) ((x) << S_CONTEXT_CMD_OPCODE) 97 98 #define S_CONTEXT_CMD_BUSY 27 99 #define V_CONTEXT_CMD_BUSY(x) ((x) << S_CONTEXT_CMD_BUSY) 100 #define F_CONTEXT_CMD_BUSY V_CONTEXT_CMD_BUSY(1U) 101 102 #define S_CQ_CREDIT 20 103 104 #define M_CQ_CREDIT 0x7f 105 106 #define V_CQ_CREDIT(x) ((x) << S_CQ_CREDIT) 107 108 #define G_CQ_CREDIT(x) (((x) >> S_CQ_CREDIT) & M_CQ_CREDIT) 109 110 #define S_CQ 19 111 112 #define V_CQ(x) ((x) << S_CQ) 113 #define F_CQ V_CQ(1U) 114 115 #define S_RESPONSEQ 18 116 #define V_RESPONSEQ(x) ((x) << S_RESPONSEQ) 117 #define F_RESPONSEQ V_RESPONSEQ(1U) 118 119 #define S_EGRESS 17 120 #define V_EGRESS(x) ((x) << S_EGRESS) 121 #define F_EGRESS V_EGRESS(1U) 122 123 #define S_FREELIST 16 124 #define V_FREELIST(x) ((x) << S_FREELIST) 125 #define F_FREELIST V_FREELIST(1U) 126 127 #define S_CONTEXT 0 128 #define M_CONTEXT 0xffff 129 #define V_CONTEXT(x) ((x) << S_CONTEXT) 130 131 #define G_CONTEXT(x) (((x) >> S_CONTEXT) & M_CONTEXT) 132 133 #define A_SG_CONTEXT_DATA0 0x10 134 135 #define A_SG_CONTEXT_DATA1 0x14 136 137 #define A_SG_CONTEXT_DATA2 0x18 138 139 #define A_SG_CONTEXT_DATA3 0x1c 140 141 #define A_SG_CONTEXT_MASK0 0x20 142 143 #define A_SG_CONTEXT_MASK1 0x24 144 145 #define A_SG_CONTEXT_MASK2 0x28 146 147 #define A_SG_CONTEXT_MASK3 0x2c 148 149 #define A_SG_RSPQ_CREDIT_RETURN 0x30 150 151 #define S_CREDITS 0 152 #define M_CREDITS 0xffff 153 #define V_CREDITS(x) ((x) << S_CREDITS) 154 155 #define A_SG_DATA_INTR 0x34 156 157 #define S_ERRINTR 31 158 #define V_ERRINTR(x) ((x) << S_ERRINTR) 159 #define F_ERRINTR V_ERRINTR(1U) 160 161 #define A_SG_HI_DRB_HI_THRSH 0x38 162 163 #define A_SG_HI_DRB_LO_THRSH 0x3c 164 165 #define A_SG_LO_DRB_HI_THRSH 0x40 166 167 #define A_SG_LO_DRB_LO_THRSH 0x44 168 169 #define A_SG_RSPQ_FL_STATUS 0x4c 170 171 #define S_RSPQ0DISABLED 8 172 173 #define S_FL0EMPTY 16 174 #define V_FL0EMPTY(x) ((x) << S_FL0EMPTY) 175 #define F_FL0EMPTY V_FL0EMPTY(1U) 176 177 #define A_SG_EGR_RCQ_DRB_THRSH 0x54 178 179 #define S_HIRCQDRBTHRSH 16 180 #define M_HIRCQDRBTHRSH 0x7ff 181 #define V_HIRCQDRBTHRSH(x) ((x) << S_HIRCQDRBTHRSH) 182 183 #define S_LORCQDRBTHRSH 0 184 #define M_LORCQDRBTHRSH 0x7ff 185 #define V_LORCQDRBTHRSH(x) ((x) << S_LORCQDRBTHRSH) 186 187 #define A_SG_EGR_CNTX_BADDR 0x58 188 189 #define A_SG_INT_CAUSE 0x5c 190 191 #define S_HIRCQPARITYERROR 31 192 #define V_HIRCQPARITYERROR(x) ((x) << S_HIRCQPARITYERROR) 193 #define F_HIRCQPARITYERROR V_HIRCQPARITYERROR(1U) 194 195 #define S_LORCQPARITYERROR 30 196 #define V_LORCQPARITYERROR(x) ((x) << S_LORCQPARITYERROR) 197 #define F_LORCQPARITYERROR V_LORCQPARITYERROR(1U) 198 199 #define S_HIDRBPARITYERROR 29 200 #define V_HIDRBPARITYERROR(x) ((x) << S_HIDRBPARITYERROR) 201 #define F_HIDRBPARITYERROR V_HIDRBPARITYERROR(1U) 202 203 #define S_LODRBPARITYERROR 28 204 #define V_LODRBPARITYERROR(x) ((x) << S_LODRBPARITYERROR) 205 #define F_LODRBPARITYERROR V_LODRBPARITYERROR(1U) 206 207 #define S_FLPARITYERROR 22 208 #define M_FLPARITYERROR 0x3f 209 #define V_FLPARITYERROR(x) ((x) << S_FLPARITYERROR) 210 #define G_FLPARITYERROR(x) (((x) >> S_FLPARITYERROR) & M_FLPARITYERROR) 211 212 #define S_ITPARITYERROR 20 213 #define M_ITPARITYERROR 0x3 214 #define V_ITPARITYERROR(x) ((x) << S_ITPARITYERROR) 215 #define G_ITPARITYERROR(x) (((x) >> S_ITPARITYERROR) & M_ITPARITYERROR) 216 217 #define S_IRPARITYERROR 19 218 #define V_IRPARITYERROR(x) ((x) << S_IRPARITYERROR) 219 #define F_IRPARITYERROR V_IRPARITYERROR(1U) 220 221 #define S_RCPARITYERROR 18 222 #define V_RCPARITYERROR(x) ((x) << S_RCPARITYERROR) 223 #define F_RCPARITYERROR V_RCPARITYERROR(1U) 224 225 #define S_OCPARITYERROR 17 226 #define V_OCPARITYERROR(x) ((x) << S_OCPARITYERROR) 227 #define F_OCPARITYERROR V_OCPARITYERROR(1U) 228 229 #define S_CPPARITYERROR 16 230 #define V_CPPARITYERROR(x) ((x) << S_CPPARITYERROR) 231 #define F_CPPARITYERROR V_CPPARITYERROR(1U) 232 233 #define S_R_REQ_FRAMINGERROR 15 234 #define V_R_REQ_FRAMINGERROR(x) ((x) << S_R_REQ_FRAMINGERROR) 235 #define F_R_REQ_FRAMINGERROR V_R_REQ_FRAMINGERROR(1U) 236 237 #define S_UC_REQ_FRAMINGERROR 14 238 #define V_UC_REQ_FRAMINGERROR(x) ((x) << S_UC_REQ_FRAMINGERROR) 239 #define F_UC_REQ_FRAMINGERROR V_UC_REQ_FRAMINGERROR(1U) 240 241 #define S_HICTLDRBDROPERR 13 242 #define V_HICTLDRBDROPERR(x) ((x) << S_HICTLDRBDROPERR) 243 #define F_HICTLDRBDROPERR V_HICTLDRBDROPERR(1U) 244 245 #define S_LOCTLDRBDROPERR 12 246 #define V_LOCTLDRBDROPERR(x) ((x) << S_LOCTLDRBDROPERR) 247 #define F_LOCTLDRBDROPERR V_LOCTLDRBDROPERR(1U) 248 249 #define S_HIPIODRBDROPERR 11 250 #define V_HIPIODRBDROPERR(x) ((x) << S_HIPIODRBDROPERR) 251 #define F_HIPIODRBDROPERR V_HIPIODRBDROPERR(1U) 252 253 #define S_LOPIODRBDROPERR 10 254 #define V_LOPIODRBDROPERR(x) ((x) << S_LOPIODRBDROPERR) 255 #define F_LOPIODRBDROPERR V_LOPIODRBDROPERR(1U) 256 257 #define S_RSPQDISABLED 3 258 #define V_RSPQDISABLED(x) ((x) << S_RSPQDISABLED) 259 #define F_RSPQDISABLED V_RSPQDISABLED(1U) 260 261 #define S_RSPQCREDITOVERFOW 2 262 #define V_RSPQCREDITOVERFOW(x) ((x) << S_RSPQCREDITOVERFOW) 263 #define F_RSPQCREDITOVERFOW V_RSPQCREDITOVERFOW(1U) 264 265 #define S_FLEMPTY 1 266 #define V_FLEMPTY(x) ((x) << S_FLEMPTY) 267 #define F_FLEMPTY V_FLEMPTY(1U) 268 269 #define A_SG_INT_ENABLE 0x60 270 271 #define A_SG_CMDQ_CREDIT_TH 0x64 272 273 #define S_TIMEOUT 8 274 #define M_TIMEOUT 0xffffff 275 #define V_TIMEOUT(x) ((x) << S_TIMEOUT) 276 277 #define S_THRESHOLD 0 278 #define M_THRESHOLD 0xff 279 #define V_THRESHOLD(x) ((x) << S_THRESHOLD) 280 281 #define A_SG_TIMER_TICK 0x68 282 283 #define A_SG_CQ_CONTEXT_BADDR 0x6c 284 285 #define A_SG_OCO_BASE 0x70 286 287 #define S_BASE1 16 288 #define M_BASE1 0xffff 289 #define V_BASE1(x) ((x) << S_BASE1) 290 291 #define A_SG_DRB_PRI_THRESH 0x74 292 293 #define A_PCIX_INT_ENABLE 0x80 294 295 #define S_MSIXPARERR 22 296 #define M_MSIXPARERR 0x7 297 298 #define V_MSIXPARERR(x) ((x) << S_MSIXPARERR) 299 300 #define S_CFPARERR 18 301 #define M_CFPARERR 0xf 302 303 #define V_CFPARERR(x) ((x) << S_CFPARERR) 304 305 #define S_RFPARERR 14 306 #define M_RFPARERR 0xf 307 308 #define V_RFPARERR(x) ((x) << S_RFPARERR) 309 310 #define S_WFPARERR 12 311 #define M_WFPARERR 0x3 312 313 #define V_WFPARERR(x) ((x) << S_WFPARERR) 314 315 #define S_PIOPARERR 11 316 #define V_PIOPARERR(x) ((x) << S_PIOPARERR) 317 #define F_PIOPARERR V_PIOPARERR(1U) 318 319 #define S_DETUNCECCERR 10 320 #define V_DETUNCECCERR(x) ((x) << S_DETUNCECCERR) 321 #define F_DETUNCECCERR V_DETUNCECCERR(1U) 322 323 #define S_DETCORECCERR 9 324 #define V_DETCORECCERR(x) ((x) << S_DETCORECCERR) 325 #define F_DETCORECCERR V_DETCORECCERR(1U) 326 327 #define S_RCVSPLCMPERR 8 328 #define V_RCVSPLCMPERR(x) ((x) << S_RCVSPLCMPERR) 329 #define F_RCVSPLCMPERR V_RCVSPLCMPERR(1U) 330 331 #define S_UNXSPLCMP 7 332 #define V_UNXSPLCMP(x) ((x) << S_UNXSPLCMP) 333 #define F_UNXSPLCMP V_UNXSPLCMP(1U) 334 335 #define S_SPLCMPDIS 6 336 #define V_SPLCMPDIS(x) ((x) << S_SPLCMPDIS) 337 #define F_SPLCMPDIS V_SPLCMPDIS(1U) 338 339 #define S_DETPARERR 5 340 #define V_DETPARERR(x) ((x) << S_DETPARERR) 341 #define F_DETPARERR V_DETPARERR(1U) 342 343 #define S_SIGSYSERR 4 344 #define V_SIGSYSERR(x) ((x) << S_SIGSYSERR) 345 #define F_SIGSYSERR V_SIGSYSERR(1U) 346 347 #define S_RCVMSTABT 3 348 #define V_RCVMSTABT(x) ((x) << S_RCVMSTABT) 349 #define F_RCVMSTABT V_RCVMSTABT(1U) 350 351 #define S_RCVTARABT 2 352 #define V_RCVTARABT(x) ((x) << S_RCVTARABT) 353 #define F_RCVTARABT V_RCVTARABT(1U) 354 355 #define S_SIGTARABT 1 356 #define V_SIGTARABT(x) ((x) << S_SIGTARABT) 357 #define F_SIGTARABT V_SIGTARABT(1U) 358 359 #define S_MSTDETPARERR 0 360 #define V_MSTDETPARERR(x) ((x) << S_MSTDETPARERR) 361 #define F_MSTDETPARERR V_MSTDETPARERR(1U) 362 363 #define A_PCIX_INT_CAUSE 0x84 364 365 #define A_PCIX_CFG 0x88 366 367 #define S_DMASTOPEN 19 368 #define V_DMASTOPEN(x) ((x) << S_DMASTOPEN) 369 #define F_DMASTOPEN V_DMASTOPEN(1U) 370 371 #define S_CLIDECEN 18 372 #define V_CLIDECEN(x) ((x) << S_CLIDECEN) 373 #define F_CLIDECEN V_CLIDECEN(1U) 374 375 #define A_PCIX_MODE 0x8c 376 377 #define S_PCLKRANGE 6 378 #define M_PCLKRANGE 0x3 379 #define V_PCLKRANGE(x) ((x) << S_PCLKRANGE) 380 #define G_PCLKRANGE(x) (((x) >> S_PCLKRANGE) & M_PCLKRANGE) 381 382 #define S_PCIXINITPAT 2 383 #define M_PCIXINITPAT 0xf 384 #define V_PCIXINITPAT(x) ((x) << S_PCIXINITPAT) 385 #define G_PCIXINITPAT(x) (((x) >> S_PCIXINITPAT) & M_PCIXINITPAT) 386 387 #define S_64BIT 0 388 #define V_64BIT(x) ((x) << S_64BIT) 389 #define F_64BIT V_64BIT(1U) 390 391 #define A_PCIE_INT_ENABLE 0x80 392 393 #define S_BISTERR 15 394 #define M_BISTERR 0xff 395 396 #define V_BISTERR(x) ((x) << S_BISTERR) 397 398 #define S_TXPARERR 18 399 #define V_TXPARERR(x) ((x) << S_TXPARERR) 400 #define F_TXPARERR V_TXPARERR(1U) 401 402 #define S_RXPARERR 17 403 #define V_RXPARERR(x) ((x) << S_RXPARERR) 404 #define F_RXPARERR V_RXPARERR(1U) 405 406 #define S_RETRYLUTPARERR 16 407 #define V_RETRYLUTPARERR(x) ((x) << S_RETRYLUTPARERR) 408 #define F_RETRYLUTPARERR V_RETRYLUTPARERR(1U) 409 410 #define S_RETRYBUFPARERR 15 411 #define V_RETRYBUFPARERR(x) ((x) << S_RETRYBUFPARERR) 412 #define F_RETRYBUFPARERR V_RETRYBUFPARERR(1U) 413 414 #define S_PCIE_MSIXPARERR 12 415 #define M_PCIE_MSIXPARERR 0x7 416 417 #define V_PCIE_MSIXPARERR(x) ((x) << S_PCIE_MSIXPARERR) 418 419 #define S_PCIE_CFPARERR 11 420 #define V_PCIE_CFPARERR(x) ((x) << S_PCIE_CFPARERR) 421 #define F_PCIE_CFPARERR V_PCIE_CFPARERR(1U) 422 423 #define S_PCIE_RFPARERR 10 424 #define V_PCIE_RFPARERR(x) ((x) << S_PCIE_RFPARERR) 425 #define F_PCIE_RFPARERR V_PCIE_RFPARERR(1U) 426 427 #define S_PCIE_WFPARERR 9 428 #define V_PCIE_WFPARERR(x) ((x) << S_PCIE_WFPARERR) 429 #define F_PCIE_WFPARERR V_PCIE_WFPARERR(1U) 430 431 #define S_PCIE_PIOPARERR 8 432 #define V_PCIE_PIOPARERR(x) ((x) << S_PCIE_PIOPARERR) 433 #define F_PCIE_PIOPARERR V_PCIE_PIOPARERR(1U) 434 435 #define S_UNXSPLCPLERRC 7 436 #define V_UNXSPLCPLERRC(x) ((x) << S_UNXSPLCPLERRC) 437 #define F_UNXSPLCPLERRC V_UNXSPLCPLERRC(1U) 438 439 #define S_UNXSPLCPLERRR 6 440 #define V_UNXSPLCPLERRR(x) ((x) << S_UNXSPLCPLERRR) 441 #define F_UNXSPLCPLERRR V_UNXSPLCPLERRR(1U) 442 443 #define S_PEXERR 0 444 #define V_PEXERR(x) ((x) << S_PEXERR) 445 #define F_PEXERR V_PEXERR(1U) 446 447 #define A_PCIE_INT_CAUSE 0x84 448 449 #define S_PCIE_DMASTOPEN 24 450 #define V_PCIE_DMASTOPEN(x) ((x) << S_PCIE_DMASTOPEN) 451 #define F_PCIE_DMASTOPEN V_PCIE_DMASTOPEN(1U) 452 453 #define A_PCIE_CFG 0x88 454 455 #define S_ENABLELINKDWNDRST 21 456 #define V_ENABLELINKDWNDRST(x) ((x) << S_ENABLELINKDWNDRST) 457 #define F_ENABLELINKDWNDRST V_ENABLELINKDWNDRST(1U) 458 459 #define S_ENABLELINKDOWNRST 20 460 #define V_ENABLELINKDOWNRST(x) ((x) << S_ENABLELINKDOWNRST) 461 #define F_ENABLELINKDOWNRST V_ENABLELINKDOWNRST(1U) 462 463 #define S_PCIE_CLIDECEN 16 464 #define V_PCIE_CLIDECEN(x) ((x) << S_PCIE_CLIDECEN) 465 #define F_PCIE_CLIDECEN V_PCIE_CLIDECEN(1U) 466 467 #define S_CRSTWRMMODE 0 468 #define V_CRSTWRMMODE(x) ((x) << S_CRSTWRMMODE) 469 #define F_CRSTWRMMODE V_CRSTWRMMODE(1U) 470 471 #define A_PCIE_MODE 0x8c 472 473 #define S_NUMFSTTRNSEQRX 10 474 #define M_NUMFSTTRNSEQRX 0xff 475 #define V_NUMFSTTRNSEQRX(x) ((x) << S_NUMFSTTRNSEQRX) 476 #define G_NUMFSTTRNSEQRX(x) (((x) >> S_NUMFSTTRNSEQRX) & M_NUMFSTTRNSEQRX) 477 478 #define A_PCIE_PEX_CTRL0 0x98 479 480 #define S_NUMFSTTRNSEQ 22 481 #define M_NUMFSTTRNSEQ 0xff 482 #define V_NUMFSTTRNSEQ(x) ((x) << S_NUMFSTTRNSEQ) 483 #define G_NUMFSTTRNSEQ(x) (((x) >> S_NUMFSTTRNSEQ) & M_NUMFSTTRNSEQ) 484 485 #define S_REPLAYLMT 2 486 #define M_REPLAYLMT 0xfffff 487 488 #define V_REPLAYLMT(x) ((x) << S_REPLAYLMT) 489 490 #define A_PCIE_PEX_CTRL1 0x9c 491 492 #define S_T3A_ACKLAT 0 493 #define M_T3A_ACKLAT 0x7ff 494 495 #define V_T3A_ACKLAT(x) ((x) << S_T3A_ACKLAT) 496 497 #define S_ACKLAT 0 498 #define M_ACKLAT 0x1fff 499 500 #define V_ACKLAT(x) ((x) << S_ACKLAT) 501 502 #define A_PCIE_PEX_ERR 0xa4 503 504 #define A_T3DBG_GPIO_EN 0xd0 505 506 #define S_GPIO11_OEN 27 507 #define V_GPIO11_OEN(x) ((x) << S_GPIO11_OEN) 508 #define F_GPIO11_OEN V_GPIO11_OEN(1U) 509 510 #define S_GPIO10_OEN 26 511 #define V_GPIO10_OEN(x) ((x) << S_GPIO10_OEN) 512 #define F_GPIO10_OEN V_GPIO10_OEN(1U) 513 514 #define S_GPIO7_OEN 23 515 #define V_GPIO7_OEN(x) ((x) << S_GPIO7_OEN) 516 #define F_GPIO7_OEN V_GPIO7_OEN(1U) 517 518 #define S_GPIO6_OEN 22 519 #define V_GPIO6_OEN(x) ((x) << S_GPIO6_OEN) 520 #define F_GPIO6_OEN V_GPIO6_OEN(1U) 521 522 #define S_GPIO5_OEN 21 523 #define V_GPIO5_OEN(x) ((x) << S_GPIO5_OEN) 524 #define F_GPIO5_OEN V_GPIO5_OEN(1U) 525 526 #define S_GPIO4_OEN 20 527 #define V_GPIO4_OEN(x) ((x) << S_GPIO4_OEN) 528 #define F_GPIO4_OEN V_GPIO4_OEN(1U) 529 530 #define S_GPIO2_OEN 18 531 #define V_GPIO2_OEN(x) ((x) << S_GPIO2_OEN) 532 #define F_GPIO2_OEN V_GPIO2_OEN(1U) 533 534 #define S_GPIO1_OEN 17 535 #define V_GPIO1_OEN(x) ((x) << S_GPIO1_OEN) 536 #define F_GPIO1_OEN V_GPIO1_OEN(1U) 537 538 #define S_GPIO0_OEN 16 539 #define V_GPIO0_OEN(x) ((x) << S_GPIO0_OEN) 540 #define F_GPIO0_OEN V_GPIO0_OEN(1U) 541 542 #define S_GPIO10_OUT_VAL 10 543 #define V_GPIO10_OUT_VAL(x) ((x) << S_GPIO10_OUT_VAL) 544 #define F_GPIO10_OUT_VAL V_GPIO10_OUT_VAL(1U) 545 546 #define S_GPIO7_OUT_VAL 7 547 #define V_GPIO7_OUT_VAL(x) ((x) << S_GPIO7_OUT_VAL) 548 #define F_GPIO7_OUT_VAL V_GPIO7_OUT_VAL(1U) 549 550 #define S_GPIO6_OUT_VAL 6 551 #define V_GPIO6_OUT_VAL(x) ((x) << S_GPIO6_OUT_VAL) 552 #define F_GPIO6_OUT_VAL V_GPIO6_OUT_VAL(1U) 553 554 #define S_GPIO5_OUT_VAL 5 555 #define V_GPIO5_OUT_VAL(x) ((x) << S_GPIO5_OUT_VAL) 556 #define F_GPIO5_OUT_VAL V_GPIO5_OUT_VAL(1U) 557 558 #define S_GPIO4_OUT_VAL 4 559 #define V_GPIO4_OUT_VAL(x) ((x) << S_GPIO4_OUT_VAL) 560 #define F_GPIO4_OUT_VAL V_GPIO4_OUT_VAL(1U) 561 562 #define S_GPIO2_OUT_VAL 2 563 #define V_GPIO2_OUT_VAL(x) ((x) << S_GPIO2_OUT_VAL) 564 #define F_GPIO2_OUT_VAL V_GPIO2_OUT_VAL(1U) 565 566 #define S_GPIO1_OUT_VAL 1 567 #define V_GPIO1_OUT_VAL(x) ((x) << S_GPIO1_OUT_VAL) 568 #define F_GPIO1_OUT_VAL V_GPIO1_OUT_VAL(1U) 569 570 #define S_GPIO0_OUT_VAL 0 571 #define V_GPIO0_OUT_VAL(x) ((x) << S_GPIO0_OUT_VAL) 572 #define F_GPIO0_OUT_VAL V_GPIO0_OUT_VAL(1U) 573 574 #define A_T3DBG_INT_ENABLE 0xd8 575 576 #define S_GPIO11 11 577 #define V_GPIO11(x) ((x) << S_GPIO11) 578 #define F_GPIO11 V_GPIO11(1U) 579 580 #define S_GPIO10 10 581 #define V_GPIO10(x) ((x) << S_GPIO10) 582 #define F_GPIO10 V_GPIO10(1U) 583 584 #define S_GPIO9 9 585 #define V_GPIO9(x) ((x) << S_GPIO9) 586 #define F_GPIO9 V_GPIO9(1U) 587 588 #define S_GPIO7 7 589 #define V_GPIO7(x) ((x) << S_GPIO7) 590 #define F_GPIO7 V_GPIO7(1U) 591 592 #define S_GPIO6 6 593 #define V_GPIO6(x) ((x) << S_GPIO6) 594 #define F_GPIO6 V_GPIO6(1U) 595 596 #define S_GPIO5 5 597 #define V_GPIO5(x) ((x) << S_GPIO5) 598 #define F_GPIO5 V_GPIO5(1U) 599 600 #define S_GPIO4 4 601 #define V_GPIO4(x) ((x) << S_GPIO4) 602 #define F_GPIO4 V_GPIO4(1U) 603 604 #define S_GPIO3 3 605 #define V_GPIO3(x) ((x) << S_GPIO3) 606 #define F_GPIO3 V_GPIO3(1U) 607 608 #define S_GPIO2 2 609 #define V_GPIO2(x) ((x) << S_GPIO2) 610 #define F_GPIO2 V_GPIO2(1U) 611 612 #define S_GPIO1 1 613 #define V_GPIO1(x) ((x) << S_GPIO1) 614 #define F_GPIO1 V_GPIO1(1U) 615 616 #define S_GPIO0 0 617 #define V_GPIO0(x) ((x) << S_GPIO0) 618 #define F_GPIO0 V_GPIO0(1U) 619 620 #define A_T3DBG_INT_CAUSE 0xdc 621 622 #define A_T3DBG_GPIO_ACT_LOW 0xf0 623 624 #define MC7_PMRX_BASE_ADDR 0x100 625 626 #define A_MC7_CFG 0x100 627 628 #define S_IFEN 13 629 #define V_IFEN(x) ((x) << S_IFEN) 630 #define F_IFEN V_IFEN(1U) 631 632 #define S_TERM150 11 633 #define V_TERM150(x) ((x) << S_TERM150) 634 #define F_TERM150 V_TERM150(1U) 635 636 #define S_SLOW 10 637 #define V_SLOW(x) ((x) << S_SLOW) 638 #define F_SLOW V_SLOW(1U) 639 640 #define S_WIDTH 8 641 #define M_WIDTH 0x3 642 #define V_WIDTH(x) ((x) << S_WIDTH) 643 #define G_WIDTH(x) (((x) >> S_WIDTH) & M_WIDTH) 644 645 #define S_BKS 6 646 #define V_BKS(x) ((x) << S_BKS) 647 #define F_BKS V_BKS(1U) 648 649 #define S_ORG 5 650 #define V_ORG(x) ((x) << S_ORG) 651 #define F_ORG V_ORG(1U) 652 653 #define S_DEN 2 654 #define M_DEN 0x7 655 #define V_DEN(x) ((x) << S_DEN) 656 #define G_DEN(x) (((x) >> S_DEN) & M_DEN) 657 658 #define S_RDY 1 659 #define V_RDY(x) ((x) << S_RDY) 660 #define F_RDY V_RDY(1U) 661 662 #define S_CLKEN 0 663 #define V_CLKEN(x) ((x) << S_CLKEN) 664 #define F_CLKEN V_CLKEN(1U) 665 666 #define A_MC7_MODE 0x104 667 668 #define S_BUSY 31 669 #define V_BUSY(x) ((x) << S_BUSY) 670 #define F_BUSY V_BUSY(1U) 671 672 #define S_BUSY 31 673 #define V_BUSY(x) ((x) << S_BUSY) 674 #define F_BUSY V_BUSY(1U) 675 676 #define A_MC7_EXT_MODE1 0x108 677 678 #define A_MC7_EXT_MODE2 0x10c 679 680 #define A_MC7_EXT_MODE3 0x110 681 682 #define A_MC7_PRE 0x114 683 684 #define A_MC7_REF 0x118 685 686 #define S_PREREFDIV 1 687 #define M_PREREFDIV 0x3fff 688 #define V_PREREFDIV(x) ((x) << S_PREREFDIV) 689 690 #define S_PERREFEN 0 691 #define V_PERREFEN(x) ((x) << S_PERREFEN) 692 #define F_PERREFEN V_PERREFEN(1U) 693 694 #define A_MC7_DLL 0x11c 695 696 #define S_DLLENB 1 697 #define V_DLLENB(x) ((x) << S_DLLENB) 698 #define F_DLLENB V_DLLENB(1U) 699 700 #define S_DLLRST 0 701 #define V_DLLRST(x) ((x) << S_DLLRST) 702 #define F_DLLRST V_DLLRST(1U) 703 704 #define A_MC7_PARM 0x120 705 706 #define S_ACTTOPREDLY 26 707 #define M_ACTTOPREDLY 0xf 708 #define V_ACTTOPREDLY(x) ((x) << S_ACTTOPREDLY) 709 710 #define S_ACTTORDWRDLY 23 711 #define M_ACTTORDWRDLY 0x7 712 #define V_ACTTORDWRDLY(x) ((x) << S_ACTTORDWRDLY) 713 714 #define S_PRECYC 20 715 #define M_PRECYC 0x7 716 #define V_PRECYC(x) ((x) << S_PRECYC) 717 718 #define S_REFCYC 13 719 #define M_REFCYC 0x7f 720 #define V_REFCYC(x) ((x) << S_REFCYC) 721 722 #define S_BKCYC 8 723 #define M_BKCYC 0x1f 724 #define V_BKCYC(x) ((x) << S_BKCYC) 725 726 #define S_WRTORDDLY 4 727 #define M_WRTORDDLY 0xf 728 #define V_WRTORDDLY(x) ((x) << S_WRTORDDLY) 729 730 #define S_RDTOWRDLY 0 731 #define M_RDTOWRDLY 0xf 732 #define V_RDTOWRDLY(x) ((x) << S_RDTOWRDLY) 733 734 #define A_MC7_CAL 0x128 735 736 #define S_BUSY 31 737 #define V_BUSY(x) ((x) << S_BUSY) 738 #define F_BUSY V_BUSY(1U) 739 740 #define S_BUSY 31 741 #define V_BUSY(x) ((x) << S_BUSY) 742 #define F_BUSY V_BUSY(1U) 743 744 #define S_CAL_FAULT 30 745 #define V_CAL_FAULT(x) ((x) << S_CAL_FAULT) 746 #define F_CAL_FAULT V_CAL_FAULT(1U) 747 748 #define S_SGL_CAL_EN 20 749 #define V_SGL_CAL_EN(x) ((x) << S_SGL_CAL_EN) 750 #define F_SGL_CAL_EN V_SGL_CAL_EN(1U) 751 752 #define A_MC7_ERR_ADDR 0x12c 753 754 #define A_MC7_ECC 0x130 755 756 #define S_ECCCHKEN 1 757 #define V_ECCCHKEN(x) ((x) << S_ECCCHKEN) 758 #define F_ECCCHKEN V_ECCCHKEN(1U) 759 760 #define S_ECCGENEN 0 761 #define V_ECCGENEN(x) ((x) << S_ECCGENEN) 762 #define F_ECCGENEN V_ECCGENEN(1U) 763 764 #define A_MC7_CE_ADDR 0x134 765 766 #define A_MC7_CE_DATA0 0x138 767 768 #define A_MC7_CE_DATA1 0x13c 769 770 #define A_MC7_CE_DATA2 0x140 771 772 #define S_DATA 0 773 #define M_DATA 0xff 774 775 #define G_DATA(x) (((x) >> S_DATA) & M_DATA) 776 777 #define A_MC7_UE_ADDR 0x144 778 779 #define A_MC7_UE_DATA0 0x148 780 781 #define A_MC7_UE_DATA1 0x14c 782 783 #define A_MC7_UE_DATA2 0x150 784 785 #define A_MC7_BD_ADDR 0x154 786 787 #define S_ADDR 3 788 789 #define M_ADDR 0x1fffffff 790 791 #define A_MC7_BD_DATA0 0x158 792 793 #define A_MC7_BD_DATA1 0x15c 794 795 #define A_MC7_BD_OP 0x164 796 797 #define S_OP 0 798 799 #define V_OP(x) ((x) << S_OP) 800 #define F_OP V_OP(1U) 801 802 #define F_OP V_OP(1U) 803 #define A_SF_OP 0x6dc 804 805 #define A_MC7_BIST_ADDR_BEG 0x168 806 807 #define A_MC7_BIST_ADDR_END 0x16c 808 809 #define A_MC7_BIST_DATA 0x170 810 811 #define A_MC7_BIST_OP 0x174 812 813 #define S_CONT 3 814 #define V_CONT(x) ((x) << S_CONT) 815 #define F_CONT V_CONT(1U) 816 817 #define F_CONT V_CONT(1U) 818 819 #define A_MC7_INT_ENABLE 0x178 820 821 #define S_AE 17 822 #define V_AE(x) ((x) << S_AE) 823 #define F_AE V_AE(1U) 824 825 #define S_PE 2 826 #define M_PE 0x7fff 827 828 #define V_PE(x) ((x) << S_PE) 829 830 #define G_PE(x) (((x) >> S_PE) & M_PE) 831 832 #define S_UE 1 833 #define V_UE(x) ((x) << S_UE) 834 #define F_UE V_UE(1U) 835 836 #define S_CE 0 837 #define V_CE(x) ((x) << S_CE) 838 #define F_CE V_CE(1U) 839 840 #define A_MC7_INT_CAUSE 0x17c 841 842 #define MC7_PMTX_BASE_ADDR 0x180 843 844 #define MC7_CM_BASE_ADDR 0x200 845 846 #define A_CIM_BOOT_CFG 0x280 847 848 #define S_BOOTADDR 2 849 #define M_BOOTADDR 0x3fffffff 850 #define V_BOOTADDR(x) ((x) << S_BOOTADDR) 851 852 #define A_CIM_SDRAM_BASE_ADDR 0x28c 853 854 #define A_CIM_SDRAM_ADDR_SIZE 0x290 855 856 #define A_CIM_HOST_INT_ENABLE 0x298 857 858 #define S_DTAGPARERR 28 859 #define V_DTAGPARERR(x) ((x) << S_DTAGPARERR) 860 #define F_DTAGPARERR V_DTAGPARERR(1U) 861 862 #define S_ITAGPARERR 27 863 #define V_ITAGPARERR(x) ((x) << S_ITAGPARERR) 864 #define F_ITAGPARERR V_ITAGPARERR(1U) 865 866 #define S_IBQTPPARERR 26 867 #define V_IBQTPPARERR(x) ((x) << S_IBQTPPARERR) 868 #define F_IBQTPPARERR V_IBQTPPARERR(1U) 869 870 #define S_IBQULPPARERR 25 871 #define V_IBQULPPARERR(x) ((x) << S_IBQULPPARERR) 872 #define F_IBQULPPARERR V_IBQULPPARERR(1U) 873 874 #define S_IBQSGEHIPARERR 24 875 #define V_IBQSGEHIPARERR(x) ((x) << S_IBQSGEHIPARERR) 876 #define F_IBQSGEHIPARERR V_IBQSGEHIPARERR(1U) 877 878 #define S_IBQSGELOPARERR 23 879 #define V_IBQSGELOPARERR(x) ((x) << S_IBQSGELOPARERR) 880 #define F_IBQSGELOPARERR V_IBQSGELOPARERR(1U) 881 882 #define S_OBQULPLOPARERR 22 883 #define V_OBQULPLOPARERR(x) ((x) << S_OBQULPLOPARERR) 884 #define F_OBQULPLOPARERR V_OBQULPLOPARERR(1U) 885 886 #define S_OBQULPHIPARERR 21 887 #define V_OBQULPHIPARERR(x) ((x) << S_OBQULPHIPARERR) 888 #define F_OBQULPHIPARERR V_OBQULPHIPARERR(1U) 889 890 #define S_OBQSGEPARERR 20 891 #define V_OBQSGEPARERR(x) ((x) << S_OBQSGEPARERR) 892 #define F_OBQSGEPARERR V_OBQSGEPARERR(1U) 893 894 #define S_DCACHEPARERR 19 895 #define V_DCACHEPARERR(x) ((x) << S_DCACHEPARERR) 896 #define F_DCACHEPARERR V_DCACHEPARERR(1U) 897 898 #define S_ICACHEPARERR 18 899 #define V_ICACHEPARERR(x) ((x) << S_ICACHEPARERR) 900 #define F_ICACHEPARERR V_ICACHEPARERR(1U) 901 902 #define S_DRAMPARERR 17 903 #define V_DRAMPARERR(x) ((x) << S_DRAMPARERR) 904 #define F_DRAMPARERR V_DRAMPARERR(1U) 905 906 #define A_CIM_HOST_INT_CAUSE 0x29c 907 908 #define S_BLKWRPLINT 12 909 #define V_BLKWRPLINT(x) ((x) << S_BLKWRPLINT) 910 #define F_BLKWRPLINT V_BLKWRPLINT(1U) 911 912 #define S_BLKRDPLINT 11 913 #define V_BLKRDPLINT(x) ((x) << S_BLKRDPLINT) 914 #define F_BLKRDPLINT V_BLKRDPLINT(1U) 915 916 #define S_BLKWRCTLINT 10 917 #define V_BLKWRCTLINT(x) ((x) << S_BLKWRCTLINT) 918 #define F_BLKWRCTLINT V_BLKWRCTLINT(1U) 919 920 #define S_BLKRDCTLINT 9 921 #define V_BLKRDCTLINT(x) ((x) << S_BLKRDCTLINT) 922 #define F_BLKRDCTLINT V_BLKRDCTLINT(1U) 923 924 #define S_BLKWRFLASHINT 8 925 #define V_BLKWRFLASHINT(x) ((x) << S_BLKWRFLASHINT) 926 #define F_BLKWRFLASHINT V_BLKWRFLASHINT(1U) 927 928 #define S_BLKRDFLASHINT 7 929 #define V_BLKRDFLASHINT(x) ((x) << S_BLKRDFLASHINT) 930 #define F_BLKRDFLASHINT V_BLKRDFLASHINT(1U) 931 932 #define S_SGLWRFLASHINT 6 933 #define V_SGLWRFLASHINT(x) ((x) << S_SGLWRFLASHINT) 934 #define F_SGLWRFLASHINT V_SGLWRFLASHINT(1U) 935 936 #define S_WRBLKFLASHINT 5 937 #define V_WRBLKFLASHINT(x) ((x) << S_WRBLKFLASHINT) 938 #define F_WRBLKFLASHINT V_WRBLKFLASHINT(1U) 939 940 #define S_BLKWRBOOTINT 4 941 #define V_BLKWRBOOTINT(x) ((x) << S_BLKWRBOOTINT) 942 #define F_BLKWRBOOTINT V_BLKWRBOOTINT(1U) 943 944 #define S_FLASHRANGEINT 2 945 #define V_FLASHRANGEINT(x) ((x) << S_FLASHRANGEINT) 946 #define F_FLASHRANGEINT V_FLASHRANGEINT(1U) 947 948 #define S_SDRAMRANGEINT 1 949 #define V_SDRAMRANGEINT(x) ((x) << S_SDRAMRANGEINT) 950 #define F_SDRAMRANGEINT V_SDRAMRANGEINT(1U) 951 952 #define S_RSVDSPACEINT 0 953 #define V_RSVDSPACEINT(x) ((x) << S_RSVDSPACEINT) 954 #define F_RSVDSPACEINT V_RSVDSPACEINT(1U) 955 956 #define A_CIM_HOST_ACC_CTRL 0x2b0 957 958 #define S_HOSTBUSY 17 959 #define V_HOSTBUSY(x) ((x) << S_HOSTBUSY) 960 #define F_HOSTBUSY V_HOSTBUSY(1U) 961 962 #define A_CIM_HOST_ACC_DATA 0x2b4 963 964 #define A_CIM_IBQ_DBG_CFG 0x2c0 965 966 #define S_IBQDBGADDR 16 967 #define M_IBQDBGADDR 0x1ff 968 #define V_IBQDBGADDR(x) ((x) << S_IBQDBGADDR) 969 #define G_IBQDBGADDR(x) (((x) >> S_IBQDBGADDR) & M_IBQDBGADDR) 970 971 #define S_IBQDBGQID 3 972 #define M_IBQDBGQID 0x3 973 #define V_IBQDBGQID(x) ((x) << S_IBQDBGQID) 974 #define G_IBQDBGQID(x) (((x) >> S_IBQDBGQID) & M_IBQDBGQID) 975 976 #define S_IBQDBGWR 2 977 #define V_IBQDBGWR(x) ((x) << S_IBQDBGWR) 978 #define F_IBQDBGWR V_IBQDBGWR(1U) 979 980 #define S_IBQDBGBUSY 1 981 #define V_IBQDBGBUSY(x) ((x) << S_IBQDBGBUSY) 982 #define F_IBQDBGBUSY V_IBQDBGBUSY(1U) 983 984 #define S_IBQDBGEN 0 985 #define V_IBQDBGEN(x) ((x) << S_IBQDBGEN) 986 #define F_IBQDBGEN V_IBQDBGEN(1U) 987 988 #define A_CIM_IBQ_DBG_DATA 0x2c8 989 990 #define A_TP_IN_CONFIG 0x300 991 992 #define S_RXFBARBPRIO 25 993 #define V_RXFBARBPRIO(x) ((x) << S_RXFBARBPRIO) 994 #define F_RXFBARBPRIO V_RXFBARBPRIO(1U) 995 996 #define S_TXFBARBPRIO 24 997 #define V_TXFBARBPRIO(x) ((x) << S_TXFBARBPRIO) 998 #define F_TXFBARBPRIO V_TXFBARBPRIO(1U) 999 1000 #define S_NICMODE 14 1001 #define V_NICMODE(x) ((x) << S_NICMODE) 1002 #define F_NICMODE V_NICMODE(1U) 1003 1004 #define F_NICMODE V_NICMODE(1U) 1005 1006 #define S_IPV6ENABLE 15 1007 #define V_IPV6ENABLE(x) ((x) << S_IPV6ENABLE) 1008 #define F_IPV6ENABLE V_IPV6ENABLE(1U) 1009 1010 #define A_TP_OUT_CONFIG 0x304 1011 1012 #define S_VLANEXTRACTIONENABLE 12 1013 1014 #define A_TP_GLOBAL_CONFIG 0x308 1015 1016 #define S_TXPACINGENABLE 24 1017 #define V_TXPACINGENABLE(x) ((x) << S_TXPACINGENABLE) 1018 #define F_TXPACINGENABLE V_TXPACINGENABLE(1U) 1019 1020 #define S_PATHMTU 15 1021 #define V_PATHMTU(x) ((x) << S_PATHMTU) 1022 #define F_PATHMTU V_PATHMTU(1U) 1023 1024 #define S_IPCHECKSUMOFFLOAD 13 1025 #define V_IPCHECKSUMOFFLOAD(x) ((x) << S_IPCHECKSUMOFFLOAD) 1026 #define F_IPCHECKSUMOFFLOAD V_IPCHECKSUMOFFLOAD(1U) 1027 1028 #define S_UDPCHECKSUMOFFLOAD 12 1029 #define V_UDPCHECKSUMOFFLOAD(x) ((x) << S_UDPCHECKSUMOFFLOAD) 1030 #define F_UDPCHECKSUMOFFLOAD V_UDPCHECKSUMOFFLOAD(1U) 1031 1032 #define S_TCPCHECKSUMOFFLOAD 11 1033 #define V_TCPCHECKSUMOFFLOAD(x) ((x) << S_TCPCHECKSUMOFFLOAD) 1034 #define F_TCPCHECKSUMOFFLOAD V_TCPCHECKSUMOFFLOAD(1U) 1035 1036 #define S_IPTTL 0 1037 #define M_IPTTL 0xff 1038 #define V_IPTTL(x) ((x) << S_IPTTL) 1039 1040 #define A_TP_CMM_MM_BASE 0x314 1041 1042 #define A_TP_CMM_TIMER_BASE 0x318 1043 1044 #define S_CMTIMERMAXNUM 28 1045 #define M_CMTIMERMAXNUM 0x3 1046 #define V_CMTIMERMAXNUM(x) ((x) << S_CMTIMERMAXNUM) 1047 1048 #define A_TP_PMM_SIZE 0x31c 1049 1050 #define A_TP_PMM_TX_BASE 0x320 1051 1052 #define A_TP_PMM_RX_BASE 0x328 1053 1054 #define A_TP_PMM_RX_PAGE_SIZE 0x32c 1055 1056 #define A_TP_PMM_RX_MAX_PAGE 0x330 1057 1058 #define A_TP_PMM_TX_PAGE_SIZE 0x334 1059 1060 #define A_TP_PMM_TX_MAX_PAGE 0x338 1061 1062 #define A_TP_TCP_OPTIONS 0x340 1063 1064 #define S_MTUDEFAULT 16 1065 #define M_MTUDEFAULT 0xffff 1066 #define V_MTUDEFAULT(x) ((x) << S_MTUDEFAULT) 1067 1068 #define S_MTUENABLE 10 1069 #define V_MTUENABLE(x) ((x) << S_MTUENABLE) 1070 #define F_MTUENABLE V_MTUENABLE(1U) 1071 1072 #define S_SACKRX 8 1073 #define V_SACKRX(x) ((x) << S_SACKRX) 1074 #define F_SACKRX V_SACKRX(1U) 1075 1076 #define S_SACKMODE 4 1077 1078 #define M_SACKMODE 0x3 1079 1080 #define V_SACKMODE(x) ((x) << S_SACKMODE) 1081 1082 #define S_WINDOWSCALEMODE 2 1083 #define M_WINDOWSCALEMODE 0x3 1084 #define V_WINDOWSCALEMODE(x) ((x) << S_WINDOWSCALEMODE) 1085 1086 #define S_TIMESTAMPSMODE 0 1087 1088 #define M_TIMESTAMPSMODE 0x3 1089 1090 #define V_TIMESTAMPSMODE(x) ((x) << S_TIMESTAMPSMODE) 1091 1092 #define A_TP_DACK_CONFIG 0x344 1093 1094 #define S_AUTOSTATE3 30 1095 #define M_AUTOSTATE3 0x3 1096 #define V_AUTOSTATE3(x) ((x) << S_AUTOSTATE3) 1097 1098 #define S_AUTOSTATE2 28 1099 #define M_AUTOSTATE2 0x3 1100 #define V_AUTOSTATE2(x) ((x) << S_AUTOSTATE2) 1101 1102 #define S_AUTOSTATE1 26 1103 #define M_AUTOSTATE1 0x3 1104 #define V_AUTOSTATE1(x) ((x) << S_AUTOSTATE1) 1105 1106 #define S_BYTETHRESHOLD 5 1107 #define M_BYTETHRESHOLD 0xfffff 1108 #define V_BYTETHRESHOLD(x) ((x) << S_BYTETHRESHOLD) 1109 1110 #define S_MSSTHRESHOLD 3 1111 #define M_MSSTHRESHOLD 0x3 1112 #define V_MSSTHRESHOLD(x) ((x) << S_MSSTHRESHOLD) 1113 1114 #define S_AUTOCAREFUL 2 1115 #define V_AUTOCAREFUL(x) ((x) << S_AUTOCAREFUL) 1116 #define F_AUTOCAREFUL V_AUTOCAREFUL(1U) 1117 1118 #define S_AUTOENABLE 1 1119 #define V_AUTOENABLE(x) ((x) << S_AUTOENABLE) 1120 #define F_AUTOENABLE V_AUTOENABLE(1U) 1121 1122 #define S_DACK_MODE 0 1123 #define V_DACK_MODE(x) ((x) << S_DACK_MODE) 1124 #define F_DACK_MODE V_DACK_MODE(1U) 1125 1126 #define A_TP_PC_CONFIG 0x348 1127 1128 #define S_TXTOSQUEUEMAPMODE 26 1129 #define V_TXTOSQUEUEMAPMODE(x) ((x) << S_TXTOSQUEUEMAPMODE) 1130 #define F_TXTOSQUEUEMAPMODE V_TXTOSQUEUEMAPMODE(1U) 1131 1132 #define S_ENABLEEPCMDAFULL 23 1133 #define V_ENABLEEPCMDAFULL(x) ((x) << S_ENABLEEPCMDAFULL) 1134 #define F_ENABLEEPCMDAFULL V_ENABLEEPCMDAFULL(1U) 1135 1136 #define S_MODULATEUNIONMODE 22 1137 #define V_MODULATEUNIONMODE(x) ((x) << S_MODULATEUNIONMODE) 1138 #define F_MODULATEUNIONMODE V_MODULATEUNIONMODE(1U) 1139 1140 #define S_TXDEFERENABLE 20 1141 #define V_TXDEFERENABLE(x) ((x) << S_TXDEFERENABLE) 1142 #define F_TXDEFERENABLE V_TXDEFERENABLE(1U) 1143 1144 #define S_RXCONGESTIONMODE 19 1145 #define V_RXCONGESTIONMODE(x) ((x) << S_RXCONGESTIONMODE) 1146 #define F_RXCONGESTIONMODE V_RXCONGESTIONMODE(1U) 1147 1148 #define S_HEARBEATDACK 16 1149 #define V_HEARBEATDACK(x) ((x) << S_HEARBEATDACK) 1150 #define F_HEARBEATDACK V_HEARBEATDACK(1U) 1151 1152 #define S_TXCONGESTIONMODE 15 1153 #define V_TXCONGESTIONMODE(x) ((x) << S_TXCONGESTIONMODE) 1154 #define F_TXCONGESTIONMODE V_TXCONGESTIONMODE(1U) 1155 1156 #define S_ENABLEOCSPIFULL 30 1157 #define V_ENABLEOCSPIFULL(x) ((x) << S_ENABLEOCSPIFULL) 1158 #define F_ENABLEOCSPIFULL V_ENABLEOCSPIFULL(1U) 1159 1160 #define S_LOCKTID 28 1161 #define V_LOCKTID(x) ((x) << S_LOCKTID) 1162 #define F_LOCKTID V_LOCKTID(1U) 1163 1164 #define S_TABLELATENCYDELTA 0 1165 #define M_TABLELATENCYDELTA 0xf 1166 #define V_TABLELATENCYDELTA(x) ((x) << S_TABLELATENCYDELTA) 1167 #define G_TABLELATENCYDELTA(x) \ 1168 (((x) >> S_TABLELATENCYDELTA) & M_TABLELATENCYDELTA) 1169 1170 #define A_TP_PC_CONFIG2 0x34c 1171 1172 #define S_DISBLEDAPARBIT0 15 1173 #define V_DISBLEDAPARBIT0(x) ((x) << S_DISBLEDAPARBIT0) 1174 #define F_DISBLEDAPARBIT0 V_DISBLEDAPARBIT0(1U) 1175 1176 #define S_ENABLEARPMISS 13 1177 #define V_ENABLEARPMISS(x) ((x) << S_ENABLEARPMISS) 1178 #define F_ENABLEARPMISS V_ENABLEARPMISS(1U) 1179 1180 #define S_ENABLENONOFDTNLSYN 12 1181 #define V_ENABLENONOFDTNLSYN(x) ((x) << S_ENABLENONOFDTNLSYN) 1182 #define F_ENABLENONOFDTNLSYN V_ENABLENONOFDTNLSYN(1U) 1183 1184 #define S_ENABLEIPV6RSS 11 1185 #define V_ENABLEIPV6RSS(x) ((x) << S_ENABLEIPV6RSS) 1186 #define F_ENABLEIPV6RSS V_ENABLEIPV6RSS(1U) 1187 1188 #define S_CHDRAFULL 4 1189 #define V_CHDRAFULL(x) ((x) << S_CHDRAFULL) 1190 #define F_CHDRAFULL V_CHDRAFULL(1U) 1191 1192 #define A_TP_TCP_BACKOFF_REG0 0x350 1193 1194 #define A_TP_TCP_BACKOFF_REG1 0x354 1195 1196 #define A_TP_TCP_BACKOFF_REG2 0x358 1197 1198 #define A_TP_TCP_BACKOFF_REG3 0x35c 1199 1200 #define A_TP_PARA_REG2 0x368 1201 1202 #define S_MAXRXDATA 16 1203 #define M_MAXRXDATA 0xffff 1204 #define V_MAXRXDATA(x) ((x) << S_MAXRXDATA) 1205 1206 #define S_RXCOALESCESIZE 0 1207 #define M_RXCOALESCESIZE 0xffff 1208 #define V_RXCOALESCESIZE(x) ((x) << S_RXCOALESCESIZE) 1209 1210 #define A_TP_PARA_REG3 0x36c 1211 1212 #define S_TXDATAACKIDX 16 1213 #define M_TXDATAACKIDX 0xf 1214 1215 #define V_TXDATAACKIDX(x) ((x) << S_TXDATAACKIDX) 1216 1217 #define S_TXPACEAUTOSTRICT 10 1218 #define V_TXPACEAUTOSTRICT(x) ((x) << S_TXPACEAUTOSTRICT) 1219 #define F_TXPACEAUTOSTRICT V_TXPACEAUTOSTRICT(1U) 1220 1221 #define S_TXPACEFIXED 9 1222 #define V_TXPACEFIXED(x) ((x) << S_TXPACEFIXED) 1223 #define F_TXPACEFIXED V_TXPACEFIXED(1U) 1224 1225 #define S_TXPACEAUTO 8 1226 #define V_TXPACEAUTO(x) ((x) << S_TXPACEAUTO) 1227 #define F_TXPACEAUTO V_TXPACEAUTO(1U) 1228 1229 #define S_RXCOALESCEENABLE 1 1230 #define V_RXCOALESCEENABLE(x) ((x) << S_RXCOALESCEENABLE) 1231 #define F_RXCOALESCEENABLE V_RXCOALESCEENABLE(1U) 1232 1233 #define S_RXCOALESCEPSHEN 0 1234 #define V_RXCOALESCEPSHEN(x) ((x) << S_RXCOALESCEPSHEN) 1235 #define F_RXCOALESCEPSHEN V_RXCOALESCEPSHEN(1U) 1236 1237 #define A_TP_PARA_REG4 0x370 1238 1239 #define A_TP_PARA_REG5 0x374 1240 1241 #define S_RXDDPOFFINIT 3 1242 #define V_RXDDPOFFINIT(x) ((x) << S_RXDDPOFFINIT) 1243 #define F_RXDDPOFFINIT V_RXDDPOFFINIT(1U) 1244 1245 #define A_TP_PARA_REG6 0x378 1246 1247 #define S_T3A_ENABLEESND 13 1248 #define V_T3A_ENABLEESND(x) ((x) << S_T3A_ENABLEESND) 1249 #define F_T3A_ENABLEESND V_T3A_ENABLEESND(1U) 1250 1251 #define S_ENABLEESND 11 1252 #define V_ENABLEESND(x) ((x) << S_ENABLEESND) 1253 #define F_ENABLEESND V_ENABLEESND(1U) 1254 1255 #define A_TP_PARA_REG7 0x37c 1256 1257 #define S_PMMAXXFERLEN1 16 1258 #define M_PMMAXXFERLEN1 0xffff 1259 #define V_PMMAXXFERLEN1(x) ((x) << S_PMMAXXFERLEN1) 1260 1261 #define S_PMMAXXFERLEN0 0 1262 #define M_PMMAXXFERLEN0 0xffff 1263 #define V_PMMAXXFERLEN0(x) ((x) << S_PMMAXXFERLEN0) 1264 1265 #define A_TP_TIMER_RESOLUTION 0x390 1266 1267 #define S_TIMERRESOLUTION 16 1268 #define M_TIMERRESOLUTION 0xff 1269 #define V_TIMERRESOLUTION(x) ((x) << S_TIMERRESOLUTION) 1270 1271 #define S_TIMESTAMPRESOLUTION 8 1272 #define M_TIMESTAMPRESOLUTION 0xff 1273 #define V_TIMESTAMPRESOLUTION(x) ((x) << S_TIMESTAMPRESOLUTION) 1274 1275 #define S_DELAYEDACKRESOLUTION 0 1276 #define M_DELAYEDACKRESOLUTION 0xff 1277 #define V_DELAYEDACKRESOLUTION(x) ((x) << S_DELAYEDACKRESOLUTION) 1278 1279 #define A_TP_MSL 0x394 1280 1281 #define A_TP_RXT_MIN 0x398 1282 1283 #define A_TP_RXT_MAX 0x39c 1284 1285 #define A_TP_PERS_MIN 0x3a0 1286 1287 #define A_TP_PERS_MAX 0x3a4 1288 1289 #define A_TP_KEEP_IDLE 0x3a8 1290 1291 #define A_TP_KEEP_INTVL 0x3ac 1292 1293 #define A_TP_INIT_SRTT 0x3b0 1294 1295 #define A_TP_DACK_TIMER 0x3b4 1296 1297 #define A_TP_FINWAIT2_TIMER 0x3b8 1298 1299 #define A_TP_SHIFT_CNT 0x3c0 1300 1301 #define S_SYNSHIFTMAX 24 1302 1303 #define M_SYNSHIFTMAX 0xff 1304 1305 #define V_SYNSHIFTMAX(x) ((x) << S_SYNSHIFTMAX) 1306 1307 #define S_RXTSHIFTMAXR1 20 1308 1309 #define M_RXTSHIFTMAXR1 0xf 1310 1311 #define V_RXTSHIFTMAXR1(x) ((x) << S_RXTSHIFTMAXR1) 1312 1313 #define S_RXTSHIFTMAXR2 16 1314 1315 #define M_RXTSHIFTMAXR2 0xf 1316 1317 #define V_RXTSHIFTMAXR2(x) ((x) << S_RXTSHIFTMAXR2) 1318 1319 #define S_PERSHIFTBACKOFFMAX 12 1320 #define M_PERSHIFTBACKOFFMAX 0xf 1321 #define V_PERSHIFTBACKOFFMAX(x) ((x) << S_PERSHIFTBACKOFFMAX) 1322 1323 #define S_PERSHIFTMAX 8 1324 #define M_PERSHIFTMAX 0xf 1325 #define V_PERSHIFTMAX(x) ((x) << S_PERSHIFTMAX) 1326 1327 #define S_KEEPALIVEMAX 0 1328 1329 #define M_KEEPALIVEMAX 0xff 1330 1331 #define V_KEEPALIVEMAX(x) ((x) << S_KEEPALIVEMAX) 1332 1333 #define A_TP_MTU_PORT_TABLE 0x3d0 1334 1335 #define A_TP_CCTRL_TABLE 0x3dc 1336 1337 #define A_TP_MTU_TABLE 0x3e4 1338 1339 #define A_TP_RSS_MAP_TABLE 0x3e8 1340 1341 #define A_TP_RSS_LKP_TABLE 0x3ec 1342 1343 #define A_TP_RSS_CONFIG 0x3f0 1344 1345 #define S_TNL4TUPEN 29 1346 #define V_TNL4TUPEN(x) ((x) << S_TNL4TUPEN) 1347 #define F_TNL4TUPEN V_TNL4TUPEN(1U) 1348 1349 #define S_TNL2TUPEN 28 1350 #define V_TNL2TUPEN(x) ((x) << S_TNL2TUPEN) 1351 #define F_TNL2TUPEN V_TNL2TUPEN(1U) 1352 1353 #define S_TNLPRTEN 26 1354 #define V_TNLPRTEN(x) ((x) << S_TNLPRTEN) 1355 #define F_TNLPRTEN V_TNLPRTEN(1U) 1356 1357 #define S_TNLMAPEN 25 1358 #define V_TNLMAPEN(x) ((x) << S_TNLMAPEN) 1359 #define F_TNLMAPEN V_TNLMAPEN(1U) 1360 1361 #define S_TNLLKPEN 24 1362 #define V_TNLLKPEN(x) ((x) << S_TNLLKPEN) 1363 #define F_TNLLKPEN V_TNLLKPEN(1U) 1364 1365 #define S_RRCPLMAPEN 7 1366 #define V_RRCPLMAPEN(x) ((x) << S_RRCPLMAPEN) 1367 #define F_RRCPLMAPEN V_RRCPLMAPEN(1U) 1368 1369 #define S_RRCPLCPUSIZE 4 1370 #define M_RRCPLCPUSIZE 0x7 1371 #define V_RRCPLCPUSIZE(x) ((x) << S_RRCPLCPUSIZE) 1372 1373 #define S_RQFEEDBACKENABLE 3 1374 #define V_RQFEEDBACKENABLE(x) ((x) << S_RQFEEDBACKENABLE) 1375 #define F_RQFEEDBACKENABLE V_RQFEEDBACKENABLE(1U) 1376 1377 #define S_HASHTOEPLITZ 2 1378 #define V_HASHTOEPLITZ(x) ((x) << S_HASHTOEPLITZ) 1379 #define F_HASHTOEPLITZ V_HASHTOEPLITZ(1U) 1380 1381 #define S_DISABLE 0 1382 1383 #define A_TP_TM_PIO_ADDR 0x418 1384 1385 #define A_TP_TM_PIO_DATA 0x41c 1386 1387 #define A_TP_TX_MOD_QUE_TABLE 0x420 1388 1389 #define A_TP_TX_RESOURCE_LIMIT 0x424 1390 1391 #define A_TP_TX_MOD_QUEUE_REQ_MAP 0x428 1392 1393 #define S_TX_MOD_QUEUE_REQ_MAP 0 1394 #define M_TX_MOD_QUEUE_REQ_MAP 0xff 1395 #define V_TX_MOD_QUEUE_REQ_MAP(x) ((x) << S_TX_MOD_QUEUE_REQ_MAP) 1396 1397 #define A_TP_TX_MOD_QUEUE_WEIGHT1 0x42c 1398 1399 #define A_TP_TX_MOD_QUEUE_WEIGHT0 0x430 1400 1401 #define A_TP_MOD_CHANNEL_WEIGHT 0x434 1402 1403 #define A_TP_MOD_RATE_LIMIT 0x438 1404 1405 #define A_TP_PIO_ADDR 0x440 1406 1407 #define A_TP_PIO_DATA 0x444 1408 1409 #define A_TP_RESET 0x44c 1410 1411 #define S_FLSTINITENABLE 1 1412 #define V_FLSTINITENABLE(x) ((x) << S_FLSTINITENABLE) 1413 #define F_FLSTINITENABLE V_FLSTINITENABLE(1U) 1414 1415 #define S_TPRESET 0 1416 #define V_TPRESET(x) ((x) << S_TPRESET) 1417 #define F_TPRESET V_TPRESET(1U) 1418 1419 #define A_TP_CMM_MM_RX_FLST_BASE 0x460 1420 1421 #define A_TP_CMM_MM_TX_FLST_BASE 0x464 1422 1423 #define A_TP_CMM_MM_PS_FLST_BASE 0x468 1424 1425 #define A_TP_MIB_INDEX 0x450 1426 1427 #define A_TP_MIB_RDATA 0x454 1428 1429 #define A_TP_CMM_MM_MAX_PSTRUCT 0x46c 1430 1431 #define A_TP_INT_ENABLE 0x470 1432 1433 #define S_FLMTXFLSTEMPTY 30 1434 #define V_FLMTXFLSTEMPTY(x) ((x) << S_FLMTXFLSTEMPTY) 1435 #define F_FLMTXFLSTEMPTY V_FLMTXFLSTEMPTY(1U) 1436 1437 #define S_FLMRXFLSTEMPTY 29 1438 #define V_FLMRXFLSTEMPTY(x) ((x) << S_FLMRXFLSTEMPTY) 1439 #define F_FLMRXFLSTEMPTY V_FLMRXFLSTEMPTY(1U) 1440 1441 #define S_ARPLUTPERR 26 1442 #define V_ARPLUTPERR(x) ((x) << S_ARPLUTPERR) 1443 #define F_ARPLUTPERR V_ARPLUTPERR(1U) 1444 1445 #define S_CMCACHEPERR 24 1446 #define V_CMCACHEPERR(x) ((x) << S_CMCACHEPERR) 1447 #define F_CMCACHEPERR V_CMCACHEPERR(1U) 1448 1449 #define A_TP_INT_CAUSE 0x474 1450 1451 #define A_TP_TX_MOD_Q1_Q0_RATE_LIMIT 0x8 1452 1453 #define A_TP_TX_DROP_CFG_CH0 0x12b 1454 1455 #define A_TP_TX_DROP_MODE 0x12f 1456 1457 #define A_TP_EGRESS_CONFIG 0x145 1458 1459 #define S_REWRITEFORCETOSIZE 0 1460 #define V_REWRITEFORCETOSIZE(x) ((x) << S_REWRITEFORCETOSIZE) 1461 #define F_REWRITEFORCETOSIZE V_REWRITEFORCETOSIZE(1U) 1462 1463 #define A_TP_TX_TRC_KEY0 0x20 1464 1465 #define A_TP_RX_TRC_KEY0 0x120 1466 1467 #define A_TP_TX_DROP_CNT_CH0 0x12d 1468 1469 #define S_TXDROPCNTCH0RCVD 0 1470 #define M_TXDROPCNTCH0RCVD 0xffff 1471 #define V_TXDROPCNTCH0RCVD(x) ((x) << S_TXDROPCNTCH0RCVD) 1472 #define G_TXDROPCNTCH0RCVD(x) (((x) >> S_TXDROPCNTCH0RCVD) & \ 1473 M_TXDROPCNTCH0RCVD) 1474 1475 #define A_TP_PROXY_FLOW_CNTL 0x4b0 1476 1477 #define A_TP_EMBED_OP_FIELD0 0x4e8 1478 #define A_TP_EMBED_OP_FIELD1 0x4ec 1479 #define A_TP_EMBED_OP_FIELD2 0x4f0 1480 #define A_TP_EMBED_OP_FIELD3 0x4f4 1481 #define A_TP_EMBED_OP_FIELD4 0x4f8 1482 #define A_TP_EMBED_OP_FIELD5 0x4fc 1483 1484 #define A_ULPRX_CTL 0x500 1485 1486 #define S_ROUND_ROBIN 4 1487 #define V_ROUND_ROBIN(x) ((x) << S_ROUND_ROBIN) 1488 #define F_ROUND_ROBIN V_ROUND_ROBIN(1U) 1489 1490 #define A_ULPRX_INT_ENABLE 0x504 1491 1492 #define S_DATASELFRAMEERR0 7 1493 #define V_DATASELFRAMEERR0(x) ((x) << S_DATASELFRAMEERR0) 1494 #define F_DATASELFRAMEERR0 V_DATASELFRAMEERR0(1U) 1495 1496 #define S_DATASELFRAMEERR1 6 1497 #define V_DATASELFRAMEERR1(x) ((x) << S_DATASELFRAMEERR1) 1498 #define F_DATASELFRAMEERR1 V_DATASELFRAMEERR1(1U) 1499 1500 #define S_PCMDMUXPERR 5 1501 #define V_PCMDMUXPERR(x) ((x) << S_PCMDMUXPERR) 1502 #define F_PCMDMUXPERR V_PCMDMUXPERR(1U) 1503 1504 #define S_ARBFPERR 4 1505 #define V_ARBFPERR(x) ((x) << S_ARBFPERR) 1506 #define F_ARBFPERR V_ARBFPERR(1U) 1507 1508 #define S_ARBPF0PERR 3 1509 #define V_ARBPF0PERR(x) ((x) << S_ARBPF0PERR) 1510 #define F_ARBPF0PERR V_ARBPF0PERR(1U) 1511 1512 #define S_ARBPF1PERR 2 1513 #define V_ARBPF1PERR(x) ((x) << S_ARBPF1PERR) 1514 #define F_ARBPF1PERR V_ARBPF1PERR(1U) 1515 1516 #define S_PARERRPCMD 1 1517 #define V_PARERRPCMD(x) ((x) << S_PARERRPCMD) 1518 #define F_PARERRPCMD V_PARERRPCMD(1U) 1519 1520 #define S_PARERRDATA 0 1521 #define V_PARERRDATA(x) ((x) << S_PARERRDATA) 1522 #define F_PARERRDATA V_PARERRDATA(1U) 1523 1524 #define A_ULPRX_INT_CAUSE 0x508 1525 1526 #define A_ULPRX_ISCSI_LLIMIT 0x50c 1527 1528 #define A_ULPRX_ISCSI_ULIMIT 0x510 1529 1530 #define A_ULPRX_ISCSI_TAGMASK 0x514 1531 1532 #define A_ULPRX_ISCSI_PSZ 0x518 1533 1534 #define A_ULPRX_TDDP_LLIMIT 0x51c 1535 1536 #define A_ULPRX_TDDP_ULIMIT 0x520 1537 #define A_ULPRX_TDDP_PSZ 0x528 1538 1539 #define S_HPZ0 0 1540 #define M_HPZ0 0xf 1541 #define V_HPZ0(x) ((x) << S_HPZ0) 1542 #define G_HPZ0(x) (((x) >> S_HPZ0) & M_HPZ0) 1543 1544 #define A_ULPRX_STAG_LLIMIT 0x52c 1545 1546 #define A_ULPRX_STAG_ULIMIT 0x530 1547 1548 #define A_ULPRX_RQ_LLIMIT 0x534 1549 #define A_ULPRX_RQ_LLIMIT 0x534 1550 1551 #define A_ULPRX_RQ_ULIMIT 0x538 1552 #define A_ULPRX_RQ_ULIMIT 0x538 1553 1554 #define A_ULPRX_PBL_LLIMIT 0x53c 1555 1556 #define A_ULPRX_PBL_ULIMIT 0x540 1557 #define A_ULPRX_PBL_ULIMIT 0x540 1558 1559 #define A_ULPRX_TDDP_TAGMASK 0x524 1560 1561 #define A_ULPRX_RQ_LLIMIT 0x534 1562 #define A_ULPRX_RQ_LLIMIT 0x534 1563 1564 #define A_ULPRX_RQ_ULIMIT 0x538 1565 #define A_ULPRX_RQ_ULIMIT 0x538 1566 1567 #define A_ULPRX_PBL_ULIMIT 0x540 1568 #define A_ULPRX_PBL_ULIMIT 0x540 1569 1570 #define A_ULPTX_CONFIG 0x580 1571 1572 #define S_CFG_CQE_SOP_MASK 1 1573 #define V_CFG_CQE_SOP_MASK(x) ((x) << S_CFG_CQE_SOP_MASK) 1574 #define F_CFG_CQE_SOP_MASK V_CFG_CQE_SOP_MASK(1U) 1575 1576 #define S_CFG_RR_ARB 0 1577 #define V_CFG_RR_ARB(x) ((x) << S_CFG_RR_ARB) 1578 #define F_CFG_RR_ARB V_CFG_RR_ARB(1U) 1579 1580 #define A_ULPTX_INT_ENABLE 0x584 1581 1582 #define S_PBL_BOUND_ERR_CH1 1 1583 #define V_PBL_BOUND_ERR_CH1(x) ((x) << S_PBL_BOUND_ERR_CH1) 1584 #define F_PBL_BOUND_ERR_CH1 V_PBL_BOUND_ERR_CH1(1U) 1585 1586 #define S_PBL_BOUND_ERR_CH0 0 1587 #define V_PBL_BOUND_ERR_CH0(x) ((x) << S_PBL_BOUND_ERR_CH0) 1588 #define F_PBL_BOUND_ERR_CH0 V_PBL_BOUND_ERR_CH0(1U) 1589 1590 #define A_ULPTX_INT_CAUSE 0x588 1591 1592 #define A_ULPTX_TPT_LLIMIT 0x58c 1593 1594 #define A_ULPTX_TPT_ULIMIT 0x590 1595 1596 #define A_ULPTX_PBL_LLIMIT 0x594 1597 1598 #define A_ULPTX_PBL_ULIMIT 0x598 1599 1600 #define A_ULPTX_DMA_WEIGHT 0x5ac 1601 1602 #define S_D1_WEIGHT 16 1603 #define M_D1_WEIGHT 0xffff 1604 #define V_D1_WEIGHT(x) ((x) << S_D1_WEIGHT) 1605 1606 #define S_D0_WEIGHT 0 1607 #define M_D0_WEIGHT 0xffff 1608 #define V_D0_WEIGHT(x) ((x) << S_D0_WEIGHT) 1609 1610 #define A_PM1_RX_CFG 0x5c0 1611 #define A_PM1_RX_MODE 0x5c4 1612 1613 #define A_PM1_RX_INT_ENABLE 0x5d8 1614 1615 #define S_ZERO_E_CMD_ERROR 18 1616 #define V_ZERO_E_CMD_ERROR(x) ((x) << S_ZERO_E_CMD_ERROR) 1617 #define F_ZERO_E_CMD_ERROR V_ZERO_E_CMD_ERROR(1U) 1618 1619 #define S_IESPI0_FIFO2X_RX_FRAMING_ERROR 17 1620 #define V_IESPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI0_FIFO2X_RX_FRAMING_ERROR) 1621 #define F_IESPI0_FIFO2X_RX_FRAMING_ERROR V_IESPI0_FIFO2X_RX_FRAMING_ERROR(1U) 1622 1623 #define S_IESPI1_FIFO2X_RX_FRAMING_ERROR 16 1624 #define V_IESPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI1_FIFO2X_RX_FRAMING_ERROR) 1625 #define F_IESPI1_FIFO2X_RX_FRAMING_ERROR V_IESPI1_FIFO2X_RX_FRAMING_ERROR(1U) 1626 1627 #define S_IESPI0_RX_FRAMING_ERROR 15 1628 #define V_IESPI0_RX_FRAMING_ERROR(x) ((x) << S_IESPI0_RX_FRAMING_ERROR) 1629 #define F_IESPI0_RX_FRAMING_ERROR V_IESPI0_RX_FRAMING_ERROR(1U) 1630 1631 #define S_IESPI1_RX_FRAMING_ERROR 14 1632 #define V_IESPI1_RX_FRAMING_ERROR(x) ((x) << S_IESPI1_RX_FRAMING_ERROR) 1633 #define F_IESPI1_RX_FRAMING_ERROR V_IESPI1_RX_FRAMING_ERROR(1U) 1634 1635 #define S_IESPI0_TX_FRAMING_ERROR 13 1636 #define V_IESPI0_TX_FRAMING_ERROR(x) ((x) << S_IESPI0_TX_FRAMING_ERROR) 1637 #define F_IESPI0_TX_FRAMING_ERROR V_IESPI0_TX_FRAMING_ERROR(1U) 1638 1639 #define S_IESPI1_TX_FRAMING_ERROR 12 1640 #define V_IESPI1_TX_FRAMING_ERROR(x) ((x) << S_IESPI1_TX_FRAMING_ERROR) 1641 #define F_IESPI1_TX_FRAMING_ERROR V_IESPI1_TX_FRAMING_ERROR(1U) 1642 1643 #define S_OCSPI0_RX_FRAMING_ERROR 11 1644 #define V_OCSPI0_RX_FRAMING_ERROR(x) ((x) << S_OCSPI0_RX_FRAMING_ERROR) 1645 #define F_OCSPI0_RX_FRAMING_ERROR V_OCSPI0_RX_FRAMING_ERROR(1U) 1646 1647 #define S_OCSPI1_RX_FRAMING_ERROR 10 1648 #define V_OCSPI1_RX_FRAMING_ERROR(x) ((x) << S_OCSPI1_RX_FRAMING_ERROR) 1649 #define F_OCSPI1_RX_FRAMING_ERROR V_OCSPI1_RX_FRAMING_ERROR(1U) 1650 1651 #define S_OCSPI0_TX_FRAMING_ERROR 9 1652 #define V_OCSPI0_TX_FRAMING_ERROR(x) ((x) << S_OCSPI0_TX_FRAMING_ERROR) 1653 #define F_OCSPI0_TX_FRAMING_ERROR V_OCSPI0_TX_FRAMING_ERROR(1U) 1654 1655 #define S_OCSPI1_TX_FRAMING_ERROR 8 1656 #define V_OCSPI1_TX_FRAMING_ERROR(x) ((x) << S_OCSPI1_TX_FRAMING_ERROR) 1657 #define F_OCSPI1_TX_FRAMING_ERROR V_OCSPI1_TX_FRAMING_ERROR(1U) 1658 1659 #define S_OCSPI0_OFIFO2X_TX_FRAMING_ERROR 7 1660 #define V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI0_OFIFO2X_TX_FRAMING_ERROR) 1661 #define F_OCSPI0_OFIFO2X_TX_FRAMING_ERROR V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(1U) 1662 1663 #define S_OCSPI1_OFIFO2X_TX_FRAMING_ERROR 6 1664 #define V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI1_OFIFO2X_TX_FRAMING_ERROR) 1665 #define F_OCSPI1_OFIFO2X_TX_FRAMING_ERROR V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(1U) 1666 1667 #define S_IESPI_PAR_ERROR 3 1668 #define M_IESPI_PAR_ERROR 0x7 1669 1670 #define V_IESPI_PAR_ERROR(x) ((x) << S_IESPI_PAR_ERROR) 1671 1672 #define S_OCSPI_PAR_ERROR 0 1673 #define M_OCSPI_PAR_ERROR 0x7 1674 1675 #define V_OCSPI_PAR_ERROR(x) ((x) << S_OCSPI_PAR_ERROR) 1676 1677 #define A_PM1_RX_INT_CAUSE 0x5dc 1678 1679 #define A_PM1_TX_CFG 0x5e0 1680 #define A_PM1_TX_MODE 0x5e4 1681 1682 #define A_PM1_TX_INT_ENABLE 0x5f8 1683 1684 #define S_ZERO_C_CMD_ERROR 18 1685 #define V_ZERO_C_CMD_ERROR(x) ((x) << S_ZERO_C_CMD_ERROR) 1686 #define F_ZERO_C_CMD_ERROR V_ZERO_C_CMD_ERROR(1U) 1687 1688 #define S_ICSPI0_FIFO2X_RX_FRAMING_ERROR 17 1689 #define V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI0_FIFO2X_RX_FRAMING_ERROR) 1690 #define F_ICSPI0_FIFO2X_RX_FRAMING_ERROR V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(1U) 1691 1692 #define S_ICSPI1_FIFO2X_RX_FRAMING_ERROR 16 1693 #define V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI1_FIFO2X_RX_FRAMING_ERROR) 1694 #define F_ICSPI1_FIFO2X_RX_FRAMING_ERROR V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(1U) 1695 1696 #define S_ICSPI0_RX_FRAMING_ERROR 15 1697 #define V_ICSPI0_RX_FRAMING_ERROR(x) ((x) << S_ICSPI0_RX_FRAMING_ERROR) 1698 #define F_ICSPI0_RX_FRAMING_ERROR V_ICSPI0_RX_FRAMING_ERROR(1U) 1699 1700 #define S_ICSPI1_RX_FRAMING_ERROR 14 1701 #define V_ICSPI1_RX_FRAMING_ERROR(x) ((x) << S_ICSPI1_RX_FRAMING_ERROR) 1702 #define F_ICSPI1_RX_FRAMING_ERROR V_ICSPI1_RX_FRAMING_ERROR(1U) 1703 1704 #define S_ICSPI0_TX_FRAMING_ERROR 13 1705 #define V_ICSPI0_TX_FRAMING_ERROR(x) ((x) << S_ICSPI0_TX_FRAMING_ERROR) 1706 #define F_ICSPI0_TX_FRAMING_ERROR V_ICSPI0_TX_FRAMING_ERROR(1U) 1707 1708 #define S_ICSPI1_TX_FRAMING_ERROR 12 1709 #define V_ICSPI1_TX_FRAMING_ERROR(x) ((x) << S_ICSPI1_TX_FRAMING_ERROR) 1710 #define F_ICSPI1_TX_FRAMING_ERROR V_ICSPI1_TX_FRAMING_ERROR(1U) 1711 1712 #define S_OESPI0_RX_FRAMING_ERROR 11 1713 #define V_OESPI0_RX_FRAMING_ERROR(x) ((x) << S_OESPI0_RX_FRAMING_ERROR) 1714 #define F_OESPI0_RX_FRAMING_ERROR V_OESPI0_RX_FRAMING_ERROR(1U) 1715 1716 #define S_OESPI1_RX_FRAMING_ERROR 10 1717 #define V_OESPI1_RX_FRAMING_ERROR(x) ((x) << S_OESPI1_RX_FRAMING_ERROR) 1718 #define F_OESPI1_RX_FRAMING_ERROR V_OESPI1_RX_FRAMING_ERROR(1U) 1719 1720 #define S_OESPI0_TX_FRAMING_ERROR 9 1721 #define V_OESPI0_TX_FRAMING_ERROR(x) ((x) << S_OESPI0_TX_FRAMING_ERROR) 1722 #define F_OESPI0_TX_FRAMING_ERROR V_OESPI0_TX_FRAMING_ERROR(1U) 1723 1724 #define S_OESPI1_TX_FRAMING_ERROR 8 1725 #define V_OESPI1_TX_FRAMING_ERROR(x) ((x) << S_OESPI1_TX_FRAMING_ERROR) 1726 #define F_OESPI1_TX_FRAMING_ERROR V_OESPI1_TX_FRAMING_ERROR(1U) 1727 1728 #define S_OESPI0_OFIFO2X_TX_FRAMING_ERROR 7 1729 #define V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI0_OFIFO2X_TX_FRAMING_ERROR) 1730 #define F_OESPI0_OFIFO2X_TX_FRAMING_ERROR V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(1U) 1731 1732 #define S_OESPI1_OFIFO2X_TX_FRAMING_ERROR 6 1733 #define V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI1_OFIFO2X_TX_FRAMING_ERROR) 1734 #define F_OESPI1_OFIFO2X_TX_FRAMING_ERROR V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(1U) 1735 1736 #define S_ICSPI_PAR_ERROR 3 1737 #define M_ICSPI_PAR_ERROR 0x7 1738 1739 #define V_ICSPI_PAR_ERROR(x) ((x) << S_ICSPI_PAR_ERROR) 1740 1741 #define S_OESPI_PAR_ERROR 0 1742 #define M_OESPI_PAR_ERROR 0x7 1743 1744 #define V_OESPI_PAR_ERROR(x) ((x) << S_OESPI_PAR_ERROR) 1745 1746 #define A_PM1_TX_INT_CAUSE 0x5fc 1747 1748 #define A_MPS_CFG 0x600 1749 1750 #define S_TPRXPORTEN 4 1751 #define V_TPRXPORTEN(x) ((x) << S_TPRXPORTEN) 1752 #define F_TPRXPORTEN V_TPRXPORTEN(1U) 1753 1754 #define S_TPTXPORT1EN 3 1755 #define V_TPTXPORT1EN(x) ((x) << S_TPTXPORT1EN) 1756 #define F_TPTXPORT1EN V_TPTXPORT1EN(1U) 1757 1758 #define S_TPTXPORT0EN 2 1759 #define V_TPTXPORT0EN(x) ((x) << S_TPTXPORT0EN) 1760 #define F_TPTXPORT0EN V_TPTXPORT0EN(1U) 1761 1762 #define S_PORT1ACTIVE 1 1763 #define V_PORT1ACTIVE(x) ((x) << S_PORT1ACTIVE) 1764 #define F_PORT1ACTIVE V_PORT1ACTIVE(1U) 1765 1766 #define S_PORT0ACTIVE 0 1767 #define V_PORT0ACTIVE(x) ((x) << S_PORT0ACTIVE) 1768 #define F_PORT0ACTIVE V_PORT0ACTIVE(1U) 1769 1770 #define S_ENFORCEPKT 11 1771 #define V_ENFORCEPKT(x) ((x) << S_ENFORCEPKT) 1772 #define F_ENFORCEPKT V_ENFORCEPKT(1U) 1773 1774 #define A_MPS_INT_ENABLE 0x61c 1775 1776 #define S_MCAPARERRENB 6 1777 #define M_MCAPARERRENB 0x7 1778 1779 #define V_MCAPARERRENB(x) ((x) << S_MCAPARERRENB) 1780 1781 #define S_RXTPPARERRENB 4 1782 #define M_RXTPPARERRENB 0x3 1783 1784 #define V_RXTPPARERRENB(x) ((x) << S_RXTPPARERRENB) 1785 1786 #define S_TX1TPPARERRENB 2 1787 #define M_TX1TPPARERRENB 0x3 1788 1789 #define V_TX1TPPARERRENB(x) ((x) << S_TX1TPPARERRENB) 1790 1791 #define S_TX0TPPARERRENB 0 1792 #define M_TX0TPPARERRENB 0x3 1793 1794 #define V_TX0TPPARERRENB(x) ((x) << S_TX0TPPARERRENB) 1795 1796 #define A_MPS_INT_CAUSE 0x620 1797 1798 #define S_MCAPARERR 6 1799 #define M_MCAPARERR 0x7 1800 1801 #define V_MCAPARERR(x) ((x) << S_MCAPARERR) 1802 1803 #define S_RXTPPARERR 4 1804 #define M_RXTPPARERR 0x3 1805 1806 #define V_RXTPPARERR(x) ((x) << S_RXTPPARERR) 1807 1808 #define S_TX1TPPARERR 2 1809 #define M_TX1TPPARERR 0x3 1810 1811 #define V_TX1TPPARERR(x) ((x) << S_TX1TPPARERR) 1812 1813 #define S_TX0TPPARERR 0 1814 #define M_TX0TPPARERR 0x3 1815 1816 #define V_TX0TPPARERR(x) ((x) << S_TX0TPPARERR) 1817 1818 #define A_CPL_SWITCH_CNTRL 0x640 1819 1820 #define A_CPL_INTR_ENABLE 0x650 1821 1822 #define S_CIM_OP_MAP_PERR 5 1823 #define V_CIM_OP_MAP_PERR(x) ((x) << S_CIM_OP_MAP_PERR) 1824 #define F_CIM_OP_MAP_PERR V_CIM_OP_MAP_PERR(1U) 1825 1826 #define S_CIM_OVFL_ERROR 4 1827 #define V_CIM_OVFL_ERROR(x) ((x) << S_CIM_OVFL_ERROR) 1828 #define F_CIM_OVFL_ERROR V_CIM_OVFL_ERROR(1U) 1829 1830 #define S_TP_FRAMING_ERROR 3 1831 #define V_TP_FRAMING_ERROR(x) ((x) << S_TP_FRAMING_ERROR) 1832 #define F_TP_FRAMING_ERROR V_TP_FRAMING_ERROR(1U) 1833 1834 #define S_SGE_FRAMING_ERROR 2 1835 #define V_SGE_FRAMING_ERROR(x) ((x) << S_SGE_FRAMING_ERROR) 1836 #define F_SGE_FRAMING_ERROR V_SGE_FRAMING_ERROR(1U) 1837 1838 #define S_CIM_FRAMING_ERROR 1 1839 #define V_CIM_FRAMING_ERROR(x) ((x) << S_CIM_FRAMING_ERROR) 1840 #define F_CIM_FRAMING_ERROR V_CIM_FRAMING_ERROR(1U) 1841 1842 #define S_ZERO_SWITCH_ERROR 0 1843 #define V_ZERO_SWITCH_ERROR(x) ((x) << S_ZERO_SWITCH_ERROR) 1844 #define F_ZERO_SWITCH_ERROR V_ZERO_SWITCH_ERROR(1U) 1845 1846 #define A_CPL_INTR_CAUSE 0x654 1847 1848 #define A_CPL_MAP_TBL_DATA 0x65c 1849 1850 #define A_SMB_GLOBAL_TIME_CFG 0x660 1851 1852 #define A_I2C_CFG 0x6a0 1853 1854 #define S_I2C_CLKDIV 0 1855 #define M_I2C_CLKDIV 0xfff 1856 #define V_I2C_CLKDIV(x) ((x) << S_I2C_CLKDIV) 1857 1858 #define A_MI1_CFG 0x6b0 1859 1860 #define S_CLKDIV 5 1861 #define M_CLKDIV 0xff 1862 #define V_CLKDIV(x) ((x) << S_CLKDIV) 1863 1864 #define S_ST 3 1865 1866 #define M_ST 0x3 1867 1868 #define V_ST(x) ((x) << S_ST) 1869 1870 #define G_ST(x) (((x) >> S_ST) & M_ST) 1871 1872 #define S_PREEN 2 1873 #define V_PREEN(x) ((x) << S_PREEN) 1874 #define F_PREEN V_PREEN(1U) 1875 1876 #define S_MDIINV 1 1877 #define V_MDIINV(x) ((x) << S_MDIINV) 1878 #define F_MDIINV V_MDIINV(1U) 1879 1880 #define S_MDIEN 0 1881 #define V_MDIEN(x) ((x) << S_MDIEN) 1882 #define F_MDIEN V_MDIEN(1U) 1883 1884 #define A_MI1_ADDR 0x6b4 1885 1886 #define S_PHYADDR 5 1887 #define M_PHYADDR 0x1f 1888 #define V_PHYADDR(x) ((x) << S_PHYADDR) 1889 1890 #define S_REGADDR 0 1891 #define M_REGADDR 0x1f 1892 #define V_REGADDR(x) ((x) << S_REGADDR) 1893 1894 #define A_MI1_DATA 0x6b8 1895 1896 #define A_MI1_OP 0x6bc 1897 1898 #define S_MDI_OP 0 1899 #define M_MDI_OP 0x3 1900 #define V_MDI_OP(x) ((x) << S_MDI_OP) 1901 1902 #define A_SF_DATA 0x6d8 1903 1904 #define A_SF_OP 0x6dc 1905 1906 #define S_BYTECNT 1 1907 #define M_BYTECNT 0x3 1908 #define V_BYTECNT(x) ((x) << S_BYTECNT) 1909 1910 #define A_PL_INT_ENABLE0 0x6e0 1911 1912 #define S_T3DBG 23 1913 #define V_T3DBG(x) ((x) << S_T3DBG) 1914 #define F_T3DBG V_T3DBG(1U) 1915 1916 #define S_XGMAC0_1 20 1917 #define V_XGMAC0_1(x) ((x) << S_XGMAC0_1) 1918 #define F_XGMAC0_1 V_XGMAC0_1(1U) 1919 1920 #define S_XGMAC0_0 19 1921 #define V_XGMAC0_0(x) ((x) << S_XGMAC0_0) 1922 #define F_XGMAC0_0 V_XGMAC0_0(1U) 1923 1924 #define S_MC5A 18 1925 #define V_MC5A(x) ((x) << S_MC5A) 1926 #define F_MC5A V_MC5A(1U) 1927 1928 #define S_CPL_SWITCH 12 1929 #define V_CPL_SWITCH(x) ((x) << S_CPL_SWITCH) 1930 #define F_CPL_SWITCH V_CPL_SWITCH(1U) 1931 1932 #define S_MPS0 11 1933 #define V_MPS0(x) ((x) << S_MPS0) 1934 #define F_MPS0 V_MPS0(1U) 1935 1936 #define S_PM1_TX 10 1937 #define V_PM1_TX(x) ((x) << S_PM1_TX) 1938 #define F_PM1_TX V_PM1_TX(1U) 1939 1940 #define S_PM1_RX 9 1941 #define V_PM1_RX(x) ((x) << S_PM1_RX) 1942 #define F_PM1_RX V_PM1_RX(1U) 1943 1944 #define S_ULP2_TX 8 1945 #define V_ULP2_TX(x) ((x) << S_ULP2_TX) 1946 #define F_ULP2_TX V_ULP2_TX(1U) 1947 1948 #define S_ULP2_RX 7 1949 #define V_ULP2_RX(x) ((x) << S_ULP2_RX) 1950 #define F_ULP2_RX V_ULP2_RX(1U) 1951 1952 #define S_TP1 6 1953 #define V_TP1(x) ((x) << S_TP1) 1954 #define F_TP1 V_TP1(1U) 1955 1956 #define S_CIM 5 1957 #define V_CIM(x) ((x) << S_CIM) 1958 #define F_CIM V_CIM(1U) 1959 1960 #define S_MC7_CM 4 1961 #define V_MC7_CM(x) ((x) << S_MC7_CM) 1962 #define F_MC7_CM V_MC7_CM(1U) 1963 1964 #define S_MC7_PMTX 3 1965 #define V_MC7_PMTX(x) ((x) << S_MC7_PMTX) 1966 #define F_MC7_PMTX V_MC7_PMTX(1U) 1967 1968 #define S_MC7_PMRX 2 1969 #define V_MC7_PMRX(x) ((x) << S_MC7_PMRX) 1970 #define F_MC7_PMRX V_MC7_PMRX(1U) 1971 1972 #define S_PCIM0 1 1973 #define V_PCIM0(x) ((x) << S_PCIM0) 1974 #define F_PCIM0 V_PCIM0(1U) 1975 1976 #define S_SGE3 0 1977 #define V_SGE3(x) ((x) << S_SGE3) 1978 #define F_SGE3 V_SGE3(1U) 1979 1980 #define A_PL_INT_CAUSE0 0x6e4 1981 1982 #define A_PL_RST 0x6f0 1983 1984 #define S_CRSTWRM 1 1985 #define V_CRSTWRM(x) ((x) << S_CRSTWRM) 1986 #define F_CRSTWRM V_CRSTWRM(1U) 1987 1988 #define A_PL_REV 0x6f4 1989 1990 #define A_PL_CLI 0x6f8 1991 1992 #define A_MC5_DB_CONFIG 0x704 1993 1994 #define S_TMTYPEHI 30 1995 #define V_TMTYPEHI(x) ((x) << S_TMTYPEHI) 1996 #define F_TMTYPEHI V_TMTYPEHI(1U) 1997 1998 #define S_TMPARTSIZE 28 1999 #define M_TMPARTSIZE 0x3 2000 #define V_TMPARTSIZE(x) ((x) << S_TMPARTSIZE) 2001 #define G_TMPARTSIZE(x) (((x) >> S_TMPARTSIZE) & M_TMPARTSIZE) 2002 2003 #define S_TMTYPE 26 2004 #define M_TMTYPE 0x3 2005 #define V_TMTYPE(x) ((x) << S_TMTYPE) 2006 #define G_TMTYPE(x) (((x) >> S_TMTYPE) & M_TMTYPE) 2007 2008 #define S_COMPEN 17 2009 #define V_COMPEN(x) ((x) << S_COMPEN) 2010 #define F_COMPEN V_COMPEN(1U) 2011 2012 #define S_PRTYEN 6 2013 #define V_PRTYEN(x) ((x) << S_PRTYEN) 2014 #define F_PRTYEN V_PRTYEN(1U) 2015 2016 #define S_MBUSEN 5 2017 #define V_MBUSEN(x) ((x) << S_MBUSEN) 2018 #define F_MBUSEN V_MBUSEN(1U) 2019 2020 #define S_DBGIEN 4 2021 #define V_DBGIEN(x) ((x) << S_DBGIEN) 2022 #define F_DBGIEN V_DBGIEN(1U) 2023 2024 #define S_TMRDY 2 2025 #define V_TMRDY(x) ((x) << S_TMRDY) 2026 #define F_TMRDY V_TMRDY(1U) 2027 2028 #define S_TMRST 1 2029 #define V_TMRST(x) ((x) << S_TMRST) 2030 #define F_TMRST V_TMRST(1U) 2031 2032 #define S_TMMODE 0 2033 #define V_TMMODE(x) ((x) << S_TMMODE) 2034 #define F_TMMODE V_TMMODE(1U) 2035 2036 #define F_TMMODE V_TMMODE(1U) 2037 2038 #define A_MC5_DB_ROUTING_TABLE_INDEX 0x70c 2039 2040 #define A_MC5_DB_FILTER_TABLE 0x710 2041 2042 #define A_MC5_DB_SERVER_INDEX 0x714 2043 2044 #define A_MC5_DB_RSP_LATENCY 0x720 2045 2046 #define S_RDLAT 16 2047 #define M_RDLAT 0x1f 2048 #define V_RDLAT(x) ((x) << S_RDLAT) 2049 2050 #define S_LRNLAT 8 2051 #define M_LRNLAT 0x1f 2052 #define V_LRNLAT(x) ((x) << S_LRNLAT) 2053 2054 #define S_SRCHLAT 0 2055 #define M_SRCHLAT 0x1f 2056 #define V_SRCHLAT(x) ((x) << S_SRCHLAT) 2057 2058 #define A_MC5_DB_PART_ID_INDEX 0x72c 2059 2060 #define A_MC5_DB_INT_ENABLE 0x740 2061 2062 #define S_DELACTEMPTY 18 2063 #define V_DELACTEMPTY(x) ((x) << S_DELACTEMPTY) 2064 #define F_DELACTEMPTY V_DELACTEMPTY(1U) 2065 2066 #define S_DISPQPARERR 17 2067 #define V_DISPQPARERR(x) ((x) << S_DISPQPARERR) 2068 #define F_DISPQPARERR V_DISPQPARERR(1U) 2069 2070 #define S_REQQPARERR 16 2071 #define V_REQQPARERR(x) ((x) << S_REQQPARERR) 2072 #define F_REQQPARERR V_REQQPARERR(1U) 2073 2074 #define S_UNKNOWNCMD 15 2075 #define V_UNKNOWNCMD(x) ((x) << S_UNKNOWNCMD) 2076 #define F_UNKNOWNCMD V_UNKNOWNCMD(1U) 2077 2078 #define S_NFASRCHFAIL 8 2079 #define V_NFASRCHFAIL(x) ((x) << S_NFASRCHFAIL) 2080 #define F_NFASRCHFAIL V_NFASRCHFAIL(1U) 2081 2082 #define S_ACTRGNFULL 7 2083 #define V_ACTRGNFULL(x) ((x) << S_ACTRGNFULL) 2084 #define F_ACTRGNFULL V_ACTRGNFULL(1U) 2085 2086 #define S_PARITYERR 6 2087 #define V_PARITYERR(x) ((x) << S_PARITYERR) 2088 #define F_PARITYERR V_PARITYERR(1U) 2089 2090 #define A_MC5_DB_INT_CAUSE 0x744 2091 2092 #define A_MC5_DB_DBGI_CONFIG 0x774 2093 2094 #define A_MC5_DB_DBGI_REQ_CMD 0x778 2095 2096 #define A_MC5_DB_DBGI_REQ_ADDR0 0x77c 2097 2098 #define A_MC5_DB_DBGI_REQ_ADDR1 0x780 2099 2100 #define A_MC5_DB_DBGI_REQ_ADDR2 0x784 2101 2102 #define A_MC5_DB_DBGI_REQ_DATA0 0x788 2103 2104 #define A_MC5_DB_DBGI_REQ_DATA1 0x78c 2105 2106 #define A_MC5_DB_DBGI_REQ_DATA2 0x790 2107 2108 #define A_MC5_DB_DBGI_RSP_STATUS 0x7b0 2109 2110 #define S_DBGIRSPVALID 0 2111 #define V_DBGIRSPVALID(x) ((x) << S_DBGIRSPVALID) 2112 #define F_DBGIRSPVALID V_DBGIRSPVALID(1U) 2113 2114 #define A_MC5_DB_DBGI_RSP_DATA0 0x7b4 2115 2116 #define A_MC5_DB_DBGI_RSP_DATA1 0x7b8 2117 2118 #define A_MC5_DB_DBGI_RSP_DATA2 0x7bc 2119 2120 #define A_MC5_DB_POPEN_DATA_WR_CMD 0x7cc 2121 2122 #define A_MC5_DB_POPEN_MASK_WR_CMD 0x7d0 2123 2124 #define A_MC5_DB_AOPEN_SRCH_CMD 0x7d4 2125 2126 #define A_MC5_DB_AOPEN_LRN_CMD 0x7d8 2127 2128 #define A_MC5_DB_SYN_SRCH_CMD 0x7dc 2129 2130 #define A_MC5_DB_SYN_LRN_CMD 0x7e0 2131 2132 #define A_MC5_DB_ACK_SRCH_CMD 0x7e4 2133 2134 #define A_MC5_DB_ACK_LRN_CMD 0x7e8 2135 2136 #define A_MC5_DB_ILOOKUP_CMD 0x7ec 2137 2138 #define A_MC5_DB_ELOOKUP_CMD 0x7f0 2139 2140 #define A_MC5_DB_DATA_WRITE_CMD 0x7f4 2141 2142 #define A_MC5_DB_DATA_READ_CMD 0x7f8 2143 2144 #define XGMAC0_0_BASE_ADDR 0x800 2145 2146 #define A_XGM_TX_CTRL 0x800 2147 2148 #define S_TXEN 0 2149 #define V_TXEN(x) ((x) << S_TXEN) 2150 #define F_TXEN V_TXEN(1U) 2151 2152 #define A_XGM_TX_CFG 0x804 2153 2154 #define S_TXPAUSEEN 0 2155 #define V_TXPAUSEEN(x) ((x) << S_TXPAUSEEN) 2156 #define F_TXPAUSEEN V_TXPAUSEEN(1U) 2157 2158 #define A_XGM_TX_PAUSE_QUANTA 0x808 2159 2160 #define A_XGM_RX_CTRL 0x80c 2161 2162 #define S_RXEN 0 2163 #define V_RXEN(x) ((x) << S_RXEN) 2164 #define F_RXEN V_RXEN(1U) 2165 2166 #define A_XGM_RX_CFG 0x810 2167 2168 #define S_DISPAUSEFRAMES 9 2169 #define V_DISPAUSEFRAMES(x) ((x) << S_DISPAUSEFRAMES) 2170 #define F_DISPAUSEFRAMES V_DISPAUSEFRAMES(1U) 2171 2172 #define S_EN1536BFRAMES 8 2173 #define V_EN1536BFRAMES(x) ((x) << S_EN1536BFRAMES) 2174 #define F_EN1536BFRAMES V_EN1536BFRAMES(1U) 2175 2176 #define S_ENJUMBO 7 2177 #define V_ENJUMBO(x) ((x) << S_ENJUMBO) 2178 #define F_ENJUMBO V_ENJUMBO(1U) 2179 2180 #define S_RMFCS 6 2181 #define V_RMFCS(x) ((x) << S_RMFCS) 2182 #define F_RMFCS V_RMFCS(1U) 2183 2184 #define S_ENHASHMCAST 2 2185 #define V_ENHASHMCAST(x) ((x) << S_ENHASHMCAST) 2186 #define F_ENHASHMCAST V_ENHASHMCAST(1U) 2187 2188 #define S_COPYALLFRAMES 0 2189 #define V_COPYALLFRAMES(x) ((x) << S_COPYALLFRAMES) 2190 #define F_COPYALLFRAMES V_COPYALLFRAMES(1U) 2191 2192 #define S_DISBCAST 1 2193 #define V_DISBCAST(x) ((x) << S_DISBCAST) 2194 #define F_DISBCAST V_DISBCAST(1U) 2195 2196 #define A_XGM_RX_HASH_LOW 0x814 2197 2198 #define A_XGM_RX_HASH_HIGH 0x818 2199 2200 #define A_XGM_RX_EXACT_MATCH_LOW_1 0x81c 2201 2202 #define A_XGM_RX_EXACT_MATCH_HIGH_1 0x820 2203 2204 #define A_XGM_RX_EXACT_MATCH_LOW_2 0x824 2205 2206 #define A_XGM_RX_EXACT_MATCH_LOW_3 0x82c 2207 2208 #define A_XGM_RX_EXACT_MATCH_LOW_4 0x834 2209 2210 #define A_XGM_RX_EXACT_MATCH_LOW_5 0x83c 2211 2212 #define A_XGM_RX_EXACT_MATCH_LOW_6 0x844 2213 2214 #define A_XGM_RX_EXACT_MATCH_LOW_7 0x84c 2215 2216 #define A_XGM_RX_EXACT_MATCH_LOW_8 0x854 2217 2218 #define A_XGM_INT_STATUS 0x86c 2219 2220 #define S_LINKFAULTCHANGE 9 2221 #define V_LINKFAULTCHANGE(x) ((x) << S_LINKFAULTCHANGE) 2222 #define F_LINKFAULTCHANGE V_LINKFAULTCHANGE(1U) 2223 2224 #define A_XGM_XGM_INT_ENABLE 0x874 2225 #define A_XGM_XGM_INT_DISABLE 0x878 2226 2227 #define A_XGM_STAT_CTRL 0x880 2228 2229 #define S_CLRSTATS 2 2230 #define V_CLRSTATS(x) ((x) << S_CLRSTATS) 2231 #define F_CLRSTATS V_CLRSTATS(1U) 2232 2233 #define A_XGM_RXFIFO_CFG 0x884 2234 2235 #define S_RXFIFO_EMPTY 31 2236 #define V_RXFIFO_EMPTY(x) ((x) << S_RXFIFO_EMPTY) 2237 #define F_RXFIFO_EMPTY V_RXFIFO_EMPTY(1U) 2238 2239 #define S_RXFIFOPAUSEHWM 17 2240 #define M_RXFIFOPAUSEHWM 0xfff 2241 2242 #define V_RXFIFOPAUSEHWM(x) ((x) << S_RXFIFOPAUSEHWM) 2243 2244 #define G_RXFIFOPAUSEHWM(x) (((x) >> S_RXFIFOPAUSEHWM) & M_RXFIFOPAUSEHWM) 2245 2246 #define S_RXFIFOPAUSELWM 5 2247 #define M_RXFIFOPAUSELWM 0xfff 2248 2249 #define V_RXFIFOPAUSELWM(x) ((x) << S_RXFIFOPAUSELWM) 2250 2251 #define G_RXFIFOPAUSELWM(x) (((x) >> S_RXFIFOPAUSELWM) & M_RXFIFOPAUSELWM) 2252 2253 #define S_RXSTRFRWRD 1 2254 #define V_RXSTRFRWRD(x) ((x) << S_RXSTRFRWRD) 2255 #define F_RXSTRFRWRD V_RXSTRFRWRD(1U) 2256 2257 #define S_DISERRFRAMES 0 2258 #define V_DISERRFRAMES(x) ((x) << S_DISERRFRAMES) 2259 #define F_DISERRFRAMES V_DISERRFRAMES(1U) 2260 2261 #define A_XGM_TXFIFO_CFG 0x888 2262 2263 #define S_UNDERUNFIX 22 2264 #define V_UNDERUNFIX(x) ((x) << S_UNDERUNFIX) 2265 #define F_UNDERUNFIX V_UNDERUNFIX(1U) 2266 2267 #define S_TXIPG 13 2268 #define M_TXIPG 0xff 2269 #define V_TXIPG(x) ((x) << S_TXIPG) 2270 #define G_TXIPG(x) (((x) >> S_TXIPG) & M_TXIPG) 2271 2272 #define S_TXFIFOTHRESH 4 2273 #define M_TXFIFOTHRESH 0x1ff 2274 2275 #define V_TXFIFOTHRESH(x) ((x) << S_TXFIFOTHRESH) 2276 2277 #define S_ENDROPPKT 21 2278 #define V_ENDROPPKT(x) ((x) << S_ENDROPPKT) 2279 #define F_ENDROPPKT V_ENDROPPKT(1U) 2280 2281 #define A_XGM_SERDES_CTRL 0x890 2282 #define A_XGM_SERDES_CTRL0 0x8e0 2283 2284 #define S_SERDESRESET_ 24 2285 #define V_SERDESRESET_(x) ((x) << S_SERDESRESET_) 2286 #define F_SERDESRESET_ V_SERDESRESET_(1U) 2287 2288 #define S_RXENABLE 4 2289 #define V_RXENABLE(x) ((x) << S_RXENABLE) 2290 #define F_RXENABLE V_RXENABLE(1U) 2291 2292 #define S_TXENABLE 3 2293 #define V_TXENABLE(x) ((x) << S_TXENABLE) 2294 #define F_TXENABLE V_TXENABLE(1U) 2295 2296 #define A_XGM_PAUSE_TIMER 0x890 2297 2298 #define A_XGM_RGMII_IMP 0x89c 2299 2300 #define S_XGM_IMPSETUPDATE 6 2301 #define V_XGM_IMPSETUPDATE(x) ((x) << S_XGM_IMPSETUPDATE) 2302 #define F_XGM_IMPSETUPDATE V_XGM_IMPSETUPDATE(1U) 2303 2304 #define S_RGMIIIMPPD 3 2305 #define M_RGMIIIMPPD 0x7 2306 #define V_RGMIIIMPPD(x) ((x) << S_RGMIIIMPPD) 2307 2308 #define S_RGMIIIMPPU 0 2309 #define M_RGMIIIMPPU 0x7 2310 #define V_RGMIIIMPPU(x) ((x) << S_RGMIIIMPPU) 2311 2312 #define S_CALRESET 8 2313 #define V_CALRESET(x) ((x) << S_CALRESET) 2314 #define F_CALRESET V_CALRESET(1U) 2315 2316 #define S_CALUPDATE 7 2317 #define V_CALUPDATE(x) ((x) << S_CALUPDATE) 2318 #define F_CALUPDATE V_CALUPDATE(1U) 2319 2320 #define A_XGM_XAUI_IMP 0x8a0 2321 2322 #define S_CALBUSY 31 2323 #define V_CALBUSY(x) ((x) << S_CALBUSY) 2324 #define F_CALBUSY V_CALBUSY(1U) 2325 2326 #define S_XGM_CALFAULT 29 2327 #define V_XGM_CALFAULT(x) ((x) << S_XGM_CALFAULT) 2328 #define F_XGM_CALFAULT V_XGM_CALFAULT(1U) 2329 2330 #define S_CALIMP 24 2331 #define M_CALIMP 0x1f 2332 #define V_CALIMP(x) ((x) << S_CALIMP) 2333 #define G_CALIMP(x) (((x) >> S_CALIMP) & M_CALIMP) 2334 2335 #define S_XAUIIMP 0 2336 #define M_XAUIIMP 0x7 2337 #define V_XAUIIMP(x) ((x) << S_XAUIIMP) 2338 2339 #define A_XGM_RX_MAX_PKT_SIZE 0x8a8 2340 2341 #define S_RXMAXFRAMERSIZE 17 2342 #define M_RXMAXFRAMERSIZE 0x3fff 2343 #define V_RXMAXFRAMERSIZE(x) ((x) << S_RXMAXFRAMERSIZE) 2344 #define G_RXMAXFRAMERSIZE(x) (((x) >> S_RXMAXFRAMERSIZE) & M_RXMAXFRAMERSIZE) 2345 2346 #define S_RXENFRAMER 14 2347 #define V_RXENFRAMER(x) ((x) << S_RXENFRAMER) 2348 #define F_RXENFRAMER V_RXENFRAMER(1U) 2349 2350 #define S_RXMAXPKTSIZE 0 2351 #define M_RXMAXPKTSIZE 0x3fff 2352 #define V_RXMAXPKTSIZE(x) ((x) << S_RXMAXPKTSIZE) 2353 #define G_RXMAXPKTSIZE(x) (((x) >> S_RXMAXPKTSIZE) & M_RXMAXPKTSIZE) 2354 2355 #define A_XGM_RESET_CTRL 0x8ac 2356 2357 #define S_XGMAC_STOP_EN 4 2358 #define V_XGMAC_STOP_EN(x) ((x) << S_XGMAC_STOP_EN) 2359 #define F_XGMAC_STOP_EN V_XGMAC_STOP_EN(1U) 2360 2361 #define S_XG2G_RESET_ 3 2362 #define V_XG2G_RESET_(x) ((x) << S_XG2G_RESET_) 2363 #define F_XG2G_RESET_ V_XG2G_RESET_(1U) 2364 2365 #define S_RGMII_RESET_ 2 2366 #define V_RGMII_RESET_(x) ((x) << S_RGMII_RESET_) 2367 #define F_RGMII_RESET_ V_RGMII_RESET_(1U) 2368 2369 #define S_PCS_RESET_ 1 2370 #define V_PCS_RESET_(x) ((x) << S_PCS_RESET_) 2371 #define F_PCS_RESET_ V_PCS_RESET_(1U) 2372 2373 #define S_MAC_RESET_ 0 2374 #define V_MAC_RESET_(x) ((x) << S_MAC_RESET_) 2375 #define F_MAC_RESET_ V_MAC_RESET_(1U) 2376 2377 #define A_XGM_PORT_CFG 0x8b8 2378 2379 #define S_CLKDIVRESET_ 3 2380 #define V_CLKDIVRESET_(x) ((x) << S_CLKDIVRESET_) 2381 #define F_CLKDIVRESET_ V_CLKDIVRESET_(1U) 2382 2383 #define S_PORTSPEED 1 2384 #define M_PORTSPEED 0x3 2385 2386 #define V_PORTSPEED(x) ((x) << S_PORTSPEED) 2387 2388 #define S_ENRGMII 0 2389 #define V_ENRGMII(x) ((x) << S_ENRGMII) 2390 #define F_ENRGMII V_ENRGMII(1U) 2391 2392 #define A_XGM_INT_ENABLE 0x8d4 2393 2394 #define S_TXFIFO_PRTY_ERR 17 2395 #define M_TXFIFO_PRTY_ERR 0x7 2396 2397 #define V_TXFIFO_PRTY_ERR(x) ((x) << S_TXFIFO_PRTY_ERR) 2398 2399 #define S_RXFIFO_PRTY_ERR 14 2400 #define M_RXFIFO_PRTY_ERR 0x7 2401 2402 #define V_RXFIFO_PRTY_ERR(x) ((x) << S_RXFIFO_PRTY_ERR) 2403 2404 #define S_TXFIFO_UNDERRUN 13 2405 #define V_TXFIFO_UNDERRUN(x) ((x) << S_TXFIFO_UNDERRUN) 2406 #define F_TXFIFO_UNDERRUN V_TXFIFO_UNDERRUN(1U) 2407 2408 #define S_RXFIFO_OVERFLOW 12 2409 #define V_RXFIFO_OVERFLOW(x) ((x) << S_RXFIFO_OVERFLOW) 2410 #define F_RXFIFO_OVERFLOW V_RXFIFO_OVERFLOW(1U) 2411 2412 #define S_SERDES_LOS 4 2413 #define M_SERDES_LOS 0xf 2414 2415 #define V_SERDES_LOS(x) ((x) << S_SERDES_LOS) 2416 2417 #define S_XAUIPCSCTCERR 3 2418 #define V_XAUIPCSCTCERR(x) ((x) << S_XAUIPCSCTCERR) 2419 #define F_XAUIPCSCTCERR V_XAUIPCSCTCERR(1U) 2420 2421 #define S_XAUIPCSALIGNCHANGE 2 2422 #define V_XAUIPCSALIGNCHANGE(x) ((x) << S_XAUIPCSALIGNCHANGE) 2423 #define F_XAUIPCSALIGNCHANGE V_XAUIPCSALIGNCHANGE(1U) 2424 2425 #define S_XGM_INT 0 2426 #define V_XGM_INT(x) ((x) << S_XGM_INT) 2427 #define F_XGM_INT V_XGM_INT(1U) 2428 2429 #define A_XGM_INT_CAUSE 0x8d8 2430 2431 #define A_XGM_XAUI_ACT_CTRL 0x8dc 2432 2433 #define S_TXACTENABLE 1 2434 #define V_TXACTENABLE(x) ((x) << S_TXACTENABLE) 2435 #define F_TXACTENABLE V_TXACTENABLE(1U) 2436 2437 #define A_XGM_SERDES_CTRL0 0x8e0 2438 2439 #define S_RESET3 23 2440 #define V_RESET3(x) ((x) << S_RESET3) 2441 #define F_RESET3 V_RESET3(1U) 2442 2443 #define S_RESET2 22 2444 #define V_RESET2(x) ((x) << S_RESET2) 2445 #define F_RESET2 V_RESET2(1U) 2446 2447 #define S_RESET1 21 2448 #define V_RESET1(x) ((x) << S_RESET1) 2449 #define F_RESET1 V_RESET1(1U) 2450 2451 #define S_RESET0 20 2452 #define V_RESET0(x) ((x) << S_RESET0) 2453 #define F_RESET0 V_RESET0(1U) 2454 2455 #define S_PWRDN3 19 2456 #define V_PWRDN3(x) ((x) << S_PWRDN3) 2457 #define F_PWRDN3 V_PWRDN3(1U) 2458 2459 #define S_PWRDN2 18 2460 #define V_PWRDN2(x) ((x) << S_PWRDN2) 2461 #define F_PWRDN2 V_PWRDN2(1U) 2462 2463 #define S_PWRDN1 17 2464 #define V_PWRDN1(x) ((x) << S_PWRDN1) 2465 #define F_PWRDN1 V_PWRDN1(1U) 2466 2467 #define S_PWRDN0 16 2468 #define V_PWRDN0(x) ((x) << S_PWRDN0) 2469 #define F_PWRDN0 V_PWRDN0(1U) 2470 2471 #define S_RESETPLL23 15 2472 #define V_RESETPLL23(x) ((x) << S_RESETPLL23) 2473 #define F_RESETPLL23 V_RESETPLL23(1U) 2474 2475 #define S_RESETPLL01 14 2476 #define V_RESETPLL01(x) ((x) << S_RESETPLL01) 2477 #define F_RESETPLL01 V_RESETPLL01(1U) 2478 2479 #define A_XGM_SERDES_STAT0 0x8f0 2480 #define A_XGM_SERDES_STAT1 0x8f4 2481 #define A_XGM_SERDES_STAT2 0x8f8 2482 2483 #define S_LOWSIG0 0 2484 #define V_LOWSIG0(x) ((x) << S_LOWSIG0) 2485 #define F_LOWSIG0 V_LOWSIG0(1U) 2486 2487 #define A_XGM_SERDES_STAT3 0x8fc 2488 2489 #define A_XGM_STAT_TX_BYTE_LOW 0x900 2490 2491 #define A_XGM_STAT_TX_BYTE_HIGH 0x904 2492 2493 #define A_XGM_STAT_TX_FRAME_LOW 0x908 2494 2495 #define A_XGM_STAT_TX_FRAME_HIGH 0x90c 2496 2497 #define A_XGM_STAT_TX_BCAST 0x910 2498 2499 #define A_XGM_STAT_TX_MCAST 0x914 2500 2501 #define A_XGM_STAT_TX_PAUSE 0x918 2502 2503 #define A_XGM_STAT_TX_64B_FRAMES 0x91c 2504 2505 #define A_XGM_STAT_TX_65_127B_FRAMES 0x920 2506 2507 #define A_XGM_STAT_TX_128_255B_FRAMES 0x924 2508 2509 #define A_XGM_STAT_TX_256_511B_FRAMES 0x928 2510 2511 #define A_XGM_STAT_TX_512_1023B_FRAMES 0x92c 2512 2513 #define A_XGM_STAT_TX_1024_1518B_FRAMES 0x930 2514 2515 #define A_XGM_STAT_TX_1519_MAXB_FRAMES 0x934 2516 2517 #define A_XGM_STAT_TX_ERR_FRAMES 0x938 2518 2519 #define A_XGM_STAT_RX_BYTES_LOW 0x93c 2520 2521 #define A_XGM_STAT_RX_BYTES_HIGH 0x940 2522 2523 #define A_XGM_STAT_RX_FRAMES_LOW 0x944 2524 2525 #define A_XGM_STAT_RX_FRAMES_HIGH 0x948 2526 2527 #define A_XGM_STAT_RX_BCAST_FRAMES 0x94c 2528 2529 #define A_XGM_STAT_RX_MCAST_FRAMES 0x950 2530 2531 #define A_XGM_STAT_RX_PAUSE_FRAMES 0x954 2532 2533 #define A_XGM_STAT_RX_64B_FRAMES 0x958 2534 2535 #define A_XGM_STAT_RX_65_127B_FRAMES 0x95c 2536 2537 #define A_XGM_STAT_RX_128_255B_FRAMES 0x960 2538 2539 #define A_XGM_STAT_RX_256_511B_FRAMES 0x964 2540 2541 #define A_XGM_STAT_RX_512_1023B_FRAMES 0x968 2542 2543 #define A_XGM_STAT_RX_1024_1518B_FRAMES 0x96c 2544 2545 #define A_XGM_STAT_RX_1519_MAXB_FRAMES 0x970 2546 2547 #define A_XGM_STAT_RX_SHORT_FRAMES 0x974 2548 2549 #define A_XGM_STAT_RX_OVERSIZE_FRAMES 0x978 2550 2551 #define A_XGM_STAT_RX_JABBER_FRAMES 0x97c 2552 2553 #define A_XGM_STAT_RX_CRC_ERR_FRAMES 0x980 2554 2555 #define A_XGM_STAT_RX_LENGTH_ERR_FRAMES 0x984 2556 2557 #define A_XGM_STAT_RX_SYM_CODE_ERR_FRAMES 0x988 2558 2559 #define A_XGM_SERDES_STATUS0 0x98c 2560 2561 #define A_XGM_SERDES_STATUS1 0x990 2562 2563 #define S_CMULOCK 31 2564 #define V_CMULOCK(x) ((x) << S_CMULOCK) 2565 #define F_CMULOCK V_CMULOCK(1U) 2566 2567 #define A_XGM_RX_MAX_PKT_SIZE_ERR_CNT 0x9a4 2568 2569 #define A_XGM_TX_SPI4_SOP_EOP_CNT 0x9a8 2570 2571 #define S_TXSPI4SOPCNT 16 2572 #define M_TXSPI4SOPCNT 0xffff 2573 #define V_TXSPI4SOPCNT(x) ((x) << S_TXSPI4SOPCNT) 2574 #define G_TXSPI4SOPCNT(x) (((x) >> S_TXSPI4SOPCNT) & M_TXSPI4SOPCNT) 2575 2576 #define A_XGM_RX_SPI4_SOP_EOP_CNT 0x9ac 2577 2578 #define XGMAC0_1_BASE_ADDR 0xa00 2579
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