1 /*****************************************************************************
2 * *
3 * File: sge.c *
4 * $Revision: 1.26 $ *
5 * $Date: 2005/06/21 18:29:48 $ *
6 * Description: *
7 * DMA engine. *
8 * part of the Chelsio 10Gb Ethernet Driver. *
9 * *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License, version 2, as *
12 * published by the Free Software Foundation. *
13 * *
14 * You should have received a copy of the GNU General Public License along *
15 * with this program; if not, write to the Free Software Foundation, Inc., *
16 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
17 * *
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
19 * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
21 * *
22 * http://www.chelsio.com *
23 * *
24 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
25 * All rights reserved. *
26 * *
27 * Maintainers: maintainers@chelsio.com *
28 * *
29 * Authors: Dimitrios Michailidis <dm@chelsio.com> *
30 * Tina Yang <tainay@chelsio.com> *
31 * Felix Marti <felix@chelsio.com> *
32 * Scott Bardone <sbardone@chelsio.com> *
33 * Kurt Ottaway <kottaway@chelsio.com> *
34 * Frank DiMambro <frank@chelsio.com> *
35 * *
36 * History: *
37 * *
38 ****************************************************************************/
39
40 #include "common.h"
41
42 #include <linux/types.h>
43 #include <linux/errno.h>
44 #include <linux/pci.h>
45 #include <linux/ktime.h>
46 #include <linux/netdevice.h>
47 #include <linux/etherdevice.h>
48 #include <linux/if_vlan.h>
49 #include <linux/skbuff.h>
50 #include <linux/init.h>
51 #include <linux/mm.h>
52 #include <linux/tcp.h>
53 #include <linux/ip.h>
54 #include <linux/in.h>
55 #include <linux/if_arp.h>
56
57 #include "cpl5_cmd.h"
58 #include "sge.h"
59 #include "regs.h"
60 #include "espi.h"
61
62 /* This belongs in if_ether.h */
63 #define ETH_P_CPL5 0xf
64
65 #define SGE_CMDQ_N 2
66 #define SGE_FREELQ_N 2
67 #define SGE_CMDQ0_E_N 1024
68 #define SGE_CMDQ1_E_N 128
69 #define SGE_FREEL_SIZE 4096
70 #define SGE_JUMBO_FREEL_SIZE 512
71 #define SGE_FREEL_REFILL_THRESH 16
72 #define SGE_RESPQ_E_N 1024
73 #define SGE_INTRTIMER_NRES 1000
74 #define SGE_RX_SM_BUF_SIZE 1536
75 #define SGE_TX_DESC_MAX_PLEN 16384
76
77 #define SGE_RESPQ_REPLENISH_THRES (SGE_RESPQ_E_N / 4)
78
79 /*
80 * Period of the TX buffer reclaim timer. This timer does not need to run
81 * frequently as TX buffers are usually reclaimed by new TX packets.
82 */
83 #define TX_RECLAIM_PERIOD (HZ / 4)
84
85 #define M_CMD_LEN 0x7fffffff
86 #define V_CMD_LEN(v) (v)
87 #define G_CMD_LEN(v) ((v) & M_CMD_LEN)
88 #define V_CMD_GEN1(v) ((v) << 31)
89 #define V_CMD_GEN2(v) (v)
90 #define F_CMD_DATAVALID (1 << 1)
91 #define F_CMD_SOP (1 << 2)
92 #define V_CMD_EOP(v) ((v) << 3)
93
94 /*
95 * Command queue, receive buffer list, and response queue descriptors.
96 */
97 #if defined(__BIG_ENDIAN_BITFIELD)
98 struct cmdQ_e {
99 u32 addr_lo;
100 u32 len_gen;
101 u32 flags;
102 u32 addr_hi;
103 };
104
105 struct freelQ_e {
106 u32 addr_lo;
107 u32 len_gen;
108 u32 gen2;
109 u32 addr_hi;
110 };
111
112 struct respQ_e {
113 u32 Qsleeping : 4;
114 u32 Cmdq1CreditReturn : 5;
115 u32 Cmdq1DmaComplete : 5;
116 u32 Cmdq0CreditReturn : 5;
117 u32 Cmdq0DmaComplete : 5;
118 u32 FreelistQid : 2;
119 u32 CreditValid : 1;
120 u32 DataValid : 1;
121 u32 Offload : 1;
122 u32 Eop : 1;
123 u32 Sop : 1;
124 u32 GenerationBit : 1;
125 u32 BufferLength;
126 };
127 #elif defined(__LITTLE_ENDIAN_BITFIELD)
128 struct cmdQ_e {
129 u32 len_gen;
130 u32 addr_lo;
131 u32 addr_hi;
132 u32 flags;
133 };
134
135 struct freelQ_e {
136 u32 len_gen;
137 u32 addr_lo;
138 u32 addr_hi;
139 u32 gen2;
140 };
141
142 struct respQ_e {
143 u32 BufferLength;
144 u32 GenerationBit : 1;
145 u32 Sop : 1;
146 u32 Eop : 1;
147 u32 Offload : 1;
148 u32 DataValid : 1;
149 u32 CreditValid : 1;
150 u32 FreelistQid : 2;
151 u32 Cmdq0DmaComplete : 5;
152 u32 Cmdq0CreditReturn : 5;
153 u32 Cmdq1DmaComplete : 5;
154 u32 Cmdq1CreditReturn : 5;
155 u32 Qsleeping : 4;
156 } ;
157 #endif
158
159 /*
160 * SW Context Command and Freelist Queue Descriptors
161 */
162 struct cmdQ_ce {
163 struct sk_buff *skb;
164 DECLARE_PCI_UNMAP_ADDR(dma_addr);
165 DECLARE_PCI_UNMAP_LEN(dma_len);
166 };
167
168 struct freelQ_ce {
169 struct sk_buff *skb;
170 DECLARE_PCI_UNMAP_ADDR(dma_addr);
171 DECLARE_PCI_UNMAP_LEN(dma_len);
172 };
173
174 /*
175 * SW command, freelist and response rings
176 */
177 struct cmdQ {
178 unsigned long status; /* HW DMA fetch status */
179 unsigned int in_use; /* # of in-use command descriptors */
180 unsigned int size; /* # of descriptors */
181 unsigned int processed; /* total # of descs HW has processed */
182 unsigned int cleaned; /* total # of descs SW has reclaimed */
183 unsigned int stop_thres; /* SW TX queue suspend threshold */
184 u16 pidx; /* producer index (SW) */
185 u16 cidx; /* consumer index (HW) */
186 u8 genbit; /* current generation (=valid) bit */
187 u8 sop; /* is next entry start of packet? */
188 struct cmdQ_e *entries; /* HW command descriptor Q */
189 struct cmdQ_ce *centries; /* SW command context descriptor Q */
190 dma_addr_t dma_addr; /* DMA addr HW command descriptor Q */
191 spinlock_t lock; /* Lock to protect cmdQ enqueuing */
192 };
193
194 struct freelQ {
195 unsigned int credits; /* # of available RX buffers */
196 unsigned int size; /* free list capacity */
197 u16 pidx; /* producer index (SW) */
198 u16 cidx; /* consumer index (HW) */
199 u16 rx_buffer_size; /* Buffer size on this free list */
200 u16 dma_offset; /* DMA offset to align IP headers */
201 u16 recycleq_idx; /* skb recycle q to use */
202 u8 genbit; /* current generation (=valid) bit */
203 struct freelQ_e *entries; /* HW freelist descriptor Q */
204 struct freelQ_ce *centries; /* SW freelist context descriptor Q */
205 dma_addr_t dma_addr; /* DMA addr HW freelist descriptor Q */
206 };
207
208 struct respQ {
209 unsigned int credits; /* credits to be returned to SGE */
210 unsigned int size; /* # of response Q descriptors */
211 u16 cidx; /* consumer index (SW) */
212 u8 genbit; /* current generation(=valid) bit */
213 struct respQ_e *entries; /* HW response descriptor Q */
214 dma_addr_t dma_addr; /* DMA addr HW response descriptor Q */
215 };
216
217 /* Bit flags for cmdQ.status */
218 enum {
219 CMDQ_STAT_RUNNING = 1, /* fetch engine is running */
220 CMDQ_STAT_LAST_PKT_DB = 2 /* last packet rung the doorbell */
221 };
222
223 /* T204 TX SW scheduler */
224
225 /* Per T204 TX port */
226 struct sched_port {
227 unsigned int avail; /* available bits - quota */
228 unsigned int drain_bits_per_1024ns; /* drain rate */
229 unsigned int speed; /* drain rate, mbps */
230 unsigned int mtu; /* mtu size */
231 struct sk_buff_head skbq; /* pending skbs */
232 };
233
234 /* Per T204 device */
235 struct sched {
236 ktime_t last_updated; /* last time quotas were computed */
237 unsigned int max_avail; /* max bits to be sent to any port */
238 unsigned int port; /* port index (round robin ports) */
239 unsigned int num; /* num skbs in per port queues */
240 struct sched_port p[MAX_NPORTS];
241 struct tasklet_struct sched_tsk;/* tasklet used to run scheduler */
242 };
243 static void restart_sched(unsigned long);
244
245
246 /*
247 * Main SGE data structure
248 *
249 * Interrupts are handled by a single CPU and it is likely that on a MP system
250 * the application is migrated to another CPU. In that scenario, we try to
251 * seperate the RX(in irq context) and TX state in order to decrease memory
252 * contention.
253 */
254 struct sge {
255 struct adapter *adapter; /* adapter backpointer */
256 struct net_device *netdev; /* netdevice backpointer */
257 struct freelQ freelQ[SGE_FREELQ_N]; /* buffer free lists */
258 struct respQ respQ; /* response Q */
259 unsigned long stopped_tx_queues; /* bitmap of suspended Tx queues */
260 unsigned int rx_pkt_pad; /* RX padding for L2 packets */
261 unsigned int jumbo_fl; /* jumbo freelist Q index */
262 unsigned int intrtimer_nres; /* no-resource interrupt timer */
263 unsigned int fixed_intrtimer;/* non-adaptive interrupt timer */
264 struct timer_list tx_reclaim_timer; /* reclaims TX buffers */
265 struct timer_list espibug_timer;
266 unsigned long espibug_timeout;
267 struct sk_buff *espibug_skb[MAX_NPORTS];
268 u32 sge_control; /* shadow value of sge control reg */
269 struct sge_intr_counts stats;
270 struct sge_port_stats *port_stats[MAX_NPORTS];
271 struct sched *tx_sched;
272 struct cmdQ cmdQ[SGE_CMDQ_N] ____cacheline_aligned_in_smp;
273 };
274
275 /*
276 * stop tasklet and free all pending skb's
277 */
278 static void tx_sched_stop(struct sge *sge)
279 {
280 struct sched *s = sge->tx_sched;
281 int i;
282
283 tasklet_kill(&s->sched_tsk);
284
285 for (i = 0; i < MAX_NPORTS; i++)
286 __skb_queue_purge(&s->p[s->port].skbq);
287 }
288
289 /*
290 * t1_sched_update_parms() is called when the MTU or link speed changes. It
291 * re-computes scheduler parameters to scope with the change.
292 */
293 unsigned int t1_sched_update_parms(struct sge *sge, unsigned int port,
294 unsigned int mtu, unsigned int speed)
295 {
296 struct sched *s = sge->tx_sched;
297 struct sched_port *p = &s->p[port];
298 unsigned int max_avail_segs;
299
300 pr_debug("t1_sched_update_params mtu=%d speed=%d\n", mtu, speed);
301 if (speed)
302 p->speed = speed;
303 if (mtu)
304 p->mtu = mtu;
305
306 if (speed || mtu) {
307 unsigned long long drain = 1024ULL * p->speed * (p->mtu - 40);
308 do_div(drain, (p->mtu + 50) * 1000);
309 p->drain_bits_per_1024ns = (unsigned int) drain;
310
311 if (p->speed < 1000)
312 p->drain_bits_per_1024ns =
313 90 * p->drain_bits_per_1024ns / 100;
314 }
315
316 if (board_info(sge->adapter)->board == CHBT_BOARD_CHT204) {
317 p->drain_bits_per_1024ns -= 16;
318 s->max_avail = max(4096U, p->mtu + 16 + 14 + 4);
319 max_avail_segs = max(1U, 4096 / (p->mtu - 40));
320 } else {
321 s->max_avail = 16384;
322 max_avail_segs = max(1U, 9000 / (p->mtu - 40));
323 }
324
325 pr_debug("t1_sched_update_parms: mtu %u speed %u max_avail %u "
326 "max_avail_segs %u drain_bits_per_1024ns %u\n", p->mtu,
327 p->speed, s->max_avail, max_avail_segs,
328 p->drain_bits_per_1024ns);
329
330 return max_avail_segs * (p->mtu - 40);
331 }
332
333 #if 0
334
335 /*
336 * t1_sched_max_avail_bytes() tells the scheduler the maximum amount of
337 * data that can be pushed per port.
338 */
339 void t1_sched_set_max_avail_bytes(struct sge *sge, unsigned int val)
340 {
341 struct sched *s = sge->tx_sched;
342 unsigned int i;
343
344 s->max_avail = val;
345 for (i = 0; i < MAX_NPORTS; i++)
346 t1_sched_update_parms(sge, i, 0, 0);
347 }
348
349 /*
350 * t1_sched_set_drain_bits_per_us() tells the scheduler at which rate a port
351 * is draining.
352 */
353 void t1_sched_set_drain_bits_per_us(struct sge *sge, unsigned int port,
354 unsigned int val)
355 {
356 struct sched *s = sge->tx_sched;
357 struct sched_port *p = &s->p[port];
358 p->drain_bits_per_1024ns = val * 1024 / 1000;
359 t1_sched_update_parms(sge, port, 0, 0);
360 }
361
362 #endif /* 0 */
363
364
365 /*
366 * get_clock() implements a ns clock (see ktime_get)
367 */
368 static inline ktime_t get_clock(void)
369 {
370 struct timespec ts;
371
372 ktime_get_ts(&ts);
373 return timespec_to_ktime(ts);
374 }
375
376 /*
377 * tx_sched_init() allocates resources and does basic initialization.
378 */
379 static int tx_sched_init(struct sge *sge)
380 {
381 struct sched *s;
382 int i;
383
384 s = kzalloc(sizeof (struct sched), GFP_KERNEL);
385 if (!s)
386 return -ENOMEM;
387
388 pr_debug("tx_sched_init\n");
389 tasklet_init(&s->sched_tsk, restart_sched, (unsigned long) sge);
390 sge->tx_sched = s;
391
392 for (i = 0; i < MAX_NPORTS; i++) {
393 skb_queue_head_init(&s->p[i].skbq);
394 t1_sched_update_parms(sge, i, 1500, 1000);
395 }
396
397 return 0;
398 }
399
400 /*
401 * sched_update_avail() computes the delta since the last time it was called
402 * and updates the per port quota (number of bits that can be sent to the any
403 * port).
404 */
405 static inline int sched_update_avail(struct sge *sge)
406 {
407 struct sched *s = sge->tx_sched;
408 ktime_t now = get_clock();
409 unsigned int i;
410 long long delta_time_ns;
411
412 delta_time_ns = ktime_to_ns(ktime_sub(now, s->last_updated));
413
414 pr_debug("sched_update_avail delta=%lld\n", delta_time_ns);
415 if (delta_time_ns < 15000)
416 return 0;
417
418 for (i = 0; i < MAX_NPORTS; i++) {
419 struct sched_port *p = &s->p[i];
420 unsigned int delta_avail;
421
422 delta_avail = (p->drain_bits_per_1024ns * delta_time_ns) >> 13;
423 p->avail = min(p->avail + delta_avail, s->max_avail);
424 }
425
426 s->last_updated = now;
427
428 return 1;
429 }
430
431 /*
432 * sched_skb() is called from two different places. In the tx path, any
433 * packet generating load on an output port will call sched_skb()
434 * (skb != NULL). In addition, sched_skb() is called from the irq/soft irq
435 * context (skb == NULL).
436 * The scheduler only returns a skb (which will then be sent) if the
437 * length of the skb is <= the current quota of the output port.
438 */
439 static struct sk_buff *sched_skb(struct sge *sge, struct sk_buff *skb,
440 unsigned int credits)
441 {
442 struct sched *s = sge->tx_sched;
443 struct sk_buff_head *skbq;
444 unsigned int i, len, update = 1;
445
446 pr_debug("sched_skb %p\n", skb);
447 if (!skb) {
448 if (!s->num)
449 return NULL;
450 } else {
451 skbq = &s->p[skb->dev->if_port].skbq;
452 __skb_queue_tail(skbq, skb);
453 s->num++;
454 skb = NULL;
455 }
456
457 if (credits < MAX_SKB_FRAGS + 1)
458 goto out;
459
460 again:
461 for (i = 0; i < MAX_NPORTS; i++) {
462 s->port = ++s->port & (MAX_NPORTS - 1);
463 skbq = &s->p[s->port].skbq;
464
465 skb = skb_peek(skbq);
466
467 if (!skb)
468 continue;
469
470 len = skb->len;
471 if (len <= s->p[s->port].avail) {
472 s->p[s->port].avail -= len;
473 s->num--;
474 __skb_unlink(skb, skbq);
475 goto out;
476 }
477 skb = NULL;
478 }
479
480 if (update-- && sched_update_avail(sge))
481 goto again;
482
483 out:
484 /* If there are more pending skbs, we use the hardware to schedule us
485 * again.
486 */
487 if (s->num && !skb) {
488 struct cmdQ *q = &sge->cmdQ[0];
489 clear_bit(CMDQ_STAT_LAST_PKT_DB, &q->status);
490 if (test_and_set_bit(CMDQ_STAT_RUNNING, &q->status) == 0) {
491 set_bit(CMDQ_STAT_LAST_PKT_DB, &q->status);
492 writel(F_CMDQ0_ENABLE, sge->adapter->regs + A_SG_DOORBELL);
493 }
494 }
495 pr_debug("sched_skb ret %p\n", skb);
496
497 return skb;
498 }
499
500 /*
501 * PIO to indicate that memory mapped Q contains valid descriptor(s).
502 */
503 static inline void doorbell_pio(struct adapter *adapter, u32 val)
504 {
505 wmb();
506 writel(val, adapter->regs + A_SG_DOORBELL);
507 }
508
509 /*
510 * Frees all RX buffers on the freelist Q. The caller must make sure that
511 * the SGE is turned off before calling this function.
512 */
513 static void free_freelQ_buffers(struct pci_dev *pdev, struct freelQ *q)
514 {
515 unsigned int cidx = q->cidx;
516
517 while (q->credits--) {
518 struct freelQ_ce *ce = &q->centries[cidx];
519
520 pci_unmap_single(pdev, pci_unmap_addr(ce, dma_addr),
521 pci_unmap_len(ce, dma_len),
522 PCI_DMA_FROMDEVICE);
523 dev_kfree_skb(ce->skb);
524 ce->skb = NULL;
525 if (++cidx == q->size)
526 cidx = 0;
527 }
528 }
529
530 /*
531 * Free RX free list and response queue resources.
532 */
533 static void free_rx_resources(struct sge *sge)
534 {
535 struct pci_dev *pdev = sge->adapter->pdev;
536 unsigned int size, i;
537
538 if (sge->respQ.entries) {
539 size = sizeof(struct respQ_e) * sge->respQ.size;
540 pci_free_consistent(pdev, size, sge->respQ.entries,
541 sge->respQ.dma_addr);
542 }
543
544 for (i = 0; i < SGE_FREELQ_N; i++) {
545 struct freelQ *q = &sge->freelQ[i];
546
547 if (q->centries) {
548 free_freelQ_buffers(pdev, q);
549 kfree(q->centries);
550 }
551 if (q->entries) {
552 size = sizeof(struct freelQ_e) * q->size;
553 pci_free_consistent(pdev, size, q->entries,
554 q->dma_addr);
555 }
556 }
557 }
558
559 /*
560 * Allocates basic RX resources, consisting of memory mapped freelist Qs and a
561 * response queue.
562 */
563 static int alloc_rx_resources(struct sge *sge, struct sge_params *p)
564 {
565 struct pci_dev *pdev = sge->adapter->pdev;
566 unsigned int size, i;
567
568 for (i = 0; i < SGE_FREELQ_N; i++) {
569 struct freelQ *q = &sge->freelQ[i];
570
571 q->genbit = 1;
572 q->size = p->freelQ_size[i];
573 q->dma_offset = sge->rx_pkt_pad ? 0 : NET_IP_ALIGN;
574 size = sizeof(struct freelQ_e) * q->size;
575 q->entries = pci_alloc_consistent(pdev, size, &q->dma_addr);
576 if (!q->entries)
577 goto err_no_mem;
578
579 size = sizeof(struct freelQ_ce) * q->size;
580 q->centries = kzalloc(size, GFP_KERNEL);
581 if (!q->centries)
582 goto err_no_mem;
583 }
584
585 /*
586 * Calculate the buffer sizes for the two free lists. FL0 accommodates
587 * regular sized Ethernet frames, FL1 is sized not to exceed 16K,
588 * including all the sk_buff overhead.
589 *
590 * Note: For T2 FL0 and FL1 are reversed.
591 */
592 sge->freelQ[!sge->jumbo_fl].rx_buffer_size = SGE_RX_SM_BUF_SIZE +
593 sizeof(struct cpl_rx_data) +
594 sge->freelQ[!sge->jumbo_fl].dma_offset;
595
596 size = (16 * 1024) -
597 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
598
599 sge->freelQ[sge->jumbo_fl].rx_buffer_size = size;
600
601 /*
602 * Setup which skb recycle Q should be used when recycling buffers from
603 * each free list.
604 */
605 sge->freelQ[!sge->jumbo_fl].recycleq_idx = 0;
606 sge->freelQ[sge->jumbo_fl].recycleq_idx = 1;
607
608 sge->respQ.genbit = 1;
609 sge->respQ.size = SGE_RESPQ_E_N;
610 sge->respQ.credits = 0;
611 size = sizeof(struct respQ_e) * sge->respQ.size;
612 sge->respQ.entries =
613 pci_alloc_consistent(pdev, size, &sge->respQ.dma_addr);
614 if (!sge->respQ.entries)
615 goto err_no_mem;
616 return 0;
617
618 err_no_mem:
619 free_rx_resources(sge);
620 return -ENOMEM;
621 }
622
623 /*
624 * Reclaims n TX descriptors and frees the buffers associated with them.
625 */
626 static void free_cmdQ_buffers(struct sge *sge, struct cmdQ *q, unsigned int n)
627 {
628 struct cmdQ_ce *ce;
629 struct pci_dev *pdev = sge->adapter->pdev;
630 unsigned int cidx = q->cidx;
631
632 q->in_use -= n;
633 ce = &q->centries[cidx];
634 while (n--) {
635 if (likely(pci_unmap_len(ce, dma_len))) {
636 pci_unmap_single(pdev, pci_unmap_addr(ce, dma_addr),
637 pci_unmap_len(ce, dma_len),
638 PCI_DMA_TODEVICE);
639 if (q->sop)
640 q->sop = 0;
641 }
642 if (ce->skb) {
643 dev_kfree_skb_any(ce->skb);
644 q->sop = 1;
645 }
646 ce++;
647 if (++cidx == q->size) {
648 cidx = 0;
649 ce = q->centries;
650 }
651 }
652 q->cidx = cidx;
653 }
654
655 /*
656 * Free TX resources.
657 *
658 * Assumes that SGE is stopped and all interrupts are disabled.
659 */
660 static void free_tx_resources(struct sge *sge)
661 {
662 struct pci_dev *pdev = sge->adapter->pdev;
663 unsigned int size, i;
664
665 for (i = 0; i < SGE_CMDQ_N; i++) {
666 struct cmdQ *q = &sge->cmdQ[i];
667
668 if (q->centries) {
669 if (q->in_use)
670 free_cmdQ_buffers(sge, q, q->in_use);
671 kfree(q->centries);
672 }
673 if (q->entries) {
674 size = sizeof(struct cmdQ_e) * q->size;
675 pci_free_consistent(pdev, size, q->entries,
676 q->dma_addr);
677 }
678 }
679 }
680
681 /*
682 * Allocates basic TX resources, consisting of memory mapped command Qs.
683 */
684 static int alloc_tx_resources(struct sge *sge, struct sge_params *p)
685 {
686 struct pci_dev *pdev = sge->adapter->pdev;
687 unsigned int size, i;
688
689 for (i = 0; i < SGE_CMDQ_N; i++) {
690 struct cmdQ *q = &sge->cmdQ[i];
691
692 q->genbit = 1;
693 q->sop = 1;
694 q->size = p->cmdQ_size[i];
695 q->in_use = 0;
696 q->status = 0;
697 q->processed = q->cleaned = 0;
698 q->stop_thres = 0;
699 spin_lock_init(&q->lock);
700 size = sizeof(struct cmdQ_e) * q->size;
701 q->entries = pci_alloc_consistent(pdev, size, &q->dma_addr);
702 if (!q->entries)
703 goto err_no_mem;
704
705 size = sizeof(struct cmdQ_ce) * q->size;
706 q->centries = kzalloc(size, GFP_KERNEL);
707 if (!q->centries)
708 goto err_no_mem;
709 }
710
711 /*
712 * CommandQ 0 handles Ethernet and TOE packets, while queue 1 is TOE
713 * only. For queue 0 set the stop threshold so we can handle one more
714 * packet from each port, plus reserve an additional 24 entries for
715 * Ethernet packets only. Queue 1 never suspends nor do we reserve
716 * space for Ethernet packets.
717 */
718 sge->cmdQ[0].stop_thres = sge->adapter->params.nports *
719 (MAX_SKB_FRAGS + 1);
720 return 0;
721
722 err_no_mem:
723 free_tx_resources(sge);
724 return -ENOMEM;
725 }
726
727 static inline void setup_ring_params(struct adapter *adapter, u64 addr,
728 u32 size, int base_reg_lo,
729 int base_reg_hi, int size_reg)
730 {
731 writel((u32)addr, adapter->regs + base_reg_lo);
732 writel(addr >> 32, adapter->regs + base_reg_hi);
733 writel(size, adapter->regs + size_reg);
734 }
735
736 /*
737 * Enable/disable VLAN acceleration.
738 */
739 void t1_set_vlan_accel(struct adapter *adapter, int on_off)
740 {
741 struct sge *sge = adapter->sge;
742
743 sge->sge_control &= ~F_VLAN_XTRACT;
744 if (on_off)
745 sge->sge_control |= F_VLAN_XTRACT;
746 if (adapter->open_device_map) {
747 writel(sge->sge_control, adapter->regs + A_SG_CONTROL);
748 readl(adapter->regs + A_SG_CONTROL); /* flush */
749 }
750 }
751
752 /*
753 * Programs the various SGE registers. However, the engine is not yet enabled,
754 * but sge->sge_control is setup and ready to go.
755 */
756 static void configure_sge(struct sge *sge, struct sge_params *p)
757 {
758 struct adapter *ap = sge->adapter;
759
760 writel(0, ap->regs + A_SG_CONTROL);
761 setup_ring_params(ap, sge->cmdQ[0].dma_addr, sge->cmdQ[0].size,
762 A_SG_CMD0BASELWR, A_SG_CMD0BASEUPR, A_SG_CMD0SIZE);
763 setup_ring_params(ap, sge->cmdQ[1].dma_addr, sge->cmdQ[1].size,
764 A_SG_CMD1BASELWR, A_SG_CMD1BASEUPR, A_SG_CMD1SIZE);
765 setup_ring_params(ap, sge->freelQ[0].dma_addr,
766 sge->freelQ[0].size, A_SG_FL0BASELWR,
767 A_SG_FL0BASEUPR, A_SG_FL0SIZE);
768 setup_ring_params(ap, sge->freelQ[1].dma_addr,
769 sge->freelQ[1].size, A_SG_FL1BASELWR,
770 A_SG_FL1BASEUPR, A_SG_FL1SIZE);
771
772 /* The threshold comparison uses <. */
773 writel(SGE_RX_SM_BUF_SIZE + 1, ap->regs + A_SG_FLTHRESHOLD);
774
775 setup_ring_params(ap, sge->respQ.dma_addr, sge->respQ.size,
776 A_SG_RSPBASELWR, A_SG_RSPBASEUPR, A_SG_RSPSIZE);
777 writel((u32)sge->respQ.size - 1, ap->regs + A_SG_RSPQUEUECREDIT);
778
779 sge->sge_control = F_CMDQ0_ENABLE | F_CMDQ1_ENABLE | F_FL0_ENABLE |
780 F_FL1_ENABLE | F_CPL_ENABLE | F_RESPONSE_QUEUE_ENABLE |
781 V_CMDQ_PRIORITY(2) | F_DISABLE_CMDQ1_GTS | F_ISCSI_COALESCE |
782 V_RX_PKT_OFFSET(sge->rx_pkt_pad);
783
784 #if defined(__BIG_ENDIAN_BITFIELD)
785 sge->sge_control |= F_ENABLE_BIG_ENDIAN;
786 #endif
787
788 /* Initialize no-resource timer */
789 sge->intrtimer_nres = SGE_INTRTIMER_NRES * core_ticks_per_usec(ap);
790
791 t1_sge_set_coalesce_params(sge, p);
792 }
793
794 /*
795 * Return the payload capacity of the jumbo free-list buffers.
796 */
797 static inline unsigned int jumbo_payload_capacity(const struct sge *sge)
798 {
799 return sge->freelQ[sge->jumbo_fl].rx_buffer_size -
800 sge->freelQ[sge->jumbo_fl].dma_offset -
801 sizeof(struct cpl_rx_data);
802 }
803
804 /*
805 * Frees all SGE related resources and the sge structure itself
806 */
807 void t1_sge_destroy(struct sge *sge)
808 {
809 int i;
810
811 for_each_port(sge->adapter, i)
812 free_percpu(sge->port_stats[i]);
813
814 kfree(sge->tx_sched);
815 free_tx_resources(sge);
816 free_rx_resources(sge);
817 kfree(sge);
818 }
819
820 /*
821 * Allocates new RX buffers on the freelist Q (and tracks them on the freelist
822 * context Q) until the Q is full or alloc_skb fails.
823 *
824 * It is possible that the generation bits already match, indicating that the
825 * buffer is already valid and nothing needs to be done. This happens when we
826 * copied a received buffer into a new sk_buff during the interrupt processing.
827 *
828 * If the SGE doesn't automatically align packets properly (!sge->rx_pkt_pad),
829 * we specify a RX_OFFSET in order to make sure that the IP header is 4B
830 * aligned.
831 */
832 static void refill_free_list(struct sge *sge, struct freelQ *q)
833 {
834 struct pci_dev *pdev = sge->adapter->pdev;
835 struct freelQ_ce *ce = &q->centries[q->pidx];
836 struct freelQ_e *e = &q->entries[q->pidx];
837 unsigned int dma_len = q->rx_buffer_size - q->dma_offset;
838
839 while (q->credits < q->size) {
840 struct sk_buff *skb;
841 dma_addr_t mapping;
842
843 skb = alloc_skb(q->rx_buffer_size, GFP_ATOMIC);
844 if (!skb)
845 break;
846
847 skb_reserve(skb, q->dma_offset);
848 mapping = pci_map_single(pdev, skb->data, dma_len,
849 PCI_DMA_FROMDEVICE);
850 skb_reserve(skb, sge->rx_pkt_pad);
851
852 ce->skb = skb;
853 pci_unmap_addr_set(ce, dma_addr, mapping);
854 pci_unmap_len_set(ce, dma_len, dma_len);
855 e->addr_lo = (u32)mapping;
856 e->addr_hi = (u64)mapping >> 32;
857 e->len_gen = V_CMD_LEN(dma_len) | V_CMD_GEN1(q->genbit);
858 wmb();
859 e->gen2 = V_CMD_GEN2(q->genbit);
860
861 e++;
862 ce++;
863 if (++q->pidx == q->size) {
864 q->pidx = 0;
865 q->genbit ^= 1;
866 ce = q->centries;
867 e = q->entries;
868 }
869 q->credits++;
870 }
871 }
872
873 /*
874 * Calls refill_free_list for both free lists. If we cannot fill at least 1/4
875 * of both rings, we go into 'few interrupt mode' in order to give the system
876 * time to free up resources.
877 */
878 static void freelQs_empty(struct sge *sge)
879 {
880 struct adapter *adapter = sge->adapter;
881 u32 irq_reg = readl(adapter->regs + A_SG_INT_ENABLE);
882 u32 irqholdoff_reg;
883
884 refill_free_list(sge, &sge->freelQ[0]);
885 refill_free_list(sge, &sge->freelQ[1]);
886
887 if (sge->freelQ[0].credits > (sge->freelQ[0].size >> 2) &&
888 sge->freelQ[1].credits > (sge->freelQ[1].size >> 2)) {
889 irq_reg |= F_FL_EXHAUSTED;
890 irqholdoff_reg = sge->fixed_intrtimer;
891 } else {
892 /* Clear the F_FL_EXHAUSTED interrupts for now */
893 irq_reg &= ~F_FL_EXHAUSTED;
894 irqholdoff_reg = sge->intrtimer_nres;
895 }
896 writel(irqholdoff_reg, adapter->regs + A_SG_INTRTIMER);
897 writel(irq_reg, adapter->regs + A_SG_INT_ENABLE);
898
899 /* We reenable the Qs to force a freelist GTS interrupt later */
900 doorbell_pio(adapter, F_FL0_ENABLE | F_FL1_ENABLE);
901 }
902
903 #define SGE_PL_INTR_MASK (F_PL_INTR_SGE_ERR | F_PL_INTR_SGE_DATA)
904 #define SGE_INT_FATAL (F_RESPQ_OVERFLOW | F_PACKET_TOO_BIG | F_PACKET_MISMATCH)
905 #define SGE_INT_ENABLE (F_RESPQ_EXHAUSTED | F_RESPQ_OVERFLOW | \
906 F_FL_EXHAUSTED | F_PACKET_TOO_BIG | F_PACKET_MISMATCH)
907
908 /*
909 * Disable SGE Interrupts
910 */
911 void t1_sge_intr_disable(struct sge *sge)
912 {
913 u32 val = readl(sge->adapter->regs + A_PL_ENABLE);
914
915 writel(val & ~SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_ENABLE);
916 writel(0, sge->adapter->regs + A_SG_INT_ENABLE);
917 }
918
919 /*
920 * Enable SGE interrupts.
921 */
922 void t1_sge_intr_enable(struct sge *sge)
923 {
924 u32 en = SGE_INT_ENABLE;
925 u32 val = readl(sge->adapter->regs + A_PL_ENABLE);
926
927 if (sge->adapter->flags & TSO_CAPABLE)
928 en &= ~F_PACKET_TOO_BIG;
929 writel(en, sge->adapter->regs + A_SG_INT_ENABLE);
930 writel(val | SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_ENABLE);
931 }
932
933 /*
934 * Clear SGE interrupts.
935 */
936 void t1_sge_intr_clear(struct sge *sge)
937 {
938 writel(SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_CAUSE);
939 writel(0xffffffff, sge->adapter->regs + A_SG_INT_CAUSE);
940 }
941
942 /*
943 * SGE 'Error' interrupt handler
944 */
945 int t1_sge_intr_error_handler(struct sge *sge)
946 {
947 struct adapter *adapter = sge->adapter;
948 u32 cause = readl(adapter->regs + A_SG_INT_CAUSE);
949
950 if (adapter->flags & TSO_CAPABLE)
951 cause &= ~F_PACKET_TOO_BIG;
952 if (cause & F_RESPQ_EXHAUSTED)
953 sge->stats.respQ_empty++;
954 if (cause & F_RESPQ_OVERFLOW) {
955 sge->stats.respQ_overflow++;
956 CH_ALERT("%s: SGE response queue overflow\n",
957 adapter->name);
958 }
959 if (cause & F_FL_EXHAUSTED) {
960 sge->stats.freelistQ_empty++;
961 freelQs_empty(sge);
962 }
963 if (cause & F_PACKET_TOO_BIG) {
964 sge->stats.pkt_too_big++;
965 CH_ALERT("%s: SGE max packet size exceeded\n",
966 adapter->name);
967 }
968 if (cause & F_PACKET_MISMATCH) {
969 sge->stats.pkt_mismatch++;
970 CH_ALERT("%s: SGE packet mismatch\n", adapter->name);
971 }
972 if (cause & SGE_INT_FATAL)
973 t1_fatal_err(adapter);
974
975 writel(cause, adapter->regs + A_SG_INT_CAUSE);
976 return 0;
977 }
978
979 const struct sge_intr_counts *t1_sge_get_intr_counts(const struct sge *sge)
980 {
981 return &sge->stats;
982 }
983
984 void t1_sge_get_port_stats(const struct sge *sge, int port,
985 struct sge_port_stats *ss)
986 {
987 int cpu;
988
989 memset(ss, 0, sizeof(*ss));
990 for_each_possible_cpu(cpu) {
991 struct sge_port_stats *st = per_cpu_ptr(sge->port_stats[port], cpu);
992
993 ss->rx_cso_good += st->rx_cso_good;
994 ss->tx_cso += st->tx_cso;
995 ss->tx_tso += st->tx_tso;
996 ss->tx_need_hdrroom += st->tx_need_hdrroom;
997 ss->vlan_xtract += st->vlan_xtract;
998 ss->vlan_insert += st->vlan_insert;
999 }
1000 }
1001
1002 /**
1003 * recycle_fl_buf - recycle a free list buffer
1004 * @fl: the free list
1005 * @idx: index of buffer to recycle
1006 *
1007 * Recycles the specified buffer on the given free list by adding it at
1008 * the next available slot on the list.
1009 */
1010 static void recycle_fl_buf(struct freelQ *fl, int idx)
1011 {
1012 struct freelQ_e *from = &fl->entries[idx];
1013 struct freelQ_e *to = &fl->entries[fl->pidx];
1014
1015 fl->centries[fl->pidx] = fl->centries[idx];
1016 to->addr_lo = from->addr_lo;
1017 to->addr_hi = from->addr_hi;
1018 to->len_gen = G_CMD_LEN(from->len_gen) | V_CMD_GEN1(fl->genbit);
1019 wmb();
1020 to->gen2 = V_CMD_GEN2(fl->genbit);
1021 fl->credits++;
1022
1023 if (++fl->pidx == fl->size) {
1024 fl->pidx = 0;
1025 fl->genbit ^= 1;
1026 }
1027 }
1028
1029 static int copybreak __read_mostly = 256;
1030 module_param(copybreak, int, 0);
1031 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
1032
1033 /**
1034 * get_packet - return the next ingress packet buffer
1035 * @pdev: the PCI device that received the packet
1036 * @fl: the SGE free list holding the packet
1037 * @len: the actual packet length, excluding any SGE padding
1038 * @dma_pad: padding at beginning of buffer left by SGE DMA
1039 * @skb_pad: padding to be used if the packet is copied
1040 * @copy_thres: length threshold under which a packet should be copied
1041 * @drop_thres: # of remaining buffers before we start dropping packets
1042 *
1043 * Get the next packet from a free list and complete setup of the
1044 * sk_buff. If the packet is small we make a copy and recycle the
1045 * original buffer, otherwise we use the original buffer itself. If a
1046 * positive drop threshold is supplied packets are dropped and their
1047 * buffers recycled if (a) the number of remaining buffers is under the
1048 * threshold and the packet is too big to copy, or (b) the packet should
1049 * be copied but there is no memory for the copy.
1050 */
1051 static inline struct sk_buff *get_packet(struct pci_dev *pdev,
1052 struct freelQ *fl, unsigned int len)
1053 {
1054 struct sk_buff *skb;
1055 const struct freelQ_ce *ce = &fl->centries[fl->cidx];
1056
1057 if (len < copybreak) {
1058 skb = alloc_skb(len + 2, GFP_ATOMIC);
1059 if (!skb)
1060 goto use_orig_buf;
1061
1062 skb_reserve(skb, 2); /* align IP header */
1063 skb_put(skb, len);
1064 pci_dma_sync_single_for_cpu(pdev,
1065 pci_unmap_addr(ce, dma_addr),
1066 pci_unmap_len(ce, dma_len),
1067 PCI_DMA_FROMDEVICE);
1068 skb_copy_from_linear_data(ce->skb, skb->data, len);
1069 pci_dma_sync_single_for_device(pdev,
1070 pci_unmap_addr(ce, dma_addr),
1071 pci_unmap_len(ce, dma_len),
1072 PCI_DMA_FROMDEVICE);
1073 recycle_fl_buf(fl, fl->cidx);
1074 return skb;
1075 }
1076
1077 use_orig_buf:
1078 if (fl->credits < 2) {
1079 recycle_fl_buf(fl, fl->cidx);
1080 return NULL;
1081 }
1082
1083 pci_unmap_single(pdev, pci_unmap_addr(ce, dma_addr),
1084 pci_unmap_len(ce, dma_len), PCI_DMA_FROMDEVICE);
1085 skb = ce->skb;
1086 prefetch(skb->data);
1087
1088 skb_put(skb, len);
1089 return skb;
1090 }
1091
1092 /**
1093 * unexpected_offload - handle an unexpected offload packet
1094 * @adapter: the adapter
1095 * @fl: the free list that received the packet
1096 *
1097 * Called when we receive an unexpected offload packet (e.g., the TOE
1098 * function is disabled or the card is a NIC). Prints a message and
1099 * recycles the buffer.
1100 */
1101 static void unexpected_offload(struct adapter *adapter, struct freelQ *fl)
1102 {
1103 struct freelQ_ce *ce = &fl->centries[fl->cidx];
1104 struct sk_buff *skb = ce->skb;
1105
1106 pci_dma_sync_single_for_cpu(adapter->pdev, pci_unmap_addr(ce, dma_addr),
1107 pci_unmap_len(ce, dma_len), PCI_DMA_FROMDEVICE);
1108 CH_ERR("%s: unexpected offload packet, cmd %u\n",
1109 adapter->name, *skb->data);
1110 recycle_fl_buf(fl, fl->cidx);
1111 }
1112
1113 /*
1114 * T1/T2 SGE limits the maximum DMA size per TX descriptor to
1115 * SGE_TX_DESC_MAX_PLEN (16KB). If the PAGE_SIZE is larger than 16KB, the
1116 * stack might send more than SGE_TX_DESC_MAX_PLEN in a contiguous manner.
1117 * Note that the *_large_page_tx_descs stuff will be optimized out when
1118 * PAGE_SIZE <= SGE_TX_DESC_MAX_PLEN.
1119 *
1120 * compute_large_page_descs() computes how many additional descriptors are
1121 * required to break down the stack's request.
1122 */
1123 static inline unsigned int compute_large_page_tx_descs(struct sk_buff *skb)
1124 {
1125 unsigned int count = 0;
1126
1127 if (PAGE_SIZE > SGE_TX_DESC_MAX_PLEN) {
1128 unsigned int nfrags = skb_shinfo(skb)->nr_frags;
1129 unsigned int i, len = skb->len - skb->data_len;
1130 while (len > SGE_TX_DESC_MAX_PLEN) {
1131 count++;
1132 len -= SGE_TX_DESC_MAX_PLEN;
1133 }
1134 for (i = 0; nfrags--; i++) {
1135 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1136 len = frag->size;
1137 while (len > SGE_TX_DESC_MAX_PLEN) {
1138 count++;
1139 len -= SGE_TX_DESC_MAX_PLEN;
1140 }
1141 }
1142 }
1143 return count;
1144 }
1145
1146 /*
1147 * Write a cmdQ entry.
1148 *
1149 * Since this function writes the 'flags' field, it must not be used to
1150 * write the first cmdQ entry.
1151 */
1152 static inline void write_tx_desc(struct cmdQ_e *e, dma_addr_t mapping,
1153 unsigned int len, unsigned int gen,
1154 unsigned int eop)
1155 {
1156 if (unlikely(len > SGE_TX_DESC_MAX_PLEN))
1157 BUG();
1158 e->addr_lo = (u32)mapping;
1159 e->addr_hi = (u64)mapping >> 32;
1160 e->len_gen = V_CMD_LEN(len) | V_CMD_GEN1(gen);
1161 e->flags = F_CMD_DATAVALID | V_CMD_EOP(eop) | V_CMD_GEN2(gen);
1162 }
1163
1164 /*
1165 * See comment for previous function.
1166 *
1167 * write_tx_descs_large_page() writes additional SGE tx descriptors if
1168 * *desc_len exceeds HW's capability.
1169 */
1170 static inline unsigned int write_large_page_tx_descs(unsigned int pidx,
1171 struct cmdQ_e **e,
1172 struct cmdQ_ce **ce,
1173 unsigned int *gen,
1174 dma_addr_t *desc_mapping,
1175 unsigned int *desc_len,
1176 unsigned int nfrags,
1177 struct cmdQ *q)
1178 {
1179 if (PAGE_SIZE > SGE_TX_DESC_MAX_PLEN) {
1180 struct cmdQ_e *e1 = *e;
1181 struct cmdQ_ce *ce1 = *ce;
1182
1183 while (*desc_len > SGE_TX_DESC_MAX_PLEN) {
1184 *desc_len -= SGE_TX_DESC_MAX_PLEN;
1185 write_tx_desc(e1, *desc_mapping, SGE_TX_DESC_MAX_PLEN,
1186 *gen, nfrags == 0 && *desc_len == 0);
1187 ce1->skb = NULL;
1188 pci_unmap_len_set(ce1, dma_len, 0);
1189 *desc_mapping += SGE_TX_DESC_MAX_PLEN;
1190 if (*desc_len) {
1191 ce1++;
1192 e1++;
1193 if (++pidx == q->size) {
1194 pidx = 0;
1195 *gen ^= 1;
1196 ce1 = q->centries;
1197 e1 = q->entries;
1198 }
1199 }
1200 }
1201 *e = e1;
1202 *ce = ce1;
1203 }
1204 return pidx;
1205 }
1206
1207 /*
1208 * Write the command descriptors to transmit the given skb starting at
1209 * descriptor pidx with the given generation.
1210 */
1211 static inline void write_tx_descs(struct adapter *adapter, struct sk_buff *skb,
1212 unsigned int pidx, unsigned int gen,
1213 struct cmdQ *q)
1214 {
1215 dma_addr_t mapping, desc_mapping;
1216 struct cmdQ_e *e, *e1;
1217 struct cmdQ_ce *ce;
1218 unsigned int i, flags, first_desc_len, desc_len,
1219 nfrags = skb_shinfo(skb)->nr_frags;
1220
1221 e = e1 = &q->entries[pidx];
1222 ce = &q->centries[pidx];
1223
1224 mapping = pci_map_single(adapter->pdev, skb->data,
1225 skb->len - skb->data_len, PCI_DMA_TODEVICE);
1226
1227 desc_mapping = mapping;
1228 desc_len = skb->len - skb->data_len;
1229
1230 flags = F_CMD_DATAVALID | F_CMD_SOP |
1231 V_CMD_EOP(nfrags == 0 && desc_len <= SGE_TX_DESC_MAX_PLEN) |
1232 V_CMD_GEN2(gen);
1233 first_desc_len = (desc_len <= SGE_TX_DESC_MAX_PLEN) ?
1234 desc_len : SGE_TX_DESC_MAX_PLEN;
1235 e->addr_lo = (u32)desc_mapping;
1236 e->addr_hi = (u64)desc_mapping >> 32;
1237 e->len_gen = V_CMD_LEN(first_desc_len) | V_CMD_GEN1(gen);
1238 ce->skb = NULL;
1239 pci_unmap_len_set(ce, dma_len, 0);
1240
1241 if (PAGE_SIZE > SGE_TX_DESC_MAX_PLEN &&
1242 desc_len > SGE_TX_DESC_MAX_PLEN) {
1243 desc_mapping += first_desc_len;
1244 desc_len -= first_desc_len;
1245 e1++;
1246 ce++;
1247 if (++pidx == q->size) {
1248 pidx = 0;
1249 gen ^= 1;
1250 e1 = q->entries;
1251 ce = q->centries;
1252 }
1253 pidx = write_large_page_tx_descs(pidx, &e1, &ce, &gen,
1254 &desc_mapping, &desc_len,
1255 nfrags, q);
1256
1257 if (likely(desc_len))
1258 write_tx_desc(e1, desc_mapping, desc_len, gen,
1259 nfrags == 0);
1260 }
1261
1262 ce->skb = NULL;
1263 pci_unmap_addr_set(ce, dma_addr, mapping);
1264 pci_unmap_len_set(ce, dma_len, skb->len - skb->data_len);
1265
1266 for (i = 0; nfrags--; i++) {
1267 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1268 e1++;
1269 ce++;
1270 if (++pidx == q->size) {
1271 pidx = 0;
1272 gen ^= 1;
1273 e1 = q->entries;
1274 ce = q->centries;
1275 }
1276
1277 mapping = pci_map_page(adapter->pdev, frag->page,
1278 frag->page_offset, frag->size,
1279 PCI_DMA_TODEVICE);
1280 desc_mapping = mapping;
1281 desc_len = frag->size;
1282
1283 pidx = write_large_page_tx_descs(pidx, &e1, &ce, &gen,
1284 &desc_mapping, &desc_len,
1285 nfrags, q);
1286 if (likely(desc_len))
1287 write_tx_desc(e1, desc_mapping, desc_len, gen,
1288 nfrags == 0);
1289 ce->skb = NULL;
1290 pci_unmap_addr_set(ce, dma_addr, mapping);
1291 pci_unmap_len_set(ce, dma_len, frag->size);
1292 }
1293 ce->skb = skb;
1294 wmb();
1295 e->flags = flags;
1296 }
1297
1298 /*
1299 * Clean up completed Tx buffers.
1300 */
1301 static inline void reclaim_completed_tx(struct sge *sge, struct cmdQ *q)
1302 {
1303 unsigned int reclaim = q->processed - q->cleaned;
1304
1305 if (reclaim) {
1306 pr_debug("reclaim_completed_tx processed:%d cleaned:%d\n",
1307 q->processed, q->cleaned);
1308 free_cmdQ_buffers(sge, q, reclaim);
1309 q->cleaned += reclaim;
1310 }
1311 }
1312
1313 /*
1314 * Called from tasklet. Checks the scheduler for any
1315 * pending skbs that can be sent.
1316 */
1317 static void restart_sched(unsigned long arg)
1318 {
1319 struct sge *sge = (struct sge *) arg;
1320 struct adapter *adapter = sge->adapter;
1321 struct cmdQ *q = &sge->cmdQ[0];
1322 struct sk_buff *skb;
1323 unsigned int credits, queued_skb = 0;
1324
1325 spin_lock(&q->lock);
1326 reclaim_completed_tx(sge, q);
1327
1328 credits = q->size - q->in_use;
1329 pr_debug("restart_sched credits=%d\n", credits);
1330 while ((skb = sched_skb(sge, NULL, credits)) != NULL) {
1331 unsigned int genbit, pidx, count;
1332 count = 1 + skb_shinfo(skb)->nr_frags;
1333 count += compute_large_page_tx_descs(skb);
1334 q->in_use += count;
1335 genbit = q->genbit;
1336 pidx = q->pidx;
1337 q->pidx += count;
1338 if (q->pidx >= q->size) {
1339 q->pidx -= q->size;
1340 q->genbit ^= 1;
1341 }
1342 write_tx_descs(adapter, skb, pidx, genbit, q);
1343 credits = q->size - q->in_use;
1344 queued_skb = 1;
1345 }
1346
1347 if (queued_skb) {
1348 clear_bit(CMDQ_STAT_LAST_PKT_DB, &q->status);
1349 if (test_and_set_bit(CMDQ_STAT_RUNNING, &q->status) == 0) {
1350 set_bit(CMDQ_STAT_LAST_PKT_DB, &q->status);
1351 writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL);
1352 }
1353 }
1354 spin_unlock(&q->lock);
1355 }
1356
1357 /**
1358 * sge_rx - process an ingress ethernet packet
1359 * @sge: the sge structure
1360 * @fl: the free list that contains the packet buffer
1361 * @len: the packet length
1362 *
1363 * Process an ingress ethernet pakcet and deliver it to the stack.
1364 */
1365 static void sge_rx(struct sge *sge, struct freelQ *fl, unsigned int len)
1366 {
1367 struct sk_buff *skb;
1368 const struct cpl_rx_pkt *p;
1369 struct adapter *adapter = sge->adapter;
1370 struct sge_port_stats *st;
1371
1372 skb = get_packet(adapter->pdev, fl, len - sge->rx_pkt_pad);
1373 if (unlikely(!skb)) {
1374 sge->stats.rx_drops++;
1375 return;
1376 }
1377
1378 p = (const struct cpl_rx_pkt *) skb->data;
1379 if (p->iff >= adapter->params.nports) {
1380 kfree_skb(skb);
1381 return;
1382 }
1383 __skb_pull(skb, sizeof(*p));
1384
1385 st = per_cpu_ptr(sge->port_stats[p->iff], smp_processor_id());
1386
1387 skb->protocol = eth_type_trans(skb, adapter->port[p->iff].dev);
1388 skb->dev->last_rx = jiffies;
1389 if ((adapter->flags & RX_CSUM_ENABLED) && p->csum == 0xffff &&
1390 skb->protocol == htons(ETH_P_IP) &&
1391 (skb->data[9] == IPPROTO_TCP || skb->data[9] == IPPROTO_UDP)) {
1392 ++st->rx_cso_good;
1393 skb->ip_summed = CHECKSUM_UNNECESSARY;
1394 } else
1395 skb->ip_summed = CHECKSUM_NONE;
1396
1397 if (unlikely(adapter->vlan_grp && p->vlan_valid)) {
1398 st->vlan_xtract++;
1399 #ifdef CONFIG_CHELSIO_T1_NAPI
1400 vlan_hwaccel_receive_skb(skb, adapter->vlan_grp,
1401 ntohs(p->vlan));
1402 #else
1403 vlan_hwaccel_rx(skb, adapter->vlan_grp,
1404 ntohs(p->vlan));
1405 #endif
1406 } else {
1407 #ifdef CONFIG_CHELSIO_T1_NAPI
1408 netif_receive_skb(skb);
1409 #else
1410 netif_rx(skb);
1411 #endif
1412 }
1413 }
1414
1415 /*
1416 * Returns true if a command queue has enough available descriptors that
1417 * we can resume Tx operation after temporarily disabling its packet queue.
1418 */
1419 static inline int enough_free_Tx_descs(const struct cmdQ *q)
1420 {
1421 unsigned int r = q->processed - q->cleaned;
1422
1423 return q->in_use - r < (q->size >> 1);
1424 }
1425
1426 /*
1427 * Called when sufficient space has become available in the SGE command queues
1428 * after the Tx packet schedulers have been suspended to restart the Tx path.
1429 */
1430 static void restart_tx_queues(struct sge *sge)
1431 {
1432 struct adapter *adap = sge->adapter;
1433 int i;
1434
1435 if (!enough_free_Tx_descs(&sge->cmdQ[0]))
1436 return;
1437
1438 for_each_port(adap, i) {
1439 struct net_device *nd = adap->port[i].dev;
1440
1441 if (test_and_clear_bit(nd->if_port, &sge->stopped_tx_queues) &&
1442 netif_running(nd)) {
1443 sge->stats.cmdQ_restarted[2]++;
1444 netif_wake_queue(nd);
1445 }
1446 }
1447 }
1448
1449 /*
1450 * update_tx_info is called from the interrupt handler/NAPI to return cmdQ0
1451 * information.
1452 */
1453 static unsigned int update_tx_info(struct adapter *adapter,
1454 unsigned int flags,
1455 unsigned int pr0)
1456 {
1457 struct sge *sge = adapter->sge;
1458 struct cmdQ *cmdq = &sge->cmdQ[0];
1459
1460 cmdq->processed += pr0;
1461 if (flags & (F_FL0_ENABLE | F_FL1_ENABLE)) {
1462 freelQs_empty(sge);
1463 flags &= ~(F_FL0_ENABLE | F_FL1_ENABLE);
1464 }
1465 if (flags & F_CMDQ0_ENABLE) {
1466 clear_bit(CMDQ_STAT_RUNNING, &cmdq->status);
1467
1468 if (cmdq->cleaned + cmdq->in_use != cmdq->processed &&
1469 !test_and_set_bit(CMDQ_STAT_LAST_PKT_DB, &cmdq->status)) {
1470 set_bit(CMDQ_STAT_RUNNING, &cmdq->status);
1471 writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL);
1472 }
1473 if (sge->tx_sched)
1474 tasklet_hi_schedule(&sge->tx_sched->sched_tsk);
1475
1476 flags &= ~F_CMDQ0_ENABLE;
1477 }
1478
1479 if (unlikely(sge->stopped_tx_queues != 0))
1480 restart_tx_queues(sge);
1481
1482 return flags;
1483 }
1484
1485 /*
1486 * Process SGE responses, up to the supplied budget. Returns the number of
1487 * responses processed. A negative budget is effectively unlimited.
1488 */
1489 static int process_responses(struct adapter *adapter, int budget)
1490 {
1491 struct sge *sge = adapter->sge;
1492 struct respQ *q = &sge->respQ;
1493 struct respQ_e *e = &q->entries[q->cidx];
1494 int done = 0;
1495 unsigned int flags = 0;
1496 unsigned int cmdq_processed[SGE_CMDQ_N] = {0, 0};
1497
1498 while (done < budget && e->GenerationBit == q->genbit) {
1499 flags |= e->Qsleeping;
1500
1501 cmdq_processed[0] += e->Cmdq0CreditReturn;
1502 cmdq_processed[1] += e->Cmdq1CreditReturn;
1503
1504 /* We batch updates to the TX side to avoid cacheline
1505 * ping-pong of TX state information on MP where the sender
1506 * might run on a different CPU than this function...
1507 */
1508 if (unlikely((flags & F_CMDQ0_ENABLE) || cmdq_processed[0] > 64)) {
1509 flags = update_tx_info(adapter, flags, cmdq_processed[0]);
1510 cmdq_processed[0] = 0;
1511 }
1512
1513 if (unlikely(cmdq_processed[1] > 16)) {
1514 sge->cmdQ[1].processed += cmdq_processed[1];
1515 cmdq_processed[1] = 0;
1516 }
1517
1518 if (likely(e->DataValid)) {
1519 struct freelQ *fl = &sge->freelQ[e->FreelistQid];
1520
1521 BUG_ON(!e->Sop || !e->Eop);
1522 if (unlikely(e->Offload))
1523 unexpected_offload(adapter, fl);
1524 else
1525 sge_rx(sge, fl, e->BufferLength);
1526
1527 ++done;
1528
1529 /*
1530 * Note: this depends on each packet consuming a
1531 * single free-list buffer; cf. the BUG above.
1532 */
1533 if (++fl->cidx == fl->size)
1534 fl->cidx = 0;
1535 prefetch(fl->centries[fl->cidx].skb);
1536
1537 if (unlikely(--fl->credits <
1538 fl->size - SGE_FREEL_REFILL_THRESH))
1539 refill_free_list(sge, fl);
1540 } else
1541 sge->stats.pure_rsps++;
1542
1543 e++;
1544 if (unlikely(++q->cidx == q->size)) {
1545 q->cidx = 0;
1546 q->genbit ^= 1;
1547 e = q->entries;
1548 }
1549 prefetch(e);
1550
1551 if (++q->credits > SGE_RESPQ_REPLENISH_THRES) {
1552 writel(q->credits, adapter->regs + A_SG_RSPQUEUECREDIT);
1553 q->credits = 0;
1554 }
1555 }
1556
1557 flags = update_tx_info(adapter, flags, cmdq_processed[0]);
1558 sge->cmdQ[1].processed += cmdq_processed[1];
1559
1560 return done;
1561 }
1562
1563 static inline int responses_pending(const struct adapter *adapter)
1564 {
1565 const struct respQ *Q = &adapter->sge->respQ;
1566 const struct respQ_e *e = &Q->entries[Q->cidx];
1567
1568 return (e->GenerationBit == Q->genbit);
1569 }
1570
1571 #ifdef CONFIG_CHELSIO_T1_NAPI
1572 /*
1573 * A simpler version of process_responses() that handles only pure (i.e.,
1574 * non data-carrying) responses. Such respones are too light-weight to justify
1575 * calling a softirq when using NAPI, so we handle them specially in hard
1576 * interrupt context. The function is called with a pointer to a response,
1577 * which the caller must ensure is a valid pure response. Returns 1 if it
1578 * encounters a valid data-carrying response, 0 otherwise.
1579 */
1580 static int process_pure_responses(struct adapter *adapter)
1581 {
1582 struct sge *sge = adapter->sge;
1583 struct respQ *q = &sge->respQ;
1584 struct respQ_e *e = &q->entries[q->cidx];
1585 const struct freelQ *fl = &sge->freelQ[e->FreelistQid];
1586 unsigned int flags = 0;
1587 unsigned int cmdq_processed[SGE_CMDQ_N] = {0, 0};
1588
1589 prefetch(fl->centries[fl->cidx].skb);
1590 if (e->DataValid)
1591 return 1;
1592
1593 do {
1594 flags |= e->Qsleeping;
1595
1596 cmdq_processed[0] += e->Cmdq0CreditReturn;
1597 cmdq_processed[1] += e->Cmdq1CreditReturn;
1598
1599 e++;
1600 if (unlikely(++q->cidx == q->size)) {
1601 q->cidx = 0;
1602 q->genbit ^= 1;
1603 e = q->entries;
1604 }
1605 prefetch(e);
1606
1607 if (++q->credits > SGE_RESPQ_REPLENISH_THRES) {
1608 writel(q->credits, adapter->regs + A_SG_RSPQUEUECREDIT);
1609 q->credits = 0;
1610 }
1611 sge->stats.pure_rsps++;
1612 } while (e->GenerationBit == q->genbit && !e->DataValid);
1613
1614 flags = update_tx_info(adapter, flags, cmdq_processed[0]);
1615 sge->cmdQ[1].processed += cmdq_processed[1];
1616
1617 return e->GenerationBit == q->genbit;
1618 }
1619
1620 /*
1621 * Handler for new data events when using NAPI. This does not need any locking
1622 * or protection from interrupts as data interrupts are off at this point and
1623 * other adapter interrupts do not interfere.
1624 */
1625 int t1_poll(struct napi_struct *napi, int budget)
1626 {
1627 struct adapter *adapter = container_of(napi, struct adapter, napi);
1628 struct net_device *dev = adapter->port[0].dev;
1629 int work_done = process_responses(adapter, budget);
1630
1631 if (likely(work_done < budget)) {
1632 netif_rx_complete(dev, napi);
1633 writel(adapter->sge->respQ.cidx,
1634 adapter->regs + A_SG_SLEEPING);
1635 }
1636 return work_done;
1637 }
1638
1639 /*
1640 * NAPI version of the main interrupt handler.
1641 */
1642 irqreturn_t t1_interrupt(int irq, void *data)
1643 {
1644 struct adapter *adapter = data;
1645 struct sge *sge = adapter->sge;
1646 int handled;
1647
1648 if (likely(responses_pending(adapter))) {
1649 struct net_device *dev = sge->netdev;
1650
1651 writel(F_PL_INTR_SGE_DATA, adapter->regs + A_PL_CAUSE);
1652
1653 if (napi_schedule_prep(&adapter->napi)) {
1654 if (process_pure_responses(adapter))
1655 __netif_rx_schedule(dev, &adapter->napi);
1656 else {
1657 /* no data, no NAPI needed */
1658 writel(sge->respQ.cidx, adapter->regs + A_SG_SLEEPING);
1659 napi_enable(&adapter->napi); /* undo schedule_prep */
1660 }
1661 }
1662 return IRQ_HANDLED;
1663 }
1664
1665 spin_lock(&adapter->async_lock);
1666 handled = t1_slow_intr_handler(adapter);
1667 spin_unlock(&adapter->async_lock);
1668
1669 if (!handled)
1670 sge->stats.unhandled_irqs++;
1671
1672 return IRQ_RETVAL(handled != 0);
1673 }
1674
1675 #else
1676 /*
1677 * Main interrupt handler, optimized assuming that we took a 'DATA'
1678 * interrupt.
1679 *
1680 * 1. Clear the interrupt
1681 * 2. Loop while we find valid descriptors and process them; accumulate
1682 * information that can be processed after the loop
1683 * 3. Tell the SGE at which index we stopped processing descriptors
1684 * 4. Bookkeeping; free TX buffers, ring doorbell if there are any
1685 * outstanding TX buffers waiting, replenish RX buffers, potentially
1686 * reenable upper layers if they were turned off due to lack of TX
1687 * resources which are available again.
1688 * 5. If we took an interrupt, but no valid respQ descriptors was found we
1689 * let the slow_intr_handler run and do error handling.
1690 */
1691 irqreturn_t t1_interrupt(int irq, void *cookie)
1692 {
1693 int work_done;
1694 struct adapter *adapter = cookie;
1695 struct respQ *Q = &adapter->sge->respQ;
1696
1697 spin_lock(&adapter->async_lock);
1698
1699 writel(F_PL_INTR_SGE_DATA, adapter->regs + A_PL_CAUSE);
1700
1701 if (likely(responses_pending(adapter)))
1702 work_done = process_responses(adapter, -1);
1703 else
1704 work_done = t1_slow_intr_handler(adapter);
1705
1706 /*
1707 * The unconditional clearing of the PL_CAUSE above may have raced
1708 * with DMA completion and the corresponding generation of a response
1709 * to cause us to miss the resulting data interrupt. The next write
1710 * is also unconditional to recover the missed interrupt and render
1711 * this race harmless.
1712 */
1713 writel(Q->cidx, adapter->regs + A_SG_SLEEPING);
1714
1715 if (!work_done)
1716 adapter->sge->stats.unhandled_irqs++;
1717 spin_unlock(&adapter->async_lock);
1718 return IRQ_RETVAL(work_done != 0);
1719 }
1720 #endif
1721
1722 /*
1723 * Enqueues the sk_buff onto the cmdQ[qid] and has hardware fetch it.
1724 *
1725 * The code figures out how many entries the sk_buff will require in the
1726 * cmdQ and updates the cmdQ data structure with the state once the enqueue
1727 * has complete. Then, it doesn't access the global structure anymore, but
1728 * uses the corresponding fields on the stack. In conjuction with a spinlock
1729 * around that code, we can make the function reentrant without holding the
1730 * lock when we actually enqueue (which might be expensive, especially on
1731 * architectures with IO MMUs).
1732 *
1733 * This runs with softirqs disabled.
1734 */
1735 static int t1_sge_tx(struct sk_buff *skb, struct adapter *adapter,
1736 unsigned int qid, struct net_device *dev)
1737 {
1738 struct sge *sge = adapter->sge;
1739 struct cmdQ *q = &sge->cmdQ[qid];
1740 unsigned int credits, pidx, genbit, count, use_sched_skb = 0;
1741
1742 if (!spin_trylock(&q->lock))
1743 return NETDEV_TX_LOCKED;
1744
1745 reclaim_completed_tx(sge, q);
1746
1747 pidx = q->pidx;
1748 credits = q->size - q->in_use;
1749 count = 1 + skb_shinfo(skb)->nr_frags;
1750 count += compute_large_page_tx_descs(skb);
1751
1752 /* Ethernet packet */
1753 if (unlikely(credits < count)) {
1754 if (!netif_queue_stopped(dev)) {
1755 netif_stop_queue(dev);
1756 set_bit(dev->if_port, &sge->stopped_tx_queues);
1757 sge->stats.cmdQ_full[2]++;
1758 CH_ERR("%s: Tx ring full while queue awake!\n",
1759 adapter->name);
1760 }
1761 spin_unlock(&q->lock);
1762 return NETDEV_TX_BUSY;
1763 }
1764
1765 if (unlikely(credits - count < q->stop_thres)) {
1766 netif_stop_queue(dev);
1767 set_bit(dev->if_port, &sge->stopped_tx_queues);
1768 sge->stats.cmdQ_full[2]++;
1769 }
1770
1771 /* T204 cmdQ0 skbs that are destined for a certain port have to go
1772 * through the scheduler.
1773 */
1774 if (sge->tx_sched && !qid && skb->dev) {
1775 use_sched:
1776 use_sched_skb = 1;
1777 /* Note that the scheduler might return a different skb than
1778 * the one passed in.
1779 */
1780 skb = sched_skb(sge, skb, credits);
1781 if (!skb) {
1782 spin_unlock(&q->lock);
1783 return NETDEV_TX_OK;
1784 }
1785 pidx = q->pidx;
1786 count = 1 + skb_shinfo(skb)->nr_frags;
1787 count += compute_large_page_tx_descs(skb);
1788 }
1789
1790 q->in_use += count;
1791 genbit = q->genbit;
1792 pidx = q->pidx;
1793 q->pidx += count;
1794 if (q->pidx >= q->size) {
1795 q->pidx -= q->size;
1796 q->genbit ^= 1;
1797 }
1798 spin_unlock(&q->lock);
1799
1800 write_tx_descs(adapter, skb, pidx, genbit, q);
1801
1802 /*
1803 * We always ring the doorbell for cmdQ1. For cmdQ0, we only ring
1804 * the doorbell if the Q is asleep. There is a natural race, where
1805 * the hardware is going to sleep just after we checked, however,
1806 * then the interrupt handler will detect the outstanding TX packet
1807 * and ring the doorbell for us.
1808 */
1809 if (qid)
1810 doorbell_pio(adapter, F_CMDQ1_ENABLE);
1811 else {
1812 clear_bit(CMDQ_STAT_LAST_PKT_DB, &q->status);
1813 if (test_and_set_bit(CMDQ_STAT_RUNNING, &q->status) == 0) {
1814 set_bit(CMDQ_STAT_LAST_PKT_DB, &q->status);
1815 writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL);
1816 }
1817 }
1818
1819 if (use_sched_skb) {
1820 if (spin_trylock(&q->lock)) {
1821 credits = q->size - q->in_use;
1822 skb = NULL;
1823 goto use_sched;
1824 }
1825 }
1826 return NETDEV_TX_OK;
1827 }
1828
1829 #define MK_ETH_TYPE_MSS(type, mss) (((mss) & 0x3FFF) | ((type) << 14))
1830
1831 /*
1832 * eth_hdr_len - return the length of an Ethernet header
1833 * @data: pointer to the start of the Ethernet header
1834 *
1835 * Returns the length of an Ethernet header, including optional VLAN tag.
1836 */
1837 static inline int eth_hdr_len(const void *data)
1838 {
1839 const struct ethhdr *e = data;
1840
1841 return e->h_proto == htons(ETH_P_8021Q) ? VLAN_ETH_HLEN : ETH_HLEN;
1842 }
1843
1844 /*
1845 * Adds the CPL header to the sk_buff and passes it to t1_sge_tx.
1846 */
1847 int t1_start_xmit(struct sk_buff *skb, struct net_device *dev)
1848 {
1849 struct adapter *adapter = dev->priv;
1850 struct sge *sge = adapter->sge;
1851 struct sge_port_stats *st = per_cpu_ptr(sge->port_stats[dev->if_port],
1852 smp_processor_id());
1853 struct cpl_tx_pkt *cpl;
1854 struct sk_buff *orig_skb = skb;
1855 int ret;
1856
1857 if (skb->protocol == htons(ETH_P_CPL5))
1858 goto send;
1859
1860 /*
1861 * We are using a non-standard hard_header_len.
1862 * Allocate more header room in the rare cases it is not big enough.
1863 */
1864 if (unlikely(skb_headroom(skb) < dev->hard_header_len - ETH_HLEN)) {
1865 skb = skb_realloc_headroom(skb, sizeof(struct cpl_tx_pkt_lso));
1866 ++st->tx_need_hdrroom;
1867 dev_kfree_skb_any(orig_skb);
1868 if (!skb)
1869 return NETDEV_TX_OK;
1870 }
1871
1872 if (skb_shinfo(skb)->gso_size) {
1873 int eth_type;
1874 struct cpl_tx_pkt_lso *hdr;
1875
1876 ++st->tx_tso;
1877
1878 eth_type = skb_network_offset(skb) == ETH_HLEN ?
1879 CPL_ETH_II : CPL_ETH_II_VLAN;
1880
1881 hdr = (struct cpl_tx_pkt_lso *)skb_push(skb, sizeof(*hdr));
1882 hdr->opcode = CPL_TX_PKT_LSO;
1883 hdr->ip_csum_dis = hdr->l4_csum_dis = 0;
1884 hdr->ip_hdr_words = ip_hdr(skb)->ihl;
1885 hdr->tcp_hdr_words = tcp_hdr(skb)->doff;
1886 hdr->eth_type_mss = htons(MK_ETH_TYPE_MSS(eth_type,
1887 skb_shinfo(skb)->gso_size));
1888 hdr->len = htonl(skb->len - sizeof(*hdr));
1889 cpl = (struct cpl_tx_pkt *)hdr;
1890 } else {
1891 /*
1892 * Packets shorter than ETH_HLEN can break the MAC, drop them
1893 * early. Also, we may get oversized packets because some
1894 * parts of the kernel don't handle our unusual hard_header_len
1895 * right, drop those too.
1896 */
1897 if (unlikely(skb->len < ETH_HLEN ||
1898 skb->len > dev->mtu + eth_hdr_len(skb->data))) {
1899 pr_debug("%s: packet size %d hdr %d mtu%d\n", dev->name,
1900 skb->len, eth_hdr_len(skb->data), dev->mtu);
1901 dev_kfree_skb_any(skb);
1902 return NETDEV_TX_OK;
1903 }
1904
1905 if (!(adapter->flags & UDP_CSUM_CAPABLE) &&
1906 skb->ip_summed == CHECKSUM_PARTIAL &&
1907 ip_hdr(skb)->protocol == IPPROTO_UDP) {
1908 if (unlikely(skb_checksum_help(skb))) {
1909 pr_debug("%s: unable to do udp checksum\n", dev->name);
1910 dev_kfree_skb_any(skb);
1911 return NETDEV_TX_OK;
1912 }
1913 }
1914
1915 /* Hmmm, assuming to catch the gratious arp... and we'll use
1916 * it to flush out stuck espi packets...
1917 */
1918 if ((unlikely(!adapter->sge->espibug_skb[dev->if_port]))) {
1919 if (skb->protocol == htons(ETH_P_ARP) &&
1920 arp_hdr(skb)->ar_op == htons(ARPOP_REQUEST)) {
1921 adapter->sge->espibug_skb[dev->if_port] = skb;
1922 /* We want to re-use this skb later. We
1923 * simply bump the reference count and it
1924 * will not be freed...
1925 */
1926 skb = skb_get(skb);
1927 }
1928 }
1929
1930 cpl = (struct cpl_tx_pkt *)__skb_push(skb, sizeof(*cpl));
1931 cpl->opcode = CPL_TX_PKT;
1932 cpl->ip_csum_dis = 1; /* SW calculates IP csum */
1933 cpl->l4_csum_dis = skb->ip_summed == CHECKSUM_PARTIAL ? 0 : 1;
1934 /* the length field isn't used so don't bother setting it */
1935
1936 st->tx_cso += (skb->ip_summed == CHECKSUM_PARTIAL);
1937 }
1938 cpl->iff = dev->if_port;
1939
1940 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
1941 if (adapter->vlan_grp && vlan_tx_tag_present(skb)) {
1942 cpl->vlan_valid = 1;
1943 cpl->vlan = htons(vlan_tx_tag_get(skb));
1944 st->vlan_insert++;
1945 } else
1946 #endif
1947 cpl->vlan_valid = 0;
1948
1949 send:
1950 dev->trans_start = jiffies;
1951 ret = t1_sge_tx(skb, adapter, 0, dev);
1952
1953 /* If transmit busy, and we reallocated skb's due to headroom limit,
1954 * then silently discard to avoid leak.
1955 */
1956 if (unlikely(ret != NETDEV_TX_OK && skb != orig_skb)) {
1957 dev_kfree_skb_any(skb);
1958 ret = NETDEV_TX_OK;
1959 }
1960 return ret;
1961 }
1962
1963 /*
1964 * Callback for the Tx buffer reclaim timer. Runs with softirqs disabled.
1965 */
1966 static void sge_tx_reclaim_cb(unsigned long data)
1967 {
1968 int i;
1969 struct sge *sge = (struct sge *)data;
1970
1971 for (i = 0; i < SGE_CMDQ_N; ++i) {
1972 struct cmdQ *q = &sge->cmdQ[i];
1973
1974 if (!spin_trylock(&q->lock))
1975 continue;
1976
1977 reclaim_completed_tx(sge, q);
1978 if (i == 0 && q->in_use) { /* flush pending credits */
1979 writel(F_CMDQ0_ENABLE, sge->adapter->regs + A_SG_DOORBELL);
1980 }
1981 spin_unlock(&q->lock);
1982 }
1983 mod_timer(&sge->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD);
1984 }
1985
1986 /*
1987 * Propagate changes of the SGE coalescing parameters to the HW.
1988 */
1989 int t1_sge_set_coalesce_params(struct sge *sge, struct sge_params *p)
1990 {
1991 sge->fixed_intrtimer = p->rx_coalesce_usecs *
1992 core_ticks_per_usec(sge->adapter);
1993 writel(sge->fixed_intrtimer, sge->adapter->regs + A_SG_INTRTIMER);
1994 return 0;
1995 }
1996
1997 /*
1998 * Allocates both RX and TX resources and configures the SGE. However,
1999 * the hardware is not enabled yet.
2000 */
2001 int t1_sge_configure(struct sge *sge, struct sge_params *p)
2002 {
2003 if (alloc_rx_resources(sge, p))
2004 return -ENOMEM;
2005 if (alloc_tx_resources(sge, p)) {
2006 free_rx_resources(sge);
2007 return -ENOMEM;
2008 }
2009 configure_sge(sge, p);
2010
2011 /*
2012 * Now that we have sized the free lists calculate the payload
2013 * capacity of the large buffers. Other parts of the driver use
2014 * this to set the max offload coalescing size so that RX packets
2015 * do not overflow our large buffers.
2016 */
2017 p->large_buf_capacity = jumbo_payload_capacity(sge);
2018 return 0;
2019 }
2020
2021 /*
2022 * Disables the DMA engine.
2023 */
2024 void t1_sge_stop(struct sge *sge)
2025 {
2026 int i;
2027 writel(0, sge->adapter->regs + A_SG_CONTROL);
2028 readl(sge->adapter->regs + A_SG_CONTROL); /* flush */
2029
2030 if (is_T2(sge->adapter))
2031 del_timer_sync(&sge->espibug_timer);
2032
2033 del_timer_sync(&sge->tx_reclaim_timer);
2034 if (sge->tx_sched)
2035 tx_sched_stop(sge);
2036
2037 for (i = 0; i < MAX_NPORTS; i++)
2038 if (sge->espibug_skb[i])
2039 kfree_skb(sge->espibug_skb[i]);
2040 }
2041
2042 /*
2043 * Enables the DMA engine.
2044 */
2045 void t1_sge_start(struct sge *sge)
2046 {
2047 refill_free_list(sge, &sge->freelQ[0]);
2048 refill_free_list(sge, &sge->freelQ[1]);
2049
2050 writel(sge->sge_control, sge->adapter->regs + A_SG_CONTROL);
2051 doorbell_pio(sge->adapter, F_FL0_ENABLE | F_FL1_ENABLE);
2052 readl(sge->adapter->regs + A_SG_CONTROL); /* flush */
2053
2054 mod_timer(&sge->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD);
2055
2056 if (is_T2(sge->adapter))
2057 mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout);
2058 }
2059
2060 /*
2061 * Callback for the T2 ESPI 'stuck packet feature' workaorund
2062 */
2063 static void espibug_workaround_t204(unsigned long data)
2064 {
2065 struct adapter *adapter = (struct adapter *)data;
2066 struct sge *sge = adapter->sge;
2067 unsigned int nports = adapter->params.nports;
2068 u32 seop[MAX_NPORTS];
2069
2070 if (adapter->open_device_map & PORT_MASK) {
2071 int i;
2072
2073 if (t1_espi_get_mon_t204(adapter, &(seop[0]), 0) < 0)
2074 return;
2075
2076 for (i = 0; i < nports; i++) {
2077 struct sk_buff *skb = sge->espibug_skb[i];
2078
2079 if (!netif_running(adapter->port[i].dev) ||
2080 netif_queue_stopped(adapter->port[i].dev) ||
2081 !seop[i] || ((seop[i] & 0xfff) != 0) || !skb)
2082 continue;
2083
2084 if (!skb->cb[0]) {
2085 u8 ch_mac_addr[ETH_ALEN] = {
2086 0x0, 0x7, 0x43, 0x0, 0x0, 0x0
2087 };
2088
2089 skb_copy_to_linear_data_offset(skb,
2090 sizeof(struct cpl_tx_pkt),
2091 ch_mac_addr,
2092 ETH_ALEN);
2093 skb_copy_to_linear_data_offset(skb,
2094 skb->len - 10,
2095 ch_mac_addr,
2096 ETH_ALEN);
2097 skb->cb[0] = 0xff;
2098 }
2099
2100 /* bump the reference count to avoid freeing of
2101 * the skb once the DMA has completed.
2102 */
2103 skb = skb_get(skb);
2104 t1_sge_tx(skb, adapter, 0, adapter->port[i].dev);
2105 }
2106 }
2107 mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout);
2108 }
2109
2110 static void espibug_workaround(unsigned long data)
2111 {
2112 struct adapter *adapter = (struct adapter *)data;
2113 struct sge *sge = adapter->sge;
2114
2115 if (netif_running(adapter->port[0].dev)) {
2116 struct sk_buff *skb = sge->espibug_skb[0];
2117 u32 seop = t1_espi_get_mon(adapter, 0x930, 0);
2118
2119 if ((seop & 0xfff0fff) == 0xfff && skb) {
2120 if (!skb->cb[0]) {
2121 u8 ch_mac_addr[ETH_ALEN] =
2122 {0x0, 0x7, 0x43, 0x0, 0x0, 0x0};
2123 skb_copy_to_linear_data_offset(skb,
2124 sizeof(struct cpl_tx_pkt),
2125 ch_mac_addr,
2126 ETH_ALEN);
2127 skb_copy_to_linear_data_offset(skb,
2128 skb->len - 10,
2129 ch_mac_addr,
2130 ETH_ALEN);
2131 skb->cb[0] = 0xff;
2132 }
2133
2134 /* bump the reference count to avoid freeing of the
2135 * skb once the DMA has completed.
2136 */
2137 skb = skb_get(skb);
2138 t1_sge_tx(skb, adapter, 0, adapter->port[0].dev);
2139 }
2140 }
2141 mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout);
2142 }
2143
2144 /*
2145 * Creates a t1_sge structure and returns suggested resource parameters.
2146 */
2147 struct sge * __devinit t1_sge_create(struct adapter *adapter,
2148 struct sge_params *p)
2149 {
2150 struct sge *sge = kzalloc(sizeof(*sge), GFP_KERNEL);
2151 int i;
2152
2153 if (!sge)
2154 return NULL;
2155
2156 sge->adapter = adapter;
2157 sge->netdev = adapter->port[0].dev;
2158 sge->rx_pkt_pad = t1_is_T1B(adapter) ? 0 : 2;
2159 sge->jumbo_fl = t1_is_T1B(adapter) ? 1 : 0;
2160
2161 for_each_port(adapter, i) {
2162 sge->port_stats[i] = alloc_percpu(struct sge_port_stats);
2163 if (!sge->port_stats[i])
2164 goto nomem_port;
2165 }
2166
2167 init_timer(&sge->tx_reclaim_timer);
2168 sge->tx_reclaim_timer.data = (unsigned long)sge;
2169 sge->tx_reclaim_timer.function = sge_tx_reclaim_cb;
2170
2171 if (is_T2(sge->adapter)) {
2172 init_timer(&sge->espibug_timer);
2173
2174 if (adapter->params.nports > 1) {
2175 tx_sched_init(sge);
2176 sge->espibug_timer.function = espibug_workaround_t204;
2177 } else
2178 sge->espibug_timer.function = espibug_workaround;
2179 sge->espibug_timer.data = (unsigned long)sge->adapter;
2180
2181 sge->espibug_timeout = 1;
2182 /* for T204, every 10ms */
2183 if (adapter->params.nports > 1)
2184 sge->espibug_timeout = HZ/100;
2185 }
2186
2187
2188 p->cmdQ_size[0] = SGE_CMDQ0_E_N;
2189 p->cmdQ_size[1] = SGE_CMDQ1_E_N;
2190 p->freelQ_size[!sge->jumbo_fl] = SGE_FREEL_SIZE;
2191 p->freelQ_size[sge->jumbo_fl] = SGE_JUMBO_FREEL_SIZE;
2192 if (sge->tx_sched) {
2193 if (board_info(sge->adapter)->board == CHBT_BOARD_CHT204)
2194 p->rx_coalesce_usecs = 15;
2195 else
2196 p->rx_coalesce_usecs = 50;
2197 } else
2198 p->rx_coalesce_usecs = 50;
2199
2200 p->coalesce_enable = 0;
2201 p->sample_interval_usecs = 0;
2202
2203 return sge;
2204 nomem_port:
2205 while (i >= 0) {
2206 free_percpu(sge->port_stats[i]);
2207 --i;
2208 }
2209 kfree(sge);
2210 return NULL;
2211
2212 }
2213
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